/* * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #include <drm/amdgpu_drm.h>#include <drm/clients/drm_client_setup.h>#include <drm/drm_drv.h>#include <drm/drm_fbdev_ttm.h>#include <drm/drm_gem.h>#include <drm/drm_managed.h>#include <drm/drm_pciids.h>#include <drm/drm_probe_helper.h>#include <drm/drm_vblank.h> #include <linux/cc_platform.h>#include <linux/dynamic_debug.h>#include <linux/module.h>#include <linux/mmu_notifier.h>#include <linux/pm_runtime.h>#include <linux/suspend.h>#include <linux/vga_switcheroo.h> #include "amdgpu.h"#include "amdgpu_amdkfd.h"#include "amdgpu_dma_buf.h"#include "amdgpu_drv.h"#include "amdgpu_fdinfo.h"#include "amdgpu_irq.h"#include "amdgpu_psp.h"#include "amdgpu_ras.h"#include "amdgpu_reset.h"#include "amdgpu_sched.h"#include "amdgpu_xgmi.h"#include "amdgpu_userq.h"#include "amdgpu_userq_fence.h"#include "../amdxcp/amdgpu_xcp_drv.h" /* * KMS wrapper. * - 3.0.0 - initial driver * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same * at the end of IBs. * - 3.3.0 - Add VM support for UVD on supported hardware. * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. * - 3.5.0 - Add support for new UVD_NO_OP register. * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. * - 3.7.0 - Add support for VCE clock list packet * - 3.8.0 - Add support raster config init in the kernel * - 3.9.0 - Add support for memory query info about VRAM and GTT. * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). * - 3.12.0 - Add query for double offchip LDS buffers * - 3.13.0 - Add PRT support * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality * - 3.15.0 - Export more gpu info for gfx9 * - 3.16.0 - Add reserved vmid support * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. * - 3.18.0 - Export gpu always on cu bitmap * - 3.19.0 - Add support for UVD MJPEG decode * - 3.20.0 - Add support for local BOs * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl * - 3.23.0 - Add query for VRAM lost counter * - 3.24.0 - Add high priority compute support for gfx9 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. * - 3.31.0 - Add support for per-flip tiling attribute changes with DC * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask * - 3.36.0 - Allow reading more status registers on si/cik * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC * - 3.39.0 - DMABUF implicit sync does a full pipeline sync * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ * - 3.41.0 - Add video codec query * - 3.42.0 - Add 16bpc fixed point display support * - 3.43.0 - Add device hot plug/unplug support * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B * - 3.45.0 - Add context ioctl stable pstate interface * - 3.46.0 - To enable hot plug amdgpu tests in libdrm * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags * - 3.48.0 - Add IP discovery version info to HW INFO * - 3.49.0 - Add gang submit into CS IOCTL * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi * 3.53.0 - Support for GFX11 CP GFX shadowing * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query * - 3.56.0 - Update IB start address and size alignment for decode and encode * - 3.57.0 - Compute tunneling on GFX10+ * - 3.58.0 - Add GFX12 DCC support * - 3.59.0 - Cleared VRAM * - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement) * - 3.61.0 - Contains fix for RV/PCO compute queues * - 3.62.0 - Add AMDGPU_IDS_FLAGS_MODE_PF, AMDGPU_IDS_FLAGS_MODE_VF & AMDGPU_IDS_FLAGS_MODE_PT * - 3.63.0 - GFX12 display DCC supports 256B max compressed block size * - 3.64.0 - Userq IP support query */#define KMS_DRIVER_MAJOR 3#define KMS_DRIVER_MINOR 64#define KMS_DRIVER_PATCHLEVEL 0 /* * amdgpu.debug module options. Are all disabled by default */enum AMDGPU_DEBUG_MASK { AMDGPU_DEBUG_VM = BIT(0), AMDGPU_DEBUG_LARGEBAR = BIT(1), AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2), AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3), AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5), AMDGPU_DEBUG_DISABLE_GPU_RING_RESET = BIT(6), AMDGPU_DEBUG_SMU_POOL = BIT(7), AMDGPU_DEBUG_VM_USERPTR = BIT(8), AMDGPU_DEBUG_DISABLE_RAS_CE_LOG = BIT(9), AMDGPU_DEBUG_ENABLE_CE_CS = BIT(10), AMDGPU_DEBUG_HIBERNATION_THAW_RESUME_GPU = BIT(11), AMDGPU_DEBUG_DISABLE_IP_BLOCK_SOFT_RESET = BIT(12),}; unsigned int amdgpu_vram_limit = UINT_MAX;int amdgpu_vis_vram_limit;int amdgpu_gart_size = -1; /* auto */int amdgpu_gtt_size = -1; /* auto */int amdgpu_moverate = -1; /* auto */int amdgpu_audio = -1;int amdgpu_disp_priority;int amdgpu_hw_i2c;int amdgpu_pcie_gen2 = -1;int amdgpu_msi = -1;char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];int amdgpu_dpm = -1;int amdgpu_fw_load_type = -1;int amdgpu_aspm = -1;int amdgpu_runtime_pm = -1;uint amdgpu_ip_block_mask = 0xffffffff;int amdgpu_bapm = -1;int amdgpu_deep_color;int amdgpu_vm_size = -1;int amdgpu_vm_fragment_size = -1;int amdgpu_vm_block_size = -1;int amdgpu_vm_fault_stop;int amdgpu_vm_update_mode = -1;int amdgpu_exp_hw_support;int amdgpu_dc = -1;int amdgpu_sched_jobs = 32;int amdgpu_sched_hw_submission = 2;uint amdgpu_pcie_gen_cap;uint amdgpu_pcie_lane_cap;u64 amdgpu_cg_mask = 0xffffffffffffffff;uint amdgpu_pg_mask = 0xffffffff;uint amdgpu_sdma_phase_quantum = 32;char *amdgpu_disable_cu;char *amdgpu_virtual_display;int amdgpu_enforce_isolation = -1;int amdgpu_modeset = -1; /* Specifies the default granularity for SVM, used in buffer * migration and restoration of backing memory when handling * recoverable page faults. * * The value is given as log(numPages(buffer)); for a 2 MiB * buffer it computes to be 9 */uint amdgpu_svm_default_granularity = 9; /* * OverDrive(bit 14) disabled by default * GFX DCS(bit 19) disabled by default */uint amdgpu_pp_feature_mask = 0xfff7bfff;uint amdgpu_force_long_training;int amdgpu_lbpw = -1;int amdgpu_compute_multipipe = -1;int amdgpu_gpu_recovery = -1; /* auto */int amdgpu_emu_mode;uint amdgpu_smu_memory_pool_size;int amdgpu_smu_pptable_id = -1;/* * FBC (bit 0) disabled by default * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default * - With this, for multiple monitors in sync(e.g. with the same model), * mclk switching will be allowed. And the mclk will be not foced to the * highest. That helps saving some idle power. * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default * PSR (bit 3) disabled by default * EDP NO POWER SEQUENCING (bit 4) disabled by default */uint amdgpu_dc_feature_mask = 2;uint amdgpu_dc_debug_mask;uint amdgpu_dc_visual_confirm;int amdgpu_async_gfx_ring = 1;int amdgpu_mcbp = -1;int amdgpu_discovery = -1;int amdgpu_mes_log_enable = 0;int amdgpu_uni_mes = 1;int amdgpu_noretry = -1;int amdgpu_force_asic_type = -1;int amdgpu_tmz = -1; /* auto */uint amdgpu_freesync_vid_mode;int amdgpu_reset_method = -1; /* auto */int amdgpu_num_kcq = -1;int amdgpu_smartshift_bias;int amdgpu_use_xgmi_p2p = 1;int amdgpu_vcnfw_log;int amdgpu_sg_display = -1; /* auto */int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE;int amdgpu_umsch_mm;int amdgpu_seamless = -1; /* auto */uint amdgpu_debug_mask;int amdgpu_agp = -1; /* auto */int amdgpu_wbrf = -1;int amdgpu_damage_clips = -1; /* auto */int amdgpu_umsch_mm_fwlog;int amdgpu_rebar = -1; /* auto */int amdgpu_user_queue = -1;uint amdgpu_hdmi_hpd_debounce_delay_ms;int amdgpu_ptl = -1; /* auto */ DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, "DRM_UT_CORE", "DRM_UT_DRIVER", "DRM_UT_KMS", "DRM_UT_PRIME", "DRM_UT_ATOMIC", "DRM_UT_VBL", "DRM_UT_STATE", "DRM_UT_LEASE", "DRM_UT_DP", "DRM_UT_DRMRES"); struct amdgpu_mgpu_info mgpu_info = { .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),};int amdgpu_ras_enable = -1;uint amdgpu_ras_mask = 0xffffffff;int amdgpu_bad_page_threshold = -1;struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { .timeout_fatal_disable = false, .period = 0x0, /* default to 0x0 (timeout disable) */}; /** * DOC: vramlimit (int) * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). */MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); /** * DOC: vis_vramlimit (int) * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). */MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); /** * DOC: gartsize (uint) * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. * The default is -1 (The size depends on asic). */MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)");module_param_named(gartsize, amdgpu_gart_size, uint, 0600); /** * DOC: gttsize (int) * Restrict the size of GTT domain (for userspace use) in MiB for testing. * The default is -1 (Use value specified by TTM). * This parameter is deprecated and will be removed in the future. */MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)");module_param_named(gttsize, amdgpu_gtt_size, int, 0600); /** * DOC: moverate (int) * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). */MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");module_param_named(moverate, amdgpu_moverate, int, 0600); /** * DOC: audio (int) * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. */MODULE_PARM_DESC(audio, "HDMI/DP Audio enable for non DC displays (-1 = auto, 0 = disable, 1 = enable)");module_param_named(audio, amdgpu_audio, int, 0444); /** * DOC: disp_priority (int) * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). */MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); /** * DOC: hw_i2c (int) * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). */MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); /** * DOC: pcie_gen2 (int) * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). */MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); /** * DOC: msi (int) * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). */MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");module_param_named(msi, amdgpu_msi, int, 0444); /** * DOC: svm_default_granularity (uint) * Used in buffer migration and handling of recoverable page faults */MODULE_PARM_DESC(svm_default_granularity, "SVM's default granularity in log(2^Pages), default 9 = 2^9 = 2 MiB");module_param_named(svm_default_granularity, amdgpu_svm_default_granularity, uint, 0644); /** * DOC: lockup_timeout (string) * Set GPU scheduler timeout value in ms. * * The format can be [single value] for setting all timeouts at once or * [GFX,Compute,SDMA,Video] to set individual timeouts. * Negative values mean infinity. * * By default(with no lockup_timeout settings), the timeout for all queues is 2000. */MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: 2000. 0: keep default value. negative: infinity timeout), format: [single value for all] or [GFX,Compute,SDMA,Video].");module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); /** * DOC: dpm (int) * Override for dynamic power management setting * (0 = disable, 1 = enable) * The default is -1 (auto). */MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");module_param_named(dpm, amdgpu_dpm, int, 0444); /** * DOC: fw_load_type (int) * Set different firmware loading type for debugging, if supported. * Set to 0 to force direct loading if supported by the ASIC. Set * to -1 to select the default loading mode for the ASIC, as defined * by the driver. The default is -1 (auto). */MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)");module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); /** * DOC: aspm (int) * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). */MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");module_param_named(aspm, amdgpu_aspm, int, 0444); /** * DOC: runpm (int) * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down * the dGPUs when they are idle if supported. The default is -1 (auto enable). * Setting the value to 0 disables this functionality. * Setting the value to -2 is auto enabled with power down when displays are attached. */MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)");module_param_named(runpm, amdgpu_runtime_pm, int, 0444); /** * DOC: ip_block_mask (uint) * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). */MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");module_param_named_unsafe(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); /** * DOC: bapm (int) * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. * The default -1 (auto, enabled) */MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");module_param_named(bapm, amdgpu_bapm, int, 0444); /** * DOC: deep_color (int) * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). */MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");module_param_named(deep_color, amdgpu_deep_color, int, 0444); /** * DOC: vm_size (int) * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). */MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");module_param_named(vm_size, amdgpu_vm_size, int, 0444); /** * DOC: vm_fragment_size (int) * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). */MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); /** * DOC: vm_block_size (int) * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). */MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); /** * DOC: vm_fault_stop (int) * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). */MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); /** * DOC: vm_update_mode (int) * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). */MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); /** * DOC: exp_hw_support (int) * Enable experimental hw support (1 = enable). The default is 0 (disabled). */MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");module_param_named_unsafe(exp_hw_support, amdgpu_exp_hw_support, int, 0444); /** * DOC: dc (int) * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). */MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");module_param_named(dc, amdgpu_dc, int, 0444); /** * DOC: sched_jobs (int) * Override the max number of jobs supported in the sw queue. The default is 32. */MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); /** * DOC: sched_hw_submission (int) * Override the max number of HW submissions. The default is 2. */MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); /** * DOC: ppfeaturemask (hexint) * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. * The default is the current set of stable power features. */MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444);Lines 1–500 of 3243. Load more
/* * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #include <drm/amdgpu_drm.h> #include <drm/clients/drm_client_setup.h> #include <drm/drm_drv.h> #include <drm/drm_fbdev_ttm.h> #include <drm/drm_gem.h> #include <drm/drm_managed.h> #include <drm/drm_pciids.h> #include <drm/drm_probe_helper.h> #include <drm/drm_vblank.h> #include <linux/cc_platform.h> #include <linux/dynamic_debug.h> #include <linux/module.h> #include <linux/mmu_notifier.h> #include <linux/pm_runtime.h> #include <linux/suspend.h> #include <linux/vga_switcheroo.h> #include "amdgpu.h" #include "amdgpu_amdkfd.h" #include "amdgpu_dma_buf.h" #include "amdgpu_drv.h" #include "amdgpu_fdinfo.h" #include "amdgpu_irq.h" #include "amdgpu_psp.h" #include "amdgpu_ras.h" #include "amdgpu_reset.h" #include "amdgpu_sched.h" #include "amdgpu_xgmi.h" #include "amdgpu_userq.h" #include "amdgpu_userq_fence.h" #include "../amdxcp/amdgpu_xcp_drv.h" /* * KMS wrapper. * - 3.0.0 - initial driver * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same * at the end of IBs. * - 3.3.0 - Add VM support for UVD on supported hardware. * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. * - 3.5.0 - Add support for new UVD_NO_OP register. * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. * - 3.7.0 - Add support for VCE clock list packet * - 3.8.0 - Add support raster config init in the kernel * - 3.9.0 - Add support for memory query info about VRAM and GTT. * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). * - 3.12.0 - Add query for double offchip LDS buffers * - 3.13.0 - Add PRT support * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality * - 3.15.0 - Export more gpu info for gfx9 * - 3.16.0 - Add reserved vmid support * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. * - 3.18.0 - Export gpu always on cu bitmap * - 3.19.0 - Add support for UVD MJPEG decode * - 3.20.0 - Add support for local BOs * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl * - 3.23.0 - Add query for VRAM lost counter * - 3.24.0 - Add high priority compute support for gfx9 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. * - 3.31.0 - Add support for per-flip tiling attribute changes with DC * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask * - 3.36.0 - Allow reading more status registers on si/cik * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC * - 3.39.0 - DMABUF implicit sync does a full pipeline sync * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ * - 3.41.0 - Add video codec query * - 3.42.0 - Add 16bpc fixed point display support * - 3.43.0 - Add device hot plug/unplug support * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B * - 3.45.0 - Add context ioctl stable pstate interface * - 3.46.0 - To enable hot plug amdgpu tests in libdrm * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags * - 3.48.0 - Add IP discovery version info to HW INFO * - 3.49.0 - Add gang submit into CS IOCTL * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi * 3.53.0 - Support for GFX11 CP GFX shadowing * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query * - 3.56.0 - Update IB start address and size alignment for decode and encode * - 3.57.0 - Compute tunneling on GFX10+ * - 3.58.0 - Add GFX12 DCC support * - 3.59.0 - Cleared VRAM * - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement) * - 3.61.0 - Contains fix for RV/PCO compute queues * - 3.62.0 - Add AMDGPU_IDS_FLAGS_MODE_PF, AMDGPU_IDS_FLAGS_MODE_VF & AMDGPU_IDS_FLAGS_MODE_PT * - 3.63.0 - GFX12 display DCC supports 256B max compressed block size * - 3.64.0 - Userq IP support query */ #define KMS_DRIVER_MAJOR 3 #define KMS_DRIVER_MINOR 64 #define KMS_DRIVER_PATCHLEVEL 0 /* * amdgpu.debug module options. Are all disabled by default */ enum AMDGPU_DEBUG_MASK { AMDGPU_DEBUG_VM = BIT(0), AMDGPU_DEBUG_LARGEBAR = BIT(1), AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2), AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3), AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5), AMDGPU_DEBUG_DISABLE_GPU_RING_RESET = BIT(6), AMDGPU_DEBUG_SMU_POOL = BIT(7), AMDGPU_DEBUG_VM_USERPTR = BIT(8), AMDGPU_DEBUG_DISABLE_RAS_CE_LOG = BIT(9), AMDGPU_DEBUG_ENABLE_CE_CS = BIT(10), AMDGPU_DEBUG_HIBERNATION_THAW_RESUME_GPU = BIT(11), AMDGPU_DEBUG_DISABLE_IP_BLOCK_SOFT_RESET = BIT(12), }; unsigned int amdgpu_vram_limit = UINT_MAX; int amdgpu_vis_vram_limit; int amdgpu_gart_size = -1; /* auto */ int amdgpu_gtt_size = -1; /* auto */ int amdgpu_moverate = -1; /* auto */ int amdgpu_audio = -1; int amdgpu_disp_priority; int amdgpu_hw_i2c; int amdgpu_pcie_gen2 = -1; int amdgpu_msi = -1; char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; int amdgpu_dpm = -1; int amdgpu_fw_load_type = -1; int amdgpu_aspm = -1; int amdgpu_runtime_pm = -1; uint amdgpu_ip_block_mask = 0xffffffff; int amdgpu_bapm = -1; int amdgpu_deep_color; int amdgpu_vm_size = -1; int amdgpu_vm_fragment_size = -1; int amdgpu_vm_block_size = -1; int amdgpu_vm_fault_stop; int amdgpu_vm_update_mode = -1; int amdgpu_exp_hw_support; int amdgpu_dc = -1; int amdgpu_sched_jobs = 32; int amdgpu_sched_hw_submission = 2; uint amdgpu_pcie_gen_cap; uint amdgpu_pcie_lane_cap; u64 amdgpu_cg_mask = 0xffffffffffffffff; uint amdgpu_pg_mask = 0xffffffff; uint amdgpu_sdma_phase_quantum = 32; char *amdgpu_disable_cu; char *amdgpu_virtual_display; int amdgpu_enforce_isolation = -1; int amdgpu_modeset = -1; /* Specifies the default granularity for SVM, used in buffer * migration and restoration of backing memory when handling * recoverable page faults. * * The value is given as log(numPages(buffer)); for a 2 MiB * buffer it computes to be 9 */ uint amdgpu_svm_default_granularity = 9; /* * OverDrive(bit 14) disabled by default * GFX DCS(bit 19) disabled by default */ uint amdgpu_pp_feature_mask = 0xfff7bfff; uint amdgpu_force_long_training; int amdgpu_lbpw = -1; int amdgpu_compute_multipipe = -1; int amdgpu_gpu_recovery = -1; /* auto */ int amdgpu_emu_mode; uint amdgpu_smu_memory_pool_size; int amdgpu_smu_pptable_id = -1; /* * FBC (bit 0) disabled by default * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default * - With this, for multiple monitors in sync(e.g. with the same model), * mclk switching will be allowed. And the mclk will be not foced to the * highest. That helps saving some idle power. * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default * PSR (bit 3) disabled by default * EDP NO POWER SEQUENCING (bit 4) disabled by default */ uint amdgpu_dc_feature_mask = 2; uint amdgpu_dc_debug_mask; uint amdgpu_dc_visual_confirm; int amdgpu_async_gfx_ring = 1; int amdgpu_mcbp = -1; int amdgpu_discovery = -1; int amdgpu_mes_log_enable = 0; int amdgpu_uni_mes = 1; int amdgpu_noretry = -1; int amdgpu_force_asic_type = -1; int amdgpu_tmz = -1; /* auto */ uint amdgpu_freesync_vid_mode; int amdgpu_reset_method = -1; /* auto */ int amdgpu_num_kcq = -1; int amdgpu_smartshift_bias; int amdgpu_use_xgmi_p2p = 1; int amdgpu_vcnfw_log; int amdgpu_sg_display = -1; /* auto */ int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; int amdgpu_umsch_mm; int amdgpu_seamless = -1; /* auto */ uint amdgpu_debug_mask; int amdgpu_agp = -1; /* auto */ int amdgpu_wbrf = -1; int amdgpu_damage_clips = -1; /* auto */ int amdgpu_umsch_mm_fwlog; int amdgpu_rebar = -1; /* auto */ int amdgpu_user_queue = -1; uint amdgpu_hdmi_hpd_debounce_delay_ms; int amdgpu_ptl = -1; /* auto */ DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, "DRM_UT_CORE", "DRM_UT_DRIVER", "DRM_UT_KMS", "DRM_UT_PRIME", "DRM_UT_ATOMIC", "DRM_UT_VBL", "DRM_UT_STATE", "DRM_UT_LEASE", "DRM_UT_DP", "DRM_UT_DRMRES"); struct amdgpu_mgpu_info mgpu_info = { .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), }; int amdgpu_ras_enable = -1; uint amdgpu_ras_mask = 0xffffffff; int amdgpu_bad_page_threshold = -1; struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { .timeout_fatal_disable = false, .period = 0x0, /* default to 0x0 (timeout disable) */ }; /** * DOC: vramlimit (int) * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). */ MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); /** * DOC: vis_vramlimit (int) * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). */ MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); /** * DOC: gartsize (uint) * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. * The default is -1 (The size depends on asic). */ MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); module_param_named(gartsize, amdgpu_gart_size, uint, 0600); /** * DOC: gttsize (int) * Restrict the size of GTT domain (for userspace use) in MiB for testing. * The default is -1 (Use value specified by TTM). * This parameter is deprecated and will be removed in the future. */ MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); module_param_named(gttsize, amdgpu_gtt_size, int, 0600); /** * DOC: moverate (int) * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). */ MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); module_param_named(moverate, amdgpu_moverate, int, 0600); /** * DOC: audio (int) * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. */ MODULE_PARM_DESC(audio, "HDMI/DP Audio enable for non DC displays (-1 = auto, 0 = disable, 1 = enable)"); module_param_named(audio, amdgpu_audio, int, 0444); /** * DOC: disp_priority (int) * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). */ MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); /** * DOC: hw_i2c (int) * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). */ MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); /** * DOC: pcie_gen2 (int) * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). */ MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); /** * DOC: msi (int) * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). */ MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); module_param_named(msi, amdgpu_msi, int, 0444); /** * DOC: svm_default_granularity (uint) * Used in buffer migration and handling of recoverable page faults */ MODULE_PARM_DESC(svm_default_granularity, "SVM's default granularity in log(2^Pages), default 9 = 2^9 = 2 MiB"); module_param_named(svm_default_granularity, amdgpu_svm_default_granularity, uint, 0644); /** * DOC: lockup_timeout (string) * Set GPU scheduler timeout value in ms. * * The format can be [single value] for setting all timeouts at once or * [GFX,Compute,SDMA,Video] to set individual timeouts. * Negative values mean infinity. * * By default(with no lockup_timeout settings), the timeout for all queues is 2000. */ MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: 2000. 0: keep default value. negative: infinity timeout), format: [single value for all] or [GFX,Compute,SDMA,Video]."); module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); /** * DOC: dpm (int) * Override for dynamic power management setting * (0 = disable, 1 = enable) * The default is -1 (auto). */ MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); module_param_named(dpm, amdgpu_dpm, int, 0444); /** * DOC: fw_load_type (int) * Set different firmware loading type for debugging, if supported. * Set to 0 to force direct loading if supported by the ASIC. Set * to -1 to select the default loading mode for the ASIC, as defined * by the driver. The default is -1 (auto). */ MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); /** * DOC: aspm (int) * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). */ MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); module_param_named(aspm, amdgpu_aspm, int, 0444); /** * DOC: runpm (int) * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down * the dGPUs when they are idle if supported. The default is -1 (auto enable). * Setting the value to 0 disables this functionality. * Setting the value to -2 is auto enabled with power down when displays are attached. */ MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)"); module_param_named(runpm, amdgpu_runtime_pm, int, 0444); /** * DOC: ip_block_mask (uint) * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). */ MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); module_param_named_unsafe(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); /** * DOC: bapm (int) * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. * The default -1 (auto, enabled) */ MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); module_param_named(bapm, amdgpu_bapm, int, 0444); /** * DOC: deep_color (int) * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). */ MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); module_param_named(deep_color, amdgpu_deep_color, int, 0444); /** * DOC: vm_size (int) * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). */ MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); module_param_named(vm_size, amdgpu_vm_size, int, 0444); /** * DOC: vm_fragment_size (int) * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). */ MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); /** * DOC: vm_block_size (int) * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). */ MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); /** * DOC: vm_fault_stop (int) * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). */ MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); /** * DOC: vm_update_mode (int) * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). */ MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); /** * DOC: exp_hw_support (int) * Enable experimental hw support (1 = enable). The default is 0 (disabled). */ MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); module_param_named_unsafe(exp_hw_support, amdgpu_exp_hw_support, int, 0444); /** * DOC: dc (int) * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). */ MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); module_param_named(dc, amdgpu_dc, int, 0444); /** * DOC: sched_jobs (int) * Override the max number of jobs supported in the sw queue. The default is 32. */ MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); /** * DOC: sched_hw_submission (int) * Override the max number of HW submissions. The default is 2. */ MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); /** * DOC: ppfeaturemask (hexint) * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. * The default is the current set of stable power features. */ MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444);