/* * Copyright 2008 Advanced Micro Devices, Inc. * Copyright 2008 Red Hat Inc. * Copyright 2009 Jerome Glisse. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Dave Airlie * Alex Deucher * Jerome Glisse */ #include "amdgpu.h"#include <drm/amdgpu_drm.h>#include <drm/drm_drv.h>#include <drm/drm_fb_helper.h>#include "amdgpu_uvd.h"#include "amdgpu_vce.h"#include "atom.h" #include <linux/vga_switcheroo.h>#include <linux/slab.h>#include <linux/uaccess.h>#include <linux/pci.h>#include <linux/pm_runtime.h>#include "amdgpu_amdkfd.h"#include "amdgpu_gem.h"#include "amdgpu_display.h"#include "amdgpu_ras.h"#include "amdgpu_reset.h"#include "amd_pcie.h"#include "amdgpu_userq.h"#include "amdgpu_video_codecs.h" void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev){ struct amdgpu_gpu_instance *gpu_instance; int i; mutex_lock(&mgpu_info.mutex); for (i = 0; i < mgpu_info.num_gpu; i++) { gpu_instance = &(mgpu_info.gpu_ins[i]); if (gpu_instance->adev == adev) { mgpu_info.gpu_ins[i] = mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; mgpu_info.num_gpu--; if (adev->flags & AMD_IS_APU) mgpu_info.num_apu--; else mgpu_info.num_dgpu--; break; } } mutex_unlock(&mgpu_info.mutex);} /** * amdgpu_driver_unload_kms - Main unload function for KMS. * * @dev: drm dev pointer * * This is the main unload function for KMS (all asics). * Returns 0 on success. */void amdgpu_driver_unload_kms(struct drm_device *dev){ struct amdgpu_device *adev = drm_to_adev(dev); if (adev == NULL || !adev->num_ip_blocks) return; amdgpu_unregister_gpu_instance(adev); if (adev->rmmio == NULL) return; if (amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DRV_UNLOAD)) drm_warn(dev, "smart shift update failed\n"); amdgpu_acpi_fini(adev); amdgpu_device_fini_hw(adev);} void amdgpu_register_gpu_instance(struct amdgpu_device *adev){ struct amdgpu_gpu_instance *gpu_instance; mutex_lock(&mgpu_info.mutex); if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { drm_err(adev_to_drm(adev), "Cannot register more gpu instance\n"); mutex_unlock(&mgpu_info.mutex); return; } gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); gpu_instance->adev = adev; gpu_instance->mgpu_fan_enabled = 0; mgpu_info.num_gpu++; if (adev->flags & AMD_IS_APU) mgpu_info.num_apu++; else mgpu_info.num_dgpu++; mutex_unlock(&mgpu_info.mutex);} /** * amdgpu_driver_load_kms - Main load function for KMS. * * @adev: pointer to struct amdgpu_device * @flags: device flags * * This is the main load function for KMS (all asics). * Returns 0 on success, error on failure. */int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags){ struct drm_device *dev; int r, acpi_status; dev = adev_to_drm(adev); /* amdgpu_device_init should report only fatal error * like memory allocation failure or iomapping failure, * or memory manager initialization failure, it must * properly initialize the GPU MC controller and permit * VRAM allocation */ r = amdgpu_device_init(adev, flags); if (r) { dev_err(dev->dev, "Fatal error during GPU init\n"); goto out; } amdgpu_device_detect_runtime_pm_mode(adev); /* Call ACPI methods: require modeset init * but failure is not fatal */ acpi_status = amdgpu_acpi_init(adev); if (acpi_status) dev_dbg(dev->dev, "Error during ACPI methods call\n"); if (amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DRV_LOAD)) drm_warn(dev, "smart shift update failed\n"); out: if (r) amdgpu_driver_unload_kms(dev); return r;} static enum amd_ip_block_type amdgpu_ip_get_block_type(struct amdgpu_device *adev, uint32_t ip){ enum amd_ip_block_type type; switch (ip) { case AMDGPU_HW_IP_GFX: type = AMD_IP_BLOCK_TYPE_GFX; break; case AMDGPU_HW_IP_COMPUTE: type = AMD_IP_BLOCK_TYPE_GFX; break; case AMDGPU_HW_IP_DMA: type = AMD_IP_BLOCK_TYPE_SDMA; break; case AMDGPU_HW_IP_UVD: case AMDGPU_HW_IP_UVD_ENC: type = AMD_IP_BLOCK_TYPE_UVD; break; case AMDGPU_HW_IP_VCE: type = AMD_IP_BLOCK_TYPE_VCE; break; case AMDGPU_HW_IP_VCN_DEC: case AMDGPU_HW_IP_VCN_ENC: type = AMD_IP_BLOCK_TYPE_VCN; break; case AMDGPU_HW_IP_VCN_JPEG: type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; break; case AMDGPU_HW_IP_VPE: type = AMD_IP_BLOCK_TYPE_VPE; break; default: type = AMD_IP_BLOCK_TYPE_NUM; break; } return type;} static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, struct drm_amdgpu_query_fw *query_fw, struct amdgpu_device *adev){ switch (query_fw->fw_type) { case AMDGPU_INFO_FW_VCE: fw_info->ver = adev->vce.fw_version; fw_info->feature = adev->vce.fb_version; break; case AMDGPU_INFO_FW_UVD: fw_info->ver = adev->uvd.fw_version; fw_info->feature = 0; break; case AMDGPU_INFO_FW_VCN: fw_info->ver = adev->vcn.fw_version; fw_info->feature = 0; break; case AMDGPU_INFO_FW_GMC: fw_info->ver = adev->gmc.fw_version; fw_info->feature = 0; break; case AMDGPU_INFO_FW_GFX_ME: fw_info->ver = adev->gfx.me_fw_version; fw_info->feature = adev->gfx.me_feature_version; break; case AMDGPU_INFO_FW_GFX_PFP: fw_info->ver = adev->gfx.pfp_fw_version; fw_info->feature = adev->gfx.pfp_feature_version; break; case AMDGPU_INFO_FW_GFX_CE: fw_info->ver = adev->gfx.ce_fw_version; fw_info->feature = adev->gfx.ce_feature_version; break; case AMDGPU_INFO_FW_GFX_RLC: fw_info->ver = adev->gfx.rlc_fw_version; fw_info->feature = adev->gfx.rlc_feature_version; break; case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: fw_info->ver = adev->gfx.rlc_srlc_fw_version; fw_info->feature = adev->gfx.rlc_srlc_feature_version; break; case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: fw_info->ver = adev->gfx.rlc_srlg_fw_version; fw_info->feature = adev->gfx.rlc_srlg_feature_version; break; case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: fw_info->ver = adev->gfx.rlc_srls_fw_version; fw_info->feature = adev->gfx.rlc_srls_feature_version; break; case AMDGPU_INFO_FW_GFX_RLCP: fw_info->ver = adev->gfx.rlcp_ucode_version; fw_info->feature = adev->gfx.rlcp_ucode_feature_version; break; case AMDGPU_INFO_FW_GFX_RLCV: fw_info->ver = adev->gfx.rlcv_ucode_version; fw_info->feature = adev->gfx.rlcv_ucode_feature_version; break; case AMDGPU_INFO_FW_GFX_MEC: if (query_fw->index == 0) { fw_info->ver = adev->gfx.mec_fw_version; fw_info->feature = adev->gfx.mec_feature_version; } else if (query_fw->index == 1) { fw_info->ver = adev->gfx.mec2_fw_version; fw_info->feature = adev->gfx.mec2_feature_version; } else return -EINVAL; break; case AMDGPU_INFO_FW_SMC: fw_info->ver = adev->pm.fw_version; fw_info->feature = 0; break; case AMDGPU_INFO_FW_TA: switch (query_fw->index) { case TA_FW_TYPE_PSP_XGMI: fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version; fw_info->feature = adev->psp.xgmi_context.context .bin_desc.feature_version; break; case TA_FW_TYPE_PSP_RAS: fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version; fw_info->feature = adev->psp.ras_context.context .bin_desc.feature_version; break; case TA_FW_TYPE_PSP_HDCP: fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version; fw_info->feature = adev->psp.hdcp_context.context .bin_desc.feature_version; break; case TA_FW_TYPE_PSP_DTM: fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version; fw_info->feature = adev->psp.dtm_context.context .bin_desc.feature_version; break; case TA_FW_TYPE_PSP_RAP: fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version; fw_info->feature = adev->psp.rap_context.context .bin_desc.feature_version; break; case TA_FW_TYPE_PSP_SECUREDISPLAY: fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version; fw_info->feature = adev->psp.securedisplay_context.context.bin_desc .feature_version; break; default: return -EINVAL; } break; case AMDGPU_INFO_FW_SDMA: if (query_fw->index >= adev->sdma.num_instances) return -EINVAL; fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; break; case AMDGPU_INFO_FW_SOS: fw_info->ver = adev->psp.sos.fw_version; fw_info->feature = adev->psp.sos.feature_version; break; case AMDGPU_INFO_FW_ASD: fw_info->ver = adev->psp.asd_context.bin_desc.fw_version; fw_info->feature = adev->psp.asd_context.bin_desc.feature_version; break; case AMDGPU_INFO_FW_DMCU: fw_info->ver = adev->dm.dmcu_fw_version; fw_info->feature = 0; break; case AMDGPU_INFO_FW_DMCUB: fw_info->ver = adev->dm.dmcub_fw_version; fw_info->feature = 0; break; case AMDGPU_INFO_FW_TOC: fw_info->ver = adev->psp.toc.fw_version; fw_info->feature = adev->psp.toc.feature_version; break; case AMDGPU_INFO_FW_CAP: fw_info->ver = adev->psp.cap_fw_version; fw_info->feature = adev->psp.cap_feature_version; break; case AMDGPU_INFO_FW_MES_KIQ: fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK; fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK) >> AMDGPU_MES_FEAT_VERSION_SHIFT; break; case AMDGPU_INFO_FW_MES: fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK) >> AMDGPU_MES_FEAT_VERSION_SHIFT; break; case AMDGPU_INFO_FW_IMU: fw_info->ver = adev->gfx.imu_fw_version; fw_info->feature = 0; break; case AMDGPU_INFO_FW_VPE: fw_info->ver = adev->vpe.fw_version; fw_info->feature = adev->vpe.feature_version; break; default: return -EINVAL; } return 0;} static int amdgpu_userq_metadata_info_gfx(struct amdgpu_device *adev, struct drm_amdgpu_info *info, struct drm_amdgpu_info_uq_metadata_gfx *meta){ int ret = -EOPNOTSUPP; if (adev->gfx.funcs->get_gfx_shadow_info) { struct amdgpu_gfx_shadow_info shadow = {}; adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow, true); meta->shadow_size = shadow.shadow_size; meta->shadow_alignment = shadow.shadow_alignment; meta->csa_size = shadow.csa_size; meta->csa_alignment = shadow.csa_alignment; ret = 0; } return ret;} static int amdgpu_userq_metadata_info_compute(struct amdgpu_device *adev, struct drm_amdgpu_info *info, struct drm_amdgpu_info_uq_metadata_compute *meta){ int ret = -EOPNOTSUPP; if (adev->gfx.funcs->get_gfx_shadow_info) { struct amdgpu_gfx_shadow_info shadow = {}; adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow, true); meta->eop_size = shadow.eop_size; meta->eop_alignment = shadow.eop_alignment; ret = 0; } return ret;} static int amdgpu_userq_metadata_info_sdma(struct amdgpu_device *adev, struct drm_amdgpu_info *info, struct drm_amdgpu_info_uq_metadata_sdma *meta){ int ret = -EOPNOTSUPP; if (adev->sdma.get_csa_info) { struct amdgpu_sdma_csa_info csa = {}; adev->sdma.get_csa_info(adev, &csa); meta->csa_size = csa.size; meta->csa_alignment = csa.alignment; ret = 0; } return ret;} static int amdgpu_hw_ip_info(struct amdgpu_device *adev, struct drm_amdgpu_info *info, struct drm_amdgpu_info_hw_ip *result){ uint32_t ib_start_alignment = 0; uint32_t ib_size_alignment = 0; enum amd_ip_block_type type; unsigned int num_rings = 0; uint32_t num_slots = 0; unsigned int i, j; if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) return -EINVAL; switch (info->query_hw_ip.type) { case AMDGPU_HW_IP_GFX: type = AMD_IP_BLOCK_TYPE_GFX; for (i = 0; i < adev->gfx.num_gfx_rings; i++) if (adev->gfx.gfx_ring[i].sched.ready && !adev->gfx.gfx_ring[i].no_user_submission) ++num_rings; if (!adev->gfx.disable_uq) { for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++) num_slots += hweight32(adev->mes.gfx_hqd_mask[i]); } ib_start_alignment = 32; ib_size_alignment = 32; break; case AMDGPU_HW_IP_COMPUTE: type = AMD_IP_BLOCK_TYPE_GFX; for (i = 0; i < adev->gfx.num_compute_rings; i++) if (adev->gfx.compute_ring[i].sched.ready && !adev->gfx.compute_ring[i].no_user_submission) ++num_rings; if (!adev->sdma.disable_uq) { for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) num_slots += hweight32(adev->mes.compute_hqd_mask[i]); } ib_start_alignment = 32; ib_size_alignment = 32; break; case AMDGPU_HW_IP_DMA: type = AMD_IP_BLOCK_TYPE_SDMA; for (i = 0; i < adev->sdma.num_instances; i++) if (adev->sdma.instance[i].ring.sched.ready && !adev->sdma.instance[i].ring.no_user_submission) ++num_rings; if (!adev->gfx.disable_uq) { for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) num_slots += hweight32(adev->mes.sdma_hqd_mask[i]); } ib_start_alignment = 256; ib_size_alignment = 4; break; case AMDGPU_HW_IP_UVD: type = AMD_IP_BLOCK_TYPE_UVD; for (i = 0; i < adev->uvd.num_uvd_inst; i++) { if (adev->uvd.harvest_config & (1 << i)) continue; if (adev->uvd.inst[i].ring.sched.ready &&Lines 1–500 of 2031. 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/* * Copyright 2008 Advanced Micro Devices, Inc. * Copyright 2008 Red Hat Inc. * Copyright 2009 Jerome Glisse. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Dave Airlie * Alex Deucher * Jerome Glisse */ #include "amdgpu.h" #include <drm/amdgpu_drm.h> #include <drm/drm_drv.h> #include <drm/drm_fb_helper.h> #include "amdgpu_uvd.h" #include "amdgpu_vce.h" #include "atom.h" #include <linux/vga_switcheroo.h> #include <linux/slab.h> #include <linux/uaccess.h> #include <linux/pci.h> #include <linux/pm_runtime.h> #include "amdgpu_amdkfd.h" #include "amdgpu_gem.h" #include "amdgpu_display.h" #include "amdgpu_ras.h" #include "amdgpu_reset.h" #include "amd_pcie.h" #include "amdgpu_userq.h" #include "amdgpu_video_codecs.h" void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) { struct amdgpu_gpu_instance *gpu_instance; int i; mutex_lock(&mgpu_info.mutex); for (i = 0; i < mgpu_info.num_gpu; i++) { gpu_instance = &(mgpu_info.gpu_ins[i]); if (gpu_instance->adev == adev) { mgpu_info.gpu_ins[i] = mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; mgpu_info.num_gpu--; if (adev->flags & AMD_IS_APU) mgpu_info.num_apu--; else mgpu_info.num_dgpu--; break; } } mutex_unlock(&mgpu_info.mutex); } /** * amdgpu_driver_unload_kms - Main unload function for KMS. * * @dev: drm dev pointer * * This is the main unload function for KMS (all asics). * Returns 0 on success. */ void amdgpu_driver_unload_kms(struct drm_device *dev) { struct amdgpu_device *adev = drm_to_adev(dev); if (adev == NULL || !adev->num_ip_blocks) return; amdgpu_unregister_gpu_instance(adev); if (adev->rmmio == NULL) return; if (amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DRV_UNLOAD)) drm_warn(dev, "smart shift update failed\n"); amdgpu_acpi_fini(adev); amdgpu_device_fini_hw(adev); } void amdgpu_register_gpu_instance(struct amdgpu_device *adev) { struct amdgpu_gpu_instance *gpu_instance; mutex_lock(&mgpu_info.mutex); if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { drm_err(adev_to_drm(adev), "Cannot register more gpu instance\n"); mutex_unlock(&mgpu_info.mutex); return; } gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); gpu_instance->adev = adev; gpu_instance->mgpu_fan_enabled = 0; mgpu_info.num_gpu++; if (adev->flags & AMD_IS_APU) mgpu_info.num_apu++; else mgpu_info.num_dgpu++; mutex_unlock(&mgpu_info.mutex); } /** * amdgpu_driver_load_kms - Main load function for KMS. * * @adev: pointer to struct amdgpu_device * @flags: device flags * * This is the main load function for KMS (all asics). * Returns 0 on success, error on failure. */ int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) { struct drm_device *dev; int r, acpi_status; dev = adev_to_drm(adev); /* amdgpu_device_init should report only fatal error * like memory allocation failure or iomapping failure, * or memory manager initialization failure, it must * properly initialize the GPU MC controller and permit * VRAM allocation */ r = amdgpu_device_init(adev, flags); if (r) { dev_err(dev->dev, "Fatal error during GPU init\n"); goto out; } amdgpu_device_detect_runtime_pm_mode(adev); /* Call ACPI methods: require modeset init * but failure is not fatal */ acpi_status = amdgpu_acpi_init(adev); if (acpi_status) dev_dbg(dev->dev, "Error during ACPI methods call\n"); if (amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DRV_LOAD)) drm_warn(dev, "smart shift update failed\n"); out: if (r) amdgpu_driver_unload_kms(dev); return r; } static enum amd_ip_block_type amdgpu_ip_get_block_type(struct amdgpu_device *adev, uint32_t ip) { enum amd_ip_block_type type; switch (ip) { case AMDGPU_HW_IP_GFX: type = AMD_IP_BLOCK_TYPE_GFX; break; case AMDGPU_HW_IP_COMPUTE: type = AMD_IP_BLOCK_TYPE_GFX; break; case AMDGPU_HW_IP_DMA: type = AMD_IP_BLOCK_TYPE_SDMA; break; case AMDGPU_HW_IP_UVD: case AMDGPU_HW_IP_UVD_ENC: type = AMD_IP_BLOCK_TYPE_UVD; break; case AMDGPU_HW_IP_VCE: type = AMD_IP_BLOCK_TYPE_VCE; break; case AMDGPU_HW_IP_VCN_DEC: case AMDGPU_HW_IP_VCN_ENC: type = AMD_IP_BLOCK_TYPE_VCN; break; case AMDGPU_HW_IP_VCN_JPEG: type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; break; case AMDGPU_HW_IP_VPE: type = AMD_IP_BLOCK_TYPE_VPE; break; default: type = AMD_IP_BLOCK_TYPE_NUM; break; } return type; } static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, struct drm_amdgpu_query_fw *query_fw, struct amdgpu_device *adev) { switch (query_fw->fw_type) { case AMDGPU_INFO_FW_VCE: fw_info->ver = adev->vce.fw_version; fw_info->feature = adev->vce.fb_version; break; case AMDGPU_INFO_FW_UVD: fw_info->ver = adev->uvd.fw_version; fw_info->feature = 0; break; case AMDGPU_INFO_FW_VCN: fw_info->ver = adev->vcn.fw_version; fw_info->feature = 0; break; case AMDGPU_INFO_FW_GMC: fw_info->ver = adev->gmc.fw_version; fw_info->feature = 0; break; case AMDGPU_INFO_FW_GFX_ME: fw_info->ver = adev->gfx.me_fw_version; fw_info->feature = adev->gfx.me_feature_version; break; case AMDGPU_INFO_FW_GFX_PFP: fw_info->ver = adev->gfx.pfp_fw_version; fw_info->feature = adev->gfx.pfp_feature_version; break; case AMDGPU_INFO_FW_GFX_CE: fw_info->ver = adev->gfx.ce_fw_version; fw_info->feature = adev->gfx.ce_feature_version; break; case AMDGPU_INFO_FW_GFX_RLC: fw_info->ver = adev->gfx.rlc_fw_version; fw_info->feature = adev->gfx.rlc_feature_version; break; case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: fw_info->ver = adev->gfx.rlc_srlc_fw_version; fw_info->feature = adev->gfx.rlc_srlc_feature_version; break; case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: fw_info->ver = adev->gfx.rlc_srlg_fw_version; fw_info->feature = adev->gfx.rlc_srlg_feature_version; break; case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: fw_info->ver = adev->gfx.rlc_srls_fw_version; fw_info->feature = adev->gfx.rlc_srls_feature_version; break; case AMDGPU_INFO_FW_GFX_RLCP: fw_info->ver = adev->gfx.rlcp_ucode_version; fw_info->feature = adev->gfx.rlcp_ucode_feature_version; break; case AMDGPU_INFO_FW_GFX_RLCV: fw_info->ver = adev->gfx.rlcv_ucode_version; fw_info->feature = adev->gfx.rlcv_ucode_feature_version; break; case AMDGPU_INFO_FW_GFX_MEC: if (query_fw->index == 0) { fw_info->ver = adev->gfx.mec_fw_version; fw_info->feature = adev->gfx.mec_feature_version; } else if (query_fw->index == 1) { fw_info->ver = adev->gfx.mec2_fw_version; fw_info->feature = adev->gfx.mec2_feature_version; } else return -EINVAL; break; case AMDGPU_INFO_FW_SMC: fw_info->ver = adev->pm.fw_version; fw_info->feature = 0; break; case AMDGPU_INFO_FW_TA: switch (query_fw->index) { case TA_FW_TYPE_PSP_XGMI: fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version; fw_info->feature = adev->psp.xgmi_context.context .bin_desc.feature_version; break; case TA_FW_TYPE_PSP_RAS: fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version; fw_info->feature = adev->psp.ras_context.context .bin_desc.feature_version; break; case TA_FW_TYPE_PSP_HDCP: fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version; fw_info->feature = adev->psp.hdcp_context.context .bin_desc.feature_version; break; case TA_FW_TYPE_PSP_DTM: fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version; fw_info->feature = adev->psp.dtm_context.context .bin_desc.feature_version; break; case TA_FW_TYPE_PSP_RAP: fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version; fw_info->feature = adev->psp.rap_context.context .bin_desc.feature_version; break; case TA_FW_TYPE_PSP_SECUREDISPLAY: fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version; fw_info->feature = adev->psp.securedisplay_context.context.bin_desc .feature_version; break; default: return -EINVAL; } break; case AMDGPU_INFO_FW_SDMA: if (query_fw->index >= adev->sdma.num_instances) return -EINVAL; fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; break; case AMDGPU_INFO_FW_SOS: fw_info->ver = adev->psp.sos.fw_version; fw_info->feature = adev->psp.sos.feature_version; break; case AMDGPU_INFO_FW_ASD: fw_info->ver = adev->psp.asd_context.bin_desc.fw_version; fw_info->feature = adev->psp.asd_context.bin_desc.feature_version; break; case AMDGPU_INFO_FW_DMCU: fw_info->ver = adev->dm.dmcu_fw_version; fw_info->feature = 0; break; case AMDGPU_INFO_FW_DMCUB: fw_info->ver = adev->dm.dmcub_fw_version; fw_info->feature = 0; break; case AMDGPU_INFO_FW_TOC: fw_info->ver = adev->psp.toc.fw_version; fw_info->feature = adev->psp.toc.feature_version; break; case AMDGPU_INFO_FW_CAP: fw_info->ver = adev->psp.cap_fw_version; fw_info->feature = adev->psp.cap_feature_version; break; case AMDGPU_INFO_FW_MES_KIQ: fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK; fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK) >> AMDGPU_MES_FEAT_VERSION_SHIFT; break; case AMDGPU_INFO_FW_MES: fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK) >> AMDGPU_MES_FEAT_VERSION_SHIFT; break; case AMDGPU_INFO_FW_IMU: fw_info->ver = adev->gfx.imu_fw_version; fw_info->feature = 0; break; case AMDGPU_INFO_FW_VPE: fw_info->ver = adev->vpe.fw_version; fw_info->feature = adev->vpe.feature_version; break; default: return -EINVAL; } return 0; } static int amdgpu_userq_metadata_info_gfx(struct amdgpu_device *adev, struct drm_amdgpu_info *info, struct drm_amdgpu_info_uq_metadata_gfx *meta) { int ret = -EOPNOTSUPP; if (adev->gfx.funcs->get_gfx_shadow_info) { struct amdgpu_gfx_shadow_info shadow = {}; adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow, true); meta->shadow_size = shadow.shadow_size; meta->shadow_alignment = shadow.shadow_alignment; meta->csa_size = shadow.csa_size; meta->csa_alignment = shadow.csa_alignment; ret = 0; } return ret; } static int amdgpu_userq_metadata_info_compute(struct amdgpu_device *adev, struct drm_amdgpu_info *info, struct drm_amdgpu_info_uq_metadata_compute *meta) { int ret = -EOPNOTSUPP; if (adev->gfx.funcs->get_gfx_shadow_info) { struct amdgpu_gfx_shadow_info shadow = {}; adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow, true); meta->eop_size = shadow.eop_size; meta->eop_alignment = shadow.eop_alignment; ret = 0; } return ret; } static int amdgpu_userq_metadata_info_sdma(struct amdgpu_device *adev, struct drm_amdgpu_info *info, struct drm_amdgpu_info_uq_metadata_sdma *meta) { int ret = -EOPNOTSUPP; if (adev->sdma.get_csa_info) { struct amdgpu_sdma_csa_info csa = {}; adev->sdma.get_csa_info(adev, &csa); meta->csa_size = csa.size; meta->csa_alignment = csa.alignment; ret = 0; } return ret; } static int amdgpu_hw_ip_info(struct amdgpu_device *adev, struct drm_amdgpu_info *info, struct drm_amdgpu_info_hw_ip *result) { uint32_t ib_start_alignment = 0; uint32_t ib_size_alignment = 0; enum amd_ip_block_type type; unsigned int num_rings = 0; uint32_t num_slots = 0; unsigned int i, j; if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) return -EINVAL; switch (info->query_hw_ip.type) { case AMDGPU_HW_IP_GFX: type = AMD_IP_BLOCK_TYPE_GFX; for (i = 0; i < adev->gfx.num_gfx_rings; i++) if (adev->gfx.gfx_ring[i].sched.ready && !adev->gfx.gfx_ring[i].no_user_submission) ++num_rings; if (!adev->gfx.disable_uq) { for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++) num_slots += hweight32(adev->mes.gfx_hqd_mask[i]); } ib_start_alignment = 32; ib_size_alignment = 32; break; case AMDGPU_HW_IP_COMPUTE: type = AMD_IP_BLOCK_TYPE_GFX; for (i = 0; i < adev->gfx.num_compute_rings; i++) if (adev->gfx.compute_ring[i].sched.ready && !adev->gfx.compute_ring[i].no_user_submission) ++num_rings; if (!adev->sdma.disable_uq) { for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) num_slots += hweight32(adev->mes.compute_hqd_mask[i]); } ib_start_alignment = 32; ib_size_alignment = 32; break; case AMDGPU_HW_IP_DMA: type = AMD_IP_BLOCK_TYPE_SDMA; for (i = 0; i < adev->sdma.num_instances; i++) if (adev->sdma.instance[i].ring.sched.ready && !adev->sdma.instance[i].ring.no_user_submission) ++num_rings; if (!adev->gfx.disable_uq) { for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) num_slots += hweight32(adev->mes.sdma_hqd_mask[i]); } ib_start_alignment = 256; ib_size_alignment = 4; break; case AMDGPU_HW_IP_UVD: type = AMD_IP_BLOCK_TYPE_UVD; for (i = 0; i < adev->uvd.num_uvd_inst; i++) { if (adev->uvd.harvest_config & (1 << i)) continue; if (adev->uvd.inst[i].ring.sched.ready &&