/* * Copyright (C) 2021  Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */#ifndef __AMDGPU_MCA_H__#define __AMDGPU_MCA_H__ #include "amdgpu_ras.h" enum amdgpu_mca_error_type {	AMDGPU_MCA_ERROR_TYPE_UE = 0,	AMDGPU_MCA_ERROR_TYPE_CE,}; struct amdgpu_mca_ras_block {	struct amdgpu_ras_block_object ras_block;}; struct amdgpu_mca_ras {	struct ras_common_if *ras_if;	struct amdgpu_mca_ras_block *ras;}; struct amdgpu_mca {	struct amdgpu_mca_ras mp0;	struct amdgpu_mca_ras mp1;	struct amdgpu_mca_ras mpio;}; void amdgpu_mca_query_correctable_error_count(struct amdgpu_device *adev,					      uint64_t mc_status_addr,					      unsigned long *error_count);void amdgpu_mca_query_uncorrectable_error_count(struct amdgpu_device *adev,						uint64_t mc_status_addr,						unsigned long *error_count);void amdgpu_mca_reset_error_count(struct amdgpu_device *adev,				  uint64_t mc_status_addr);void amdgpu_mca_query_ras_error_count(struct amdgpu_device *adev,				      uint64_t mc_status_addr,				      void *ras_error_status);int amdgpu_mca_mp0_ras_sw_init(struct amdgpu_device *adev);int amdgpu_mca_mp1_ras_sw_init(struct amdgpu_device *adev);int amdgpu_mca_mpio_ras_sw_init(struct amdgpu_device *adev); #endif