/* * Copyright 2009 Jerome Glisse. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE * USE OR OTHER DEALINGS IN THE SOFTWARE. * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * *//* * Authors: *    Jerome Glisse <glisse@freedesktop.org> *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> *    Dave Airlie */ #include <linux/dma-mapping.h>#include <linux/iommu.h>#include <linux/pagemap.h>#include <linux/sched/task.h>#include <linux/sched/mm.h>#include <linux/seq_file.h>#include <linux/slab.h>#include <linux/swap.h>#include <linux/dma-buf.h>#include <linux/sizes.h>#include <linux/module.h> #include <drm/drm_drv.h>#include <drm/ttm/ttm_bo.h>#include <drm/ttm/ttm_placement.h>#include <drm/ttm/ttm_range_manager.h>#include <drm/ttm/ttm_tt.h> #include <drm/amdgpu_drm.h> #include "amdgpu.h"#include "amdgpu_object.h"#include "amdgpu_trace.h"#include "amdgpu_amdkfd.h"#include "amdgpu_sdma.h"#include "amdgpu_ras.h"#include "amdgpu_hmm.h"#include "amdgpu_atomfirmware.h"#include "amdgpu_res_cursor.h"#include "bif/bif_4_1_d.h"#include "kfd_svm.h" MODULE_IMPORT_NS("DMA_BUF"); #define AMDGPU_TTM_VRAM_MAX_DW_READ	((size_t)128) static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,				   struct ttm_tt *ttm,				   struct ttm_resource *bo_mem);static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,				      struct ttm_tt *ttm); static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,				    unsigned int type,				    uint64_t size_in_page){	if (!size_in_page)		return 0; 	return ttm_range_man_init(&adev->mman.bdev, type,				  false, size_in_page);} /** * amdgpu_evict_flags - Compute placement flags * * @bo: The buffer object to evict * @placement: Possible destination(s) for evicted BO * * Fill in placement data when ttm_bo_evict() is called */static void amdgpu_evict_flags(struct ttm_buffer_object *bo,				struct ttm_placement *placement){	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);	struct amdgpu_bo *abo;	static const struct ttm_place placements = {		.fpfn = 0,		.lpfn = 0,		.mem_type = TTM_PL_SYSTEM,		.flags = 0	}; 	/* Don't handle scatter gather BOs */	if (bo->type == ttm_bo_type_sg) {		placement->num_placement = 0;		return;	} 	/* Object isn't an AMDGPU object so ignore */	if (!amdgpu_bo_is_amdgpu_bo(bo)) {		placement->placement = &placements;		placement->num_placement = 1;		return;	} 	abo = ttm_to_amdgpu_bo(bo);	if (abo->flags & AMDGPU_GEM_CREATE_DISCARDABLE) {		placement->num_placement = 0;		return;	} 	switch (bo->resource->mem_type) {	case AMDGPU_PL_GDS:	case AMDGPU_PL_GWS:	case AMDGPU_PL_OA:	case AMDGPU_PL_DOORBELL:	case AMDGPU_PL_MMIO_REMAP:		placement->num_placement = 0;		return; 	case TTM_PL_VRAM:		if (!adev->mman.buffer_funcs_enabled) {			/* Move to system memory */			amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 		} else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&			   !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&			   amdgpu_res_cpu_visible(adev, bo->resource)) { 			/* Try evicting to the CPU inaccessible part of VRAM			 * first, but only set GTT as busy placement, so this			 * BO will be evicted to GTT rather than causing other			 * BOs to be evicted from VRAM			 */			amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |							AMDGPU_GEM_DOMAIN_GTT |							AMDGPU_GEM_DOMAIN_CPU);			abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;			abo->placements[0].lpfn = 0;			abo->placements[0].flags |= TTM_PL_FLAG_DESIRED;		} else {			/* Move to GTT memory */			amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT |							AMDGPU_GEM_DOMAIN_CPU);		}		break;	case TTM_PL_TT:	case AMDGPU_PL_PREEMPT:	default:		amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);		break;	}	*placement = abo->placement;} static struct dma_fence *amdgpu_ttm_job_submit(struct amdgpu_device *adev, struct amdgpu_ttm_buffer_entity *entity,		      struct amdgpu_job *job, u32 num_dw){	struct amdgpu_ring *ring; 	ring = to_amdgpu_ring(adev->mman.buffer_funcs_scheds[0]);	amdgpu_ring_pad_ib(ring, &job->ibs[0]);	WARN_ON(job->ibs[0].length_dw > num_dw); 	lockdep_assert_held(&entity->lock); 	return amdgpu_job_submit(job);} /** * amdgpu_ttm_map_buffer - Map memory into the GART windows * @entity: entity to run the window setup job * @bo: buffer object to map * @mem: memory object to map * @mm_cur: range to map * @window: which GART window to use * @tmz: if we should setup a TMZ enabled mapping * @size: in number of bytes to map, out number of bytes mapped * @addr: resulting address inside the MC address space * * Setup one of the GART windows to access a specific piece of memory or return * the physical address for local memory. */static int amdgpu_ttm_map_buffer(struct amdgpu_ttm_buffer_entity *entity,				 struct ttm_buffer_object *bo,				 struct ttm_resource *mem,				 struct amdgpu_res_cursor *mm_cur,				 unsigned int window,				 bool tmz, uint64_t *size, uint64_t *addr){	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);	unsigned int offset, num_pages, num_dw, num_bytes;	uint64_t src_addr, dst_addr;	struct amdgpu_job *job;	void *cpu_addr;	uint64_t flags;	int r;	const u64 GTT_MAX_PAGES = (AMDGPU_GTT_MAX_TRANSFER_SIZE >> PAGE_SHIFT); 	BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <	       GTT_MAX_PAGES * AMDGPU_GPU_PAGES_IN_CPU_PAGE * 8); 	if (WARN_ON(mem->mem_type == AMDGPU_PL_PREEMPT))		return -EINVAL; 	/* Map only what can't be accessed directly */	if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {		*addr = amdgpu_ttm_domain_start(adev, mem->mem_type) +			mm_cur->start;		return 0;	}  	/*	 * If start begins at an offset inside the page, then adjust the size	 * and addr accordingly	 */	offset = mm_cur->start & ~PAGE_MASK; 	num_pages = PFN_UP(*size + offset);	num_pages = min_t(uint32_t, num_pages, GTT_MAX_PAGES); 	*size = min(*size, (uint64_t)num_pages * PAGE_SIZE - offset); 	*addr = amdgpu_compute_gart_address(&adev->gmc, entity, window);	*addr += offset; 	num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);	num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE; 	r = amdgpu_job_alloc_with_ib(adev, &entity->base,				     AMDGPU_FENCE_OWNER_UNDEFINED,				     num_dw * 4 + num_bytes,				     AMDGPU_IB_POOL_DELAYED,				     AMDGPU_KERNEL_JOB_ID_TTM_MAP_BUFFER,				     &job);	if (r)		return r; 	src_addr = num_dw * 4;	src_addr += job->ibs[0].gpu_addr; 	dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);	dst_addr += (entity->gart_window_offs[window] >> AMDGPU_GPU_PAGE_SHIFT) * 8;	amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,				dst_addr, num_bytes, 0); 	flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);	if (tmz)		flags |= AMDGPU_PTE_TMZ; 	cpu_addr = &job->ibs[0].ptr[num_dw]; 	if (mem->mem_type == TTM_PL_TT) {		dma_addr_t *dma_addr; 		dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT];		amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags, cpu_addr);	} else {		u64 pa = mm_cur->start + adev->vm_manager.vram_base_offset; 		amdgpu_gart_map_vram_range(adev, pa, 0, num_pages, flags, cpu_addr);	} 	dma_fence_put(amdgpu_ttm_job_submit(adev, entity, job, num_dw));	return 0;} /** * amdgpu_ttm_copy_mem_to_mem - Helper function for copy * @adev: amdgpu device * @entity: entity to run the jobs * @src: buffer/address where to read from * @dst: buffer/address where to write to * @size: number of bytes to copy * @tmz: if a secure copy should be used * @resv: resv object to sync to * @f: Returns the last fence if multiple jobs are submitted. * * The function copies @size bytes from {src->mem + src->offset} to * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a * move and different for a BO to BO copy. * */__attribute__((nonnull))static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,				      struct amdgpu_ttm_buffer_entity *entity,				      const struct amdgpu_copy_mem *src,				      const struct amdgpu_copy_mem *dst,				      uint64_t size, bool tmz,				      struct dma_resv *resv,				      struct dma_fence **f){	struct amdgpu_res_cursor src_mm, dst_mm;	struct dma_fence *fence = NULL;	int r = 0;	uint32_t copy_flags = 0;	struct amdgpu_bo *abo_src, *abo_dst; 	if (!adev->mman.buffer_funcs_enabled) {		dev_err(adev->dev,			"Trying to move memory with ring turned off.\n");		return -EINVAL;	} 	amdgpu_res_first(src->mem, src->offset, size, &src_mm);	amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm); 	mutex_lock(&entity->lock);	while (src_mm.remaining) {		uint64_t from, to, cur_size, tiling_flags;		uint32_t num_type, data_format, max_com, write_compress_disable;		struct dma_fence *next; 		/* Never copy more than 256MiB at once to avoid a timeout */		cur_size = min3(src_mm.size, dst_mm.size, 256ULL << 20); 		/* Map src to window 0 and dst to window 1. */		r = amdgpu_ttm_map_buffer(entity, src->bo, src->mem, &src_mm,					  0, tmz, &cur_size, &from);		if (r)			goto error; 		r = amdgpu_ttm_map_buffer(entity, dst->bo, dst->mem, &dst_mm,					  1, tmz, &cur_size, &to);		if (r)			goto error; 		abo_src = ttm_to_amdgpu_bo(src->bo);		abo_dst = ttm_to_amdgpu_bo(dst->bo);		if (tmz)			copy_flags |= AMDGPU_COPY_FLAGS_TMZ;		if ((abo_src->flags & AMDGPU_GEM_CREATE_GFX12_DCC) &&		    (abo_src->tbo.resource->mem_type == TTM_PL_VRAM))			copy_flags |= AMDGPU_COPY_FLAGS_READ_DECOMPRESSED;		if ((abo_dst->flags & AMDGPU_GEM_CREATE_GFX12_DCC) &&		    (dst->mem->mem_type == TTM_PL_VRAM)) {			copy_flags |= AMDGPU_COPY_FLAGS_WRITE_COMPRESSED;			amdgpu_bo_get_tiling_flags(abo_dst, &tiling_flags);			max_com = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK);			num_type = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_NUMBER_TYPE);			data_format = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_DATA_FORMAT);			write_compress_disable =				AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_WRITE_COMPRESS_DISABLE);			copy_flags |= (AMDGPU_COPY_FLAGS_SET(MAX_COMPRESSED, max_com) |				       AMDGPU_COPY_FLAGS_SET(NUMBER_TYPE, num_type) |				       AMDGPU_COPY_FLAGS_SET(DATA_FORMAT, data_format) |				       AMDGPU_COPY_FLAGS_SET(WRITE_COMPRESS_DISABLE,							     write_compress_disable));		} 		r = amdgpu_copy_buffer(adev, entity, from, to, cur_size, resv,				       &next, true, copy_flags);		if (r)			goto error; 		dma_fence_put(fence);		fence = next; 		amdgpu_res_next(&src_mm, cur_size);		amdgpu_res_next(&dst_mm, cur_size);	}error:	mutex_unlock(&entity->lock);	*f = fence;	return r;} /* * amdgpu_move_blit - Copy an entire buffer to another buffer * * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to * help move buffers to and from VRAM. */static int amdgpu_move_blit(struct ttm_buffer_object *bo,			    bool evict,			    struct ttm_resource *new_mem,			    struct ttm_resource *old_mem){	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);	struct amdgpu_ttm_buffer_entity *entity;	struct amdgpu_copy_mem src, dst;	struct dma_fence *fence = NULL;	int r;	u32 e; 	src.bo = bo;	dst.bo = bo;	src.mem = old_mem;	dst.mem = new_mem;	src.offset = 0;	dst.offset = 0; 	e = atomic_inc_return(&adev->mman.next_move_entity) %			      adev->mman.num_move_entities;	entity = &adev->mman.move_entities[e]; 	r = amdgpu_ttm_copy_mem_to_mem(adev,				       entity,				       &src, &dst,				       new_mem->size,				       amdgpu_bo_encrypted(abo),				       bo->base.resv, &fence);	if (r)		goto error; 	/* clear the space being freed */	if (old_mem->mem_type == TTM_PL_VRAM &&	    (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {		struct dma_fence *wipe_fence = NULL;		r = amdgpu_ttm_clear_buffer(entity, abo, NULL, &wipe_fence,					    false, AMDGPU_KERNEL_JOB_ID_MOVE_BLIT);		if (r) {			goto error;		} else if (wipe_fence) {			amdgpu_vram_mgr_set_cleared(bo->resource);			dma_fence_put(fence);			fence = wipe_fence;		}	} 	/* Always block for VM page tables before committing the new location */	if (bo->type == ttm_bo_type_kernel)		r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);	else		r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);	dma_fence_put(fence);	return r; error:	if (fence)		dma_fence_wait(fence, false);	dma_fence_put(fence);	return r;} /** * amdgpu_res_cpu_visible - Check that resource can be accessed by CPU * @adev: amdgpu device * @res: the resource to check * * Returns: true if the full resource is CPU visible, false otherwise. */bool amdgpu_res_cpu_visible(struct amdgpu_device *adev,			    struct ttm_resource *res){	struct amdgpu_res_cursor cursor; 	if (!res)		return false; 	if (res->mem_type == TTM_PL_SYSTEM || res->mem_type == TTM_PL_TT ||	    res->mem_type == AMDGPU_PL_PREEMPT || res->mem_type == AMDGPU_PL_DOORBELL ||	    res->mem_type == AMDGPU_PL_MMIO_REMAP)		return true; 	if (res->mem_type != TTM_PL_VRAM)		return false; 	amdgpu_res_first(res, 0, res->size, &cursor);	while (cursor.remaining) {		if ((cursor.start + cursor.size) > adev->gmc.visible_vram_size)			return false;		amdgpu_res_next(&cursor, cursor.size);	} 	return true;} /* * amdgpu_res_copyable - Check that memory can be accessed by ttm_bo_move_memcpy * * Called by amdgpu_bo_move() */static bool amdgpu_res_copyable(struct amdgpu_device *adev,				struct ttm_resource *mem){	if (!amdgpu_res_cpu_visible(adev, mem))		return false; 	/* ttm_resource_ioremap only supports contiguous memory */	if (mem->mem_type == TTM_PL_VRAM &&	    !(mem->placement & TTM_PL_FLAG_CONTIGUOUS))		return false; 

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