/* * Copyright 2011 Advanced Micro Devices, Inc. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE * USE OR OTHER DEALINGS IN THE SOFTWARE. * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * *//* * Authors: *    Christian König <deathsimple@vodafone.de> */ #include <linux/firmware.h>#include <linux/module.h> #include <drm/drm.h>#include <drm/drm_drv.h> #include "amdgpu.h"#include "amdgpu_pm.h"#include "amdgpu_uvd.h"#include "amdgpu_cs.h"#include "cikd.h"#include "uvd/uvd_4_2_d.h" #include "amdgpu_ras.h" /* 1 second timeout */#define UVD_IDLE_TIMEOUT	msecs_to_jiffies(1000) /* Firmware versions for VI */#define FW_1_65_10	((1 << 24) | (65 << 16) | (10 << 8))#define FW_1_87_11	((1 << 24) | (87 << 16) | (11 << 8))#define FW_1_87_12	((1 << 24) | (87 << 16) | (12 << 8))#define FW_1_37_15	((1 << 24) | (37 << 16) | (15 << 8)) /* Polaris10/11 firmware version */#define FW_1_66_16	((1 << 24) | (66 << 16) | (16 << 8)) /* Firmware Names */#ifdef CONFIG_DRM_AMDGPU_SI#define FIRMWARE_TAHITI		"amdgpu/tahiti_uvd.bin"#define FIRMWARE_VERDE		"amdgpu/verde_uvd.bin"#define FIRMWARE_PITCAIRN	"amdgpu/pitcairn_uvd.bin"#define FIRMWARE_OLAND		"amdgpu/oland_uvd.bin"#endif#ifdef CONFIG_DRM_AMDGPU_CIK#define FIRMWARE_BONAIRE	"amdgpu/bonaire_uvd.bin"#define FIRMWARE_KABINI	"amdgpu/kabini_uvd.bin"#define FIRMWARE_KAVERI	"amdgpu/kaveri_uvd.bin"#define FIRMWARE_HAWAII	"amdgpu/hawaii_uvd.bin"#define FIRMWARE_MULLINS	"amdgpu/mullins_uvd.bin"#endif#define FIRMWARE_TONGA		"amdgpu/tonga_uvd.bin"#define FIRMWARE_CARRIZO	"amdgpu/carrizo_uvd.bin"#define FIRMWARE_FIJI		"amdgpu/fiji_uvd.bin"#define FIRMWARE_STONEY		"amdgpu/stoney_uvd.bin"#define FIRMWARE_POLARIS10	"amdgpu/polaris10_uvd.bin"#define FIRMWARE_POLARIS11	"amdgpu/polaris11_uvd.bin"#define FIRMWARE_POLARIS12	"amdgpu/polaris12_uvd.bin"#define FIRMWARE_VEGAM		"amdgpu/vegam_uvd.bin" #define FIRMWARE_VEGA10		"amdgpu/vega10_uvd.bin"#define FIRMWARE_VEGA12		"amdgpu/vega12_uvd.bin"#define FIRMWARE_VEGA20		"amdgpu/vega20_uvd.bin" /* These are common relative offsets for all asics, from uvd_7_0_offset.h,  */#define UVD_GPCOM_VCPU_CMD		0x03c3#define UVD_GPCOM_VCPU_DATA0	0x03c4#define UVD_GPCOM_VCPU_DATA1	0x03c5#define UVD_NO_OP				0x03ff#define UVD_BASE_SI				0x3800 /* * amdgpu_uvd_cs_ctx - Command submission parser context * * Used for emulating virtual memory support on UVD 4.2. */struct amdgpu_uvd_cs_ctx {	struct amdgpu_cs_parser *parser;	unsigned int reg, count;	unsigned int data0, data1;	unsigned int idx;	struct amdgpu_ib *ib; 	/* does the IB has a msg command */	bool has_msg_cmd; 	/* minimum buffer sizes */	unsigned int *buf_sizes;}; #ifdef CONFIG_DRM_AMDGPU_SIMODULE_FIRMWARE(FIRMWARE_TAHITI);MODULE_FIRMWARE(FIRMWARE_VERDE);MODULE_FIRMWARE(FIRMWARE_PITCAIRN);MODULE_FIRMWARE(FIRMWARE_OLAND);#endif#ifdef CONFIG_DRM_AMDGPU_CIKMODULE_FIRMWARE(FIRMWARE_BONAIRE);MODULE_FIRMWARE(FIRMWARE_KABINI);MODULE_FIRMWARE(FIRMWARE_KAVERI);MODULE_FIRMWARE(FIRMWARE_HAWAII);MODULE_FIRMWARE(FIRMWARE_MULLINS);#endifMODULE_FIRMWARE(FIRMWARE_TONGA);MODULE_FIRMWARE(FIRMWARE_CARRIZO);MODULE_FIRMWARE(FIRMWARE_FIJI);MODULE_FIRMWARE(FIRMWARE_STONEY);MODULE_FIRMWARE(FIRMWARE_POLARIS10);MODULE_FIRMWARE(FIRMWARE_POLARIS11);MODULE_FIRMWARE(FIRMWARE_POLARIS12);MODULE_FIRMWARE(FIRMWARE_VEGAM); MODULE_FIRMWARE(FIRMWARE_VEGA10);MODULE_FIRMWARE(FIRMWARE_VEGA12);MODULE_FIRMWARE(FIRMWARE_VEGA20); static void amdgpu_uvd_idle_work_handler(struct work_struct *work);static void amdgpu_uvd_force_into_vcpu_segment(struct amdgpu_bo *abo); static int amdgpu_uvd_create_msg_bo_helper(struct amdgpu_device *adev,					   uint32_t size,					   struct amdgpu_bo **bo_ptr){	struct ttm_operation_ctx ctx = { true, false };	struct amdgpu_bo *bo = NULL;	void *addr;	int r; 	r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE,				      AMDGPU_GEM_DOMAIN_GTT,				      &bo, NULL, &addr);	if (r)		return r; 	if (adev->uvd.address_64_bit)		goto succ; 	amdgpu_bo_kunmap(bo);	amdgpu_bo_unpin(bo);	amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);	amdgpu_uvd_force_into_vcpu_segment(bo);	r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);	if (r)		goto err;	r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_VRAM);	if (r)		goto err_pin;	r = amdgpu_bo_kmap(bo, &addr);	if (r)		goto err_kmap;succ:	amdgpu_bo_unreserve(bo);	*bo_ptr = bo;	return 0;err_kmap:	amdgpu_bo_unpin(bo);err_pin:err:	amdgpu_bo_unreserve(bo);	amdgpu_bo_unref(&bo);	return r;} int amdgpu_uvd_sw_init(struct amdgpu_device *adev){	unsigned long bo_size;	const char *fw_name;	const struct common_firmware_header *hdr;	unsigned int family_id;	int i, j, r;	u32 vcpu_bo_domain; 	INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); 	switch (adev->asic_type) {#ifdef CONFIG_DRM_AMDGPU_SI	case CHIP_TAHITI:		fw_name = FIRMWARE_TAHITI;		break;	case CHIP_VERDE:		fw_name = FIRMWARE_VERDE;		break;	case CHIP_PITCAIRN:		fw_name = FIRMWARE_PITCAIRN;		break;	case CHIP_OLAND:		fw_name = FIRMWARE_OLAND;		break;#endif#ifdef CONFIG_DRM_AMDGPU_CIK	case CHIP_BONAIRE:		fw_name = FIRMWARE_BONAIRE;		break;	case CHIP_KABINI:		fw_name = FIRMWARE_KABINI;		break;	case CHIP_KAVERI:		fw_name = FIRMWARE_KAVERI;		break;	case CHIP_HAWAII:		fw_name = FIRMWARE_HAWAII;		break;	case CHIP_MULLINS:		fw_name = FIRMWARE_MULLINS;		break;#endif	case CHIP_TONGA:		fw_name = FIRMWARE_TONGA;		break;	case CHIP_FIJI:		fw_name = FIRMWARE_FIJI;		break;	case CHIP_CARRIZO:		fw_name = FIRMWARE_CARRIZO;		break;	case CHIP_STONEY:		fw_name = FIRMWARE_STONEY;		break;	case CHIP_POLARIS10:		fw_name = FIRMWARE_POLARIS10;		break;	case CHIP_POLARIS11:		fw_name = FIRMWARE_POLARIS11;		break;	case CHIP_POLARIS12:		fw_name = FIRMWARE_POLARIS12;		break;	case CHIP_VEGA10:		fw_name = FIRMWARE_VEGA10;		break;	case CHIP_VEGA12:		fw_name = FIRMWARE_VEGA12;		break;	case CHIP_VEGAM:		fw_name = FIRMWARE_VEGAM;		break;	case CHIP_VEGA20:		fw_name = FIRMWARE_VEGA20;		break;	default:		return -EINVAL;	} 	r = amdgpu_ucode_request(adev, &adev->uvd.fw, AMDGPU_UCODE_REQUIRED, "%s", fw_name);	if (r) {		dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",			fw_name);		amdgpu_ucode_release(&adev->uvd.fw);		return r;	} 	/* Set the default UVD handles that the firmware can handle */	adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; 	hdr = (const struct common_firmware_header *)adev->uvd.fw->data;	family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 	if (adev->asic_type < CHIP_VEGA20) {		unsigned int version_major, version_minor; 		version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;		version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;		drm_info(adev_to_drm(adev), "Found UVD firmware Version: %u.%u Family ID: %u\n",			version_major, version_minor, family_id); 		/*		 * Limit the number of UVD handles depending on microcode major		 * and minor versions. The firmware version which has 40 UVD		 * instances support is 1.80. So all subsequent versions should		 * also have the same support.		 */		if ((version_major > 0x01) ||		    ((version_major == 0x01) && (version_minor >= 0x50)))			adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 		adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |					(family_id << 8)); 		if ((adev->asic_type == CHIP_POLARIS10 ||		     adev->asic_type == CHIP_POLARIS11) &&		    (adev->uvd.fw_version < FW_1_66_16))			DRM_ERROR("POLARIS10/11 UVD firmware version %u.%u is too old.\n",				  version_major, version_minor);	} else {		unsigned int enc_major, enc_minor, dec_minor; 		dec_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;		enc_minor = (le32_to_cpu(hdr->ucode_version) >> 24) & 0x3f;		enc_major = (le32_to_cpu(hdr->ucode_version) >> 30) & 0x3;		drm_info(adev_to_drm(adev), "Found UVD firmware ENC: %u.%u DEC: .%u Family ID: %u\n",			enc_major, enc_minor, dec_minor, family_id); 		adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 		adev->uvd.fw_version = le32_to_cpu(hdr->ucode_version);	} 	bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE		  +  AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles;	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)		bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 	/* UVD 5.0 and newer HW can use 64 bit addressing. */	adev->uvd.address_64_bit =		!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0); 	vcpu_bo_domain = AMDGPU_GEM_DOMAIN_VRAM;	if (adev->uvd.address_64_bit)		vcpu_bo_domain |= AMDGPU_GEM_DOMAIN_GTT; 	for (j = 0; j < adev->uvd.num_uvd_inst; j++) {		if (adev->uvd.harvest_config & (1 << j))			continue; 		r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,					    vcpu_bo_domain,					    &adev->uvd.inst[j].vcpu_bo,					    &adev->uvd.inst[j].gpu_addr,					    &adev->uvd.inst[j].cpu_addr);		if (r) {			dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);			return r;		}	} 	for (i = 0; i < adev->uvd.max_handles; ++i) {		atomic_set(&adev->uvd.handles[i], 0);		adev->uvd.filp[i] = NULL;	} 	r = amdgpu_uvd_create_msg_bo_helper(adev, 128 << 10, &adev->uvd.ib_bo);	if (r)		return r; 	switch (adev->asic_type) {	case CHIP_TONGA:		adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10;		break;	case CHIP_CARRIZO:		adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11;		break;	case CHIP_FIJI:		adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12;		break;	case CHIP_STONEY:		adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15;		break;	default:		adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10;	} 	return 0;} int amdgpu_uvd_sw_fini(struct amdgpu_device *adev){	void *addr = amdgpu_bo_kptr(adev->uvd.ib_bo);	int i, j; 	drm_sched_entity_destroy(&adev->uvd.entity); 	for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {		if (adev->uvd.harvest_config & (1 << j))			continue;		kvfree(adev->uvd.inst[j].saved_bo); 		amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo,				      &adev->uvd.inst[j].gpu_addr,				      (void **)&adev->uvd.inst[j].cpu_addr); 		amdgpu_ring_fini(&adev->uvd.inst[j].ring); 		for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i)			amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);	}	amdgpu_bo_free_kernel(&adev->uvd.ib_bo, NULL, &addr);	amdgpu_ucode_release(&adev->uvd.fw); 	return 0;} /** * amdgpu_uvd_entity_init - init entity * * @adev: amdgpu_device pointer * @ring: amdgpu_ring pointer to check * * Initialize the entity used for handle management in the kernel driver. */int amdgpu_uvd_entity_init(struct amdgpu_device *adev, struct amdgpu_ring *ring){	if (ring == &adev->uvd.inst[0].ring) {		struct drm_gpu_scheduler *sched = &ring->sched;		int r; 		r = drm_sched_entity_init(&adev->uvd.entity, DRM_SCHED_PRIORITY_NORMAL,					  &sched, 1, NULL);		if (r) {			DRM_ERROR("Failed setting up UVD kernel entity.\n");			return r;		}	} 	return 0;} int amdgpu_uvd_prepare_suspend(struct amdgpu_device *adev){	unsigned int size;	void *ptr;	int i, j, idx; 	cancel_delayed_work_sync(&adev->uvd.idle_work); 	/* only valid for physical mode */	if (adev->asic_type < CHIP_POLARIS10) {		for (i = 0; i < adev->uvd.max_handles; ++i)			if (atomic_read(&adev->uvd.handles[i]))				break; 		if (i == adev->uvd.max_handles)			return 0;	} 	for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {		if (adev->uvd.harvest_config & (1 << j))			continue;		if (adev->uvd.inst[j].vcpu_bo == NULL)			continue; 		size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo);		ptr = adev->uvd.inst[j].cpu_addr; 		adev->uvd.inst[j].saved_bo = kvmalloc(size, GFP_KERNEL);		if (!adev->uvd.inst[j].saved_bo)			return -ENOMEM; 		if (drm_dev_enter(adev_to_drm(adev), &idx)) {			/* re-write 0 since err_event_athub will corrupt VCPU buffer */			if (amdgpu_ras_intr_triggered())				memset(adev->uvd.inst[j].saved_bo, 0, size);			else				memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size); 			drm_dev_exit(idx);		}	} 	return 0;} int amdgpu_uvd_suspend(struct amdgpu_device *adev){	if (amdgpu_ras_intr_triggered())		drm_warn(adev_to_drm(adev),			"UVD VCPU state may lost due to RAS ERREVENT_ATHUB_INTERRUPT\n"); 	return 0;} int amdgpu_uvd_resume(struct amdgpu_device *adev){	unsigned int size;	void *ptr;	int i, idx; 	for (i = 0; i < adev->uvd.num_uvd_inst; i++) {		if (adev->uvd.harvest_config & (1 << i))			continue;		if (adev->uvd.inst[i].vcpu_bo == NULL)			return -EINVAL; 		size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo);		ptr = adev->uvd.inst[i].cpu_addr; 		if (adev->uvd.inst[i].saved_bo != NULL) {			if (drm_dev_enter(adev_to_drm(adev), &idx)) {				memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size);				drm_dev_exit(idx);			}

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