// SPDX-License-Identifier: MIT/* * Copyright 2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */#include <drm/drm_vblank.h>#include <drm/drm_atomic_helper.h> #include "dc.h"#include "amdgpu.h"#include "amdgpu_dm_psr.h"#include "amdgpu_dm_replay.h"#include "amdgpu_dm_crtc.h"#include "amdgpu_dm_plane.h"#include "amdgpu_dm_trace.h"#include "amdgpu_dm_debugfs.h"#include "dm_helpers.h"#include "modules/inc/mod_power.h" #define HPD_DETECTION_PERIOD_uS 2000000#define HPD_DETECTION_TIME_uS 100000 void amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc){ struct drm_crtc *crtc = &acrtc->base; struct drm_device *dev = crtc->dev; unsigned long flags; drm_crtc_handle_vblank(crtc); spin_lock_irqsave(&dev->event_lock, flags); /* Send completion event for cursor-only commits */ if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { drm_crtc_send_vblank_event(crtc, acrtc->event); drm_crtc_vblank_put(crtc); acrtc->event = NULL; } spin_unlock_irqrestore(&dev->event_lock, flags);}EXPORT_IF_KUNIT(amdgpu_dm_crtc_handle_vblank); bool amdgpu_dm_crtc_modeset_required(struct drm_crtc_state *crtc_state, struct dc_stream_state *new_stream, struct dc_stream_state *old_stream){ return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);}EXPORT_IF_KUNIT(amdgpu_dm_crtc_modeset_required); bool amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc *acrtc) { return acrtc->dm_irq_params.freesync_config.state == VRR_STATE_ACTIVE_VARIABLE || acrtc->dm_irq_params.freesync_config.state == VRR_STATE_ACTIVE_FIXED;}EXPORT_IF_KUNIT(amdgpu_dm_crtc_vrr_active_irq); int amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc *crtc, bool enable){ enum dc_irq_source irq_source; struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); struct amdgpu_device *adev = drm_to_adev(crtc->dev); int rc; if (acrtc->otg_inst == -1) return 0; irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst; rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n", acrtc->crtc_id, enable ? "en" : "dis", rc); return rc;}EXPORT_IF_KUNIT(amdgpu_dm_crtc_set_vupdate_irq); bool amdgpu_dm_crtc_vrr_active(const struct dm_crtc_state *dm_state){ return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE || dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;}EXPORT_IF_KUNIT(amdgpu_dm_crtc_vrr_active); /** * amdgpu_dm_crtc_set_static_screen_optimze() - Toggle static screen optimizations. * * @dm: display manager * @stream: DC stream state * @sso_enable: desired static screen optimization state * @allow_sr_entry: whether entry into self-refresh mode is allowed * * This function uses the static-screen optimization state as the trigger to * set/clear the Replay and PSR vsync-related events. */void amdgpu_dm_crtc_set_static_screen_optimze( struct amdgpu_display_manager *dm, struct dc_stream_state *stream, bool sso_enable, bool allow_sr_entry){ struct dc_link *link = stream->link; bool set_vsync_event = !sso_enable; /* * allow_sr_entry gates only entry. A disable request must still set * the vsync events to force Replay and PSR1 out and keep them blocked. */ if (sso_enable && !allow_sr_entry) return; amdgpu_dm_replay_set_event(dm, stream, set_vsync_event, replay_event_vsync, set_vsync_event); if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1) amdgpu_dm_psr_set_event(dm, stream, set_vsync_event, psr_event_vsync, set_vsync_event);}EXPORT_IF_KUNIT(amdgpu_dm_crtc_set_static_screen_optimze); bool amdgpu_dm_is_headless(struct amdgpu_device *adev){ struct drm_connector *connector; struct drm_connector_list_iter iter; struct drm_device *dev; bool is_headless = true; if (adev == NULL) return true; dev = adev->dm.ddev; drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue; if (connector->status == connector_status_connected) { is_headless = false; break; } } drm_connector_list_iter_end(&iter); return is_headless;}EXPORT_IF_KUNIT(amdgpu_dm_is_headless); STATIC_IFN_KUNIT void amdgpu_dm_idle_worker(struct work_struct *work){ struct idle_workqueue *idle_work; idle_work = container_of(work, struct idle_workqueue, work); idle_work->dm->idle_workqueue->running = true; while (idle_work->enable) { fsleep(HPD_DETECTION_PERIOD_uS); mutex_lock(&idle_work->dm->dc_lock); if (!idle_work->dm->dc->idle_optimizations_allowed) { mutex_unlock(&idle_work->dm->dc_lock); break; } dc_allow_idle_optimizations(idle_work->dm->dc, false); mutex_unlock(&idle_work->dm->dc_lock); fsleep(HPD_DETECTION_TIME_uS); mutex_lock(&idle_work->dm->dc_lock); if (!amdgpu_dm_is_headless(idle_work->dm->adev) && !amdgpu_dm_psr_is_active_allowed(idle_work->dm)) { mutex_unlock(&idle_work->dm->dc_lock); break; } if (idle_work->enable) { dc_post_update_surfaces_to_stream(idle_work->dm->dc); dc_allow_idle_optimizations(idle_work->dm->dc, true); } mutex_unlock(&idle_work->dm->dc_lock); } idle_work->dm->idle_workqueue->running = false;}EXPORT_IF_KUNIT(amdgpu_dm_idle_worker); struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev){ struct idle_workqueue *idle_work; idle_work = kzalloc_obj(*idle_work); if (ZERO_OR_NULL_PTR(idle_work)) return NULL; idle_work->dm = &adev->dm; idle_work->enable = false; idle_work->running = false; INIT_WORK(&idle_work->work, amdgpu_dm_idle_worker); return idle_work;}EXPORT_IF_KUNIT(idle_create_workqueue); STATIC_IFN_KUNIT void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work){ struct vblank_control_work *vblank_work = container_of(work, struct vblank_control_work, work); struct amdgpu_display_manager *dm = vblank_work->dm; mutex_lock(&dm->dc_lock); if (vblank_work->enable) { dm->active_vblank_irq_count++; amdgpu_dm_ism_commit_event(&vblank_work->acrtc->ism, DM_ISM_EVENT_EXIT_IDLE_REQUESTED); } else { if (dm->active_vblank_irq_count > 0) dm->active_vblank_irq_count--; amdgpu_dm_ism_commit_event(&vblank_work->acrtc->ism, DM_ISM_EVENT_ENTER_IDLE_REQUESTED); } mutex_unlock(&dm->dc_lock); dc_stream_release(vblank_work->stream); kfree(vblank_work);}EXPORT_IF_KUNIT(amdgpu_dm_crtc_vblank_control_worker); static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable){ struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); struct amdgpu_device *adev = drm_to_adev(crtc->dev); struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); struct amdgpu_display_manager *dm = &adev->dm; struct vblank_control_work *work; int irq_type; int rc = 0; if (enable && !acrtc->base.enabled) { drm_dbg_vbl(crtc->dev, "Reject vblank enable on unconfigured CRTC %d (enabled=%d)\n", acrtc->crtc_id, acrtc->base.enabled); return -EINVAL; } irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); if (enable && acrtc_state->stream) { struct dc *dc = adev->dm.dc; struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); struct psr_settings *psr = &acrtc_state->stream->link->psr_settings; struct replay_settings *pr = &acrtc_state->stream->link->replay_settings; bool sr_supported = (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED) || pr->config.replay_supported; /* * IPS & self-refresh feature can cause vblank counter resets between * vblank disable and enable. * It may cause system stuck due to waiting for the vblank counter. * Call this function to estimate missed vblanks by using timestamps and * update the vblank counter in DRM. */ if (dc->caps.ips_support && dc->config.disable_ips != DMUB_IPS_DISABLE_ALL && sr_supported && vblank->config.disable_immediate) drm_crtc_vblank_restore(crtc); } /* * On DCN, VUPDATE_NO_LOCK is the single OTG interrupt used to deliver * vblank and pageflip completion events, so enable it whenever vblank * is enabled. On DCE, vupdate is only needed in VRR mode. */ if (amdgpu_ip_version(adev, DCE_HWIP, 0) != 0) { if (enable) { rc = amdgpu_irq_get(adev, &adev->vupdate_irq, irq_type); drm_dbg_vbl(crtc->dev, "Get vupdate_irq ret=%d\n", rc); } else { rc = amdgpu_irq_put(adev, &adev->vupdate_irq, irq_type); drm_dbg_vbl(crtc->dev, "Put vupdate_irq ret=%d\n", rc); } } else if (dc_supports_vrr(dm->dc->ctx->dce_version)) { if (enable) { /* vblank irq on -> Only need vupdate irq in vrr mode * Not ref-counted since we need explicit enable/disable * for DCE VRR handling */ if (amdgpu_dm_crtc_vrr_active(acrtc_state)) rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true); } else { /* vblank irq off -> vupdate irq off */ rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, false); } } if (rc) return rc; /* * VLINE0 (crtc_irq) and GRPH_PFLIP (pageflip_irq) are only used on * DCE. On DCN, vblank and pageflip completion are delivered from * VUPDATE_NO_LOCK (enabled above), so don't touch them here. */ if (amdgpu_ip_version(adev, DCE_HWIP, 0) == 0) { /* crtc vblank or vstartup interrupt */ if (enable) { rc = amdgpu_irq_get(adev, &adev->crtc_irq, irq_type); drm_dbg_vbl(crtc->dev, "Get crtc_irq ret=%d\n", rc); } else { rc = amdgpu_irq_put(adev, &adev->crtc_irq, irq_type); drm_dbg_vbl(crtc->dev, "Put crtc_irq ret=%d\n", rc); } if (rc) return rc; /* * hubp surface flip interrupt * * We have no guarantee that the frontend index maps to the same * backend index - some even map to more than one. * * TODO: Use a different interrupt or check DC itself for the mapping. */ if (enable) { rc = amdgpu_irq_get(adev, &adev->pageflip_irq, irq_type); drm_dbg_vbl(crtc->dev, "Get pageflip_irq ret=%d\n", rc); } else { rc = amdgpu_irq_put(adev, &adev->pageflip_irq, irq_type); drm_dbg_vbl(crtc->dev, "Put pageflip_irq ret=%d\n", rc); } if (rc) return rc; } #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) /* crtc vline0 interrupt, only available on DCN+ */ if (amdgpu_ip_version(adev, DCE_HWIP, 0) != 0) { if (enable) { rc = amdgpu_irq_get(adev, &adev->vline0_irq, irq_type); drm_dbg_vbl(crtc->dev, "Get vline0_irq ret=%d\n", rc); } else { rc = amdgpu_irq_put(adev, &adev->vline0_irq, irq_type); drm_dbg_vbl(crtc->dev, "Put vline0_irq ret=%d\n", rc); } if (rc) return rc; }#endif if (amdgpu_in_reset(adev)) return 0; if (dm->vblank_control_workqueue) { work = kzalloc_obj(*work, GFP_ATOMIC); if (!work) return -ENOMEM; INIT_WORK(&work->work, amdgpu_dm_crtc_vblank_control_worker); work->dm = dm; work->acrtc = acrtc; work->enable = enable; if (acrtc_state->stream) { dc_stream_retain(acrtc_state->stream); work->stream = acrtc_state->stream; } queue_work(dm->vblank_control_workqueue, &work->work); } return 0;} int amdgpu_dm_crtc_enable_vblank(struct drm_crtc *crtc){ return amdgpu_dm_crtc_set_vblank(crtc, true);}EXPORT_IF_KUNIT(amdgpu_dm_crtc_enable_vblank); void amdgpu_dm_crtc_disable_vblank(struct drm_crtc *crtc){ amdgpu_dm_crtc_set_vblank(crtc, false);}EXPORT_IF_KUNIT(amdgpu_dm_crtc_disable_vblank); STATIC_IFN_KUNIT void amdgpu_dm_crtc_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *state){ struct dm_crtc_state *cur = to_dm_crtc_state(state); /* TODO Destroy dc_stream objects are stream object is flattened */ if (cur->stream) dc_stream_release(cur->stream); __drm_atomic_helper_crtc_destroy_state(state); kfree(state);}EXPORT_IF_KUNIT(amdgpu_dm_crtc_destroy_state); STATIC_IFN_KUNIT struct drm_crtc_state *amdgpu_dm_crtc_duplicate_state(struct drm_crtc *crtc){ struct dm_crtc_state *state, *cur; cur = to_dm_crtc_state(crtc->state); if (WARN_ON(!crtc->state)) return NULL; state = kzalloc_obj(*state); if (!state) return NULL; __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); if (cur->stream) { state->stream = cur->stream; dc_stream_retain(state->stream); } state->active_planes = cur->active_planes; state->vrr_infopacket = cur->vrr_infopacket; state->abm_level = cur->abm_level; state->vrr_supported = cur->vrr_supported; state->freesync_config = cur->freesync_config; state->cm_has_degamma = cur->cm_has_degamma; state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb; state->regamma_tf = cur->regamma_tf; state->crc_skip_count = cur->crc_skip_count; state->mpo_requested = cur->mpo_requested; state->cursor_mode = cur->cursor_mode; /* TODO Duplicate dc_stream after objects are stream object is flattened */ return &state->base;}EXPORT_IF_KUNIT(amdgpu_dm_crtc_duplicate_state); static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc){ /* * amdgpu_dm_ism_fini() is intentionally called in amdgpu_dm_fini(). * It must be called before dc_destroy() in amdgpu_dm_fini() * to avoid ISM accessing an invalid dc handle once dc is released. */ drm_crtc_cleanup(crtc); kfree(crtc);} STATIC_IFN_KUNIT void amdgpu_dm_crtc_reset_state(struct drm_crtc *crtc){ struct dm_crtc_state *state; state = kzalloc_obj(*state); if (!state) return; if (crtc->state) amdgpu_dm_crtc_destroy_state(crtc, crtc->state); __drm_atomic_helper_crtc_reset(crtc, &state->base);}EXPORT_IF_KUNIT(amdgpu_dm_crtc_reset_state); #ifdef CONFIG_DEBUG_FSstatic int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc){ crtc_debugfs_init(crtc); return 0;}#endifLines 1–500 of 823. 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// SPDX-License-Identifier: MIT /* * Copyright 2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #include <drm/drm_vblank.h> #include <drm/drm_atomic_helper.h> #include "dc.h" #include "amdgpu.h" #include "amdgpu_dm_psr.h" #include "amdgpu_dm_replay.h" #include "amdgpu_dm_crtc.h" #include "amdgpu_dm_plane.h" #include "amdgpu_dm_trace.h" #include "amdgpu_dm_debugfs.h" #include "dm_helpers.h" #include "modules/inc/mod_power.h" #define HPD_DETECTION_PERIOD_uS 2000000 #define HPD_DETECTION_TIME_uS 100000 void amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc) { struct drm_crtc *crtc = &acrtc->base; struct drm_device *dev = crtc->dev; unsigned long flags; drm_crtc_handle_vblank(crtc); spin_lock_irqsave(&dev->event_lock, flags); /* Send completion event for cursor-only commits */ if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { drm_crtc_send_vblank_event(crtc, acrtc->event); drm_crtc_vblank_put(crtc); acrtc->event = NULL; } spin_unlock_irqrestore(&dev->event_lock, flags); } EXPORT_IF_KUNIT(amdgpu_dm_crtc_handle_vblank); bool amdgpu_dm_crtc_modeset_required(struct drm_crtc_state *crtc_state, struct dc_stream_state *new_stream, struct dc_stream_state *old_stream) { return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); } EXPORT_IF_KUNIT(amdgpu_dm_crtc_modeset_required); bool amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc *acrtc) { return acrtc->dm_irq_params.freesync_config.state == VRR_STATE_ACTIVE_VARIABLE || acrtc->dm_irq_params.freesync_config.state == VRR_STATE_ACTIVE_FIXED; } EXPORT_IF_KUNIT(amdgpu_dm_crtc_vrr_active_irq); int amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc *crtc, bool enable) { enum dc_irq_source irq_source; struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); struct amdgpu_device *adev = drm_to_adev(crtc->dev); int rc; if (acrtc->otg_inst == -1) return 0; irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst; rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n", acrtc->crtc_id, enable ? "en" : "dis", rc); return rc; } EXPORT_IF_KUNIT(amdgpu_dm_crtc_set_vupdate_irq); bool amdgpu_dm_crtc_vrr_active(const struct dm_crtc_state *dm_state) { return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE || dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; } EXPORT_IF_KUNIT(amdgpu_dm_crtc_vrr_active); /** * amdgpu_dm_crtc_set_static_screen_optimze() - Toggle static screen optimizations. * * @dm: display manager * @stream: DC stream state * @sso_enable: desired static screen optimization state * @allow_sr_entry: whether entry into self-refresh mode is allowed * * This function uses the static-screen optimization state as the trigger to * set/clear the Replay and PSR vsync-related events. */ void amdgpu_dm_crtc_set_static_screen_optimze( struct amdgpu_display_manager *dm, struct dc_stream_state *stream, bool sso_enable, bool allow_sr_entry) { struct dc_link *link = stream->link; bool set_vsync_event = !sso_enable; /* * allow_sr_entry gates only entry. A disable request must still set * the vsync events to force Replay and PSR1 out and keep them blocked. */ if (sso_enable && !allow_sr_entry) return; amdgpu_dm_replay_set_event(dm, stream, set_vsync_event, replay_event_vsync, set_vsync_event); if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1) amdgpu_dm_psr_set_event(dm, stream, set_vsync_event, psr_event_vsync, set_vsync_event); } EXPORT_IF_KUNIT(amdgpu_dm_crtc_set_static_screen_optimze); bool amdgpu_dm_is_headless(struct amdgpu_device *adev) { struct drm_connector *connector; struct drm_connector_list_iter iter; struct drm_device *dev; bool is_headless = true; if (adev == NULL) return true; dev = adev->dm.ddev; drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue; if (connector->status == connector_status_connected) { is_headless = false; break; } } drm_connector_list_iter_end(&iter); return is_headless; } EXPORT_IF_KUNIT(amdgpu_dm_is_headless); STATIC_IFN_KUNIT void amdgpu_dm_idle_worker(struct work_struct *work) { struct idle_workqueue *idle_work; idle_work = container_of(work, struct idle_workqueue, work); idle_work->dm->idle_workqueue->running = true; while (idle_work->enable) { fsleep(HPD_DETECTION_PERIOD_uS); mutex_lock(&idle_work->dm->dc_lock); if (!idle_work->dm->dc->idle_optimizations_allowed) { mutex_unlock(&idle_work->dm->dc_lock); break; } dc_allow_idle_optimizations(idle_work->dm->dc, false); mutex_unlock(&idle_work->dm->dc_lock); fsleep(HPD_DETECTION_TIME_uS); mutex_lock(&idle_work->dm->dc_lock); if (!amdgpu_dm_is_headless(idle_work->dm->adev) && !amdgpu_dm_psr_is_active_allowed(idle_work->dm)) { mutex_unlock(&idle_work->dm->dc_lock); break; } if (idle_work->enable) { dc_post_update_surfaces_to_stream(idle_work->dm->dc); dc_allow_idle_optimizations(idle_work->dm->dc, true); } mutex_unlock(&idle_work->dm->dc_lock); } idle_work->dm->idle_workqueue->running = false; } EXPORT_IF_KUNIT(amdgpu_dm_idle_worker); struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev) { struct idle_workqueue *idle_work; idle_work = kzalloc_obj(*idle_work); if (ZERO_OR_NULL_PTR(idle_work)) return NULL; idle_work->dm = &adev->dm; idle_work->enable = false; idle_work->running = false; INIT_WORK(&idle_work->work, amdgpu_dm_idle_worker); return idle_work; } EXPORT_IF_KUNIT(idle_create_workqueue); STATIC_IFN_KUNIT void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work) { struct vblank_control_work *vblank_work = container_of(work, struct vblank_control_work, work); struct amdgpu_display_manager *dm = vblank_work->dm; mutex_lock(&dm->dc_lock); if (vblank_work->enable) { dm->active_vblank_irq_count++; amdgpu_dm_ism_commit_event(&vblank_work->acrtc->ism, DM_ISM_EVENT_EXIT_IDLE_REQUESTED); } else { if (dm->active_vblank_irq_count > 0) dm->active_vblank_irq_count--; amdgpu_dm_ism_commit_event(&vblank_work->acrtc->ism, DM_ISM_EVENT_ENTER_IDLE_REQUESTED); } mutex_unlock(&dm->dc_lock); dc_stream_release(vblank_work->stream); kfree(vblank_work); } EXPORT_IF_KUNIT(amdgpu_dm_crtc_vblank_control_worker); static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); struct amdgpu_device *adev = drm_to_adev(crtc->dev); struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); struct amdgpu_display_manager *dm = &adev->dm; struct vblank_control_work *work; int irq_type; int rc = 0; if (enable && !acrtc->base.enabled) { drm_dbg_vbl(crtc->dev, "Reject vblank enable on unconfigured CRTC %d (enabled=%d)\n", acrtc->crtc_id, acrtc->base.enabled); return -EINVAL; } irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); if (enable && acrtc_state->stream) { struct dc *dc = adev->dm.dc; struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); struct psr_settings *psr = &acrtc_state->stream->link->psr_settings; struct replay_settings *pr = &acrtc_state->stream->link->replay_settings; bool sr_supported = (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED) || pr->config.replay_supported; /* * IPS & self-refresh feature can cause vblank counter resets between * vblank disable and enable. * It may cause system stuck due to waiting for the vblank counter. * Call this function to estimate missed vblanks by using timestamps and * update the vblank counter in DRM. */ if (dc->caps.ips_support && dc->config.disable_ips != DMUB_IPS_DISABLE_ALL && sr_supported && vblank->config.disable_immediate) drm_crtc_vblank_restore(crtc); } /* * On DCN, VUPDATE_NO_LOCK is the single OTG interrupt used to deliver * vblank and pageflip completion events, so enable it whenever vblank * is enabled. On DCE, vupdate is only needed in VRR mode. */ if (amdgpu_ip_version(adev, DCE_HWIP, 0) != 0) { if (enable) { rc = amdgpu_irq_get(adev, &adev->vupdate_irq, irq_type); drm_dbg_vbl(crtc->dev, "Get vupdate_irq ret=%d\n", rc); } else { rc = amdgpu_irq_put(adev, &adev->vupdate_irq, irq_type); drm_dbg_vbl(crtc->dev, "Put vupdate_irq ret=%d\n", rc); } } else if (dc_supports_vrr(dm->dc->ctx->dce_version)) { if (enable) { /* vblank irq on -> Only need vupdate irq in vrr mode * Not ref-counted since we need explicit enable/disable * for DCE VRR handling */ if (amdgpu_dm_crtc_vrr_active(acrtc_state)) rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true); } else { /* vblank irq off -> vupdate irq off */ rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, false); } } if (rc) return rc; /* * VLINE0 (crtc_irq) and GRPH_PFLIP (pageflip_irq) are only used on * DCE. On DCN, vblank and pageflip completion are delivered from * VUPDATE_NO_LOCK (enabled above), so don't touch them here. */ if (amdgpu_ip_version(adev, DCE_HWIP, 0) == 0) { /* crtc vblank or vstartup interrupt */ if (enable) { rc = amdgpu_irq_get(adev, &adev->crtc_irq, irq_type); drm_dbg_vbl(crtc->dev, "Get crtc_irq ret=%d\n", rc); } else { rc = amdgpu_irq_put(adev, &adev->crtc_irq, irq_type); drm_dbg_vbl(crtc->dev, "Put crtc_irq ret=%d\n", rc); } if (rc) return rc; /* * hubp surface flip interrupt * * We have no guarantee that the frontend index maps to the same * backend index - some even map to more than one. * * TODO: Use a different interrupt or check DC itself for the mapping. */ if (enable) { rc = amdgpu_irq_get(adev, &adev->pageflip_irq, irq_type); drm_dbg_vbl(crtc->dev, "Get pageflip_irq ret=%d\n", rc); } else { rc = amdgpu_irq_put(adev, &adev->pageflip_irq, irq_type); drm_dbg_vbl(crtc->dev, "Put pageflip_irq ret=%d\n", rc); } if (rc) return rc; } #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) /* crtc vline0 interrupt, only available on DCN+ */ if (amdgpu_ip_version(adev, DCE_HWIP, 0) != 0) { if (enable) { rc = amdgpu_irq_get(adev, &adev->vline0_irq, irq_type); drm_dbg_vbl(crtc->dev, "Get vline0_irq ret=%d\n", rc); } else { rc = amdgpu_irq_put(adev, &adev->vline0_irq, irq_type); drm_dbg_vbl(crtc->dev, "Put vline0_irq ret=%d\n", rc); } if (rc) return rc; } #endif if (amdgpu_in_reset(adev)) return 0; if (dm->vblank_control_workqueue) { work = kzalloc_obj(*work, GFP_ATOMIC); if (!work) return -ENOMEM; INIT_WORK(&work->work, amdgpu_dm_crtc_vblank_control_worker); work->dm = dm; work->acrtc = acrtc; work->enable = enable; if (acrtc_state->stream) { dc_stream_retain(acrtc_state->stream); work->stream = acrtc_state->stream; } queue_work(dm->vblank_control_workqueue, &work->work); } return 0; } int amdgpu_dm_crtc_enable_vblank(struct drm_crtc *crtc) { return amdgpu_dm_crtc_set_vblank(crtc, true); } EXPORT_IF_KUNIT(amdgpu_dm_crtc_enable_vblank); void amdgpu_dm_crtc_disable_vblank(struct drm_crtc *crtc) { amdgpu_dm_crtc_set_vblank(crtc, false); } EXPORT_IF_KUNIT(amdgpu_dm_crtc_disable_vblank); STATIC_IFN_KUNIT void amdgpu_dm_crtc_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *state) { struct dm_crtc_state *cur = to_dm_crtc_state(state); /* TODO Destroy dc_stream objects are stream object is flattened */ if (cur->stream) dc_stream_release(cur->stream); __drm_atomic_helper_crtc_destroy_state(state); kfree(state); } EXPORT_IF_KUNIT(amdgpu_dm_crtc_destroy_state); STATIC_IFN_KUNIT struct drm_crtc_state *amdgpu_dm_crtc_duplicate_state(struct drm_crtc *crtc) { struct dm_crtc_state *state, *cur; cur = to_dm_crtc_state(crtc->state); if (WARN_ON(!crtc->state)) return NULL; state = kzalloc_obj(*state); if (!state) return NULL; __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); if (cur->stream) { state->stream = cur->stream; dc_stream_retain(state->stream); } state->active_planes = cur->active_planes; state->vrr_infopacket = cur->vrr_infopacket; state->abm_level = cur->abm_level; state->vrr_supported = cur->vrr_supported; state->freesync_config = cur->freesync_config; state->cm_has_degamma = cur->cm_has_degamma; state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb; state->regamma_tf = cur->regamma_tf; state->crc_skip_count = cur->crc_skip_count; state->mpo_requested = cur->mpo_requested; state->cursor_mode = cur->cursor_mode; /* TODO Duplicate dc_stream after objects are stream object is flattened */ return &state->base; } EXPORT_IF_KUNIT(amdgpu_dm_crtc_duplicate_state); static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc) { /* * amdgpu_dm_ism_fini() is intentionally called in amdgpu_dm_fini(). * It must be called before dc_destroy() in amdgpu_dm_fini() * to avoid ISM accessing an invalid dc handle once dc is released. */ drm_crtc_cleanup(crtc); kfree(crtc); } STATIC_IFN_KUNIT void amdgpu_dm_crtc_reset_state(struct drm_crtc *crtc) { struct dm_crtc_state *state; state = kzalloc_obj(*state); if (!state) return; if (crtc->state) amdgpu_dm_crtc_destroy_state(crtc, crtc->state); __drm_atomic_helper_crtc_reset(crtc, &state->base); } EXPORT_IF_KUNIT(amdgpu_dm_crtc_reset_state); #ifdef CONFIG_DEBUG_FS static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc) { crtc_debugfs_init(crtc); return 0; } #endif