/* * Copyright 2008 Advanced Micro Devices, Inc. * Copyright 2008 Red Hat Inc. * Copyright 2009 Jerome Glisse. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Dave Airlie * Alex Deucher * Jerome Glisse */#include <linux/ktime.h>#include <linux/module.h>#include <linux/pagemap.h>#include <linux/pci.h>#include <linux/dma-buf.h> #include <drm/amdgpu_drm.h>#include <drm/drm_gem_ttm_helper.h> #include "amdgpu.h"#include "amdgpu_display.h"#include "amdgpu_dma_buf.h"#include "amdgpu_xgmi.h" static const struct drm_gem_object_funcs amdgpu_gem_object_funcs; static void amdgpu_gem_object_free(struct drm_gem_object *gobj){ struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); if (robj) { amdgpu_mn_unregister(robj); amdgpu_bo_unref(&robj); }} int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, int alignment, u32 initial_domain, u64 flags, enum ttm_bo_type type, struct dma_resv *resv, struct drm_gem_object **obj){ struct amdgpu_bo *bo; struct amdgpu_bo_user *ubo; struct amdgpu_bo_param bp; int r; memset(&bp, 0, sizeof(bp)); *obj = NULL; bp.size = size; bp.byte_align = alignment; bp.type = type; bp.resv = resv; bp.preferred_domain = initial_domain; bp.flags = flags; bp.domain = initial_domain; bp.bo_ptr_size = sizeof(struct amdgpu_bo); r = amdgpu_bo_create_user(adev, &bp, &ubo); if (r) return r; bo = &ubo->bo; *obj = &bo->tbo.base; (*obj)->funcs = &amdgpu_gem_object_funcs; return 0;} void amdgpu_gem_force_release(struct amdgpu_device *adev){ struct drm_device *ddev = adev_to_drm(adev); struct drm_file *file; mutex_lock(&ddev->filelist_mutex); list_for_each_entry(file, &ddev->filelist, lhead) { struct drm_gem_object *gobj; int handle; WARN_ONCE(1, "Still active user space clients!\n"); spin_lock(&file->table_lock); idr_for_each_entry(&file->object_idr, gobj, handle) { WARN_ONCE(1, "And also active allocations!\n"); drm_gem_object_put(gobj); } idr_destroy(&file->object_idr); spin_unlock(&file->table_lock); } mutex_unlock(&ddev->filelist_mutex);} /* * Call from drm_gem_handle_create which appear in both new and open ioctl * case. */static int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv){ struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); struct amdgpu_fpriv *fpriv = file_priv->driver_priv; struct amdgpu_vm *vm = &fpriv->vm; struct amdgpu_bo_va *bo_va; struct mm_struct *mm; int r; mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm); if (mm && mm != current->mm) return -EPERM; if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID && abo->tbo.base.resv != vm->root.base.bo->tbo.base.resv) return -EPERM; r = amdgpu_bo_reserve(abo, false); if (r) return r; bo_va = amdgpu_vm_bo_find(vm, abo); if (!bo_va) { bo_va = amdgpu_vm_bo_add(adev, vm, abo); } else { ++bo_va->ref_count; } amdgpu_bo_unreserve(abo); return 0;} static void amdgpu_gem_object_close(struct drm_gem_object *obj, struct drm_file *file_priv){ struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); struct amdgpu_fpriv *fpriv = file_priv->driver_priv; struct amdgpu_vm *vm = &fpriv->vm; struct amdgpu_bo_list_entry vm_pd; struct list_head list, duplicates; struct dma_fence *fence = NULL; struct ttm_validate_buffer tv; struct ww_acquire_ctx ticket; struct amdgpu_bo_va *bo_va; long r; INIT_LIST_HEAD(&list); INIT_LIST_HEAD(&duplicates); tv.bo = &bo->tbo; tv.num_shared = 2; list_add(&tv.head, &list); amdgpu_vm_get_pd_bo(vm, &list, &vm_pd); r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); if (r) { dev_err(adev->dev, "leaking bo va because " "we fail to reserve bo (%ld)\n", r); return; } bo_va = amdgpu_vm_bo_find(vm, bo); if (!bo_va || --bo_va->ref_count) goto out_unlock; amdgpu_vm_bo_rmv(adev, bo_va); if (!amdgpu_vm_ready(vm)) goto out_unlock; fence = dma_resv_get_excl(bo->tbo.base.resv); if (fence) { amdgpu_bo_fence(bo, fence, true); fence = NULL; } r = amdgpu_vm_clear_freed(adev, vm, &fence); if (r || !fence) goto out_unlock; amdgpu_bo_fence(bo, fence, true); dma_fence_put(fence); out_unlock: if (unlikely(r < 0)) dev_err(adev->dev, "failed to clear page " "tables on GEM object close (%ld)\n", r); ttm_eu_backoff_reservation(&ticket, &list);} static const struct drm_gem_object_funcs amdgpu_gem_object_funcs = { .free = amdgpu_gem_object_free, .open = amdgpu_gem_object_open, .close = amdgpu_gem_object_close, .export = amdgpu_gem_prime_export, .vmap = drm_gem_ttm_vmap, .vunmap = drm_gem_ttm_vunmap,}; /* * GEM ioctls. */int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, struct drm_file *filp){ struct amdgpu_device *adev = drm_to_adev(dev); struct amdgpu_fpriv *fpriv = filp->driver_priv; struct amdgpu_vm *vm = &fpriv->vm; union drm_amdgpu_gem_create *args = data; uint64_t flags = args->in.domain_flags; uint64_t size = args->in.bo_size; struct dma_resv *resv = NULL; struct drm_gem_object *gobj; uint32_t handle, initial_domain; int r; /* reject invalid gem flags */ if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | AMDGPU_GEM_CREATE_NO_CPU_ACCESS | AMDGPU_GEM_CREATE_CPU_GTT_USWC | AMDGPU_GEM_CREATE_VRAM_CLEARED | AMDGPU_GEM_CREATE_VM_ALWAYS_VALID | AMDGPU_GEM_CREATE_EXPLICIT_SYNC | AMDGPU_GEM_CREATE_ENCRYPTED)) return -EINVAL; /* reject invalid gem domains */ if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK) return -EINVAL; if (!amdgpu_is_tmz(adev) && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) { DRM_NOTE_ONCE("Cannot allocate secure buffer since TMZ is disabled\n"); return -EINVAL; } /* create a gem object to contain this object in */ if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { /* if gds bo is created from user space, it must be * passed to bo list */ DRM_ERROR("GDS bo cannot be per-vm-bo\n"); return -EINVAL; } flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS; } if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { r = amdgpu_bo_reserve(vm->root.base.bo, false); if (r) return r; resv = vm->root.base.bo->tbo.base.resv; } initial_domain = (u32)(0xffffffff & args->in.domains);retry: r = amdgpu_gem_object_create(adev, size, args->in.alignment, initial_domain, flags, ttm_bo_type_device, resv, &gobj); if (r) { if (r != -ERESTARTSYS) { if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) { flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; goto retry; } if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { initial_domain |= AMDGPU_GEM_DOMAIN_GTT; goto retry; } DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu, %d)\n", size, initial_domain, args->in.alignment, r); } return r; } if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { if (!r) { struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); abo->parent = amdgpu_bo_ref(vm->root.base.bo); } amdgpu_bo_unreserve(vm->root.base.bo); } if (r) return r; r = drm_gem_handle_create(filp, gobj, &handle); /* drop reference from allocate - handle holds it now */ drm_gem_object_put(gobj); if (r) return r; memset(args, 0, sizeof(*args)); args->out.handle = handle; return 0;} int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, struct drm_file *filp){ struct ttm_operation_ctx ctx = { true, false }; struct amdgpu_device *adev = drm_to_adev(dev); struct drm_amdgpu_gem_userptr *args = data; struct drm_gem_object *gobj; struct amdgpu_bo *bo; uint32_t handle; int r; args->addr = untagged_addr(args->addr); if (offset_in_page(args->addr | args->size)) return -EINVAL; /* reject unknown flag values */ if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | AMDGPU_GEM_USERPTR_REGISTER)) return -EINVAL; if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { /* if we want to write to it we must install a MMU notifier */ return -EACCES; } /* create a gem object to contain this object in */ r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU, 0, ttm_bo_type_device, NULL, &gobj); if (r) return r; bo = gem_to_amdgpu_bo(gobj); bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; r = amdgpu_ttm_tt_set_userptr(&bo->tbo, args->addr, args->flags); if (r) goto release_object; if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) { r = amdgpu_mn_register(bo, args->addr); if (r) goto release_object; } if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages); if (r) goto release_object; r = amdgpu_bo_reserve(bo, true); if (r) goto user_pages_done; amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); amdgpu_bo_unreserve(bo); if (r) goto user_pages_done; } r = drm_gem_handle_create(filp, gobj, &handle); if (r) goto user_pages_done; args->handle = handle; user_pages_done: if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm); release_object: drm_gem_object_put(gobj); return r;} int amdgpu_mode_dumb_mmap(struct drm_file *filp, struct drm_device *dev, uint32_t handle, uint64_t *offset_p){ struct drm_gem_object *gobj; struct amdgpu_bo *robj; gobj = drm_gem_object_lookup(filp, handle); if (gobj == NULL) { return -ENOENT; } robj = gem_to_amdgpu_bo(gobj); if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) || (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { drm_gem_object_put(gobj); return -EPERM; } *offset_p = amdgpu_bo_mmap_offset(robj); drm_gem_object_put(gobj); return 0;} int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, struct drm_file *filp){ union drm_amdgpu_gem_mmap *args = data; uint32_t handle = args->in.handle; memset(args, 0, sizeof(*args)); return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);} /** * amdgpu_gem_timeout - calculate jiffies timeout from absolute value * * @timeout_ns: timeout in ns * * Calculate the timeout in jiffies from an absolute timeout in ns. */unsigned long amdgpu_gem_timeout(uint64_t timeout_ns){ unsigned long timeout_jiffies; ktime_t timeout; /* clamp timeout if it's to large */ if (((int64_t)timeout_ns) < 0) return MAX_SCHEDULE_TIMEOUT; timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); if (ktime_to_ns(timeout) < 0) return 0; timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); /* clamp timeout to avoid unsigned-> signed overflow */ if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) return MAX_SCHEDULE_TIMEOUT - 1; return timeout_jiffies;} int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, struct drm_file *filp){ union drm_amdgpu_gem_wait_idle *args = data; struct drm_gem_object *gobj; struct amdgpu_bo *robj; uint32_t handle = args->in.handle; unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); int r = 0; long ret; gobj = drm_gem_object_lookup(filp, handle); if (gobj == NULL) { return -ENOENT; } robj = gem_to_amdgpu_bo(gobj); ret = dma_resv_wait_timeout_rcu(robj->tbo.base.resv, true, true, timeout); /* ret == 0 means not signaled, * ret > 0 means signaled * ret < 0 means interrupted before timeout */ if (ret >= 0) { memset(args, 0, sizeof(*args)); args->out.status = (ret == 0); } else r = ret; drm_gem_object_put(gobj); return r;} int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, struct drm_file *filp){ struct drm_amdgpu_gem_metadata *args = data; struct drm_gem_object *gobj; struct amdgpu_bo *robj; int r = -1; DRM_DEBUG("%d \n", args->handle); gobj = drm_gem_object_lookup(filp, args->handle);Lines 1–500 of 915. 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/* * Copyright 2008 Advanced Micro Devices, Inc. * Copyright 2008 Red Hat Inc. * Copyright 2009 Jerome Glisse. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Dave Airlie * Alex Deucher * Jerome Glisse */ #include <linux/ktime.h> #include <linux/module.h> #include <linux/pagemap.h> #include <linux/pci.h> #include <linux/dma-buf.h> #include <drm/amdgpu_drm.h> #include <drm/drm_gem_ttm_helper.h> #include "amdgpu.h" #include "amdgpu_display.h" #include "amdgpu_dma_buf.h" #include "amdgpu_xgmi.h" static const struct drm_gem_object_funcs amdgpu_gem_object_funcs; static void amdgpu_gem_object_free(struct drm_gem_object *gobj) { struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); if (robj) { amdgpu_mn_unregister(robj); amdgpu_bo_unref(&robj); } } int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, int alignment, u32 initial_domain, u64 flags, enum ttm_bo_type type, struct dma_resv *resv, struct drm_gem_object **obj) { struct amdgpu_bo *bo; struct amdgpu_bo_user *ubo; struct amdgpu_bo_param bp; int r; memset(&bp, 0, sizeof(bp)); *obj = NULL; bp.size = size; bp.byte_align = alignment; bp.type = type; bp.resv = resv; bp.preferred_domain = initial_domain; bp.flags = flags; bp.domain = initial_domain; bp.bo_ptr_size = sizeof(struct amdgpu_bo); r = amdgpu_bo_create_user(adev, &bp, &ubo); if (r) return r; bo = &ubo->bo; *obj = &bo->tbo.base; (*obj)->funcs = &amdgpu_gem_object_funcs; return 0; } void amdgpu_gem_force_release(struct amdgpu_device *adev) { struct drm_device *ddev = adev_to_drm(adev); struct drm_file *file; mutex_lock(&ddev->filelist_mutex); list_for_each_entry(file, &ddev->filelist, lhead) { struct drm_gem_object *gobj; int handle; WARN_ONCE(1, "Still active user space clients!\n"); spin_lock(&file->table_lock); idr_for_each_entry(&file->object_idr, gobj, handle) { WARN_ONCE(1, "And also active allocations!\n"); drm_gem_object_put(gobj); } idr_destroy(&file->object_idr); spin_unlock(&file->table_lock); } mutex_unlock(&ddev->filelist_mutex); } /* * Call from drm_gem_handle_create which appear in both new and open ioctl * case. */ static int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv) { struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); struct amdgpu_fpriv *fpriv = file_priv->driver_priv; struct amdgpu_vm *vm = &fpriv->vm; struct amdgpu_bo_va *bo_va; struct mm_struct *mm; int r; mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm); if (mm && mm != current->mm) return -EPERM; if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID && abo->tbo.base.resv != vm->root.base.bo->tbo.base.resv) return -EPERM; r = amdgpu_bo_reserve(abo, false); if (r) return r; bo_va = amdgpu_vm_bo_find(vm, abo); if (!bo_va) { bo_va = amdgpu_vm_bo_add(adev, vm, abo); } else { ++bo_va->ref_count; } amdgpu_bo_unreserve(abo); return 0; } static void amdgpu_gem_object_close(struct drm_gem_object *obj, struct drm_file *file_priv) { struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); struct amdgpu_fpriv *fpriv = file_priv->driver_priv; struct amdgpu_vm *vm = &fpriv->vm; struct amdgpu_bo_list_entry vm_pd; struct list_head list, duplicates; struct dma_fence *fence = NULL; struct ttm_validate_buffer tv; struct ww_acquire_ctx ticket; struct amdgpu_bo_va *bo_va; long r; INIT_LIST_HEAD(&list); INIT_LIST_HEAD(&duplicates); tv.bo = &bo->tbo; tv.num_shared = 2; list_add(&tv.head, &list); amdgpu_vm_get_pd_bo(vm, &list, &vm_pd); r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); if (r) { dev_err(adev->dev, "leaking bo va because " "we fail to reserve bo (%ld)\n", r); return; } bo_va = amdgpu_vm_bo_find(vm, bo); if (!bo_va || --bo_va->ref_count) goto out_unlock; amdgpu_vm_bo_rmv(adev, bo_va); if (!amdgpu_vm_ready(vm)) goto out_unlock; fence = dma_resv_get_excl(bo->tbo.base.resv); if (fence) { amdgpu_bo_fence(bo, fence, true); fence = NULL; } r = amdgpu_vm_clear_freed(adev, vm, &fence); if (r || !fence) goto out_unlock; amdgpu_bo_fence(bo, fence, true); dma_fence_put(fence); out_unlock: if (unlikely(r < 0)) dev_err(adev->dev, "failed to clear page " "tables on GEM object close (%ld)\n", r); ttm_eu_backoff_reservation(&ticket, &list); } static const struct drm_gem_object_funcs amdgpu_gem_object_funcs = { .free = amdgpu_gem_object_free, .open = amdgpu_gem_object_open, .close = amdgpu_gem_object_close, .export = amdgpu_gem_prime_export, .vmap = drm_gem_ttm_vmap, .vunmap = drm_gem_ttm_vunmap, }; /* * GEM ioctls. */ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { struct amdgpu_device *adev = drm_to_adev(dev); struct amdgpu_fpriv *fpriv = filp->driver_priv; struct amdgpu_vm *vm = &fpriv->vm; union drm_amdgpu_gem_create *args = data; uint64_t flags = args->in.domain_flags; uint64_t size = args->in.bo_size; struct dma_resv *resv = NULL; struct drm_gem_object *gobj; uint32_t handle, initial_domain; int r; /* reject invalid gem flags */ if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | AMDGPU_GEM_CREATE_NO_CPU_ACCESS | AMDGPU_GEM_CREATE_CPU_GTT_USWC | AMDGPU_GEM_CREATE_VRAM_CLEARED | AMDGPU_GEM_CREATE_VM_ALWAYS_VALID | AMDGPU_GEM_CREATE_EXPLICIT_SYNC | AMDGPU_GEM_CREATE_ENCRYPTED)) return -EINVAL; /* reject invalid gem domains */ if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK) return -EINVAL; if (!amdgpu_is_tmz(adev) && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) { DRM_NOTE_ONCE("Cannot allocate secure buffer since TMZ is disabled\n"); return -EINVAL; } /* create a gem object to contain this object in */ if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { /* if gds bo is created from user space, it must be * passed to bo list */ DRM_ERROR("GDS bo cannot be per-vm-bo\n"); return -EINVAL; } flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS; } if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { r = amdgpu_bo_reserve(vm->root.base.bo, false); if (r) return r; resv = vm->root.base.bo->tbo.base.resv; } initial_domain = (u32)(0xffffffff & args->in.domains); retry: r = amdgpu_gem_object_create(adev, size, args->in.alignment, initial_domain, flags, ttm_bo_type_device, resv, &gobj); if (r) { if (r != -ERESTARTSYS) { if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) { flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; goto retry; } if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { initial_domain |= AMDGPU_GEM_DOMAIN_GTT; goto retry; } DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu, %d)\n", size, initial_domain, args->in.alignment, r); } return r; } if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { if (!r) { struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); abo->parent = amdgpu_bo_ref(vm->root.base.bo); } amdgpu_bo_unreserve(vm->root.base.bo); } if (r) return r; r = drm_gem_handle_create(filp, gobj, &handle); /* drop reference from allocate - handle holds it now */ drm_gem_object_put(gobj); if (r) return r; memset(args, 0, sizeof(*args)); args->out.handle = handle; return 0; } int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { struct ttm_operation_ctx ctx = { true, false }; struct amdgpu_device *adev = drm_to_adev(dev); struct drm_amdgpu_gem_userptr *args = data; struct drm_gem_object *gobj; struct amdgpu_bo *bo; uint32_t handle; int r; args->addr = untagged_addr(args->addr); if (offset_in_page(args->addr | args->size)) return -EINVAL; /* reject unknown flag values */ if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | AMDGPU_GEM_USERPTR_REGISTER)) return -EINVAL; if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { /* if we want to write to it we must install a MMU notifier */ return -EACCES; } /* create a gem object to contain this object in */ r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU, 0, ttm_bo_type_device, NULL, &gobj); if (r) return r; bo = gem_to_amdgpu_bo(gobj); bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; r = amdgpu_ttm_tt_set_userptr(&bo->tbo, args->addr, args->flags); if (r) goto release_object; if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) { r = amdgpu_mn_register(bo, args->addr); if (r) goto release_object; } if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages); if (r) goto release_object; r = amdgpu_bo_reserve(bo, true); if (r) goto user_pages_done; amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); amdgpu_bo_unreserve(bo); if (r) goto user_pages_done; } r = drm_gem_handle_create(filp, gobj, &handle); if (r) goto user_pages_done; args->handle = handle; user_pages_done: if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm); release_object: drm_gem_object_put(gobj); return r; } int amdgpu_mode_dumb_mmap(struct drm_file *filp, struct drm_device *dev, uint32_t handle, uint64_t *offset_p) { struct drm_gem_object *gobj; struct amdgpu_bo *robj; gobj = drm_gem_object_lookup(filp, handle); if (gobj == NULL) { return -ENOENT; } robj = gem_to_amdgpu_bo(gobj); if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) || (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { drm_gem_object_put(gobj); return -EPERM; } *offset_p = amdgpu_bo_mmap_offset(robj); drm_gem_object_put(gobj); return 0; } int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { union drm_amdgpu_gem_mmap *args = data; uint32_t handle = args->in.handle; memset(args, 0, sizeof(*args)); return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); } /** * amdgpu_gem_timeout - calculate jiffies timeout from absolute value * * @timeout_ns: timeout in ns * * Calculate the timeout in jiffies from an absolute timeout in ns. */ unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) { unsigned long timeout_jiffies; ktime_t timeout; /* clamp timeout if it's to large */ if (((int64_t)timeout_ns) < 0) return MAX_SCHEDULE_TIMEOUT; timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); if (ktime_to_ns(timeout) < 0) return 0; timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); /* clamp timeout to avoid unsigned-> signed overflow */ if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) return MAX_SCHEDULE_TIMEOUT - 1; return timeout_jiffies; } int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { union drm_amdgpu_gem_wait_idle *args = data; struct drm_gem_object *gobj; struct amdgpu_bo *robj; uint32_t handle = args->in.handle; unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); int r = 0; long ret; gobj = drm_gem_object_lookup(filp, handle); if (gobj == NULL) { return -ENOENT; } robj = gem_to_amdgpu_bo(gobj); ret = dma_resv_wait_timeout_rcu(robj->tbo.base.resv, true, true, timeout); /* ret == 0 means not signaled, * ret > 0 means signaled * ret < 0 means interrupted before timeout */ if (ret >= 0) { memset(args, 0, sizeof(*args)); args->out.status = (ret == 0); } else r = ret; drm_gem_object_put(gobj); return r; } int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { struct drm_amdgpu_gem_metadata *args = data; struct drm_gem_object *gobj; struct amdgpu_bo *robj; int r = -1; DRM_DEBUG("%d \n", args->handle); gobj = drm_gem_object_lookup(filp, args->handle);