/* * Copyright 2009 Jerome Glisse. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE * USE OR OTHER DEALINGS IN THE SOFTWARE. * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * *//* * Authors: *    Jerome Glisse <glisse@freedesktop.org> *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> *    Dave Airlie */ #include <linux/dma-mapping.h>#include <linux/iommu.h>#include <linux/hmm.h>#include <linux/pagemap.h>#include <linux/sched/task.h>#include <linux/sched/mm.h>#include <linux/seq_file.h>#include <linux/slab.h>#include <linux/swap.h>#include <linux/swiotlb.h>#include <linux/dma-buf.h>#include <linux/sizes.h> #include <drm/ttm/ttm_bo_api.h>#include <drm/ttm/ttm_bo_driver.h>#include <drm/ttm/ttm_placement.h> #include <drm/amdgpu_drm.h> #include "amdgpu.h"#include "amdgpu_object.h"#include "amdgpu_trace.h"#include "amdgpu_amdkfd.h"#include "amdgpu_sdma.h"#include "amdgpu_ras.h"#include "amdgpu_atomfirmware.h"#include "amdgpu_res_cursor.h"#include "bif/bif_4_1_d.h" #define AMDGPU_TTM_VRAM_MAX_DW_READ	(size_t)128 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,				   struct ttm_tt *ttm,				   struct ttm_resource *bo_mem);static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,				      struct ttm_tt *ttm); static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,				    unsigned int type,				    uint64_t size_in_page){	return ttm_range_man_init(&adev->mman.bdev, type,				  false, size_in_page);} /** * amdgpu_evict_flags - Compute placement flags * * @bo: The buffer object to evict * @placement: Possible destination(s) for evicted BO * * Fill in placement data when ttm_bo_evict() is called */static void amdgpu_evict_flags(struct ttm_buffer_object *bo,				struct ttm_placement *placement){	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);	struct amdgpu_bo *abo;	static const struct ttm_place placements = {		.fpfn = 0,		.lpfn = 0,		.mem_type = TTM_PL_SYSTEM,		.flags = 0	}; 	/* Don't handle scatter gather BOs */	if (bo->type == ttm_bo_type_sg) {		placement->num_placement = 0;		placement->num_busy_placement = 0;		return;	} 	/* Object isn't an AMDGPU object so ignore */	if (!amdgpu_bo_is_amdgpu_bo(bo)) {		placement->placement = &placements;		placement->busy_placement = &placements;		placement->num_placement = 1;		placement->num_busy_placement = 1;		return;	} 	abo = ttm_to_amdgpu_bo(bo);	switch (bo->mem.mem_type) {	case AMDGPU_PL_GDS:	case AMDGPU_PL_GWS:	case AMDGPU_PL_OA:		placement->num_placement = 0;		placement->num_busy_placement = 0;		return; 	case TTM_PL_VRAM:		if (!adev->mman.buffer_funcs_enabled) {			/* Move to system memory */			amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);		} else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&			   !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&			   amdgpu_bo_in_cpu_visible_vram(abo)) { 			/* Try evicting to the CPU inaccessible part of VRAM			 * first, but only set GTT as busy placement, so this			 * BO will be evicted to GTT rather than causing other			 * BOs to be evicted from VRAM			 */			amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |							 AMDGPU_GEM_DOMAIN_GTT);			abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;			abo->placements[0].lpfn = 0;			abo->placement.busy_placement = &abo->placements[1];			abo->placement.num_busy_placement = 1;		} else {			/* Move to GTT memory */			amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);		}		break;	case TTM_PL_TT:	default:		amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);		break;	}	*placement = abo->placement;} /** * amdgpu_verify_access - Verify access for a mmap call * * @bo:	The buffer object to map * @filp: The file pointer from the process performing the mmap * * This is called by ttm_bo_mmap() to verify whether a process * has the right to mmap a BO to their process space. */static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp){	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 	/*	 * Don't verify access for KFD BOs. They don't have a GEM	 * object associated with them.	 */	if (abo->kfd_bo)		return 0; 	if (amdgpu_ttm_tt_get_usermm(bo->ttm))		return -EPERM;	return drm_vma_node_verify_access(&abo->tbo.base.vma_node,					  filp->private_data);} /** * amdgpu_ttm_map_buffer - Map memory into the GART windows * @bo: buffer object to map * @mem: memory object to map * @mm_cur: range to map * @num_pages: number of pages to map * @window: which GART window to use * @ring: DMA ring to use for the copy * @tmz: if we should setup a TMZ enabled mapping * @addr: resulting address inside the MC address space * * Setup one of the GART windows to access a specific piece of memory or return * the physical address for local memory. */static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,				 struct ttm_resource *mem,				 struct amdgpu_res_cursor *mm_cur,				 unsigned num_pages, unsigned window,				 struct amdgpu_ring *ring, bool tmz,				 uint64_t *addr){	struct amdgpu_device *adev = ring->adev;	struct amdgpu_job *job;	unsigned num_dw, num_bytes;	struct dma_fence *fence;	uint64_t src_addr, dst_addr;	void *cpu_addr;	uint64_t flags;	unsigned int i;	int r; 	BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <	       AMDGPU_GTT_MAX_TRANSFER_SIZE * 8); 	/* Map only what can't be accessed directly */	if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {		*addr = amdgpu_ttm_domain_start(adev, mem->mem_type) +			mm_cur->start;		return 0;	} 	*addr = adev->gmc.gart_start;	*addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *		AMDGPU_GPU_PAGE_SIZE;	*addr += mm_cur->start & ~PAGE_MASK; 	num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);	num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE; 	r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,				     AMDGPU_IB_POOL_DELAYED, &job);	if (r)		return r; 	src_addr = num_dw * 4;	src_addr += job->ibs[0].gpu_addr; 	dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);	dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;	amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,				dst_addr, num_bytes, false); 	amdgpu_ring_pad_ib(ring, &job->ibs[0]);	WARN_ON(job->ibs[0].length_dw > num_dw); 	flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);	if (tmz)		flags |= AMDGPU_PTE_TMZ; 	cpu_addr = &job->ibs[0].ptr[num_dw]; 	if (mem->mem_type == TTM_PL_TT) {		dma_addr_t *dma_addr; 		dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT];		r = amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags,				    cpu_addr);		if (r)			goto error_free;	} else {		dma_addr_t dma_address; 		dma_address = mm_cur->start;		dma_address += adev->vm_manager.vram_base_offset; 		for (i = 0; i < num_pages; ++i) {			r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,					    &dma_address, flags, cpu_addr);			if (r)				goto error_free; 			dma_address += PAGE_SIZE;		}	} 	r = amdgpu_job_submit(job, &adev->mman.entity,			      AMDGPU_FENCE_OWNER_UNDEFINED, &fence);	if (r)		goto error_free; 	dma_fence_put(fence); 	return r; error_free:	amdgpu_job_free(job);	return r;} /** * amdgpu_copy_ttm_mem_to_mem - Helper function for copy * @adev: amdgpu device * @src: buffer/address where to read from * @dst: buffer/address where to write to * @size: number of bytes to copy * @tmz: if a secure copy should be used * @resv: resv object to sync to * @f: Returns the last fence if multiple jobs are submitted. * * The function copies @size bytes from {src->mem + src->offset} to * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a * move and different for a BO to BO copy. * */int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,			       const struct amdgpu_copy_mem *src,			       const struct amdgpu_copy_mem *dst,			       uint64_t size, bool tmz,			       struct dma_resv *resv,			       struct dma_fence **f){	const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *					AMDGPU_GPU_PAGE_SIZE); 	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;	struct amdgpu_res_cursor src_mm, dst_mm;	struct dma_fence *fence = NULL;	int r = 0; 	if (!adev->mman.buffer_funcs_enabled) {		DRM_ERROR("Trying to move memory with ring turned off.\n");		return -EINVAL;	} 	amdgpu_res_first(src->mem, src->offset, size, &src_mm);	amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm); 	mutex_lock(&adev->mman.gtt_window_lock);	while (src_mm.remaining) {		uint32_t src_page_offset = src_mm.start & ~PAGE_MASK;		uint32_t dst_page_offset = dst_mm.start & ~PAGE_MASK;		struct dma_fence *next;		uint32_t cur_size;		uint64_t from, to; 		/* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst		 * begins at an offset, then adjust the size accordingly		 */		cur_size = max(src_page_offset, dst_page_offset);		cur_size = min(min3(src_mm.size, dst_mm.size, size),			       (uint64_t)(GTT_MAX_BYTES - cur_size)); 		/* Map src to window 0 and dst to window 1. */		r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm,					  PFN_UP(cur_size + src_page_offset),					  0, ring, tmz, &from);		if (r)			goto error; 		r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm,					  PFN_UP(cur_size + dst_page_offset),					  1, ring, tmz, &to);		if (r)			goto error; 		r = amdgpu_copy_buffer(ring, from, to, cur_size,				       resv, &next, false, true, tmz);		if (r)			goto error; 		dma_fence_put(fence);		fence = next; 		amdgpu_res_next(&src_mm, cur_size);		amdgpu_res_next(&dst_mm, cur_size);	}error:	mutex_unlock(&adev->mman.gtt_window_lock);	if (f)		*f = dma_fence_get(fence);	dma_fence_put(fence);	return r;} /* * amdgpu_move_blit - Copy an entire buffer to another buffer * * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to * help move buffers to and from VRAM. */static int amdgpu_move_blit(struct ttm_buffer_object *bo,			    bool evict,			    struct ttm_resource *new_mem,			    struct ttm_resource *old_mem){	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);	struct amdgpu_copy_mem src, dst;	struct dma_fence *fence = NULL;	int r; 	src.bo = bo;	dst.bo = bo;	src.mem = old_mem;	dst.mem = new_mem;	src.offset = 0;	dst.offset = 0; 	r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,				       new_mem->num_pages << PAGE_SHIFT,				       amdgpu_bo_encrypted(abo),				       bo->base.resv, &fence);	if (r)		goto error; 	/* clear the space being freed */	if (old_mem->mem_type == TTM_PL_VRAM &&	    (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {		struct dma_fence *wipe_fence = NULL; 		r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,				       NULL, &wipe_fence);		if (r) {			goto error;		} else if (wipe_fence) {			dma_fence_put(fence);			fence = wipe_fence;		}	} 	/* Always block for VM page tables before committing the new location */	if (bo->type == ttm_bo_type_kernel)		r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);	else		r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);	dma_fence_put(fence);	return r; error:	if (fence)		dma_fence_wait(fence, false);	dma_fence_put(fence);	return r;} /* * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy * * Called by amdgpu_bo_move() */static bool amdgpu_mem_visible(struct amdgpu_device *adev,			       struct ttm_resource *mem){	uint64_t mem_size = (u64)mem->num_pages << PAGE_SHIFT;	struct amdgpu_res_cursor cursor; 	if (mem->mem_type == TTM_PL_SYSTEM ||	    mem->mem_type == TTM_PL_TT)		return true;	if (mem->mem_type != TTM_PL_VRAM)		return false; 	amdgpu_res_first(mem, 0, mem_size, &cursor); 	/* ttm_resource_ioremap only supports contiguous memory */	if (cursor.size != mem_size)		return false; 	return cursor.start + cursor.size <= adev->gmc.visible_vram_size;} /* * amdgpu_bo_move - Move a buffer object to a new memory location * * Called by ttm_bo_handle_move_mem() */static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,			  struct ttm_operation_ctx *ctx,			  struct ttm_resource *new_mem,			  struct ttm_place *hop){	struct amdgpu_device *adev;	struct amdgpu_bo *abo;	struct ttm_resource *old_mem = &bo->mem;	int r; 	if (new_mem->mem_type == TTM_PL_TT) {		r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem);		if (r)			return r;	} 	/* Can't move a pinned BO */	abo = ttm_to_amdgpu_bo(bo);	if (WARN_ON_ONCE(abo->tbo.pin_count > 0))		return -EINVAL; 	adev = amdgpu_ttm_adev(bo->bdev); 	if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {		ttm_bo_move_null(bo, new_mem);		goto out;	}	if (old_mem->mem_type == TTM_PL_SYSTEM &&	    new_mem->mem_type == TTM_PL_TT) {		ttm_bo_move_null(bo, new_mem);		goto out;	}	if (old_mem->mem_type == TTM_PL_TT &&	    new_mem->mem_type == TTM_PL_SYSTEM) {

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