/* * Copyright 2018 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * */#include <linux/debugfs.h>#include <linux/list.h>#include <linux/module.h>#include <linux/uaccess.h>#include <linux/reboot.h>#include <linux/syscalls.h> #include "amdgpu.h"#include "amdgpu_ras.h"#include "amdgpu_atomfirmware.h"#include "amdgpu_xgmi.h"#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" const char *ras_error_string[] = { "none", "parity", "single_correctable", "multi_uncorrectable", "poison",}; const char *ras_block_string[] = { "umc", "sdma", "gfx", "mmhub", "athub", "pcie_bif", "hdp", "xgmi_wafl", "df", "smn", "sem", "mp0", "mp1", "fuse",}; #define ras_err_str(i) (ras_error_string[ffs(i)])#define ras_block_str(i) (ras_block_string[i]) #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS 1#define AMDGPU_RAS_FLAG_INIT_NEED_RESET 2#define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS) /* inject address is 52 bits */#define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52) enum amdgpu_ras_retire_page_reservation { AMDGPU_RAS_RETIRE_PAGE_RESERVED, AMDGPU_RAS_RETIRE_PAGE_PENDING, AMDGPU_RAS_RETIRE_PAGE_FAULT,}; atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0); static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, uint64_t addr); void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready){ if (adev && amdgpu_ras_get_context(adev)) amdgpu_ras_get_context(adev)->error_query_ready = ready;} bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev){ if (adev && amdgpu_ras_get_context(adev)) return amdgpu_ras_get_context(adev)->error_query_ready; return false;} static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf, size_t size, loff_t *pos){ struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private; struct ras_query_if info = { .head = obj->head, }; ssize_t s; char val[128]; if (amdgpu_ras_error_query(obj->adev, &info)) return -EINVAL; s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n", "ue", info.ue_count, "ce", info.ce_count); if (*pos >= s) return 0; s -= *pos; s = min_t(u64, s, size); if (copy_to_user(buf, &val[*pos], s)) return -EINVAL; *pos += s; return s;} static const struct file_operations amdgpu_ras_debugfs_ops = { .owner = THIS_MODULE, .read = amdgpu_ras_debugfs_read, .write = NULL, .llseek = default_llseek}; static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id){ int i; for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) { *block_id = i; if (strcmp(name, ras_block_str(i)) == 0) return 0; } return -EINVAL;} static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f, const char __user *buf, size_t size, loff_t *pos, struct ras_debug_if *data){ ssize_t s = min_t(u64, 64, size); char str[65]; char block_name[33]; char err[9] = "ue"; int op = -1; int block_id; uint32_t sub_block; u64 address, value; if (*pos) return -EINVAL; *pos = size; memset(str, 0, sizeof(str)); memset(data, 0, sizeof(*data)); if (copy_from_user(str, buf, s)) return -EINVAL; if (sscanf(str, "disable %32s", block_name) == 1) op = 0; else if (sscanf(str, "enable %32s %8s", block_name, err) == 2) op = 1; else if (sscanf(str, "inject %32s %8s", block_name, err) == 2) op = 2; else if (str[0] && str[1] && str[2] && str[3]) /* ascii string, but commands are not matched. */ return -EINVAL; if (op != -1) { if (amdgpu_ras_find_block_id_by_name(block_name, &block_id)) return -EINVAL; data->head.block = block_id; /* only ue and ce errors are supported */ if (!memcmp("ue", err, 2)) data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; else if (!memcmp("ce", err, 2)) data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE; else return -EINVAL; data->op = op; if (op == 2) { if (sscanf(str, "%*s %*s %*s %u %llu %llu", &sub_block, &address, &value) != 3) if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx", &sub_block, &address, &value) != 3) return -EINVAL; data->head.sub_block_index = sub_block; data->inject.address = address; data->inject.value = value; } } else { if (size < sizeof(*data)) return -EINVAL; if (copy_from_user(data, buf, sizeof(*data))) return -EINVAL; } return 0;} /** * DOC: AMDGPU RAS debugfs control interface * * It accepts struct ras_debug_if who has two members. * * First member: ras_debug_if::head or ras_debug_if::inject. * * head is used to indicate which IP block will be under control. * * head has four members, they are block, type, sub_block_index, name. * block: which IP will be under control. * type: what kind of error will be enabled/disabled/injected. * sub_block_index: some IPs have subcomponets. say, GFX, sDMA. * name: the name of IP. * * inject has two more members than head, they are address, value. * As their names indicate, inject operation will write the * value to the address. * * The second member: struct ras_debug_if::op. * It has three kinds of operations. * * - 0: disable RAS on the block. Take ::head as its data. * - 1: enable RAS on the block. Take ::head as its data. * - 2: inject errors on the block. Take ::inject as its data. * * How to use the interface? * * Programs * * Copy the struct ras_debug_if in your codes and initialize it. * Write the struct to the control node. * * Shells * * .. code-block:: bash * * echo op block [error [sub_block address value]] > .../ras/ras_ctrl * * Parameters: * * op: disable, enable, inject * disable: only block is needed * enable: block and error are needed * inject: error, address, value are needed * block: umc, sdma, gfx, ......... * see ras_block_string[] for details * error: ue, ce * ue: multi_uncorrectable * ce: single_correctable * sub_block: * sub block index, pass 0 if there is no sub block * * here are some examples for bash commands: * * .. code-block:: bash * * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl * echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl * * How to check the result? * * For disable/enable, please check ras features at * /sys/class/drm/card[0/1/2...]/device/ras/features * * For inject, please check corresponding err count at * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count * * .. note:: * Operations are only allowed on blocks which are supported. * Please check ras mask at /sys/module/amdgpu/parameters/ras_mask * to see which blocks support RAS on a particular asic. * */static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf, size_t size, loff_t *pos){ struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; struct ras_debug_if data; int ret = 0; if (!amdgpu_ras_get_error_query_ready(adev)) { dev_warn(adev->dev, "RAS WARN: error injection " "currently inaccessible\n"); return size; } ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data); if (ret) return -EINVAL; if (!amdgpu_ras_is_supported(adev, data.head.block)) return -EINVAL; switch (data.op) { case 0: ret = amdgpu_ras_feature_enable(adev, &data.head, 0); break; case 1: ret = amdgpu_ras_feature_enable(adev, &data.head, 1); break; case 2: if ((data.inject.address >= adev->gmc.mc_vram_size) || (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) { ret = -EINVAL; break; } /* umc ce/ue error injection for a bad page is not allowed */ if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) && amdgpu_ras_check_bad_page(adev, data.inject.address)) { dev_warn(adev->dev, "RAS WARN: 0x%llx has been marked " "as bad before error injection!\n", data.inject.address); break; } /* data.inject.address is offset instead of absolute gpu address */ ret = amdgpu_ras_error_inject(adev, &data.inject); break; default: ret = -EINVAL; break; } if (ret) return -EINVAL; return size;} /** * DOC: AMDGPU RAS debugfs EEPROM table reset interface * * Some boards contain an EEPROM which is used to persistently store a list of * bad pages which experiences ECC errors in vram. This interface provides * a way to reset the EEPROM, e.g., after testing error injection. * * Usage: * * .. code-block:: bash * * echo 1 > ../ras/ras_eeprom_reset * * will reset EEPROM table to 0 entries. * */static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, const char __user *buf, size_t size, loff_t *pos){ struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; int ret; ret = amdgpu_ras_eeprom_reset_table(&adev->psp.ras.ras->eeprom_control); return ret == 1 ? size : -EIO;} static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = { .owner = THIS_MODULE, .read = NULL, .write = amdgpu_ras_debugfs_ctrl_write, .llseek = default_llseek}; static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = { .owner = THIS_MODULE, .read = NULL, .write = amdgpu_ras_debugfs_eeprom_write, .llseek = default_llseek}; /** * DOC: AMDGPU RAS sysfs Error Count Interface * * It allows the user to read the error count for each IP block on the gpu through * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count * * It outputs the multiple lines which report the uncorrected (ue) and corrected * (ce) error counts. * * The format of one line is below, * * [ce|ue]: count * * Example: * * .. code-block:: bash * * ue: 0 * ce: 1 * */static ssize_t amdgpu_ras_sysfs_read(struct device *dev, struct device_attribute *attr, char *buf){ struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr); struct ras_query_if info = { .head = obj->head, }; if (!amdgpu_ras_get_error_query_ready(obj->adev)) return snprintf(buf, PAGE_SIZE, "Query currently inaccessible\n"); if (amdgpu_ras_error_query(obj->adev, &info)) return -EINVAL; return snprintf(buf, PAGE_SIZE, "%s: %lu\n%s: %lu\n", "ue", info.ue_count, "ce", info.ce_count);} /* obj begin */ #define get_obj(obj) do { (obj)->use++; } while (0)#define alive_obj(obj) ((obj)->use) static inline void put_obj(struct ras_manager *obj){ if (obj && --obj->use == 0) list_del(&obj->node); if (obj && obj->use < 0) { DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name); }} /* make one obj and return it. */static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev, struct ras_common_if *head){ struct amdgpu_ras *con = amdgpu_ras_get_context(adev); struct ras_manager *obj; if (!con) return NULL; if (head->block >= AMDGPU_RAS_BLOCK_COUNT) return NULL; obj = &con->objs[head->block]; /* already exist. return obj? */ if (alive_obj(obj)) return NULL; obj->head = *head; obj->adev = adev; list_add(&obj->node, &con->head); get_obj(obj); return obj;} /* return an obj equal to head, or the first when head is NULL */struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, struct ras_common_if *head){ struct amdgpu_ras *con = amdgpu_ras_get_context(adev); struct ras_manager *obj; int i; if (!con) return NULL; if (head) { if (head->block >= AMDGPU_RAS_BLOCK_COUNT) return NULL; obj = &con->objs[head->block]; if (alive_obj(obj)) { WARN_ON(head->block != obj->head.block); return obj; } } else { for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) { obj = &con->objs[i]; if (alive_obj(obj)) { WARN_ON(i != obj->head.block); return obj; } } } Lines 1–500 of 2131. Load more
/* * Copyright 2018 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * */ #include <linux/debugfs.h> #include <linux/list.h> #include <linux/module.h> #include <linux/uaccess.h> #include <linux/reboot.h> #include <linux/syscalls.h> #include "amdgpu.h" #include "amdgpu_ras.h" #include "amdgpu_atomfirmware.h" #include "amdgpu_xgmi.h" #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" const char *ras_error_string[] = { "none", "parity", "single_correctable", "multi_uncorrectable", "poison", }; const char *ras_block_string[] = { "umc", "sdma", "gfx", "mmhub", "athub", "pcie_bif", "hdp", "xgmi_wafl", "df", "smn", "sem", "mp0", "mp1", "fuse", }; #define ras_err_str(i) (ras_error_string[ffs(i)]) #define ras_block_str(i) (ras_block_string[i]) #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS 1 #define AMDGPU_RAS_FLAG_INIT_NEED_RESET 2 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS) /* inject address is 52 bits */ #define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52) enum amdgpu_ras_retire_page_reservation { AMDGPU_RAS_RETIRE_PAGE_RESERVED, AMDGPU_RAS_RETIRE_PAGE_PENDING, AMDGPU_RAS_RETIRE_PAGE_FAULT, }; atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0); static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, uint64_t addr); void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready) { if (adev && amdgpu_ras_get_context(adev)) amdgpu_ras_get_context(adev)->error_query_ready = ready; } bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev) { if (adev && amdgpu_ras_get_context(adev)) return amdgpu_ras_get_context(adev)->error_query_ready; return false; } static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf, size_t size, loff_t *pos) { struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private; struct ras_query_if info = { .head = obj->head, }; ssize_t s; char val[128]; if (amdgpu_ras_error_query(obj->adev, &info)) return -EINVAL; s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n", "ue", info.ue_count, "ce", info.ce_count); if (*pos >= s) return 0; s -= *pos; s = min_t(u64, s, size); if (copy_to_user(buf, &val[*pos], s)) return -EINVAL; *pos += s; return s; } static const struct file_operations amdgpu_ras_debugfs_ops = { .owner = THIS_MODULE, .read = amdgpu_ras_debugfs_read, .write = NULL, .llseek = default_llseek }; static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id) { int i; for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) { *block_id = i; if (strcmp(name, ras_block_str(i)) == 0) return 0; } return -EINVAL; } static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f, const char __user *buf, size_t size, loff_t *pos, struct ras_debug_if *data) { ssize_t s = min_t(u64, 64, size); char str[65]; char block_name[33]; char err[9] = "ue"; int op = -1; int block_id; uint32_t sub_block; u64 address, value; if (*pos) return -EINVAL; *pos = size; memset(str, 0, sizeof(str)); memset(data, 0, sizeof(*data)); if (copy_from_user(str, buf, s)) return -EINVAL; if (sscanf(str, "disable %32s", block_name) == 1) op = 0; else if (sscanf(str, "enable %32s %8s", block_name, err) == 2) op = 1; else if (sscanf(str, "inject %32s %8s", block_name, err) == 2) op = 2; else if (str[0] && str[1] && str[2] && str[3]) /* ascii string, but commands are not matched. */ return -EINVAL; if (op != -1) { if (amdgpu_ras_find_block_id_by_name(block_name, &block_id)) return -EINVAL; data->head.block = block_id; /* only ue and ce errors are supported */ if (!memcmp("ue", err, 2)) data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; else if (!memcmp("ce", err, 2)) data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE; else return -EINVAL; data->op = op; if (op == 2) { if (sscanf(str, "%*s %*s %*s %u %llu %llu", &sub_block, &address, &value) != 3) if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx", &sub_block, &address, &value) != 3) return -EINVAL; data->head.sub_block_index = sub_block; data->inject.address = address; data->inject.value = value; } } else { if (size < sizeof(*data)) return -EINVAL; if (copy_from_user(data, buf, sizeof(*data))) return -EINVAL; } return 0; } /** * DOC: AMDGPU RAS debugfs control interface * * It accepts struct ras_debug_if who has two members. * * First member: ras_debug_if::head or ras_debug_if::inject. * * head is used to indicate which IP block will be under control. * * head has four members, they are block, type, sub_block_index, name. * block: which IP will be under control. * type: what kind of error will be enabled/disabled/injected. * sub_block_index: some IPs have subcomponets. say, GFX, sDMA. * name: the name of IP. * * inject has two more members than head, they are address, value. * As their names indicate, inject operation will write the * value to the address. * * The second member: struct ras_debug_if::op. * It has three kinds of operations. * * - 0: disable RAS on the block. Take ::head as its data. * - 1: enable RAS on the block. Take ::head as its data. * - 2: inject errors on the block. Take ::inject as its data. * * How to use the interface? * * Programs * * Copy the struct ras_debug_if in your codes and initialize it. * Write the struct to the control node. * * Shells * * .. code-block:: bash * * echo op block [error [sub_block address value]] > .../ras/ras_ctrl * * Parameters: * * op: disable, enable, inject * disable: only block is needed * enable: block and error are needed * inject: error, address, value are needed * block: umc, sdma, gfx, ......... * see ras_block_string[] for details * error: ue, ce * ue: multi_uncorrectable * ce: single_correctable * sub_block: * sub block index, pass 0 if there is no sub block * * here are some examples for bash commands: * * .. code-block:: bash * * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl * echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl * * How to check the result? * * For disable/enable, please check ras features at * /sys/class/drm/card[0/1/2...]/device/ras/features * * For inject, please check corresponding err count at * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count * * .. note:: * Operations are only allowed on blocks which are supported. * Please check ras mask at /sys/module/amdgpu/parameters/ras_mask * to see which blocks support RAS on a particular asic. * */ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf, size_t size, loff_t *pos) { struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; struct ras_debug_if data; int ret = 0; if (!amdgpu_ras_get_error_query_ready(adev)) { dev_warn(adev->dev, "RAS WARN: error injection " "currently inaccessible\n"); return size; } ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data); if (ret) return -EINVAL; if (!amdgpu_ras_is_supported(adev, data.head.block)) return -EINVAL; switch (data.op) { case 0: ret = amdgpu_ras_feature_enable(adev, &data.head, 0); break; case 1: ret = amdgpu_ras_feature_enable(adev, &data.head, 1); break; case 2: if ((data.inject.address >= adev->gmc.mc_vram_size) || (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) { ret = -EINVAL; break; } /* umc ce/ue error injection for a bad page is not allowed */ if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) && amdgpu_ras_check_bad_page(adev, data.inject.address)) { dev_warn(adev->dev, "RAS WARN: 0x%llx has been marked " "as bad before error injection!\n", data.inject.address); break; } /* data.inject.address is offset instead of absolute gpu address */ ret = amdgpu_ras_error_inject(adev, &data.inject); break; default: ret = -EINVAL; break; } if (ret) return -EINVAL; return size; } /** * DOC: AMDGPU RAS debugfs EEPROM table reset interface * * Some boards contain an EEPROM which is used to persistently store a list of * bad pages which experiences ECC errors in vram. This interface provides * a way to reset the EEPROM, e.g., after testing error injection. * * Usage: * * .. code-block:: bash * * echo 1 > ../ras/ras_eeprom_reset * * will reset EEPROM table to 0 entries. * */ static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, const char __user *buf, size_t size, loff_t *pos) { struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; int ret; ret = amdgpu_ras_eeprom_reset_table(&adev->psp.ras.ras->eeprom_control); return ret == 1 ? size : -EIO; } static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = { .owner = THIS_MODULE, .read = NULL, .write = amdgpu_ras_debugfs_ctrl_write, .llseek = default_llseek }; static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = { .owner = THIS_MODULE, .read = NULL, .write = amdgpu_ras_debugfs_eeprom_write, .llseek = default_llseek }; /** * DOC: AMDGPU RAS sysfs Error Count Interface * * It allows the user to read the error count for each IP block on the gpu through * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count * * It outputs the multiple lines which report the uncorrected (ue) and corrected * (ce) error counts. * * The format of one line is below, * * [ce|ue]: count * * Example: * * .. code-block:: bash * * ue: 0 * ce: 1 * */ static ssize_t amdgpu_ras_sysfs_read(struct device *dev, struct device_attribute *attr, char *buf) { struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr); struct ras_query_if info = { .head = obj->head, }; if (!amdgpu_ras_get_error_query_ready(obj->adev)) return snprintf(buf, PAGE_SIZE, "Query currently inaccessible\n"); if (amdgpu_ras_error_query(obj->adev, &info)) return -EINVAL; return snprintf(buf, PAGE_SIZE, "%s: %lu\n%s: %lu\n", "ue", info.ue_count, "ce", info.ce_count); } /* obj begin */ #define get_obj(obj) do { (obj)->use++; } while (0) #define alive_obj(obj) ((obj)->use) static inline void put_obj(struct ras_manager *obj) { if (obj && --obj->use == 0) list_del(&obj->node); if (obj && obj->use < 0) { DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name); } } /* make one obj and return it. */ static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev, struct ras_common_if *head) { struct amdgpu_ras *con = amdgpu_ras_get_context(adev); struct ras_manager *obj; if (!con) return NULL; if (head->block >= AMDGPU_RAS_BLOCK_COUNT) return NULL; obj = &con->objs[head->block]; /* already exist. return obj? */ if (alive_obj(obj)) return NULL; obj->head = *head; obj->adev = adev; list_add(&obj->node, &con->head); get_obj(obj); return obj; } /* return an obj equal to head, or the first when head is NULL */ struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, struct ras_common_if *head) { struct amdgpu_ras *con = amdgpu_ras_get_context(adev); struct ras_manager *obj; int i; if (!con) return NULL; if (head) { if (head->block >= AMDGPU_RAS_BLOCK_COUNT) return NULL; obj = &con->objs[head->block]; if (alive_obj(obj)) { WARN_ON(head->block != obj->head.block); return obj; } } else { for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) { obj = &con->objs[i]; if (alive_obj(obj)) { WARN_ON(i != obj->head.block); return obj; } } }