/* * Copyright 2008 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Author: Stanislaw Skowronek */ #include <linux/module.h>#include <linux/sched.h>#include <linux/slab.h>#include <linux/string_helpers.h> #include <asm/unaligned.h> #include <drm/drm_util.h> #define ATOM_DEBUG #include "atomfirmware.h"#include "atom.h"#include "atom-names.h"#include "atom-bits.h"#include "amdgpu.h" #define ATOM_COND_ABOVE 0#define ATOM_COND_ABOVEOREQUAL 1#define ATOM_COND_ALWAYS 2#define ATOM_COND_BELOW 3#define ATOM_COND_BELOWOREQUAL 4#define ATOM_COND_EQUAL 5#define ATOM_COND_NOTEQUAL 6 #define ATOM_PORT_ATI 0#define ATOM_PORT_PCI 1#define ATOM_PORT_SYSIO 2 #define ATOM_UNIT_MICROSEC 0#define ATOM_UNIT_MILLISEC 1 #define PLL_INDEX 2#define PLL_DATA 3 #define ATOM_CMD_TIMEOUT_SEC 20 typedef struct { struct atom_context *ctx; uint32_t *ps, *ws; int ps_shift; uint16_t start; unsigned last_jump; unsigned long last_jump_jiffies; bool abort;} atom_exec_context; int amdgpu_atom_debug;static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t *params);int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t *params); static uint32_t atom_arg_mask[8] = { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000, 0xFF000000 };static int atom_arg_shift[8] = { 0, 0, 8, 16, 0, 8, 16, 24 }; static int atom_dst_to_src[8][4] = { /* translate destination alignment field to the source alignment encoding */ {0, 0, 0, 0}, {1, 2, 3, 0}, {1, 2, 3, 0}, {1, 2, 3, 0}, {4, 5, 6, 7}, {4, 5, 6, 7}, {4, 5, 6, 7}, {4, 5, 6, 7},};static int atom_def_dst[8] = { 0, 0, 1, 2, 0, 1, 2, 3 }; static int debug_depth;#ifdef ATOM_DEBUGstatic void debug_print_spaces(int n){ while (n--) printk(" ");} #define DEBUG(...) do if (amdgpu_atom_debug) { printk(KERN_DEBUG __VA_ARGS__); } while (0)#define SDEBUG(...) do if (amdgpu_atom_debug) { printk(KERN_DEBUG); debug_print_spaces(debug_depth); printk(__VA_ARGS__); } while (0)#else#define DEBUG(...) do { } while (0)#define SDEBUG(...) do { } while (0)#endif static uint32_t atom_iio_execute(struct atom_context *ctx, int base, uint32_t index, uint32_t data){ uint32_t temp = 0xCDCDCDCD; while (1) switch (CU8(base)) { case ATOM_IIO_NOP: base++; break; case ATOM_IIO_READ: temp = ctx->card->reg_read(ctx->card, CU16(base + 1)); base += 3; break; case ATOM_IIO_WRITE: ctx->card->reg_write(ctx->card, CU16(base + 1), temp); base += 3; break; case ATOM_IIO_CLEAR: temp &= ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base + 2)); base += 3; break; case ATOM_IIO_SET: temp |= (0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base + 2); base += 3; break; case ATOM_IIO_MOVE_INDEX: temp &= ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base + 3)); temp |= ((index >> CU8(base + 2)) & (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + 3); base += 4; break; case ATOM_IIO_MOVE_DATA: temp &= ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base + 3)); temp |= ((data >> CU8(base + 2)) & (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + 3); base += 4; break; case ATOM_IIO_MOVE_ATTR: temp &= ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base + 3)); temp |= ((ctx-> io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 - CU8 (base + 1)))) << CU8(base + 3); base += 4; break; case ATOM_IIO_END: return temp; default: pr_info("Unknown IIO opcode\n"); return 0; }} static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr, int *ptr, uint32_t *saved, int print){ uint32_t idx, val = 0xCDCDCDCD, align, arg; struct atom_context *gctx = ctx->ctx; arg = attr & 7; align = (attr >> 3) & 7; switch (arg) { case ATOM_ARG_REG: idx = U16(*ptr); (*ptr) += 2; if (print) DEBUG("REG[0x%04X]", idx); idx += gctx->reg_block; switch (gctx->io_mode) { case ATOM_IO_MM: val = gctx->card->reg_read(gctx->card, idx); break; case ATOM_IO_PCI: pr_info("PCI registers are not implemented\n"); return 0; case ATOM_IO_SYSIO: pr_info("SYSIO registers are not implemented\n"); return 0; default: if (!(gctx->io_mode & 0x80)) { pr_info("Bad IO mode\n"); return 0; } if (!gctx->iio[gctx->io_mode & 0x7F]) { pr_info("Undefined indirect IO read method %d\n", gctx->io_mode & 0x7F); return 0; } val = atom_iio_execute(gctx, gctx->iio[gctx->io_mode & 0x7F], idx, 0); } break; case ATOM_ARG_PS: idx = U8(*ptr); (*ptr)++; /* get_unaligned_le32 avoids unaligned accesses from atombios * tables, noticed on a DEC Alpha. */ val = get_unaligned_le32((u32 *)&ctx->ps[idx]); if (print) DEBUG("PS[0x%02X,0x%04X]", idx, val); break; case ATOM_ARG_WS: idx = U8(*ptr); (*ptr)++; if (print) DEBUG("WS[0x%02X]", idx); switch (idx) { case ATOM_WS_QUOTIENT: val = gctx->divmul[0]; break; case ATOM_WS_REMAINDER: val = gctx->divmul[1]; break; case ATOM_WS_DATAPTR: val = gctx->data_block; break; case ATOM_WS_SHIFT: val = gctx->shift; break; case ATOM_WS_OR_MASK: val = 1 << gctx->shift; break; case ATOM_WS_AND_MASK: val = ~(1 << gctx->shift); break; case ATOM_WS_FB_WINDOW: val = gctx->fb_base; break; case ATOM_WS_ATTRIBUTES: val = gctx->io_attr; break; case ATOM_WS_REGPTR: val = gctx->reg_block; break; default: val = ctx->ws[idx]; } break; case ATOM_ARG_ID: idx = U16(*ptr); (*ptr) += 2; if (print) { if (gctx->data_block) DEBUG("ID[0x%04X+%04X]", idx, gctx->data_block); else DEBUG("ID[0x%04X]", idx); } val = U32(idx + gctx->data_block); break; case ATOM_ARG_FB: idx = U8(*ptr); (*ptr)++; if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) { DRM_ERROR("ATOM: fb read beyond scratch region: %d vs. %d\n", gctx->fb_base + (idx * 4), gctx->scratch_size_bytes); val = 0; } else val = gctx->scratch[(gctx->fb_base / 4) + idx]; if (print) DEBUG("FB[0x%02X]", idx); break; case ATOM_ARG_IMM: switch (align) { case ATOM_SRC_DWORD: val = U32(*ptr); (*ptr) += 4; if (print) DEBUG("IMM 0x%08X\n", val); return val; case ATOM_SRC_WORD0: case ATOM_SRC_WORD8: case ATOM_SRC_WORD16: val = U16(*ptr); (*ptr) += 2; if (print) DEBUG("IMM 0x%04X\n", val); return val; case ATOM_SRC_BYTE0: case ATOM_SRC_BYTE8: case ATOM_SRC_BYTE16: case ATOM_SRC_BYTE24: val = U8(*ptr); (*ptr)++; if (print) DEBUG("IMM 0x%02X\n", val); return val; } return 0; case ATOM_ARG_PLL: idx = U8(*ptr); (*ptr)++; if (print) DEBUG("PLL[0x%02X]", idx); val = gctx->card->pll_read(gctx->card, idx); break; case ATOM_ARG_MC: idx = U8(*ptr); (*ptr)++; if (print) DEBUG("MC[0x%02X]", idx); val = gctx->card->mc_read(gctx->card, idx); break; } if (saved) *saved = val; val &= atom_arg_mask[align]; val >>= atom_arg_shift[align]; if (print) switch (align) { case ATOM_SRC_DWORD: DEBUG(".[31:0] -> 0x%08X\n", val); break; case ATOM_SRC_WORD0: DEBUG(".[15:0] -> 0x%04X\n", val); break; case ATOM_SRC_WORD8: DEBUG(".[23:8] -> 0x%04X\n", val); break; case ATOM_SRC_WORD16: DEBUG(".[31:16] -> 0x%04X\n", val); break; case ATOM_SRC_BYTE0: DEBUG(".[7:0] -> 0x%02X\n", val); break; case ATOM_SRC_BYTE8: DEBUG(".[15:8] -> 0x%02X\n", val); break; case ATOM_SRC_BYTE16: DEBUG(".[23:16] -> 0x%02X\n", val); break; case ATOM_SRC_BYTE24: DEBUG(".[31:24] -> 0x%02X\n", val); break; } return val;} static void atom_skip_src_int(atom_exec_context *ctx, uint8_t attr, int *ptr){ uint32_t align = (attr >> 3) & 7, arg = attr & 7; switch (arg) { case ATOM_ARG_REG: case ATOM_ARG_ID: (*ptr) += 2; break; case ATOM_ARG_PLL: case ATOM_ARG_MC: case ATOM_ARG_PS: case ATOM_ARG_WS: case ATOM_ARG_FB: (*ptr)++; break; case ATOM_ARG_IMM: switch (align) { case ATOM_SRC_DWORD: (*ptr) += 4; return; case ATOM_SRC_WORD0: case ATOM_SRC_WORD8: case ATOM_SRC_WORD16: (*ptr) += 2; return; case ATOM_SRC_BYTE0: case ATOM_SRC_BYTE8: case ATOM_SRC_BYTE16: case ATOM_SRC_BYTE24: (*ptr)++; return; } return; }} static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr){ return atom_get_src_int(ctx, attr, ptr, NULL, 1);} static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr){ uint32_t val = 0xCDCDCDCD; switch (align) { case ATOM_SRC_DWORD: val = U32(*ptr); (*ptr) += 4; break; case ATOM_SRC_WORD0: case ATOM_SRC_WORD8: case ATOM_SRC_WORD16: val = U16(*ptr); (*ptr) += 2; break; case ATOM_SRC_BYTE0: case ATOM_SRC_BYTE8: case ATOM_SRC_BYTE16: case ATOM_SRC_BYTE24: val = U8(*ptr); (*ptr)++; break; } return val;} static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr, uint32_t *saved, int print){ return atom_get_src_int(ctx, arg | atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3] << 3, ptr, saved, print);} static void atom_skip_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr){ atom_skip_src_int(ctx, arg | atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3] << 3, ptr);} static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr, uint32_t val, uint32_t saved){ uint32_t align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3], old_val = val, idx; struct atom_context *gctx = ctx->ctx; old_val &= atom_arg_mask[align] >> atom_arg_shift[align]; val <<= atom_arg_shift[align]; val &= atom_arg_mask[align]; saved &= ~atom_arg_mask[align]; val |= saved; switch (arg) { case ATOM_ARG_REG: idx = U16(*ptr); (*ptr) += 2; DEBUG("REG[0x%04X]", idx); idx += gctx->reg_block; switch (gctx->io_mode) { case ATOM_IO_MM: if (idx == 0) gctx->card->reg_write(gctx->card, idx, val << 2); else gctx->card->reg_write(gctx->card, idx, val); break; case ATOM_IO_PCI: pr_info("PCI registers are not implemented\n"); return; case ATOM_IO_SYSIO: pr_info("SYSIO registers are not implemented\n"); return; default: if (!(gctx->io_mode & 0x80)) { pr_info("Bad IO mode\n"); return; } if (!gctx->iio[gctx->io_mode & 0xFF]) { pr_info("Undefined indirect IO write method %d\n", gctx->io_mode & 0x7F); return; } atom_iio_execute(gctx, gctx->iio[gctx->io_mode & 0xFF], idx, val); } break; case ATOM_ARG_PS: idx = U8(*ptr); (*ptr)++; DEBUG("PS[0x%02X]", idx); ctx->ps[idx] = cpu_to_le32(val); break;Lines 1–500 of 1601. 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/* * Copyright 2008 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Author: Stanislaw Skowronek */ #include <linux/module.h> #include <linux/sched.h> #include <linux/slab.h> #include <linux/string_helpers.h> #include <asm/unaligned.h> #include <drm/drm_util.h> #define ATOM_DEBUG #include "atomfirmware.h" #include "atom.h" #include "atom-names.h" #include "atom-bits.h" #include "amdgpu.h" #define ATOM_COND_ABOVE 0 #define ATOM_COND_ABOVEOREQUAL 1 #define ATOM_COND_ALWAYS 2 #define ATOM_COND_BELOW 3 #define ATOM_COND_BELOWOREQUAL 4 #define ATOM_COND_EQUAL 5 #define ATOM_COND_NOTEQUAL 6 #define ATOM_PORT_ATI 0 #define ATOM_PORT_PCI 1 #define ATOM_PORT_SYSIO 2 #define ATOM_UNIT_MICROSEC 0 #define ATOM_UNIT_MILLISEC 1 #define PLL_INDEX 2 #define PLL_DATA 3 #define ATOM_CMD_TIMEOUT_SEC 20 typedef struct { struct atom_context *ctx; uint32_t *ps, *ws; int ps_shift; uint16_t start; unsigned last_jump; unsigned long last_jump_jiffies; bool abort; } atom_exec_context; int amdgpu_atom_debug; static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t *params); int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t *params); static uint32_t atom_arg_mask[8] = { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000, 0xFF000000 }; static int atom_arg_shift[8] = { 0, 0, 8, 16, 0, 8, 16, 24 }; static int atom_dst_to_src[8][4] = { /* translate destination alignment field to the source alignment encoding */ {0, 0, 0, 0}, {1, 2, 3, 0}, {1, 2, 3, 0}, {1, 2, 3, 0}, {4, 5, 6, 7}, {4, 5, 6, 7}, {4, 5, 6, 7}, {4, 5, 6, 7}, }; static int atom_def_dst[8] = { 0, 0, 1, 2, 0, 1, 2, 3 }; static int debug_depth; #ifdef ATOM_DEBUG static void debug_print_spaces(int n) { while (n--) printk(" "); } #define DEBUG(...) do if (amdgpu_atom_debug) { printk(KERN_DEBUG __VA_ARGS__); } while (0) #define SDEBUG(...) do if (amdgpu_atom_debug) { printk(KERN_DEBUG); debug_print_spaces(debug_depth); printk(__VA_ARGS__); } while (0) #else #define DEBUG(...) do { } while (0) #define SDEBUG(...) do { } while (0) #endif static uint32_t atom_iio_execute(struct atom_context *ctx, int base, uint32_t index, uint32_t data) { uint32_t temp = 0xCDCDCDCD; while (1) switch (CU8(base)) { case ATOM_IIO_NOP: base++; break; case ATOM_IIO_READ: temp = ctx->card->reg_read(ctx->card, CU16(base + 1)); base += 3; break; case ATOM_IIO_WRITE: ctx->card->reg_write(ctx->card, CU16(base + 1), temp); base += 3; break; case ATOM_IIO_CLEAR: temp &= ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base + 2)); base += 3; break; case ATOM_IIO_SET: temp |= (0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base + 2); base += 3; break; case ATOM_IIO_MOVE_INDEX: temp &= ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base + 3)); temp |= ((index >> CU8(base + 2)) & (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + 3); base += 4; break; case ATOM_IIO_MOVE_DATA: temp &= ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base + 3)); temp |= ((data >> CU8(base + 2)) & (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + 3); base += 4; break; case ATOM_IIO_MOVE_ATTR: temp &= ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base + 3)); temp |= ((ctx-> io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 - CU8 (base + 1)))) << CU8(base + 3); base += 4; break; case ATOM_IIO_END: return temp; default: pr_info("Unknown IIO opcode\n"); return 0; } } static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr, int *ptr, uint32_t *saved, int print) { uint32_t idx, val = 0xCDCDCDCD, align, arg; struct atom_context *gctx = ctx->ctx; arg = attr & 7; align = (attr >> 3) & 7; switch (arg) { case ATOM_ARG_REG: idx = U16(*ptr); (*ptr) += 2; if (print) DEBUG("REG[0x%04X]", idx); idx += gctx->reg_block; switch (gctx->io_mode) { case ATOM_IO_MM: val = gctx->card->reg_read(gctx->card, idx); break; case ATOM_IO_PCI: pr_info("PCI registers are not implemented\n"); return 0; case ATOM_IO_SYSIO: pr_info("SYSIO registers are not implemented\n"); return 0; default: if (!(gctx->io_mode & 0x80)) { pr_info("Bad IO mode\n"); return 0; } if (!gctx->iio[gctx->io_mode & 0x7F]) { pr_info("Undefined indirect IO read method %d\n", gctx->io_mode & 0x7F); return 0; } val = atom_iio_execute(gctx, gctx->iio[gctx->io_mode & 0x7F], idx, 0); } break; case ATOM_ARG_PS: idx = U8(*ptr); (*ptr)++; /* get_unaligned_le32 avoids unaligned accesses from atombios * tables, noticed on a DEC Alpha. */ val = get_unaligned_le32((u32 *)&ctx->ps[idx]); if (print) DEBUG("PS[0x%02X,0x%04X]", idx, val); break; case ATOM_ARG_WS: idx = U8(*ptr); (*ptr)++; if (print) DEBUG("WS[0x%02X]", idx); switch (idx) { case ATOM_WS_QUOTIENT: val = gctx->divmul[0]; break; case ATOM_WS_REMAINDER: val = gctx->divmul[1]; break; case ATOM_WS_DATAPTR: val = gctx->data_block; break; case ATOM_WS_SHIFT: val = gctx->shift; break; case ATOM_WS_OR_MASK: val = 1 << gctx->shift; break; case ATOM_WS_AND_MASK: val = ~(1 << gctx->shift); break; case ATOM_WS_FB_WINDOW: val = gctx->fb_base; break; case ATOM_WS_ATTRIBUTES: val = gctx->io_attr; break; case ATOM_WS_REGPTR: val = gctx->reg_block; break; default: val = ctx->ws[idx]; } break; case ATOM_ARG_ID: idx = U16(*ptr); (*ptr) += 2; if (print) { if (gctx->data_block) DEBUG("ID[0x%04X+%04X]", idx, gctx->data_block); else DEBUG("ID[0x%04X]", idx); } val = U32(idx + gctx->data_block); break; case ATOM_ARG_FB: idx = U8(*ptr); (*ptr)++; if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) { DRM_ERROR("ATOM: fb read beyond scratch region: %d vs. %d\n", gctx->fb_base + (idx * 4), gctx->scratch_size_bytes); val = 0; } else val = gctx->scratch[(gctx->fb_base / 4) + idx]; if (print) DEBUG("FB[0x%02X]", idx); break; case ATOM_ARG_IMM: switch (align) { case ATOM_SRC_DWORD: val = U32(*ptr); (*ptr) += 4; if (print) DEBUG("IMM 0x%08X\n", val); return val; case ATOM_SRC_WORD0: case ATOM_SRC_WORD8: case ATOM_SRC_WORD16: val = U16(*ptr); (*ptr) += 2; if (print) DEBUG("IMM 0x%04X\n", val); return val; case ATOM_SRC_BYTE0: case ATOM_SRC_BYTE8: case ATOM_SRC_BYTE16: case ATOM_SRC_BYTE24: val = U8(*ptr); (*ptr)++; if (print) DEBUG("IMM 0x%02X\n", val); return val; } return 0; case ATOM_ARG_PLL: idx = U8(*ptr); (*ptr)++; if (print) DEBUG("PLL[0x%02X]", idx); val = gctx->card->pll_read(gctx->card, idx); break; case ATOM_ARG_MC: idx = U8(*ptr); (*ptr)++; if (print) DEBUG("MC[0x%02X]", idx); val = gctx->card->mc_read(gctx->card, idx); break; } if (saved) *saved = val; val &= atom_arg_mask[align]; val >>= atom_arg_shift[align]; if (print) switch (align) { case ATOM_SRC_DWORD: DEBUG(".[31:0] -> 0x%08X\n", val); break; case ATOM_SRC_WORD0: DEBUG(".[15:0] -> 0x%04X\n", val); break; case ATOM_SRC_WORD8: DEBUG(".[23:8] -> 0x%04X\n", val); break; case ATOM_SRC_WORD16: DEBUG(".[31:16] -> 0x%04X\n", val); break; case ATOM_SRC_BYTE0: DEBUG(".[7:0] -> 0x%02X\n", val); break; case ATOM_SRC_BYTE8: DEBUG(".[15:8] -> 0x%02X\n", val); break; case ATOM_SRC_BYTE16: DEBUG(".[23:16] -> 0x%02X\n", val); break; case ATOM_SRC_BYTE24: DEBUG(".[31:24] -> 0x%02X\n", val); break; } return val; } static void atom_skip_src_int(atom_exec_context *ctx, uint8_t attr, int *ptr) { uint32_t align = (attr >> 3) & 7, arg = attr & 7; switch (arg) { case ATOM_ARG_REG: case ATOM_ARG_ID: (*ptr) += 2; break; case ATOM_ARG_PLL: case ATOM_ARG_MC: case ATOM_ARG_PS: case ATOM_ARG_WS: case ATOM_ARG_FB: (*ptr)++; break; case ATOM_ARG_IMM: switch (align) { case ATOM_SRC_DWORD: (*ptr) += 4; return; case ATOM_SRC_WORD0: case ATOM_SRC_WORD8: case ATOM_SRC_WORD16: (*ptr) += 2; return; case ATOM_SRC_BYTE0: case ATOM_SRC_BYTE8: case ATOM_SRC_BYTE16: case ATOM_SRC_BYTE24: (*ptr)++; return; } return; } } static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr) { return atom_get_src_int(ctx, attr, ptr, NULL, 1); } static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr) { uint32_t val = 0xCDCDCDCD; switch (align) { case ATOM_SRC_DWORD: val = U32(*ptr); (*ptr) += 4; break; case ATOM_SRC_WORD0: case ATOM_SRC_WORD8: case ATOM_SRC_WORD16: val = U16(*ptr); (*ptr) += 2; break; case ATOM_SRC_BYTE0: case ATOM_SRC_BYTE8: case ATOM_SRC_BYTE16: case ATOM_SRC_BYTE24: val = U8(*ptr); (*ptr)++; break; } return val; } static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr, uint32_t *saved, int print) { return atom_get_src_int(ctx, arg | atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3] << 3, ptr, saved, print); } static void atom_skip_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr) { atom_skip_src_int(ctx, arg | atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3] << 3, ptr); } static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr, uint32_t val, uint32_t saved) { uint32_t align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3], old_val = val, idx; struct atom_context *gctx = ctx->ctx; old_val &= atom_arg_mask[align] >> atom_arg_shift[align]; val <<= atom_arg_shift[align]; val &= atom_arg_mask[align]; saved &= ~atom_arg_mask[align]; val |= saved; switch (arg) { case ATOM_ARG_REG: idx = U16(*ptr); (*ptr) += 2; DEBUG("REG[0x%04X]", idx); idx += gctx->reg_block; switch (gctx->io_mode) { case ATOM_IO_MM: if (idx == 0) gctx->card->reg_write(gctx->card, idx, val << 2); else gctx->card->reg_write(gctx->card, idx, val); break; case ATOM_IO_PCI: pr_info("PCI registers are not implemented\n"); return; case ATOM_IO_SYSIO: pr_info("SYSIO registers are not implemented\n"); return; default: if (!(gctx->io_mode & 0x80)) { pr_info("Bad IO mode\n"); return; } if (!gctx->iio[gctx->io_mode & 0xFF]) { pr_info("Undefined indirect IO write method %d\n", gctx->io_mode & 0x7F); return; } atom_iio_execute(gctx, gctx->iio[gctx->io_mode & 0xFF], idx, val); } break; case ATOM_ARG_PS: idx = U8(*ptr); (*ptr)++; DEBUG("PS[0x%02X]", idx); ctx->ps[idx] = cpu_to_le32(val); break;