The current write wqe mechanism is to write to DDR first, and then notify the hardware through doorbell to read the data. Direct wqe is a mechanism to fill wqe directly into the hardware. In the case of light load, the wqe will be filled into pcie bar space of the hardware, this will reduce one memory access operation and therefore reduce the latency. SIMD instructions allows cpu to write the 512 bits at one time to device memory, thus it can be used for posting direct wqe. Add direct wqe enable switch and address mapping.
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| @@ -77,10 +77,12 @@ enum hns_roce_qp_cap_flags { · 76 unmodified lines | |||
| 77 | HNS_ROCE_QP_CAP_RQ_RECORD_DB = 1 << 0, | 77 | HNS_ROCE_QP_CAP_RQ_RECORD_DB = 1 << 0, |
| 78 | HNS_ROCE_QP_CAP_SQ_RECORD_DB = 1 << 1, | 78 | HNS_ROCE_QP_CAP_SQ_RECORD_DB = 1 << 1, |
| 79 | HNS_ROCE_QP_CAP_OWNER_DB = 1 << 2, | 79 | HNS_ROCE_QP_CAP_OWNER_DB = 1 << 2, |
| 80 | HNS_ROCE_QP_CAP_DIRECT_WQE = 1 << 5, | ||
| 80 | }; | 81 | }; |
| 81 | 82 | ||
| 82 | struct hns_roce_ib_create_qp_resp { | 83 | struct hns_roce_ib_create_qp_resp { |
| 83 | __aligned_u64 cap_flags; | 84 | __aligned_u64 cap_flags; |
| 85 | __aligned_u64 dwqe_mmap_key; | ||
| 84 | }; | 86 | }; |
| 85 | 87 | ||
| 86 | struct hns_roce_ib_alloc_ucontext_resp { | 88 | struct hns_roce_ib_alloc_ucontext_resp { |