The mpic is either the main interrupt controller or is cascaded behind a GIC. The mpic is single instance and the modes are mutually exclusive, so there is no reason to have seperate cpu hotplug states.
Unified · Split
| @@ -583,7 +583,7 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node, · 582 unmodified lines | ||
| 583 | 583 | #endif |
| 584 | 584 | } else { |
| 585 | 585 | #ifdef CONFIG_SMP |
| 586 | − cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_CASC_STARTING, | |
| 586 | + cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_XP_STARTING, | |
| 587 | 587 | "irqchip/armada/cascade:starting", |
| 588 | 588 | mpic_cascaded_starting_cpu, NULL); |
| 589 | 589 | #endif |
| @@ -82,7 +82,6 @@ enum cpuhp_state { · 81 unmodified lines | ||
| 82 | 82 | CPUHP_AP_IRQ_GIC_STARTING, |
| 83 | 83 | CPUHP_AP_IRQ_HIP04_STARTING, |
| 84 | 84 | CPUHP_AP_IRQ_ARMADA_XP_STARTING, |
| 85 | − CPUHP_AP_IRQ_ARMADA_CASC_STARTING, | |
| 86 | 85 | CPUHP_AP_IRQ_BCM2836_STARTING, |
| 87 | 86 | CPUHP_AP_ARM_MVEBU_COHERENCY, |
| 88 | 87 | CPUHP_AP_PERF_X86_UNCORE_STARTING, |