amd-drm-fixes-6.3-2023-04-19: amdgpu: - GPU reset fix - DCN 3.1.5 line buffer fix - Display fix for single channel memory configs - Fix a possible divide by 0
Unified · Split
| @@ -596,6 +596,9 @@ int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src, · 595 unmodified lines | ||
| 596 | 596 | if (!src->enabled_types || !src->funcs->set) |
| 597 | 597 | return -EINVAL; |
| 598 | 598 | |
| 599 | + if (WARN_ON(!amdgpu_irq_enabled(adev, src, type))) | |
| 600 | + return -EINVAL; | |
| 601 | + | |
| 599 | 602 | if (atomic_dec_and_test(&src->enabled_types[type])) |
| 600 | 603 | return amdgpu_irq_update(adev, src, type); |
| 601 | 604 | |
| @@ -169,10 +169,21 @@ static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable) · 168 unmodified lines | ||
| 169 | 169 | if (rc) |
| 170 | 170 | return rc; |
| 171 | 171 | |
| 172 | − irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; | |
| 172 | + if (amdgpu_in_reset(adev)) { | |
| 173 | + irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; | |
| 174 | + /* During gpu-reset we disable and then enable vblank irq, so | |
| 175 | + * don't use amdgpu_irq_get/put() to avoid refcount change. | |
| 176 | + */ | |
| 177 | + if (!dc_interrupt_set(adev->dm.dc, irq_source, enable)) | |
| 178 | + rc = -EBUSY; | |
| 179 | + } else { | |
| 180 | + rc = (enable) | |
| 181 | + ? amdgpu_irq_get(adev, &adev->crtc_irq, acrtc->crtc_id) | |
| 182 | + : amdgpu_irq_put(adev, &adev->crtc_irq, acrtc->crtc_id); | |
| 183 | + } | |
| 173 | 184 | |
| 174 | − if (!dc_interrupt_set(adev->dm.dc, irq_source, enable)) | |
| 175 | − return -EBUSY; | |
| 185 | + if (rc) | |
| 186 | + return rc; | |
| 176 | 187 | |
| 177 | 188 | skip: |
| 178 | 189 | if (amdgpu_in_reset(adev)) |
| @@ -1697,6 +1697,23 @@ static void dcn314_get_panel_config_defaults(struct dc_panel_config *panel_confi · 1696 unmodified lines | ||
| 1697 | 1697 | *panel_config = panel_config_defaults; |
| 1698 | 1698 | } |
| 1699 | 1699 | |
| 1700 | +static bool filter_modes_for_single_channel_workaround(struct dc *dc, | |
| 1701 | + struct dc_state *context) | |
| 1702 | +{ | |
| 1703 | + // Filter 2K@240Hz+8K@24fps above combination timing if memory only has single dimm LPDDR | |
| 1704 | + if (dc->clk_mgr->bw_params->vram_type == 34 && dc->clk_mgr->bw_params->num_channels < 2) { | |
| 1705 | + int total_phy_pix_clk = 0; | |
| 1706 | + | |
| 1707 | + for (int i = 0; i < context->stream_count; i++) | |
| 1708 | + if (context->res_ctx.pipe_ctx[i].stream) | |
| 1709 | + total_phy_pix_clk += context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; | |
| 1710 | + | |
| 1711 | + if (total_phy_pix_clk >= (1148928+826260)) //2K@240Hz+8K@24fps | |
| 1712 | + return true; | |
| 1713 | + } | |
| 1714 | + return false; | |
| 1715 | +} | |
| 1716 | + | |
| 1700 | 1717 | bool dcn314_validate_bandwidth(struct dc *dc, |
| 1701 | 1718 | struct dc_state *context, |
| 1702 | 1719 | bool fast_validate) |
| @@ -1712,6 +1729,9 @@ bool dcn314_validate_bandwidth(struct dc *dc, · 9 unmodified lines | ||
| 1712 | 1729 | |
| 1713 | 1730 | BW_VAL_TRACE_COUNT(); |
| 1714 | 1731 | |
| 1732 | + if (filter_modes_for_single_channel_workaround(dc, context)) | |
| 1733 | + goto validate_fail; | |
| 1734 | + | |
| 1715 | 1735 | DC_FP_START(); |
| 1716 | 1736 | // do not support self refresh only |
| 1717 | 1737 | out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, false); |
| @@ -222,7 +222,7 @@ struct _vcs_dpi_ip_params_st dcn3_15_ip = { · 221 unmodified lines | ||
| 222 | 222 | .maximum_dsc_bits_per_component = 10, |
| 223 | 223 | .dsc422_native_support = false, |
| 224 | 224 | .is_line_buffer_bpp_fixed = true, |
| 225 | − .line_buffer_fixed_bpp = 49, | |
| 225 | + .line_buffer_fixed_bpp = 48, | |
| 226 | 226 | .line_buffer_size_bits = 789504, |
| 227 | 227 | .max_line_buffer_lines = 12, |
| 228 | 228 | .writeback_interface_buffer_size_kbytes = 90, |
| @@ -934,6 +934,10 @@ bool psr_su_set_dsc_slice_height(struct dc *dc, struct dc_link *link, · 933 unmodified lines | ||
| 934 | 934 | |
| 935 | 935 | pic_height = stream->timing.v_addressable + |
| 936 | 936 | stream->timing.v_border_top + stream->timing.v_border_bottom; |
| 937 | + | |
| 938 | + if (stream->timing.dsc_cfg.num_slices_v == 0) | |
| 939 | + return false; | |
| 940 | + | |
| 937 | 941 | slice_height = pic_height / stream->timing.dsc_cfg.num_slices_v; |
| 938 | 942 | config->dsc_slice_height = slice_height; |
| 939 | 943 | |