Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm

Pull ARM fixes from Russell King: "A number of fixes: Patrik found a problem with preempt counting in the VFP assembly functions which can cause the preempt count to be upset. Nicolas fixed a problem with the parsing of the DT when it straddles a 1MB boundary. Subhash Jadavani reported a problem with sparsemem and our highmem support for cache maintanence for DMA areas, and TI found a bug in their strongly ordered memory mapping type. Also, three fixes by way of Will Deacon's tree from Dave Martin for instruction compatibility and Marc Zyngier to fix hypervisor boot mode issues." * 'fixes' of git://git.linaro.org/people/rmk/linux-arm: ARM: 7629/1: mm: Fix missing XN flag for for MT_MEMORY_SO ARM: DMA: Fix struct page iterator in dma_cache_maint() to work with sparsemem ARM: 7628/1: head.S: map one extra section for the ATAG/DTB area ARM: 7627/1: Predicate preempt logic on PREEMP_COUNT not PREEMPT alone ARM: virt: simplify __hyp_stub_install epilog ARM: virt: boot secondary CPUs through the right entry point ARM: virt: Avoid bx instruction for compatibility with <=ARMv4

Linus Torvalds committed 13 years ago

Commit 01acd3e2 parents 1496ec1 210b1846 files · +26 −27Browse files

Unified · Split

6 files

arch/arm/kernel/head.S +4 −1
arch/arm/kernel/hyp-stub.S +6 −12
arch/arm/mm/dma-mapping.c +10 −8
arch/arm/mm/mmu.c +1 −1
arch/arm/vfp/entry.S +3 −3
arch/arm/vfp/vfphw.S +2 −2

arch/arm/kernel/head.S+4−1

@@ -246,6 +246,7 @@ __create_page_tables: · 245 unmodified lines
246	246
247	247	/*
248	248	* Then map boot params address in r2 if specified.
	249	+ * We map 2 sections in case the ATAGs/DTB crosses a section boundary.
249	250	*/
250	251	mov r0, r2, lsr #SECTION_SHIFT
251	252	movs r0, r0, lsl #SECTION_SHIFT
@@ -253,6 +254,8 @@ __create_page_tables: · 1 unmodified line
253	254	addne r3, r3, #PAGE_OFFSET
254	255	addne r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER)
255	256	orrne r6, r7, r0
	257	+ strne r6, [r3], #1 << PMD_ORDER
	258	+ addne r6, r6, #1 << SECTION_SHIFT
256	259	strne r6, [r3]
257	260
258	261	#ifdef CONFIG_DEBUG_LL
@@ -331,7 +334,7 @@ ENTRY(secondary_startup) · 72 unmodified lines
331	334	* as it has already been validated by the primary processor.
332	335	*/
333	336	#ifdef CONFIG_ARM_VIRT_EXT
334		− bl __hyp_stub_install
	337	+ bl __hyp_stub_install_secondary
335	338	#endif
336	339	safe_svcmode_maskall r9
337	340

arch/arm/kernel/hyp-stub.S+6−12

@@ -99,7 +99,7 @@ ENTRY(__hyp_stub_install_secondary) · 98 unmodified lines
99	99	* immediately.
100	100	*/
101	101	compare_cpu_mode_with_primary r4, r5, r6, r7
102		− bxne lr
	102	+ movne pc, lr
103	103
104	104	/*
105	105	* Once we have given up on one CPU, we do not try to install the
@@ -111,7 +111,7 @@ ENTRY(__hyp_stub_install_secondary) · 5 unmodified lines
111	111	*/
112	112
113	113	cmp r4, #HYP_MODE
114		− bxne lr @ give up if the CPU is not in HYP mode
	114	+ movne pc, lr @ give up if the CPU is not in HYP mode
115	115
116	116	/*
117	117	* Configure HSCTLR to set correct exception endianness/instruction set
@@ -120,7 +120,8 @@ ENTRY(__hyp_stub_install_secondary) · 2 unmodified lines
120	120	* Eventually, CPU-specific code might be needed -- assume not for now
121	121	*
122	122	* This code relies on the "eret" instruction to synchronize the
123		− * various coprocessor accesses.
	123	+ * various coprocessor accesses. This is done when we switch to SVC
	124	+ * (see safe_svcmode_maskall).
124	125	*/
125	126	@ Now install the hypervisor stub:
126	127	adr r7, __hyp_stub_vectors
@@ -155,14 +156,7 @@ THUMB( orr r7, #(1 << 30) ) @ HSCTLR.TE · 28 unmodified lines
155	156	1:
156	157	#endif
157	158
158		− bic r7, r4, #MODE_MASK
159		− orr r7, r7, #SVC_MODE
160		−THUMB( orr r7, r7, #PSR_T_BIT )
161		− msr spsr_cxsf, r7 @ This is SPSR_hyp.
162		−
163		− __MSR_ELR_HYP(14) @ msr elr_hyp, lr
164		− __ERET @ return, switching to SVC mode
165		− @ The boot CPU mode is left in r4.
	159	+ bx lr @ The boot CPU mode is left in r4.
166	160	ENDPROC(__hyp_stub_install_secondary)
167	161
168	162	__hyp_stub_do_trap:
@@ -200,7 +194,7 @@ ENDPROC(__hyp_get_vectors) · 31 unmodified lines
200	194	@ fall through
201	195	ENTRY(__hyp_set_vectors)
202	196	__HVC(0)
203		− bx lr
	197	+ mov pc, lr
204	198	ENDPROC(__hyp_set_vectors)
205	199
206	200	#ifndef ZIMAGE

arch/arm/mm/dma-mapping.c+10−8

@@ -774,25 +774,27 @@ static void dma_cache_maint_page(struct page *page, unsigned long offset, · 773 unmodified lines
774	774	size_t size, enum dma_data_direction dir,
775	775	void (op)(const void , size_t, int))
776	776	{
	777	+ unsigned long pfn;
	778	+ size_t left = size;
	779	+
	780	+ pfn = page_to_pfn(page) + offset / PAGE_SIZE;
	781	+ offset %= PAGE_SIZE;
	782	+
777	783	/*
778	784	* A single sg entry may refer to multiple physically contiguous
779	785	* pages. But we still need to process highmem pages individually.
780	786	* If highmem is not configured then the bulk of this loop gets
781	787	* optimized out.
782	788	*/
783		− size_t left = size;
784	789	do {
785	790	size_t len = left;
786	791	void *vaddr;
787	792
	793	+ page = pfn_to_page(pfn);
	794	+
788	795	if (PageHighMem(page)) {
789		− if (len + offset > PAGE_SIZE) {
790		− if (offset >= PAGE_SIZE) {
791		− page += offset / PAGE_SIZE;
792		− offset %= PAGE_SIZE;
793		− }
	796	+ if (len + offset > PAGE_SIZE)
794	797	len = PAGE_SIZE - offset;
795		− }
796	798	vaddr = kmap_high_get(page);
797	799	if (vaddr) {
798	800	vaddr += offset;
@@ -809,7 +811,7 @@ static void dma_cache_maint_page(struct page *page, unsigned long offset, · 10 unmodified lines
809	811	op(vaddr, len, dir);
810	812	}
811	813	offset = 0;
812		− page++;
	814	+ pfn++;
813	815	left -= len;
814	816	} while (left);
815	817	}

arch/arm/mm/mmu.c+1−1

@@ -283,7 +283,7 @@ static struct mem_type mem_types[] = { · 282 unmodified lines
283	283	},
284	284	[MT_MEMORY_SO] = {
285	285	.prot_pte = L_PTE_PRESENT \| L_PTE_YOUNG \| L_PTE_DIRTY \|
286		− L_PTE_MT_UNCACHED,
	286	+ L_PTE_MT_UNCACHED \| L_PTE_XN,
287	287	.prot_l1 = PMD_TYPE_TABLE,
288	288	.prot_sect = PMD_TYPE_SECT \| PMD_SECT_AP_WRITE \| PMD_SECT_S \|
289	289	PMD_SECT_UNCACHED \| PMD_SECT_XN,

arch/arm/vfp/entry.S+3−3

@@ -22,7 +22,7 @@ · 21 unmodified lines
22	22	@ IRQs disabled.
23	23	@
24	24	ENTRY(do_vfp)
25		−#ifdef CONFIG_PREEMPT
	25	+#ifdef CONFIG_PREEMPT_COUNT
26	26	ldr r4, [r10, #TI_PREEMPT] @ get preempt count
27	27	add r11, r4, #1 @ increment it
28	28	str r11, [r10, #TI_PREEMPT]
@@ -35,7 +35,7 @@ ENTRY(do_vfp) · 6 unmodified lines
35	35	ENDPROC(do_vfp)
36	36
37	37	ENTRY(vfp_null_entry)
38		−#ifdef CONFIG_PREEMPT
	38	+#ifdef CONFIG_PREEMPT_COUNT
39	39	get_thread_info r10
40	40	ldr r4, [r10, #TI_PREEMPT] @ get preempt count
41	41	sub r11, r4, #1 @ decrement it
@@ -53,7 +53,7 @@ ENDPROC(vfp_null_entry) · 11 unmodified lines
53	53
54	54	__INIT
55	55	ENTRY(vfp_testing_entry)
56		−#ifdef CONFIG_PREEMPT
	56	+#ifdef CONFIG_PREEMPT_COUNT
57	57	get_thread_info r10
58	58	ldr r4, [r10, #TI_PREEMPT] @ get preempt count
59	59	sub r11, r4, #1 @ decrement it

arch/arm/vfp/vfphw.S+2−2

@@ -168,7 +168,7 @@ vfp_hw_state_valid: · 167 unmodified lines
168	168	@ else it's one 32-bit instruction, so
169	169	@ always subtract 4 from the following
170	170	@ instruction address.
171		−#ifdef CONFIG_PREEMPT
	171	+#ifdef CONFIG_PREEMPT_COUNT
172	172	get_thread_info r10
173	173	ldr r4, [r10, #TI_PREEMPT] @ get preempt count
174	174	sub r11, r4, #1 @ decrement it
@@ -192,7 +192,7 @@ look_for_VFP_exceptions: · 17 unmodified lines
192	192	@ not recognised by VFP
193	193
194	194	DBGSTR "not VFP"
195		−#ifdef CONFIG_PREEMPT
	195	+#ifdef CONFIG_PREEMPT_COUNT
196	196	get_thread_info r10
197	197	ldr r4, [r10, #TI_PREEMPT] @ get preempt count
198	198	sub r11, r4, #1 @ decrement it