When remapping hardware is configured by system software in scalable mode as Nested (PGTT=011b) and with PWSNP field Set in the PASID-table-entry, it may Set Accessed bit and Dirty bit (and Extended Access bit if enabled) in first-stage page-table entries even when second-stage mappings indicate that corresponding first-stage page-table is Read-Only. As the result, contents of pages designated by VMM as Read-Only can be modified by IOMMU via PML5E (PML4E for 4-level tables) access as part of address translation process due to DMAs issued by Guest. This disallows read-only mappings in the domain that is supposed to be used as nested parent. Reference from Sapphire Rapids Specification Update [1], errata details, SPR17. Userspace should know this limitation by checking the IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17 flag reported in the IOMMU_GET_HW_INFO ioctl. [1] https://www.intel.com/content/www/us/en/content-details/772415/content-details.html
Unified · Split
| @@ -2194,6 +2194,11 @@ __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn, · 2193 unmodified lines | |||
| 2194 | if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0) | 2194 | if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0) |
| 2195 | return -EINVAL; | 2195 | return -EINVAL; |
| 2196 | 2196 | ||
| 2197 | if (!(prot & DMA_PTE_WRITE) && domain->nested_parent) { | ||
| 2198 | pr_err_ratelimited("Read-only mapping is disallowed on the domain which serves as the parent in a nested configuration, due to HW errata (ERRATA_772415_SPR17)\n"); | ||
| 2199 | return -EINVAL; | ||
| 2200 | } | ||
| 2201 | |||
| 2197 | attr = prot & (DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP); | 2202 | attr = prot & (DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP); |
| 2198 | attr |= DMA_FL_PTE_PRESENT; | 2203 | attr |= DMA_FL_PTE_PRESENT; |
| 2199 | if (domain->use_first_level) { | 2204 | if (domain->use_first_level) { |
| @@ -4850,6 +4855,7 @@ static void *intel_iommu_hw_info(struct device *dev, u32 *length, u32 *type) · 2650 unmodified lines | |||
| 4850 | if (!vtd) | 4855 | if (!vtd) |
| 4851 | return ERR_PTR(-ENOMEM); | 4856 | return ERR_PTR(-ENOMEM); |
| 4852 | 4857 | ||
| 4858 | vtd->flags = IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17; | ||
| 4853 | vtd->cap_reg = iommu->cap; | 4859 | vtd->cap_reg = iommu->cap; |
| 4854 | vtd->ecap_reg = iommu->ecap; | 4860 | vtd->ecap_reg = iommu->ecap; |
| 4855 | *length = sizeof(*vtd); | 4861 | *length = sizeof(*vtd); |
| @@ -443,10 +443,20 @@ struct iommu_hwpt_alloc { · 442 unmodified lines | |||
| 443 | }; | 443 | }; |
| 444 | #define IOMMU_HWPT_ALLOC _IO(IOMMUFD_TYPE, IOMMUFD_CMD_HWPT_ALLOC) | 444 | #define IOMMU_HWPT_ALLOC _IO(IOMMUFD_TYPE, IOMMUFD_CMD_HWPT_ALLOC) |
| 445 | 445 | ||
| 446 | /** | ||
| 447 | * enum iommu_hw_info_vtd_flags - Flags for VT-d hw_info | ||
| 448 | * @IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17: If set, disallow read-only mappings | ||
| 449 | * on a nested_parent domain. | ||
| 450 | * https://www.intel.com/content/www/us/en/content-details/772415/content-details.html | ||
| 451 | */ | ||
| 452 | enum iommu_hw_info_vtd_flags { | ||
| 453 | IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17 = 1 << 0, | ||
| 454 | }; | ||
| 455 | |||
| 446 | /** | 456 | /** |
| 447 | * struct iommu_hw_info_vtd - Intel VT-d hardware information | 457 | * struct iommu_hw_info_vtd - Intel VT-d hardware information |
| 448 | * | 458 | * |
| 449 | * @flags: Must be 0 | 459 | * @flags: Combination of enum iommu_hw_info_vtd_flags |
| 450 | * @__reserved: Must be 0 | 460 | * @__reserved: Must be 0 |
| 451 | * | 461 | * |
| 452 | * @cap_reg: Value of Intel VT-d capability register defined in VT-d spec | 462 | * @cap_reg: Value of Intel VT-d capability register defined in VT-d spec |