When remapping hardware is configured by system software in scalable mode as Nested (PGTT=011b) and with PWSNP field Set in the PASID-table-entry, it may Set Accessed bit and Dirty bit (and Extended Access bit if enabled) in first-stage page-table entries even when second-stage mappings indicate that corresponding first-stage page-table is Read-Only. As the result, contents of pages designated by VMM as Read-Only can be modified by IOMMU via PML5E (PML4E for 4-level tables) access as part of address translation process due to DMAs issued by Guest. This disallows read-only mappings in the domain that is supposed to be used as nested parent. Reference from Sapphire Rapids Specification Update [1], errata details, SPR17. Userspace should know this limitation by checking the IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17 flag reported in the IOMMU_GET_HW_INFO ioctl. [1] https://www.intel.com/content/www/us/en/content-details/772415/content-details.html
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| @@ -443,10 +443,20 @@ struct iommu_hwpt_alloc { · 442 unmodified lines | ||
| 443 | 443 | }; |
| 444 | 444 | #define IOMMU_HWPT_ALLOC _IO(IOMMUFD_TYPE, IOMMUFD_CMD_HWPT_ALLOC) |
| 445 | 445 | |
| 446 | +/** | |
| 447 | + * enum iommu_hw_info_vtd_flags - Flags for VT-d hw_info | |
| 448 | + * @IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17: If set, disallow read-only mappings | |
| 449 | + * on a nested_parent domain. | |
| 450 | + * https://www.intel.com/content/www/us/en/content-details/772415/content-details.html | |
| 451 | + */ | |
| 452 | +enum iommu_hw_info_vtd_flags { | |
| 453 | + IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17 = 1 << 0, | |
| 454 | +}; | |
| 455 | + | |
| 446 | 456 | /** |
| 447 | 457 | * struct iommu_hw_info_vtd - Intel VT-d hardware information |
| 448 | 458 | * |
| 449 | − * @flags: Must be 0 | |
| 459 | + * @flags: Combination of enum iommu_hw_info_vtd_flags | |
| 450 | 460 | * @__reserved: Must be 0 |
| 451 | 461 | * |
| 452 | 462 | * @cap_reg: Value of Intel VT-d capability register defined in VT-d spec |