[airlied: had to reapply drm/amdgpu: Implement "color format" DRM property by hand to amdgpu_dm_connector.c] amd-drm-next-7.3-2026-07-02: amdgpu: - Queue reset updates - Initial compute pipe reset support - Improved boundary checking for bios parsing - Cleaned up sysfs input parsing - devcoredump fixes - RAS updates and rework - VCN secure submission fixes - 8K panel fix - Add display KUnit tests - Display CRC fixes - UserQ updates - Backlight fixes - Parse panel type info from DisplayID - Align IP discovery to pci device lifetime - IOCTL boundary check fixes - Convert amdgpu_vm_lock_by_pasid() to drm_exec - Ctx fixes and cleanup - SOC15 register macro cleanups - Memory placement fixes for UVD - Disable KQ support for MI3xx - GFX9 mode2 reset fix - BO list cleanup - Soc24 aborted suspend fix - Gfx8 soft reset rework - Enable soft reset on gfx8 - Drop unnecessary BUG() and BUG_ON() in error paths - Fix power reporting unit conversion - Improve vbios command table bounds checking - UVD bounds checking improvements - VCN bounds checking improvements - PSR and replay fixes - DCN 4.2 updates - Colorop updates - DC GPIO rework - ACP fixes - Fix aperture mapping leak - Ignore_damage_clips fix - Fixes for non-4K pages - JPEG idle check fixes - Userptr fixes - GPUVM fixes - GC 11.7 updates - SMU 13 fixes amdkfd: - Initial compute pipe reset support - Allow applications to opt out of sigbus on fatal errors - Fix doorbell/mmio BO cleanup - Improved CRIU boundary checking - MQD handling rework - SMI fixes - Reset event fixes - CRIU fixes - Sysfs teardown fixes - IOCTL boundary check fixes - SVM fixes - Soft IH ring fixes - Move TBA/TMA from system to device memory radeon: - Blit fix for large BOs - r600 dpm cleanup fix drm: - Extract EDID base section header processing into helper - Parse panel type from DisplayID 2.x Display Parameters UAPI: - KFD interface for applications to select sigbus behavior on fatal errors Proposed userspace: https://github.com/ROCm/rocm-systems/pull/6190
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| @@ -58,6 +58,7 @@ extern "C" { · 57 unmodified lines | |||
| 58 | #define DRM_AMDGPU_USERQ_SIGNAL 0x17 | 58 | #define DRM_AMDGPU_USERQ_SIGNAL 0x17 |
| 59 | #define DRM_AMDGPU_USERQ_WAIT 0x18 | 59 | #define DRM_AMDGPU_USERQ_WAIT 0x18 |
| 60 | #define DRM_AMDGPU_GEM_LIST_HANDLES 0x19 | 60 | #define DRM_AMDGPU_GEM_LIST_HANDLES 0x19 |
| 61 | #define DRM_AMDGPU_PROC_OPTIONS 0x1A | ||
| 61 | 62 | ||
| 62 | #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) | 63 | #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) |
| 63 | #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) | 64 | #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) |
| @@ -79,6 +80,7 @@ extern "C" { · 15 unmodified lines | |||
| 79 | #define DRM_IOCTL_AMDGPU_USERQ_SIGNAL DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal) | 80 | #define DRM_IOCTL_AMDGPU_USERQ_SIGNAL DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal) |
| 80 | #define DRM_IOCTL_AMDGPU_USERQ_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait) | 81 | #define DRM_IOCTL_AMDGPU_USERQ_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait) |
| 81 | #define DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_LIST_HANDLES, struct drm_amdgpu_gem_list_handles) | 82 | #define DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_LIST_HANDLES, struct drm_amdgpu_gem_list_handles) |
| 83 | #define DRM_IOCTL_AMDGPU_PROC_OPTIONS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_PROC_OPTIONS, struct drm_amdgpu_proc_options) | ||
| 82 | 84 | ||
| 83 | /** | 85 | /** |
| 84 | * DOC: memory domains | 86 | * DOC: memory domains |
| @@ -1673,6 +1675,25 @@ struct drm_amdgpu_info_uq_metadata { · 1588 unmodified lines | |||
| 1673 | #define AMDGPU_FAMILY_GC_11_5_4 154 /* GC 11.5.4 */ | 1675 | #define AMDGPU_FAMILY_GC_11_5_4 154 /* GC 11.5.4 */ |
| 1674 | #define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */ | 1676 | #define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */ |
| 1675 | 1677 | ||
| 1678 | /* | ||
| 1679 | * Definition of user options | ||
| 1680 | * | ||
| 1681 | * option: AMDGPU_PROC_OPTIONS_OP_KFD_SIGBUS_DELAY | ||
| 1682 | * 0: Disable sigbus delay - SIGBUS will be raised immediately | ||
| 1683 | * 0xFFFFFFFF: SIGBUS will not be raised | ||
| 1684 | * other: Set the sigbus delay in milliseconds | ||
| 1685 | */ | ||
| 1686 | #define AMDGPU_PROC_OPTIONS_OP_KFD_SIGBUS_DELAY 0 | ||
| 1687 | |||
| 1688 | #define AMDGPU_PROC_OPTIONS_KFD_SIGBUS_DELAY_DISABLED 0xFFFFFFFFu | ||
| 1689 | |||
| 1690 | struct drm_amdgpu_proc_options { | ||
| 1691 | __u32 op; | ||
| 1692 | struct { | ||
| 1693 | __u32 value; | ||
| 1694 | } kfd_sigbus_delay; | ||
| 1695 | }; | ||
| 1696 | |||
| 1676 | #if defined(__cplusplus) | 1697 | #if defined(__cplusplus) |
| 1677 | } | 1698 | } |
| 1678 | #endif | 1699 | #endif |