Need to take some Xe bo definition in here before we can add the BMG display 64k aligned size restrictions.
Showing the changes to include/uapi (9 of 2025 files). Show all
Unified · Split
| @@ -841,11 +841,8 @@ __SYSCALL(__NR_lsm_list_modules, sys_lsm_list_modules) · 840 unmodified lines | |||
| 841 | #define __NR_mseal 462 | 841 | #define __NR_mseal 462 |
| 842 | __SYSCALL(__NR_mseal, sys_mseal) | 842 | __SYSCALL(__NR_mseal, sys_mseal) |
| 843 | 843 | ||
| 844 | #define __NR_uretprobe 463 | ||
| 845 | __SYSCALL(__NR_uretprobe, sys_uretprobe) | ||
| 846 | |||
| 847 | #undef __NR_syscalls | 844 | #undef __NR_syscalls |
| 848 | #define __NR_syscalls 464 | 845 | #define __NR_syscalls 463 |
| 849 | 846 | ||
| 850 | /* | 847 | /* |
| 851 | * 32 bit systems traditionally used different | 848 | * 32 bit systems traditionally used different |
| @@ -859,6 +859,8 @@ struct drm_color_lut { · 858 unmodified lines | |||
| 859 | 859 | ||
| 860 | /** | 860 | /** |
| 861 | * struct drm_plane_size_hint - Plane size hints | 861 | * struct drm_plane_size_hint - Plane size hints |
| 862 | * @width: The width of the plane in pixel | ||
| 863 | * @height: The height of the plane in pixel | ||
| 862 | * | 864 | * |
| 863 | * The plane SIZE_HINTS property blob contains an | 865 | * The plane SIZE_HINTS property blob contains an |
| 864 | * array of struct drm_plane_size_hint. | 866 | * array of struct drm_plane_size_hint. |
| @@ -517,7 +517,14 @@ struct drm_xe_query_gt_list { · 516 unmodified lines | |||
| 517 | * available per Dual Sub Slices (DSS). For example a query response | 517 | * available per Dual Sub Slices (DSS). For example a query response |
| 518 | * containing the following in mask: | 518 | * containing the following in mask: |
| 519 | * ``EU_PER_DSS ff ff 00 00 00 00 00 00`` | 519 | * ``EU_PER_DSS ff ff 00 00 00 00 00 00`` |
| 520 | * means each DSS has 16 EU. | 520 | * means each DSS has 16 SIMD8 EUs. This type may be omitted if device |
| 521 | * doesn't have SIMD8 EUs. | ||
| 522 | * - %DRM_XE_TOPO_SIMD16_EU_PER_DSS - To query the mask of SIMD16 Execution | ||
| 523 | * Units (EU) available per Dual Sub Slices (DSS). For example a query | ||
| 524 | * response containing the following in mask: | ||
| 525 | * ``SIMD16_EU_PER_DSS ff ff 00 00 00 00 00 00`` | ||
| 526 | * means each DSS has 16 SIMD16 EUs. This type may be omitted if device | ||
| 527 | * doesn't have SIMD16 EUs. | ||
| 521 | */ | 528 | */ |
| 522 | struct drm_xe_query_topology_mask { | 529 | struct drm_xe_query_topology_mask { |
| 523 | /** @gt_id: GT ID the mask is associated with */ | 530 | /** @gt_id: GT ID the mask is associated with */ |
| @@ -527,6 +534,7 @@ struct drm_xe_query_topology_mask { · 3 unmodified lines | |||
| 527 | #define DRM_XE_TOPO_DSS_COMPUTE 2 | 534 | #define DRM_XE_TOPO_DSS_COMPUTE 2 |
| 528 | #define DRM_XE_TOPO_L3_BANK 3 | 535 | #define DRM_XE_TOPO_L3_BANK 3 |
| 529 | #define DRM_XE_TOPO_EU_PER_DSS 4 | 536 | #define DRM_XE_TOPO_EU_PER_DSS 4 |
| 537 | #define DRM_XE_TOPO_SIMD16_EU_PER_DSS 5 | ||
| 530 | /** @type: type of mask */ | 538 | /** @type: type of mask */ |
| 531 | __u16 type; | 539 | __u16 type; |
| 532 | 540 | ||
| @@ -1590,10 +1598,10 @@ enum drm_xe_oa_property_id { · 1057 unmodified lines | |||
| 1590 | * b. Counter select c. Counter size and d. BC report. Also refer to the | 1598 | * b. Counter select c. Counter size and d. BC report. Also refer to the |
| 1591 | * oa_formats array in drivers/gpu/drm/xe/xe_oa.c. | 1599 | * oa_formats array in drivers/gpu/drm/xe/xe_oa.c. |
| 1592 | */ | 1600 | */ |
| 1593 | #define DRM_XE_OA_FORMAT_MASK_FMT_TYPE (0xff << 0) | 1601 | #define DRM_XE_OA_FORMAT_MASK_FMT_TYPE (0xffu << 0) |
| 1594 | #define DRM_XE_OA_FORMAT_MASK_COUNTER_SEL (0xff << 8) | 1602 | #define DRM_XE_OA_FORMAT_MASK_COUNTER_SEL (0xffu << 8) |
| 1595 | #define DRM_XE_OA_FORMAT_MASK_COUNTER_SIZE (0xff << 16) | 1603 | #define DRM_XE_OA_FORMAT_MASK_COUNTER_SIZE (0xffu << 16) |
| 1596 | #define DRM_XE_OA_FORMAT_MASK_BC_REPORT (0xff << 24) | 1604 | #define DRM_XE_OA_FORMAT_MASK_BC_REPORT (0xffu << 24) |
| 1597 | 1605 | ||
| 1598 | /** | 1606 | /** |
| 1599 | * @DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT: Requests periodic OA unit | 1607 | * @DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT: Requests periodic OA unit |
| @@ -421,7 +421,7 @@ enum io_uring_msg_ring_flags { · 420 unmodified lines | |||
| 421 | * IO completion data structure (Completion Queue Entry) | 421 | * IO completion data structure (Completion Queue Entry) |
| 422 | */ | 422 | */ |
| 423 | struct io_uring_cqe { | 423 | struct io_uring_cqe { |
| 424 | __u64 user_data; /* sqe->data submission passed back */ | 424 | __u64 user_data; /* sqe->user_data value passed back */ |
| 425 | __s32 res; /* result code for this event */ | 425 | __s32 res; /* result code for this event */ |
| 426 | __u32 flags; | 426 | __u32 flags; |
| 427 | 427 | ||
| @@ -42,9 +42,10 @@ · 41 unmodified lines | |||
| 42 | * - 1.14 - Update kfd_event_data | 42 | * - 1.14 - Update kfd_event_data |
| 43 | * - 1.15 - Enable managing mappings in compute VMs with GEM_VA ioctl | 43 | * - 1.15 - Enable managing mappings in compute VMs with GEM_VA ioctl |
| 44 | * - 1.16 - Add contiguous VRAM allocation flag | 44 | * - 1.16 - Add contiguous VRAM allocation flag |
| 45 | * - 1.17 - Add SDMA queue creation with target SDMA engine ID | ||
| 45 | */ | 46 | */ |
| 46 | #define KFD_IOCTL_MAJOR_VERSION 1 | 47 | #define KFD_IOCTL_MAJOR_VERSION 1 |
| 47 | #define KFD_IOCTL_MINOR_VERSION 16 | 48 | #define KFD_IOCTL_MINOR_VERSION 17 |
| 48 | 49 | ||
| 49 | struct kfd_ioctl_get_version_args { | 50 | struct kfd_ioctl_get_version_args { |
| 50 | __u32 major_version; /* from KFD */ | 51 | __u32 major_version; /* from KFD */ |
| @@ -56,6 +57,7 @@ struct kfd_ioctl_get_version_args { · 5 unmodified lines | |||
| 56 | #define KFD_IOC_QUEUE_TYPE_SDMA 0x1 | 57 | #define KFD_IOC_QUEUE_TYPE_SDMA 0x1 |
| 57 | #define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 0x2 | 58 | #define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 0x2 |
| 58 | #define KFD_IOC_QUEUE_TYPE_SDMA_XGMI 0x3 | 59 | #define KFD_IOC_QUEUE_TYPE_SDMA_XGMI 0x3 |
| 60 | #define KFD_IOC_QUEUE_TYPE_SDMA_BY_ENG_ID 0x4 | ||
| 59 | 61 | ||
| 60 | #define KFD_MAX_QUEUE_PERCENTAGE 100 | 62 | #define KFD_MAX_QUEUE_PERCENTAGE 100 |
| 61 | #define KFD_MAX_QUEUE_PRIORITY 15 | 63 | #define KFD_MAX_QUEUE_PRIORITY 15 |
| @@ -78,6 +80,8 @@ struct kfd_ioctl_create_queue_args { · 16 unmodified lines | |||
| 78 | __u64 ctx_save_restore_address; /* to KFD */ | 80 | __u64 ctx_save_restore_address; /* to KFD */ |
| 79 | __u32 ctx_save_restore_size; /* to KFD */ | 81 | __u32 ctx_save_restore_size; /* to KFD */ |
| 80 | __u32 ctl_stack_size; /* to KFD */ | 82 | __u32 ctl_stack_size; /* to KFD */ |
| 83 | __u32 sdma_engine_id; /* to KFD */ | ||
| 84 | __u32 pad; | ||
| 81 | }; | 85 | }; |
| 82 | 86 | ||
| 83 | struct kfd_ioctl_destroy_queue_args { | 87 | struct kfd_ioctl_destroy_queue_args { |
| @@ -3,6 +3,7 @@ · 2 unmodified lines | |||
| 3 | #define __LINUX_NSFS_H | 3 | #define __LINUX_NSFS_H |
| 4 | 4 | ||
| 5 | #include <linux/ioctl.h> | 5 | #include <linux/ioctl.h> |
| 6 | #include <linux/types.h> | ||
| 6 | 7 | ||
| 7 | #define NSIO 0xb7 | 8 | #define NSIO 0xb7 |
| 8 | 9 | ||
| @@ -16,7 +17,7 @@ · 7 unmodified lines | |||
| 16 | /* Get owner UID (in the caller's user namespace) for a user namespace */ | 17 | /* Get owner UID (in the caller's user namespace) for a user namespace */ |
| 17 | #define NS_GET_OWNER_UID _IO(NSIO, 0x4) | 18 | #define NS_GET_OWNER_UID _IO(NSIO, 0x4) |
| 18 | /* Get the id for a mount namespace */ | 19 | /* Get the id for a mount namespace */ |
| 19 | #define NS_GET_MNTNS_ID _IO(NSIO, 0x5) | 20 | #define NS_GET_MNTNS_ID _IOR(NSIO, 0x5, __u64) |
| 20 | /* Translate pid from target pid namespace into the caller's pid namespace. */ | 21 | /* Translate pid from target pid namespace into the caller's pid namespace. */ |
| 21 | #define NS_GET_PID_FROM_PIDNS _IOR(NSIO, 0x6, int) | 22 | #define NS_GET_PID_FROM_PIDNS _IOR(NSIO, 0x6, int) |
| 22 | /* Return thread-group leader id of pid in the callers pid namespace. */ | 23 | /* Return thread-group leader id of pid in the callers pid namespace. */ |
| @@ -51,6 +51,7 @@ typedef enum { · 50 unmodified lines | |||
| 51 | SEV_RET_INVALID_PLATFORM_STATE, | 51 | SEV_RET_INVALID_PLATFORM_STATE, |
| 52 | SEV_RET_INVALID_GUEST_STATE, | 52 | SEV_RET_INVALID_GUEST_STATE, |
| 53 | SEV_RET_INAVLID_CONFIG, | 53 | SEV_RET_INAVLID_CONFIG, |
| 54 | SEV_RET_INVALID_CONFIG = SEV_RET_INAVLID_CONFIG, | ||
| 54 | SEV_RET_INVALID_LEN, | 55 | SEV_RET_INVALID_LEN, |
| 55 | SEV_RET_ALREADY_OWNED, | 56 | SEV_RET_ALREADY_OWNED, |
| 56 | SEV_RET_INVALID_CERTIFICATE, | 57 | SEV_RET_INVALID_CERTIFICATE, |
| @@ -311,6 +311,7 @@ struct virtio_gpu_cmd_submit { · 310 unmodified lines | |||
| 311 | #define VIRTIO_GPU_CAPSET_VIRGL2 2 | 311 | #define VIRTIO_GPU_CAPSET_VIRGL2 2 |
| 312 | /* 3 is reserved for gfxstream */ | 312 | /* 3 is reserved for gfxstream */ |
| 313 | #define VIRTIO_GPU_CAPSET_VENUS 4 | 313 | #define VIRTIO_GPU_CAPSET_VENUS 4 |
| 314 | #define VIRTIO_GPU_CAPSET_DRM 6 | ||
| 314 | 315 | ||
| 315 | /* VIRTIO_GPU_CMD_GET_CAPSET_INFO */ | 316 | /* VIRTIO_GPU_CMD_GET_CAPSET_INFO */ |
| 316 | struct virtio_gpu_get_capset_info { | 317 | struct virtio_gpu_get_capset_info { |
| @@ -8,14 +8,11 @@ · 7 unmodified lines | |||
| 8 | #define FASTRPC_IOCTL_ALLOC_DMA_BUFF _IOWR('R', 1, struct fastrpc_alloc_dma_buf) | 8 | #define FASTRPC_IOCTL_ALLOC_DMA_BUFF _IOWR('R', 1, struct fastrpc_alloc_dma_buf) |
| 9 | #define FASTRPC_IOCTL_FREE_DMA_BUFF _IOWR('R', 2, __u32) | 9 | #define FASTRPC_IOCTL_FREE_DMA_BUFF _IOWR('R', 2, __u32) |
| 10 | #define FASTRPC_IOCTL_INVOKE _IOWR('R', 3, struct fastrpc_invoke) | 10 | #define FASTRPC_IOCTL_INVOKE _IOWR('R', 3, struct fastrpc_invoke) |
| 11 | /* This ioctl is only supported with secure device nodes */ | ||
| 12 | #define FASTRPC_IOCTL_INIT_ATTACH _IO('R', 4) | 11 | #define FASTRPC_IOCTL_INIT_ATTACH _IO('R', 4) |
| 13 | #define FASTRPC_IOCTL_INIT_CREATE _IOWR('R', 5, struct fastrpc_init_create) | 12 | #define FASTRPC_IOCTL_INIT_CREATE _IOWR('R', 5, struct fastrpc_init_create) |
| 14 | #define FASTRPC_IOCTL_MMAP _IOWR('R', 6, struct fastrpc_req_mmap) | 13 | #define FASTRPC_IOCTL_MMAP _IOWR('R', 6, struct fastrpc_req_mmap) |
| 15 | #define FASTRPC_IOCTL_MUNMAP _IOWR('R', 7, struct fastrpc_req_munmap) | 14 | #define FASTRPC_IOCTL_MUNMAP _IOWR('R', 7, struct fastrpc_req_munmap) |
| 16 | /* This ioctl is only supported with secure device nodes */ | ||
| 17 | #define FASTRPC_IOCTL_INIT_ATTACH_SNS _IO('R', 8) | 15 | #define FASTRPC_IOCTL_INIT_ATTACH_SNS _IO('R', 8) |
| 18 | /* This ioctl is only supported with secure device nodes */ | ||
| 19 | #define FASTRPC_IOCTL_INIT_CREATE_STATIC _IOWR('R', 9, struct fastrpc_init_create_static) | 16 | #define FASTRPC_IOCTL_INIT_CREATE_STATIC _IOWR('R', 9, struct fastrpc_init_create_static) |
| 20 | #define FASTRPC_IOCTL_MEM_MAP _IOWR('R', 10, struct fastrpc_mem_map) | 17 | #define FASTRPC_IOCTL_MEM_MAP _IOWR('R', 10, struct fastrpc_mem_map) |
| 21 | #define FASTRPC_IOCTL_MEM_UNMAP _IOWR('R', 11, struct fastrpc_mem_unmap) | 18 | #define FASTRPC_IOCTL_MEM_UNMAP _IOWR('R', 11, struct fastrpc_mem_unmap) |