New radeon and amdgpu features for 4.13: - Lots of Vega10 bug fixes - Preliminary Raven support - KIQ support for compute rings - MEC queue management rework from Andres - Audio support for DCE6 - SR-IOV improvements - Improved module parameters for controlling radeon vs amdgpu support for SI and CIK - Bug fixes - General code cleanups [airlied: dropped drmP.h header from one file was needed and build broke] * 'drm-next-4.13' of git://people.freedesktop.org/~agd5f/linux: (362 commits) drm/amdgpu: Fix compiler warnings drm/amdgpu: vm_update_ptes remove code duplication drm/amd/amdgpu: Port VCN over to new SOC15 macros drm/amd/amdgpu: Port PSP v10.0 over to new SOC15 macros drm/amd/amdgpu: Port PSP v3.1 over to new SOC15 macros drm/amd/amdgpu: Port NBIO v7.0 driver over to new SOC15 macros drm/amd/amdgpu: Port NBIO v6.1 driver over to new SOC15 macros drm/amd/amdgpu: Port UVD 7.0 over to new SOC15 macros drm/amd/amdgpu: Port MMHUB over to new SOC15 macros drm/amd/amdgpu: Cleanup gfxhub read-modify-write patterns drm/amd/amdgpu: Port GFXHUB over to new SOC15 macros drm/amd/amdgpu: Add offset variant to SOC15 macros drm/amd/powerplay: add avfs control for Vega10 drm/amdgpu: add virtual display support for raven drm/amdgpu/gfx9: fix compute ring doorbell index drm/amd/amdgpu: Rename KIQ ring to avoid spaces drm/amd/amdgpu: gfx9 tidy ups (v2) drm/amdgpu: add contiguous flag in ucode bo create drm/amdgpu: fix missed gpu info firmware when cache firmware during S3 drm/amdgpu: export test ib debugfs interface ...
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| @@ -51,6 +51,7 @@ extern "C" { · 50 unmodified lines | ||
| 51 | 51 | #define DRM_AMDGPU_GEM_OP 0x10 |
| 52 | 52 | #define DRM_AMDGPU_GEM_USERPTR 0x11 |
| 53 | 53 | #define DRM_AMDGPU_WAIT_FENCES 0x12 |
| 54 | +#define DRM_AMDGPU_VM 0x13 | |
| 54 | 55 | |
| 55 | 56 | #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) |
| 56 | 57 | #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) |
| @@ -65,6 +66,7 @@ extern "C" { · 8 unmodified lines | ||
| 65 | 66 | #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) |
| 66 | 67 | #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) |
| 67 | 68 | #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) |
| 69 | +#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) | |
| 68 | 70 | |
| 69 | 71 | #define AMDGPU_GEM_DOMAIN_CPU 0x1 |
| 70 | 72 | #define AMDGPU_GEM_DOMAIN_GTT 0x2 |
| @@ -190,6 +192,26 @@ union drm_amdgpu_ctx { · 119 unmodified lines | ||
| 190 | 192 | union drm_amdgpu_ctx_out out; |
| 191 | 193 | }; |
| 192 | 194 | |
| 195 | +/* vm ioctl */ | |
| 196 | +#define AMDGPU_VM_OP_RESERVE_VMID 1 | |
| 197 | +#define AMDGPU_VM_OP_UNRESERVE_VMID 2 | |
| 198 | + | |
| 199 | +struct drm_amdgpu_vm_in { | |
| 200 | + /** AMDGPU_VM_OP_* */ | |
| 201 | + __u32 op; | |
| 202 | + __u32 flags; | |
| 203 | +}; | |
| 204 | + | |
| 205 | +struct drm_amdgpu_vm_out { | |
| 206 | + /** For future use, no flags defined so far */ | |
| 207 | + __u64 flags; | |
| 208 | +}; | |
| 209 | + | |
| 210 | +union drm_amdgpu_vm { | |
| 211 | + struct drm_amdgpu_vm_in in; | |
| 212 | + struct drm_amdgpu_vm_out out; | |
| 213 | +}; | |
| 214 | + | |
| 193 | 215 | /* |
| 194 | 216 | * This is not a reliable API and you should expect it to fail for any |
| 195 | 217 | * number of reasons and have fallback path that do not use userptr to |
| @@ -409,7 +431,9 @@ struct drm_amdgpu_gem_va { · 213 unmodified lines | ||
| 409 | 431 | #define AMDGPU_HW_IP_UVD 3 |
| 410 | 432 | #define AMDGPU_HW_IP_VCE 4 |
| 411 | 433 | #define AMDGPU_HW_IP_UVD_ENC 5 |
| 412 | −#define AMDGPU_HW_IP_NUM 6 | |
| 434 | +#define AMDGPU_HW_IP_VCN_DEC 6 | |
| 435 | +#define AMDGPU_HW_IP_VCN_ENC 7 | |
| 436 | +#define AMDGPU_HW_IP_NUM 8 | |
| 413 | 437 | |
| 414 | 438 | #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 |
| 415 | 439 | |
| @@ -579,6 +603,8 @@ struct drm_amdgpu_cs_chunk_data { · 163 unmodified lines | ||
| 579 | 603 | #define AMDGPU_INFO_SENSOR_VDDNB 0x6 |
| 580 | 604 | /* Subquery id: Query graphics voltage */ |
| 581 | 605 | #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 |
| 606 | +/* Number of VRAM page faults on CPU access. */ | |
| 607 | +#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E | |
| 582 | 608 | |
| 583 | 609 | #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 |
| 584 | 610 | #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff |
| @@ -838,6 +864,7 @@ struct drm_amdgpu_info_vce_clock_table { · 253 unmodified lines | ||
| 838 | 864 | #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ |
| 839 | 865 | #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ |
| 840 | 866 | #define AMDGPU_FAMILY_AI 141 /* Vega10 */ |
| 867 | +#define AMDGPU_FAMILY_RV 142 /* Raven */ | |
| 841 | 868 | |
| 842 | 869 | #if defined(__cplusplus) |
| 843 | 870 | } |