History

qed: FW 8.42.2.0 HSI changes

This patch contains several HSI changes. The changes are part of features like RDMA VF and OVS, the patch also contains a fix to how the init code determines if the dmae is ready to be used.

Michal Kalderon committed 6 years ago

Commit 0500a701 parent 6459d937 files · +280 −154Browse files

Unified · Split

7 files
  1. drivers/net/ethernet/qlogic/qed/qed_hsi.h +201 −116
  2. drivers/net/ethernet/qlogic/qed/qed_init_ops.c +4 −2
  3. drivers/net/ethernet/qlogic/qed/qed_mcp.c +2 −0
  4. drivers/net/ethernet/qlogic/qed/qed_roce.c +1 −1
  5. drivers/net/ethernet/qlogic/qede/qede_fp.c +4 −4
  6. include/linux/qed/common_hsi.h +12 −9
  7. include/linux/qed/eth_common.h +56 −22
drivers/net/ethernet/qlogic/qed/qed_hsi.h+201−116
@@ -250,7 +250,8 @@ struct core_rx_gsi_offload_cqe { · 249 unmodified lines
250250 __le16 src_mac_addrlo;
251251 __le16 qp_id;
252252 __le32 src_qp;
253− __le32 reserved[3];
253+ struct core_rx_cqe_opaque_data opaque_data;
254+ __le32 reserved;
254255 };
255256
256257 /* Core RX CQE for Light L2 */
@@ -405,7 +406,7 @@ struct ystorm_core_conn_st_ctx { · 148 unmodified lines
405406
406407 /* The core storm context for the Pstorm */
407408 struct pstorm_core_conn_st_ctx {
408− __le32 reserved[4];
409+ __le32 reserved[20];
409410 };
410411
411412 /* Core Slowpath Connection storm context of Xstorm */
@@ -856,12 +857,12 @@ struct e4_ustorm_core_conn_ag_ctx { · 444 unmodified lines
856857
857858 /* The core storm context for the Mstorm */
858859 struct mstorm_core_conn_st_ctx {
859− __le32 reserved[24];
860+ __le32 reserved[40];
860861 };
861862
862863 /* The core storm context for the Ustorm */
863864 struct ustorm_core_conn_st_ctx {
864− __le32 reserved[4];
865+ __le32 reserved[20];
865866 };
866867
867868 /* The core storm context for the Tstorm */
@@ -915,12 +916,21 @@ struct eth_pstorm_per_pf_stat { · 47 unmodified lines
915916 struct regpair sent_gre_bytes;
916917 struct regpair sent_vxlan_bytes;
917918 struct regpair sent_geneve_bytes;
919+ struct regpair sent_mpls_bytes;
920+ struct regpair sent_gre_mpls_bytes;
921+ struct regpair sent_udp_mpls_bytes;
918922 struct regpair sent_gre_pkts;
919923 struct regpair sent_vxlan_pkts;
920924 struct regpair sent_geneve_pkts;
925+ struct regpair sent_mpls_pkts;
926+ struct regpair sent_gre_mpls_pkts;
927+ struct regpair sent_udp_mpls_pkts;
921928 struct regpair gre_drop_pkts;
922929 struct regpair vxlan_drop_pkts;
923930 struct regpair geneve_drop_pkts;
931+ struct regpair mpls_drop_pkts;
932+ struct regpair gre_mpls_drop_pkts;
933+ struct regpair udp_mpls_drop_pkts;
924934 };
925935
926936 /* Ethernet TX Per Queue Stats */
@@ -1010,7 +1020,8 @@ union event_ring_data { · 83 unmodified lines
10101020 struct event_ring_entry {
10111021 u8 protocol_id;
10121022 u8 opcode;
1013− __le16 reserved0;
1023+ u8 reserved0;
1024+ u8 vf_id;
10141025 __le16 echo;
10151026 u8 fw_return_code;
10161027 u8 flags;
@@ -1088,7 +1099,20 @@ enum malicious_vf_error_id { · 71 unmodified lines
10881099 ETH_CONTROL_PACKET_VIOLATION,
10891100 ETH_ANTI_SPOOFING_ERR,
10901101 ETH_PACKET_SIZE_TOO_LARGE,
1091− MAX_MALICIOUS_VF_ERROR_ID
1102+ CORE_ILLEGAL_VLAN_MODE,
1103+ CORE_ILLEGAL_NBDS,
1104+ CORE_FIRST_BD_WO_SOP,
1105+ CORE_INSUFFICIENT_BDS,
1106+ CORE_PACKET_TOO_SMALL,
1107+ CORE_ILLEGAL_INBAND_TAGS,
1108+ CORE_VLAN_INSERT_AND_INBAND_VLAN,
1109+ CORE_MTU_VIOLATION,
1110+ CORE_CONTROL_PACKET_VIOLATION,
1111+ CORE_ANTI_SPOOFING_ERR,
1112+ CORE_PACKET_SIZE_TOO_LARGE,
1113+ CORE_ILLEGAL_BD_FLAGS,
1114+ CORE_GSI_PACKET_VIOLATION,
1115+ MAX_MALICIOUS_VF_ERROR_ID,
10921116 };
10931117
10941118 /* Mstorm non-triggering VF zone */
@@ -1394,6 +1418,16 @@ enum vf_zone_size_mode { · 299 unmodified lines
13941418 MAX_VF_ZONE_SIZE_MODE
13951419 };
13961420
1421+/* Xstorm non-triggering VF zone */
1422+struct xstorm_non_trigger_vf_zone {
1423+ struct regpair non_edpm_ack_pkts;
1424+};
1425+
1426+/* Tstorm VF zone */
1427+struct xstorm_vf_zone {
1428+ struct xstorm_non_trigger_vf_zone non_trigger;
1429+};
1430+
13971431 /* Attentions status block */
13981432 struct atten_status_block {
13991433 __le32 atten_bits;
@@ -2748,8 +2782,8 @@ enum chip_ids { · 1348 unmodified lines
27482782 };
27492783
27502784 struct fw_asserts_ram_section {
2751− u16 section_ram_line_offset;
2752− u16 section_ram_line_size;
2785+ __le16 section_ram_line_offset;
2786+ __le16 section_ram_line_size;
27532787 u8 list_dword_offset;
27542788 u8 list_element_dword_size;
27552789 u8 list_num_elements;
@@ -2799,6 +2833,7 @@ enum init_modes { · 43 unmodified lines
27992833 MODE_PORTS_PER_ENG_4,
28002834 MODE_100G,
28012835 MODE_RESERVED6,
2836+ MODE_RESERVED7,
28022837 MAX_INIT_MODES
28032838 };
28042839
@@ -2833,6 +2868,7 @@ enum bin_init_buffer_type { · 28 unmodified lines
28332868 BIN_BUF_INIT_VAL,
28342869 BIN_BUF_INIT_MODE_TREE,
28352870 BIN_BUF_INIT_IRO,
2871+ BIN_BUF_INIT_OVERLAYS,
28362872 MAX_BIN_INIT_BUFFER_TYPE
28372873 };
28382874
@@ -2929,10 +2965,8 @@ struct init_if_phase_op { · 90 unmodified lines
29292965 u32 op_data;
29302966 #define INIT_IF_PHASE_OP_OP_MASK 0xF
29312967 #define INIT_IF_PHASE_OP_OP_SHIFT 0
2932−#define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1
2933−#define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4
2934−#define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF
2935−#define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5
2968+#define INIT_IF_PHASE_OP_RESERVED1_MASK 0xFFF
2969+#define INIT_IF_PHASE_OP_RESERVED1_SHIFT 4
29362970 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF
29372971 #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16
29382972 u32 phase_data;
@@ -4226,7 +4260,7 @@ void qed_gft_disable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 pf_id); · 1287 unmodified lines
42264260 /**
42274261 * @brief qed_gft_config - Enable and configure HW for GFT
42284262 *
4229− * @param p_hwfn
4263+ * @param p_hwfn - HW device data
42304264 * @param p_ptt - ptt window used for writing the registers.
42314265 * @param pf_id - pf on which to enable GFT.
42324266 * @param tcp - set profile tcp packets.
@@ -5673,9 +5707,9 @@ struct e4_eth_conn_context { · 1440 unmodified lines
56735707 struct pstorm_eth_conn_st_ctx pstorm_st_context;
56745708 struct xstorm_eth_conn_st_ctx xstorm_st_context;
56755709 struct e4_xstorm_eth_conn_ag_ctx xstorm_ag_context;
5710+ struct e4_tstorm_eth_conn_ag_ctx tstorm_ag_context;
56765711 struct ystorm_eth_conn_st_ctx ystorm_st_context;
56775712 struct e4_ystorm_eth_conn_ag_ctx ystorm_ag_context;
5678− struct e4_tstorm_eth_conn_ag_ctx tstorm_ag_context;
56795713 struct e4_ustorm_eth_conn_ag_ctx ustorm_ag_context;
56805714 struct ustorm_eth_conn_st_ctx ustorm_st_context;
56815715 struct mstorm_eth_conn_st_ctx mstorm_st_context;
@@ -5705,6 +5739,16 @@ enum eth_error_code { · 23 unmodified lines
57055739 ETH_FILTERS_VNI_ADD_FAIL_FULL,
57065740 ETH_FILTERS_VNI_ADD_FAIL_DUP,
57075741 ETH_FILTERS_GFT_UPDATE_FAIL,
5742+ ETH_RX_QUEUE_FAIL_LOAD_VF_DATA,
5743+ ETH_FILTERS_GFS_ADD_FILTER_FAIL_MAX_HOPS,
5744+ ETH_FILTERS_GFS_ADD_FILTER_FAIL_NO_FREE_ENRTY,
5745+ ETH_FILTERS_GFS_ADD_FILTER_FAIL_ALREADY_EXISTS,
5746+ ETH_FILTERS_GFS_ADD_FILTER_FAIL_PCI_ERROR,
5747+ ETH_FILTERS_GFS_ADD_FINLER_FAIL_MAGIC_NUM_ERROR,
5748+ ETH_FILTERS_GFS_DEL_FILTER_FAIL_MAX_HOPS,
5749+ ETH_FILTERS_GFS_DEL_FILTER_FAIL_NO_MATCH_ENRTY,
5750+ ETH_FILTERS_GFS_DEL_FILTER_FAIL_PCI_ERROR,
5751+ ETH_FILTERS_GFS_DEL_FILTER_FAIL_MAGIC_NUM_ERROR,
57085752 MAX_ETH_ERROR_CODE
57095753 };
57105754
@@ -5728,6 +5772,11 @@ enum eth_event_opcode { · 17 unmodified lines
57285772 ETH_EVENT_RX_CREATE_GFT_ACTION,
57295773 ETH_EVENT_RX_GFT_UPDATE_FILTER,
57305774 ETH_EVENT_TX_QUEUE_UPDATE,
5775+ ETH_EVENT_RGFS_ADD_FILTER,
5776+ ETH_EVENT_RGFS_DEL_FILTER,
5777+ ETH_EVENT_TGFS_ADD_FILTER,
5778+ ETH_EVENT_TGFS_DEL_FILTER,
5779+ ETH_EVENT_GFS_COUNTERS_REPORT_REQUEST,
57315780 MAX_ETH_EVENT_OPCODE
57325781 };
57335782
@@ -5820,18 +5869,31 @@ enum eth_ramrod_cmd_id { · 86 unmodified lines
58205869 ETH_RAMROD_RX_CREATE_GFT_ACTION,
58215870 ETH_RAMROD_GFT_UPDATE_FILTER,
58225871 ETH_RAMROD_TX_QUEUE_UPDATE,
5872+ ETH_RAMROD_RGFS_FILTER_ADD,
5873+ ETH_RAMROD_RGFS_FILTER_DEL,
5874+ ETH_RAMROD_TGFS_FILTER_ADD,
5875+ ETH_RAMROD_TGFS_FILTER_DEL,
5876+ ETH_RAMROD_GFS_COUNTERS_REPORT_REQUEST,
58235877 MAX_ETH_RAMROD_CMD_ID
58245878 };
58255879
58265880 /* Return code from eth sp ramrods */
58275881 struct eth_return_code {
58285882 u8 value;
5829−#define ETH_RETURN_CODE_ERR_CODE_MASK 0x1F
5830−#define ETH_RETURN_CODE_ERR_CODE_SHIFT 0
5831−#define ETH_RETURN_CODE_RESERVED_MASK 0x3
5832−#define ETH_RETURN_CODE_RESERVED_SHIFT 5
5833−#define ETH_RETURN_CODE_RX_TX_MASK 0x1
5834−#define ETH_RETURN_CODE_RX_TX_SHIFT 7
5883+#define ETH_RETURN_CODE_ERR_CODE_MASK 0x3F
5884+#define ETH_RETURN_CODE_ERR_CODE_SHIFT 0
5885+#define ETH_RETURN_CODE_RESERVED_MASK 0x1
5886+#define ETH_RETURN_CODE_RESERVED_SHIFT 6
5887+#define ETH_RETURN_CODE_RX_TX_MASK 0x1
5888+#define ETH_RETURN_CODE_RX_TX_SHIFT 7
5889+};
5890+
5891+/* tx destination enum */
5892+enum eth_tx_dst_mode_config_enum {
5893+ ETH_TX_DST_MODE_CONFIG_DISABLE,
5894+ ETH_TX_DST_MODE_CONFIG_FORWARD_DATA_IN_BD,
5895+ ETH_TX_DST_MODE_CONFIG_FORWARD_DATA_IN_VPORT,
5896+ MAX_ETH_TX_DST_MODE_CONFIG_ENUM
58355897 };
58365898
58375899 /* What to do in case an error occurs */
@@ -5858,8 +5920,10 @@ struct eth_tx_err_vals { · 20 unmodified lines
58585920 #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5
58595921 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1
58605922 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6
5861−#define ETH_TX_ERR_VALS_RESERVED_MASK 0x1FF
5862−#define ETH_TX_ERR_VALS_RESERVED_SHIFT 7
5923+#define ETH_TX_ERR_VALS_ILLEGAL_BD_FLAGS_MASK 0x1
5924+#define ETH_TX_ERR_VALS_ILLEGAL_BD_FLAGS_SHIFT 7
5925+#define ETH_TX_ERR_VALS_RESERVED_MASK 0xFF
5926+#define ETH_TX_ERR_VALS_RESERVED_SHIFT 8
58635927 };
58645928
58655929 /* vport rss configuration data */
@@ -5889,7 +5953,6 @@ struct eth_vport_rss_config { · 23 unmodified lines
58895953 u8 tbl_size;
58905954 __le32 reserved2[2];
58915955 __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM];
5892−
58935956 __le32 rss_key[ETH_RSS_KEY_SIZE_REGS];
58945957 __le32 reserved3[2];
58955958 };
@@ -6091,7 +6154,7 @@ struct rx_update_gft_filter_data { · 195 unmodified lines
60916154 u8 inner_vlan_removal_en;
60926155 };
60936156
6094−/* Ramrod data for rx queue start ramrod */
6157+/* Ramrod data for tx queue start ramrod */
60956158 struct tx_queue_start_ramrod_data {
60966159 __le16 sb_id;
60976160 u8 sb_index;
@@ -6104,16 +6167,14 @@ struct tx_queue_start_ramrod_data { · 6 unmodified lines
61046167 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0
61056168 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1
61066169 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1
6107−#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK 0x1
6108−#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT 2
61096170 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1
6110−#define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 3
6171+#define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 2
61116172 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1
6112−#define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 4
6173+#define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 3
61136174 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1
6114−#define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 5
6115−#define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x3
6116−#define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 6
6175+#define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 4
6176+#define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x7
6177+#define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 5
61176178 u8 pxp_st_hint;
61186179 u8 pxp_tph_valid_bd;
61196180 u8 pxp_tph_valid_pkt;
@@ -6169,18 +6230,22 @@ struct vport_start_ramrod_data { · 49 unmodified lines
61696230 __le16 default_vlan;
61706231 u8 tx_switching_en;
61716232 u8 anti_spoofing_en;
6172−
61736233 u8 default_vlan_en;
6174−
61756234 u8 handle_ptp_pkts;
61766235 u8 silent_vlan_removal_en;
61776236 u8 untagged;
61786237 struct eth_tx_err_vals tx_err_behav;
6179−
61806238 u8 zero_placement_offset;
61816239 u8 ctl_frame_mac_check_en;
61826240 u8 ctl_frame_ethtype_check_en;
6241+ u8 reserved0;
6242+ u8 reserved1;
6243+ u8 tx_dst_port_mode_config;
6244+ u8 dst_vport_id;
6245+ u8 tx_dst_port_mode;
6246+ u8 dst_vport_id_valid;
61836247 u8 wipe_inner_vlan_pri_en;
6248+ u8 reserved2[2];
61846249 struct eth_in_to_in_pri_map_cfg in_to_in_vlan_pri_map_cfg;
61856250 };
61866251
@@ -6740,19 +6805,6 @@ struct e4_xstorm_eth_hw_conn_ag_ctx { · 553 unmodified lines
67406805 __le16 conn_dpi;
67416806 };
67426807
6743−/* GFT CAM line struct */
6744−struct gft_cam_line {
6745− __le32 camline;
6746−#define GFT_CAM_LINE_VALID_MASK 0x1
6747−#define GFT_CAM_LINE_VALID_SHIFT 0
6748−#define GFT_CAM_LINE_DATA_MASK 0x3FFF
6749−#define GFT_CAM_LINE_DATA_SHIFT 1
6750−#define GFT_CAM_LINE_MASK_BITS_MASK 0x3FFF
6751−#define GFT_CAM_LINE_MASK_BITS_SHIFT 15
6752−#define GFT_CAM_LINE_RESERVED1_MASK 0x7
6753−#define GFT_CAM_LINE_RESERVED1_SHIFT 29
6754−};
6755−
67566808 /* GFT CAM line struct with fields breakout */
67576809 struct gft_cam_line_mapped {
67586810 __le32 camline;
@@ -6782,10 +6834,6 @@ struct gft_cam_line_mapped { · 23 unmodified lines
67826834 #define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT 29
67836835 };
67846836
6785−union gft_cam_line_union {
6786− struct gft_cam_line cam_line;
6787− struct gft_cam_line_mapped cam_line_mapped;
6788−};
67896837
67906838 /* Used in gft_profile_key: Indication for ip version */
67916839 enum gft_profile_ip_version {
@@ -7064,6 +7112,11 @@ struct mstorm_rdma_task_st_ctx { · 272 unmodified lines
70647112 struct regpair temp[4];
70657113 };
70667114
7115+/* The roce task context of Ustorm */
7116+struct ustorm_rdma_task_st_ctx {
7117+ struct regpair temp[6];
7118+};
7119+
70677120 struct e4_ustorm_rdma_task_ag_ctx {
70687121 u8 reserved;
70697122 u8 state;
@@ -7073,8 +7126,8 @@ struct e4_ustorm_rdma_task_ag_ctx { · 3 unmodified lines
70737126 #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
70747127 #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
70757128 #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
7076−#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK 0x1
7077−#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT 5
7129+#define E4_USTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
7130+#define E4_USTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
70787131 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3
70797132 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6
70807133 u8 flags1;
@@ -7104,29 +7157,29 @@ struct e4_ustorm_rdma_task_ag_ctx { · 23 unmodified lines
71047157 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
71057158 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7
71067159 u8 flags3;
7107−#define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
7108−#define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 0
7109−#define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
7110−#define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1
7111−#define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
7112−#define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 2
7113−#define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
7114−#define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3
7115−#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
7116−#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
7160+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RXMIT_PROD_CONS_EN_MASK 0x1
7161+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RXMIT_PROD_CONS_EN_SHIFT 0
7162+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
7163+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1
7164+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_PROD_CONS_EN_MASK 0x1
7165+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_PROD_CONS_EN_SHIFT 2
7166+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
7167+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3
7168+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
7169+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
71177170 __le32 dif_err_intervals;
71187171 __le32 dif_error_1st_interval;
7119− __le32 sq_cons;
7120− __le32 dif_runt_value;
7172+ __le32 dif_rxmit_cons;
7173+ __le32 dif_rxmit_prod;
71217174 __le32 sge_index;
7122− __le32 reg5;
7175+ __le32 sq_cons;
71237176 u8 byte2;
71247177 u8 byte3;
7125− __le16 word1;
7126− __le16 word2;
7178+ __le16 dif_write_cons;
7179+ __le16 dif_write_prod;
71277180 __le16 word3;
7128− __le32 reg6;
7129− __le32 reg7;
7181+ __le32 dif_error_buffer_address_lo;
7182+ __le32 dif_error_buffer_address_hi;
71307183 };
71317184
71327185 /* RDMA task context */
@@ -7137,6 +7190,8 @@ struct e4_rdma_task_context { · 4 unmodified lines
71377190 struct e4_mstorm_rdma_task_ag_ctx mstorm_ag_context;
71387191 struct mstorm_rdma_task_st_ctx mstorm_st_context;
71397192 struct rdif_task_context rdif_context;
7193+ struct ustorm_rdma_task_st_ctx ustorm_st_context;
7194+ struct regpair ustorm_st_padding[2];
71407195 struct e4_ustorm_rdma_task_ag_ctx ustorm_ag_context;
71417196 };
71427197
@@ -7172,7 +7227,12 @@ struct rdma_create_cq_ramrod_data { · 29 unmodified lines
71727227 u8 pbl_log_page_size;
71737228 u8 toggle_bit;
71747229 __le16 int_timeout;
7175− __le16 reserved1;
7230+ u8 vf_id;
7231+ u8 flags;
7232+#define RDMA_CREATE_CQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1
7233+#define RDMA_CREATE_CQ_RAMROD_DATA_VF_ID_VALID_SHIFT 0
7234+#define RDMA_CREATE_CQ_RAMROD_DATA_RESERVED1_MASK 0x7F
7235+#define RDMA_CREATE_CQ_RAMROD_DATA_RESERVED1_SHIFT 1
71767236 };
71777237
71787238 /* rdma deregister tid ramrod data */
@@ -7216,6 +7276,7 @@ enum rdma_fw_return_code { · 37 unmodified lines
72167276 RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR,
72177277 RDMA_RETURN_RESIZE_CQ_ERR,
72187278 RDMA_RETURN_NIG_DRAIN_REQ,
7279+ RDMA_RETURN_GENERAL_ERR,
72197280 MAX_RDMA_FW_RETURN_CODE
72207281 };
72217282
@@ -7229,7 +7290,10 @@ struct rdma_init_func_hdr { · 7 unmodified lines
72297290 u8 relaxed_ordering;
72307291 __le16 first_reg_srq_id;
72317292 __le32 reg_srq_base_addr;
7232− __le32 reserved;
7293+ u8 searcher_mode;
7294+ u8 pvrdma_mode;
7295+ u8 max_num_ns_log;
7296+ u8 reserved;
72337297 };
72347298
72357299 /* rdma function init ramrod data */
@@ -7319,16 +7383,20 @@ struct rdma_resize_cq_ramrod_data { · 83 unmodified lines
73197383 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT 0
73207384 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK 0x1
73217385 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1
7322−#define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x3F
7323−#define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT 2
7386+#define RDMA_RESIZE_CQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1
7387+#define RDMA_RESIZE_CQ_RAMROD_DATA_VF_ID_VALID_SHIFT 2
7388+#define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x1F
7389+#define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT 3
73247390 u8 pbl_log_page_size;
73257391 __le16 pbl_num_pages;
73267392 __le32 max_cqes;
73277393 struct regpair pbl_addr;
73287394 struct regpair output_params_addr;
7395+ u8 vf_id;
7396+ u8 reserved1[7];
73297397 };
73307398
7331−/* The rdma storm context of Mstorm */
7399+/* The rdma SRQ context */
73327400 struct rdma_srq_context {
73337401 struct regpair temp[8];
73347402 };
@@ -7375,6 +7443,7 @@ enum rdma_tid_type { · 40 unmodified lines
73757443 MAX_RDMA_TID_TYPE
73767444 };
73777445
7446+/* The rdma XRC SRQ context */
73787447 struct rdma_xrc_srq_context {
73797448 struct regpair temp[9];
73807449 };
@@ -7556,12 +7625,12 @@ struct e4_xstorm_roce_conn_ag_ctx { · 175 unmodified lines
75567625 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT10_SHIFT 2
75577626 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT11_MASK 0x1
75587627 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT11_SHIFT 3
7559−#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT12_MASK 0x1
7560−#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT12_SHIFT 4
7628+#define E4_XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1
7629+#define E4_XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_SHIFT 4
75617630 #define E4_XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1
75627631 #define E4_XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_SHIFT 5
7563−#define E4_XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1
7564−#define E4_XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_SHIFT 6
7632+#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT14_MASK 0x1
7633+#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT14_SHIFT 6
75657634 #define E4_XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
75667635 #define E4_XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
75677636 u8 flags2;
@@ -7885,9 +7954,9 @@ struct mstorm_roce_conn_st_ctx { · 317 unmodified lines
78857954 struct regpair temp[6];
78867955 };
78877956
7888−/* The roce storm context of Ystorm */
7957+/* The roce storm context of Ustorm */
78897958 struct ustorm_roce_conn_st_ctx {
7890− struct regpair temp[12];
7959+ struct regpair temp[14];
78917960 };
78927961
78937962 /* roce connection context */
@@ -7905,6 +7974,7 @@ struct e4_roce_conn_context { · 11 unmodified lines
79057974 struct mstorm_roce_conn_st_ctx mstorm_st_context;
79067975 struct regpair mstorm_st_padding[2];
79077976 struct ustorm_roce_conn_st_ctx ustorm_st_context;
7977+ struct regpair ustorm_st_padding[2];
79087978 };
79097979
79107980 /* roce cqes statistics */
@@ -7959,12 +8029,17 @@ struct roce_create_qp_req_ramrod_data { · 48 unmodified lines
79598029 struct regpair qp_handle_for_cqe;
79608030 struct regpair qp_handle_for_async;
79618031 u8 stats_counter_id;
7962− u8 reserved3[6];
8032+ u8 vf_id;
8033+ u8 vport_id;
79638034 u8 flags2;
79648035 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_MASK 0x1
79658036 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_SHIFT 0
7966−#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK 0x7F
7967−#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_SHIFT 1
8037+#define ROCE_CREATE_QP_REQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1
8038+#define ROCE_CREATE_QP_REQ_RAMROD_DATA_VF_ID_VALID_SHIFT 1
8039+#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK 0x3F
8040+#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_SHIFT 2
8041+ u8 name_space;
8042+ u8 reserved3[3];
79688043 __le16 regular_latency_phy_queue;
79698044 __le16 dpi;
79708045 };
@@ -7992,8 +8067,10 @@ struct roce_create_qp_resp_ramrod_data { · 21 unmodified lines
79928067 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 11
79938068 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_MASK 0x1
79948069 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_SHIFT 16
7995−#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_MASK 0x7FFF
7996−#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_SHIFT 17
8070+#define ROCE_CREATE_QP_RESP_RAMROD_DATA_VF_ID_VALID_MASK 0x1
8071+#define ROCE_CREATE_QP_RESP_RAMROD_DATA_VF_ID_VALID_SHIFT 17
8072+#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_MASK 0x3FFF
8073+#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_SHIFT 18
79978074 __le16 xrc_domain;
79988075 u8 max_ird;
79998076 u8 traffic_class;
@@ -8020,10 +8097,14 @@ struct roce_create_qp_resp_ramrod_data { · 20 unmodified lines
80208097 struct regpair qp_handle_for_cqe;
80218098 struct regpair qp_handle_for_async;
80228099 __le16 low_latency_phy_queue;
8023− u8 reserved2[2];
8100+ u8 vf_id;
8101+ u8 vport_id;
80248102 __le32 cq_cid;
80258103 __le16 regular_latency_phy_queue;
80268104 __le16 dpi;
8105+ __le32 src_qp_id;
8106+ u8 name_space;
8107+ u8 reserved3[3];
80278108 };
80288109
80298110 /* roce DCQCN received statistics */
@@ -8057,6 +8138,8 @@ struct roce_destroy_qp_resp_output_params { · 27 unmodified lines
80578138 /* RoCE destroy qp responder ramrod data */
80588139 struct roce_destroy_qp_resp_ramrod_data {
80598140 struct regpair output_params_addr;
8141+ __le32 src_qp_id;
8142+ __le32 reserved;
80608143 };
80618144
80628145 /* roce error statistics */
@@ -8140,8 +8223,8 @@ struct roce_modify_qp_req_ramrod_data { · 77 unmodified lines
81408223 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT 9
81418224 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
81428225 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT 10
8143−#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUES_FLG_MASK 0x1
8144−#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUES_FLG_SHIFT 13
8226+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1
8227+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT 13
81458228 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x3
81468229 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT 14
81478230 u8 fields;
@@ -8187,8 +8270,8 @@ struct roce_modify_qp_resp_ramrod_data { · 39 unmodified lines
81878270 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT 8
81888271 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1
81898272 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 9
8190−#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUES_FLG_MASK 0x1
8191−#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUES_FLG_SHIFT 10
8273+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1
8274+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT 10
81928275 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK 0x1F
81938276 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT 11
81948277 u8 fields;
@@ -8229,7 +8312,7 @@ struct roce_query_qp_req_ramrod_data { · 34 unmodified lines
82298312 /* RoCE query qp responder output params */
82308313 struct roce_query_qp_resp_output_params {
82318314 __le32 psn;
8232− __le32 err_flag;
8315+ __le32 flags;
82338316 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1
82348317 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
82358318 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF
@@ -8296,12 +8379,12 @@ struct e4_xstorm_roce_conn_ag_ctx_dq_ext_ld_part { · 60 unmodified lines
82968379 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2
82978380 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
82988381 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
8299−#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK 0x1
8300−#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT 4
8301−#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_MASK 0x1
8302−#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_SHIFT 5
8303−#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_MASK 0x1
8304−#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_SHIFT 6
8382+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_MASK 0x1
8383+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_SHIFT 4
8384+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_MASK 0x1
8385+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_SHIFT 5
8386+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1
8387+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT 6
83058388 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1
83068389 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7
83078390 u8 flags2;
@@ -8674,8 +8757,8 @@ struct e4_tstorm_roce_req_conn_ag_ctx { · 366 unmodified lines
86748757 u8 flags5;
86758758 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
86768759 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
8677−#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
8678−#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
8760+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_DIF_CNT_EN_MASK 0x1
8761+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_DIF_CNT_EN_SHIFT 1
86798762 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
86808763 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
86818764 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
@@ -8688,13 +8771,13 @@ struct e4_tstorm_roce_req_conn_ag_ctx { · 6 unmodified lines
86888771 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
86898772 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
86908773 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
8691− __le32 reg0;
8774+ __le32 dif_rxmit_cnt;
86928775 __le32 snd_nxt_psn;
86938776 __le32 snd_max_psn;
86948777 __le32 orq_prod;
86958778 __le32 reg4;
8696− __le32 reg5;
8697− __le32 reg6;
8779+ __le32 dif_acked_cnt;
8780+ __le32 dif_cnt;
86988781 __le32 reg7;
86998782 __le32 reg8;
87008783 u8 tx_cqe_error_type;
@@ -8705,7 +8788,7 @@ struct e4_tstorm_roce_req_conn_ag_ctx { · 4 unmodified lines
87058788 __le16 snd_sq_cons;
87068789 __le16 conn_dpi;
87078790 __le16 force_comp_cons;
8708− __le32 reg9;
8791+ __le32 dif_rxmit_acked_cnt;
87098792 __le32 reg10;
87108793 };
87118794
@@ -8980,10 +9063,10 @@ struct e4_xstorm_roce_req_conn_ag_ctx { · 268 unmodified lines
89809063 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2
89819064 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1
89829065 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3
8983−#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK 0x1
8984−#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT 4
8985−#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK 0x1
8986−#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT 5
9066+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1
9067+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MSDM_FLUSH_SHIFT 4
9068+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1
9069+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MSEM_FLUSH_SHIFT 5
89879070 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1
89889071 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6
89899072 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
@@ -9209,10 +9292,10 @@ struct e4_xstorm_roce_resp_conn_ag_ctx { · 219 unmodified lines
92099292 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2
92109293 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1
92119294 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3
9212−#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK 0x1
9213−#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT 4
9214−#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK 0x1
9215−#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT 5
9295+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1
9296+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_MSDM_FLUSH_SHIFT 4
9297+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1
9298+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_MSEM_FLUSH_SHIFT 5
92169299 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1
92179300 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6
92189301 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
@@ -9939,7 +10022,7 @@ struct mstorm_iwarp_conn_st_ctx { · 720 unmodified lines
993910022
994010023 /* The iwarp storm context of Ustorm */
994110024 struct ustorm_iwarp_conn_st_ctx {
9942− __le32 reserved[24];
10025+ struct regpair reserved[14];
994310026 };
994410027
994510028 /* iwarp connection context */
@@ -9957,6 +10040,7 @@ struct e4_iwarp_conn_context { · 11 unmodified lines
995710040 struct regpair tstorm_st_padding[2];
995810041 struct mstorm_iwarp_conn_st_ctx mstorm_st_context;
995910042 struct ustorm_iwarp_conn_st_ctx ustorm_st_context;
10043+ struct regpair ustorm_st_padding[2];
996010044 };
996110045
996210046 /* iWARP create QP params passed by driver to FW in CreateQP Request Ramrod */
@@ -10009,7 +10093,8 @@ enum iwarp_eqe_async_opcode { · 46 unmodified lines
1000910093
1001010094 struct iwarp_eqe_data_mpa_async_completion {
1001110095 __le16 ulp_data_len;
10012− u8 reserved[6];
10096+ u8 rtr_type_sent;
10097+ u8 reserved[5];
1001310098 };
1001410099
1001510100 struct iwarp_eqe_data_tcp_async_completion {
@@ -10034,7 +10119,7 @@ enum iwarp_eqe_sync_opcode { · 18 unmodified lines
1003410119
1003510120 /* iWARP EQE completion status */
1003610121 enum iwarp_fw_return_code {
10037− IWARP_CONN_ERROR_TCP_CONNECT_INVALID_PACKET = 5,
10122+ IWARP_CONN_ERROR_TCP_CONNECT_INVALID_PACKET = 6,
1003810123 IWARP_CONN_ERROR_TCP_CONNECTION_RST,
1003910124 IWARP_CONN_ERROR_TCP_CONNECT_TIMEOUT,
1004010125 IWARP_CONN_ERROR_MPA_ERROR_REJECT,
@@ -10203,8 +10288,8 @@ struct iwarp_rxmit_stats_drv { · 162 unmodified lines
1020310288 * offload ramrod.
1020410289 */
1020510290 struct iwarp_tcp_offload_ramrod_data {
10206− struct iwarp_offload_params iwarp;
1020710291 struct tcp_offload_params_opt2 tcp;
10292+ struct iwarp_offload_params iwarp;
1020810293 };
1020910294
1021010295 /* iWARP MPA negotiation types */
drivers/net/ethernet/qlogic/qed/qed_init_ops.c+4−2
@@ -490,10 +490,10 @@ static u32 qed_init_cmd_phase(struct qed_hwfn *p_hwfn, · 489 unmodified lines
490490 int qed_init_run(struct qed_hwfn *p_hwfn,
491491 struct qed_ptt *p_ptt, int phase, int phase_id, int modes)
492492 {
493+ bool b_dmae = (phase != PHASE_ENGINE);
493494 struct qed_dev *cdev = p_hwfn->cdev;
494495 u32 cmd_num, num_init_ops;
495496 union init_op *init_ops;
496− bool b_dmae = false;
497497 int rc = 0;
498498
499499 num_init_ops = cdev->fw_data->init_ops_size;
@@ -522,7 +522,6 @@ int qed_init_run(struct qed_hwfn *p_hwfn, · 22 unmodified lines
522522 case INIT_OP_IF_PHASE:
523523 cmd_num += qed_init_cmd_phase(p_hwfn, &cmd->if_phase,
524524 phase, phase_id);
525− b_dmae = GET_FIELD(data, INIT_IF_PHASE_OP_DMAE_ENABLE);
526525 break;
527526 case INIT_OP_DELAY:
528527 /* qed_init_run is always invoked from
@@ -533,6 +532,9 @@ int qed_init_run(struct qed_hwfn *p_hwfn, · 4 unmodified lines
533532
534533 case INIT_OP_CALLBACK:
535534 rc = qed_init_cmd_cb(p_hwfn, p_ptt, &cmd->callback);
535+ if (phase == PHASE_ENGINE &&
536+ cmd->callback.callback_id == DMAE_READY_CB)
537+ b_dmae = true;
536538 break;
537539 }
538540
drivers/net/ethernet/qlogic/qed/qed_mcp.c+2−0
@@ -48,6 +48,8 @@ · 47 unmodified lines
4848 #include "qed_reg_addr.h"
4949 #include "qed_sriov.h"
5050
51+#define GRCBASE_MCP 0xe00000
52+
5153 #define QED_MCP_RESP_ITER_US 10
5254
5355 #define QED_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */
drivers/net/ethernet/qlogic/qed/qed_roce.c+1−1
@@ -900,7 +900,7 @@ int qed_roce_query_qp(struct qed_hwfn *p_hwfn, · 899 unmodified lines
900900 goto err_resp;
901901
902902 out_params->rq_psn = le32_to_cpu(p_resp_ramrod_res->psn);
903− rq_err_state = GET_FIELD(le32_to_cpu(p_resp_ramrod_res->err_flag),
903+ rq_err_state = GET_FIELD(le32_to_cpu(p_resp_ramrod_res->flags),
904904 ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG);
905905
906906 dma_free_coherent(&p_hwfn->cdev->pdev->dev, sizeof(*p_resp_ramrod_res),
drivers/net/ethernet/qlogic/qede/qede_fp.c+4−4
@@ -848,13 +848,13 @@ static void qede_tpa_start(struct qede_dev *edev, · 847 unmodified lines
848848 qede_set_gro_params(edev, tpa_info->skb, cqe);
849849
850850 cons_buf: /* We still need to handle bd_len_list to consume buffers */
851− if (likely(cqe->ext_bd_len_list[0]))
851+ if (likely(cqe->bw_ext_bd_len_list[0]))
852852 qede_fill_frag_skb(edev, rxq, cqe->tpa_agg_index,
853− le16_to_cpu(cqe->ext_bd_len_list[0]));
853+ le16_to_cpu(cqe->bw_ext_bd_len_list[0]));
854854
855− if (unlikely(cqe->ext_bd_len_list[1])) {
855+ if (unlikely(cqe->bw_ext_bd_len_list[1])) {
856856 DP_ERR(edev,
857− "Unlikely - got a TPA aggregation with more than one ext_bd_len_list entry in the TPA start\n");
857+ "Unlikely - got a TPA aggregation with more than one bw_ext_bd_len_list entry in the TPA start\n");
858858 tpa_info->state = QEDE_AGG_STATE_ERROR;
859859 }
860860 }
include/linux/qed/common_hsi.h+12−9
@@ -76,7 +76,6 @@ · 75 unmodified lines
7676
7777 #define FW_ASSERT_GENERAL_ATTN_IDX 32
7878
79−#define MAX_PINNED_CCFC 32
8079
8180 /* Queue Zone sizes in bytes */
8281 #define TSTORM_QZONE_SIZE 8
@@ -139,10 +138,10 @@ · 56 unmodified lines
139138 #define MAX_NUM_VFS (MAX_NUM_VFS_K2)
140139
141140 #define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB)
142−#define MAX_NUM_FUNCTIONS (MAX_NUM_PFS + MAX_NUM_VFS)
143141
144142 #define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB)
145−#define MAX_FUNCTION_NUMBER (MAX_NUM_PFS + MAX_NUM_VFS)
143+#define MAX_FUNCTION_NUMBER_K2 (MAX_NUM_PFS + MAX_NUM_VFS_K2)
144+#define MAX_NUM_FUNCTIONS (MAX_FUNCTION_NUMBER_K2)
146145
147146 #define MAX_NUM_VPORTS_K2 (208)
148147 #define MAX_NUM_VPORTS_BB (160)
@@ -229,6 +228,7 @@ · 80 unmodified lines
229228 #define DQ_XCM_TOE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
230229 #define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3
231230 #define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG4
231+#define DQ_XCM_ROCE_ACK_EDPM_DORQ_SEQ_CMD DQ_XCM_AGG_VAL_SEL_WORD5
232232
233233 /* UCM agg val selection (HW) */
234234 #define DQ_UCM_AGG_VAL_SEL_WORD0 0
@@ -406,6 +406,7 @@ · 171 unmodified lines
406406
407407 /* Number of Protocol Indices per Status Block */
408408 #define PIS_PER_SB_E4 12
409+#define MAX_PIS_PER_SB PIS_PER_SB
409410
410411 #define CAU_HC_STOPPED_STATE 3
411412 #define CAU_HC_DISABLE_STATE 4
@@ -436,8 +437,6 @@ · 24 unmodified lines
436437 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
437438
438439 #define IGU_CMD_INT_ACK_BASE 0x0400
439−#define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + \
440− MAX_TOT_SB_PER_PATH - 1)
441440 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff
442441
443442 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0
@@ -450,8 +449,6 @@ · 6 unmodified lines
450449 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05f6
451450
452451 #define IGU_CMD_PROD_UPD_BASE 0x0600
453−#define IGU_CMD_PROD_UPD_UPPER (IGU_CMD_PROD_UPD_BASE +\
454− MAX_TOT_SB_PER_PATH - 1)
455452 #define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff
456453
457454 /*****************/
@@ -741,6 +738,8 @@ enum protocol_type { · 283 unmodified lines
741738 PROTOCOLID_PREROCE,
742739 PROTOCOLID_COMMON,
743740 PROTOCOLID_RESERVED1,
741+ PROTOCOLID_RDMA,
742+ PROTOCOLID_SCSI,
744743 MAX_PROTOCOL_TYPE
745744 };
746745
@@ -761,6 +760,10 @@ union rdma_eqe_data { · 14 unmodified lines
761760 struct rdma_eqe_destroy_qp rdma_destroy_qp_data;
762761 };
763762
763+struct tstorm_queue_zone {
764+ __le32 reserved[2];
765+};
766+
764767 /* Ustorm Queue Zone */
765768 struct ustorm_eth_queue_zone {
766769 struct coalescing_timeset int_coalescing_timeset;
@@ -883,8 +886,8 @@ struct db_l2_dpm_data { · 116 unmodified lines
883886 #define DB_L2_DPM_DATA_RESERVED0_SHIFT 27
884887 #define DB_L2_DPM_DATA_SGE_NUM_MASK 0x7
885888 #define DB_L2_DPM_DATA_SGE_NUM_SHIFT 28
886−#define DB_L2_DPM_DATA_GFS_SRC_EN_MASK 0x1
887−#define DB_L2_DPM_DATA_GFS_SRC_EN_SHIFT 31
889+#define DB_L2_DPM_DATA_TGFS_SRC_EN_MASK 0x1
890+#define DB_L2_DPM_DATA_TGFS_SRC_EN_SHIFT 31
888891 };
889892
890893 /* Structure for SGE in a DPM doorbell of type DPM_L2_BD */
include/linux/qed/eth_common.h+56−22
@@ -38,9 +38,11 @@ · 37 unmodified lines
3838 /********************/
3939
4040 #define ETH_HSI_VER_MAJOR 3
41−#define ETH_HSI_VER_MINOR 10
41+#define ETH_HSI_VER_MINOR 11
4242
43−#define ETH_HSI_VER_NO_PKT_LEN_TUNN 5
43+#define ETH_HSI_VER_NO_PKT_LEN_TUNN 5
44+/* Maximum number of pinned L2 connections (CIDs) */
45+#define ETH_PINNED_CONN_MAX_NUM 32
4446
4547 #define ETH_CACHE_LINE_SIZE 64
4648 #define ETH_RX_CQE_GAP 32
@@ -61,6 +63,7 @@ · 14 unmodified lines
6163 #define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3
6264 #define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2
6365 #define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2
66+#define ETH_TX_MIN_BDS_PER_PKT_W_VPORT_FORWARDING 4
6467 #define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 4 + 12 + 8))
6568 #define ETH_TX_MAX_LSO_HDR_BYTES 510
6669 #define ETH_TX_LSO_WINDOW_BDS_NUM (18 - 1)
@@ -75,9 +78,8 @@ · 8 unmodified lines
7578 #define ETH_NUM_STATISTIC_COUNTERS_QUAD_VF_ZONE \
7679 (ETH_NUM_STATISTIC_COUNTERS - 3 * MAX_NUM_VFS / 4)
7780
78−/* Maximum number of buffers, used for RX packet placement */
7981 #define ETH_RX_MAX_BUFF_PER_PKT 5
80−#define ETH_RX_BD_THRESHOLD 12
82+#define ETH_RX_BD_THRESHOLD 16
8183
8284 /* Num of MAC/VLAN filters */
8385 #define ETH_NUM_MAC_FILTERS 512
@@ -96,24 +98,24 @@ · 12 unmodified lines
9698 #define ETH_RSS_ENGINE_NUM_BB 127
9799
98100 /* TPA constants */
99−#define ETH_TPA_MAX_AGGS_NUM 64
100−#define ETH_TPA_CQE_START_LEN_LIST_SIZE ETH_RX_MAX_BUFF_PER_PKT
101−#define ETH_TPA_CQE_CONT_LEN_LIST_SIZE 6
102−#define ETH_TPA_CQE_END_LEN_LIST_SIZE 4
101+#define ETH_TPA_MAX_AGGS_NUM 64
102+#define ETH_TPA_CQE_START_BW_LEN_LIST_SIZE 2
103+#define ETH_TPA_CQE_CONT_LEN_LIST_SIZE 6
104+#define ETH_TPA_CQE_END_LEN_LIST_SIZE 4
103105
104106 /* Control frame check constants */
105−#define ETH_CTL_FRAME_ETH_TYPE_NUM 4
107+#define ETH_CTL_FRAME_ETH_TYPE_NUM 4
106108
107109 /* GFS constants */
108110 #define ETH_GFT_TRASHCAN_VPORT 0x1FF /* GFT drop flow vport number */
109111
110112 /* Destination port mode */
111−enum dest_port_mode {
112− DEST_PORT_PHY,
113− DEST_PORT_LOOPBACK,
114− DEST_PORT_PHY_LOOPBACK,
115− DEST_PORT_DROP,
116− MAX_DEST_PORT_MODE
113+enum dst_port_mode {
114+ DST_PORT_PHY,
115+ DST_PORT_LOOPBACK,
116+ DST_PORT_PHY_LOOPBACK,
117+ DST_PORT_DROP,
118+ MAX_DST_PORT_MODE
117119 };
118120
119121 /* Ethernet address type */
@@ -167,8 +169,8 @@ struct eth_tx_data_2nd_bd { · 47 unmodified lines
167169 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0
168170 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK 0x3
169171 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT 4
170−#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_MASK 0x3
171−#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_SHIFT 6
172+#define ETH_TX_DATA_2ND_BD_DST_PORT_MODE_MASK 0x3
173+#define ETH_TX_DATA_2ND_BD_DST_PORT_MODE_SHIFT 6
172174 #define ETH_TX_DATA_2ND_BD_START_BD_MASK 0x1
173175 #define ETH_TX_DATA_2ND_BD_START_BD_SHIFT 8
174176 #define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK 0x3
@@ -244,8 +246,9 @@ struct eth_fast_path_rx_reg_cqe { · 69 unmodified lines
244246 struct eth_tunnel_parsing_flags tunnel_pars_flags;
245247 u8 bd_num;
246248 u8 reserved;
247− __le16 flow_id;
248− u8 reserved1[11];
249+ __le16 reserved2;
250+ __le32 flow_id_or_resource_id;
251+ u8 reserved1[7];
249252 struct eth_pmd_flow_flags pmd_flags;
250253 };
251254
@@ -296,9 +299,10 @@ struct eth_fast_path_rx_tpa_start_cqe { · 44 unmodified lines
296299 struct eth_tunnel_parsing_flags tunnel_pars_flags;
297300 u8 tpa_agg_index;
298301 u8 header_len;
299− __le16 ext_bd_len_list[ETH_TPA_CQE_START_LEN_LIST_SIZE];
300− __le16 flow_id;
301− u8 reserved;
302+ __le16 bw_ext_bd_len_list[ETH_TPA_CQE_START_BW_LEN_LIST_SIZE];
303+ __le16 reserved2;
304+ __le32 flow_id_or_resource_id;
305+ u8 reserved[3];
302306 struct eth_pmd_flow_flags pmd_flags;
303307 };
304308
@@ -407,6 +411,29 @@ struct eth_tx_3rd_bd { · 102 unmodified lines
407411 struct eth_tx_data_3rd_bd data;
408412 };
409413
414+/* The parsing information data for the forth tx bd of a given packet. */
415+struct eth_tx_data_4th_bd {
416+ u8 dst_vport_id;
417+ u8 reserved4;
418+ __le16 bitfields;
419+#define ETH_TX_DATA_4TH_BD_DST_VPORT_ID_VALID_MASK 0x1
420+#define ETH_TX_DATA_4TH_BD_DST_VPORT_ID_VALID_SHIFT 0
421+#define ETH_TX_DATA_4TH_BD_RESERVED1_MASK 0x7F
422+#define ETH_TX_DATA_4TH_BD_RESERVED1_SHIFT 1
423+#define ETH_TX_DATA_4TH_BD_START_BD_MASK 0x1
424+#define ETH_TX_DATA_4TH_BD_START_BD_SHIFT 8
425+#define ETH_TX_DATA_4TH_BD_RESERVED2_MASK 0x7F
426+#define ETH_TX_DATA_4TH_BD_RESERVED2_SHIFT 9
427+ __le16 reserved3;
428+};
429+
430+/* The forth tx bd of a given packet */
431+struct eth_tx_4th_bd {
432+ struct regpair addr; /* Single continuous buffer */
433+ __le16 nbytes; /* Number of bytes in this BD */
434+ struct eth_tx_data_4th_bd data; /* Parsing information data */
435+};
436+
410437 /* Complementary information for the regular tx bd of a given packet */
411438 struct eth_tx_data_bd {
412439 __le16 reserved0;
@@ -431,6 +458,7 @@ union eth_tx_bd_types { · 18 unmodified lines
431458 struct eth_tx_1st_bd first_bd;
432459 struct eth_tx_2nd_bd second_bd;
433460 struct eth_tx_3rd_bd third_bd;
461+ struct eth_tx_4th_bd fourth_bd;
434462 struct eth_tx_bd reg_bd;
435463 };
436464
@@ -443,6 +471,12 @@ enum eth_tx_tunn_type { · 6 unmodified lines
443471 MAX_ETH_TX_TUNN_TYPE
444472 };
445473
474+/* Mstorm Queue Zone */
475+struct mstorm_eth_queue_zone {
476+ struct eth_rx_prod_data rx_producers;
477+ __le32 reserved[3];
478+};
479+
446480 /* Ystorm Queue Zone */
447481 struct xstorm_eth_queue_zone {
448482 struct coalescing_timeset int_coalescing_timeset;