Future devices will support multiple device memory page sizes. In addition, an API for the user was added for it to be able to control the device memory allocation page size. This patch is a complementary patch to inform the user of the available page size supported by the device.
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| @@ -348,33 +348,35 @@ enum hl_server_type { · 347 unmodified lines | |||
| 348 | * The address which accessing it caused the razwi. | 348 | * The address which accessing it caused the razwi. |
| 349 | * Razwi initiator. | 349 | * Razwi initiator. |
| 350 | * Razwi cause, was it a page fault or MMU access error. | 350 | * Razwi cause, was it a page fault or MMU access error. |
| 351 | * HL_INFO_DEV_MEM_ALLOC_PAGE_SIZES - Retrieve valid page sizes for device memory allocation | ||
| 351 | */ | 352 | */ |
| 352 | #define HL_INFO_HW_IP_INFO 0 | 353 | #define HL_INFO_HW_IP_INFO 0 |
| 353 | #define HL_INFO_HW_EVENTS 1 | 354 | #define HL_INFO_HW_EVENTS 1 |
| 354 | #define HL_INFO_DRAM_USAGE 2 | 355 | #define HL_INFO_DRAM_USAGE 2 |
| 355 | #define HL_INFO_HW_IDLE 3 | 356 | #define HL_INFO_HW_IDLE 3 |
| 356 | #define HL_INFO_DEVICE_STATUS 4 | 357 | #define HL_INFO_DEVICE_STATUS 4 |
| 357 | #define HL_INFO_DEVICE_UTILIZATION 6 | 358 | #define HL_INFO_DEVICE_UTILIZATION 6 |
| 358 | #define HL_INFO_HW_EVENTS_AGGREGATE 7 | 359 | #define HL_INFO_HW_EVENTS_AGGREGATE 7 |
| 359 | #define HL_INFO_CLK_RATE 8 | 360 | #define HL_INFO_CLK_RATE 8 |
| 360 | #define HL_INFO_RESET_COUNT 9 | 361 | #define HL_INFO_RESET_COUNT 9 |
| 361 | #define HL_INFO_TIME_SYNC 10 | 362 | #define HL_INFO_TIME_SYNC 10 |
| 362 | #define HL_INFO_CS_COUNTERS 11 | 363 | #define HL_INFO_CS_COUNTERS 11 |
| 363 | #define HL_INFO_PCI_COUNTERS 12 | 364 | #define HL_INFO_PCI_COUNTERS 12 |
| 364 | #define HL_INFO_CLK_THROTTLE_REASON 13 | 365 | #define HL_INFO_CLK_THROTTLE_REASON 13 |
| 365 | #define HL_INFO_SYNC_MANAGER 14 | 366 | #define HL_INFO_SYNC_MANAGER 14 |
| 366 | #define HL_INFO_TOTAL_ENERGY 15 | 367 | #define HL_INFO_TOTAL_ENERGY 15 |
| 367 | #define HL_INFO_PLL_FREQUENCY 16 | 368 | #define HL_INFO_PLL_FREQUENCY 16 |
| 368 | #define HL_INFO_POWER 17 | 369 | #define HL_INFO_POWER 17 |
| 369 | #define HL_INFO_OPEN_STATS 18 | 370 | #define HL_INFO_OPEN_STATS 18 |
| 370 | #define HL_INFO_DRAM_REPLACED_ROWS 21 | 371 | #define HL_INFO_DRAM_REPLACED_ROWS 21 |
| 371 | #define HL_INFO_DRAM_PENDING_ROWS 22 | 372 | #define HL_INFO_DRAM_PENDING_ROWS 22 |
| 372 | #define HL_INFO_LAST_ERR_OPEN_DEV_TIME 23 | 373 | #define HL_INFO_LAST_ERR_OPEN_DEV_TIME 23 |
| 373 | #define HL_INFO_CS_TIMEOUT_EVENT 24 | 374 | #define HL_INFO_CS_TIMEOUT_EVENT 24 |
| 374 | #define HL_INFO_RAZWI_EVENT 25 | 375 | #define HL_INFO_RAZWI_EVENT 25 |
| 375 | 376 | #define HL_INFO_DEV_MEM_ALLOC_PAGE_SIZES 26 | |
| 376 | #define HL_INFO_VERSION_MAX_LEN 128 | 377 | |
| 377 | #define HL_INFO_CARD_NAME_MAX_LEN 16 | 378 | #define HL_INFO_VERSION_MAX_LEN 128 |
| 379 | #define HL_INFO_CARD_NAME_MAX_LEN 16 | ||
| 378 | 380 | ||
| 379 | /** | 381 | /** |
| 380 | * struct hl_info_hw_ip_info - hardware information on various IPs in the ASIC | 382 | * struct hl_info_hw_ip_info - hardware information on various IPs in the ASIC |
| @@ -643,6 +645,15 @@ struct hl_info_razwi_event { · 262 unmodified lines | |||
| 643 | __u8 pad[2]; | 645 | __u8 pad[2]; |
| 644 | }; | 646 | }; |
| 645 | 647 | ||
| 648 | /** | ||
| 649 | * struct hl_info_dev_memalloc_page_sizes - valid page sizes in device mem alloc information. | ||
| 650 | * @page_order_bitmask: bitmap in which a set bit represents the order of the supported page size | ||
| 651 | * (e.g. 0x2100000 means that 1MB and 32MB pages are supported). | ||
| 652 | */ | ||
| 653 | struct hl_info_dev_memalloc_page_sizes { | ||
| 654 | __u64 page_order_bitmask; | ||
| 655 | }; | ||
| 656 | |||
| 646 | enum gaudi_dcores { | 657 | enum gaudi_dcores { |
| 647 | HL_GAUDI_WS_DCORE, | 658 | HL_GAUDI_WS_DCORE, |
| 648 | HL_GAUDI_WN_DCORE, | 659 | HL_GAUDI_WN_DCORE, |