Merge tag 'dmaengine-5.2-rc1' of git://git.infradead.org/users/vkoul/slave-dma

Pull dmaengine updates from Vinod Koul: - Updates to stm32 dma residue calculations - Interleave dma capability to axi-dmac and support for ZynqMP arch - Rework of channel assignment for rcar dma - Debugfs for pl330 driver - Support for Tegra186/Tegra194, refactoring for new chips and support for pause/resume - Updates to axi-dmac, bcm2835, fsl-edma, idma64, imx-sdma, rcar-dmac, stm32-dma etc - dev_get_drvdata() updates on few drivers * tag 'dmaengine-5.2-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (34 commits) dmaengine: tegra210-adma: restore channel status dmaengine: tegra210-dma: free dma controller in remove() dmaengine: tegra210-adma: add pause/resume support dmaengine: tegra210-adma: add support for Tegra186/Tegra194 Documentation: DT: Add compatibility binding for Tegra186 dmaengine: tegra210-adma: prepare for supporting newer Tegra chips dmaengine: at_xdmac: remove a stray bottom half unlock dmaengine: fsl-edma: Adjust indentation dmaengine: fsl-edma: Fix typo in Vybrid name dmaengine: stm32-dma: fix residue calculation in stm32-dma dmaengine: nbpfaxi: Use dev_get_drvdata() dmaengine: bcm-sba-raid: Use dev_get_drvdata() dmaengine: stm32-dma: Fix unsigned variable compared with zero dmaengine: stm32-dma: use platform_get_irq() dmaengine: rcar-dmac: Update copyright information dmaengine: imx-sdma: Only check ratio on parts that support 1:1 dmaengine: xgene-dma: fix spelling mistake "descripto" -> "descriptor" dmaengine: idma64: Move driver name to the header dmaengine: bcm2835: Drop duplicate capability setting. dmaengine: pl330: _stop: clear interrupt status ...

Linus Torvalds committed 7 years ago

Commit 055128e2 parents ddab533 f33e7bb23 files · +566 −169Browse files

Unified · Split

23 files

Documentation/devicetree/bindings/dma/adi,axi-dmac.txt +2 −2
Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.txt +3 −1
drivers/dma/Kconfig +1 −1
drivers/dma/amba-pl08x.c +16 −6
drivers/dma/at_xdmac.c +59 −8
drivers/dma/bcm-sba-raid.c +1 −2
drivers/dma/bcm2835-dma.c +0 −1
drivers/dma/dma-axi-dmac.c +83 −33
drivers/dma/fsl-edma-common.h +1 −1
drivers/dma/fsl-edma.c +3 −3
drivers/dma/idma64.c +8 −7
drivers/dma/idma64.h +2 −0
drivers/dma/imx-sdma.c +14 −1
drivers/dma/nbpfaxi.c +2 −2
drivers/dma/pl330.c +58 −3
drivers/dma/sh/rcar-dmac.c +2 −2
drivers/dma/stm32-dma.c +85 −18
drivers/dma/tegra210-adma.c +204 −65
drivers/dma/xgene-dma.c +3 −3
drivers/mfd/intel-lpss.c +2 −2
drivers/spi/spi-pxa2xx.c +1 −6
drivers/tty/serial/8250/8250_dw.c +2 −2
include/linux/dma/idma64.h +14 −0

Documentation/devicetree/bindings/dma/adi,axi-dmac.txt+2−2

@@ -18,7 +18,6 @@ Required properties for adi,channels sub-node: · 17 unmodified lines
18	18
19	19	Required channel sub-node properties:
20	20	- reg: Which channel this node refers to.
21		− - adi,length-width: Width of the DMA transfer length register.
22	21	- adi,source-bus-width,
23	22	adi,destination-bus-width: Width of the source or destination bus in bits.
24	23	- adi,source-bus-type,
@@ -28,7 +27,8 @@ Required channel sub-node properties: · 3 unmodified lines
28	27	1 (AXI_DMAC_TYPE_AXI_STREAM): Streaming AXI interface
29	28	2 (AXI_DMAC_TYPE_AXI_FIFO): FIFO interface
30	29
31		−Optional channel properties:
	30	+Deprecated optional channel properties:
	31	+ - adi,length-width: Width of the DMA transfer length register.
32	32	- adi,cyclic: Must be set if the channel supports hardware cyclic DMA
33	33	transfers.
34	34	- adi,2d: Must be set if the channel supports hardware 2D DMA transfers.

Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.txt+3−1

@@ -4,7 +4,9 @@ The Tegra Audio DMA controller that is used for transferring data · 3 unmodified lines
4	4	between system memory and the Audio Processing Engine (APE).
5	5
6	6	Required properties:
7		−- compatible: Must be "nvidia,tegra210-adma".
	7	+- compatible: Should contain one of the following:
	8	+ - "nvidia,tegra210-adma": for Tegra210
	9	+ - "nvidia,tegra186-adma": for Tegra186 and Tegra194
8	10	- reg: Should contain DMA registers location and length. This should be
9	11	a single entry that includes all of the per-channel registers in one
10	12	contiguous bank.

drivers/dma/Kconfig+1−1

@@ -99,7 +99,7 @@ config AT_XDMAC · 98 unmodified lines
99	99
100	100	config AXI_DMAC
101	101	tristate "Analog Devices AXI-DMAC DMA support"
102		− depends on MICROBLAZE \|\| NIOS2 \|\| ARCH_ZYNQ \|\| ARCH_SOCFPGA \|\| COMPILE_TEST
	102	+ depends on MICROBLAZE \|\| NIOS2 \|\| ARCH_ZYNQ \|\| ARCH_ZYNQMP \|\| ARCH_SOCFPGA \|\| COMPILE_TEST
103	103	select DMA_ENGINE
104	104	select DMA_VIRTUAL_CHANNELS
105	105	help

drivers/dma/amba-pl08x.c+16−6

@@ -254,6 +254,7 @@ enum pl08x_dma_chan_state { · 253 unmodified lines
254	254	* @slave: whether this channel is a device (slave) or for memcpy
255	255	* @signal: the physical DMA request signal which this channel is using
256	256	* @mux_use: count of descriptors using this DMA request signal setting
	257	+ * @waiting_at: time in jiffies when this channel moved to waiting state
257	258	*/
258	259	struct pl08x_dma_chan {
259	260	struct virt_dma_chan vc;
@@ -267,6 +268,7 @@ struct pl08x_dma_chan { · 7 unmodified lines
267	268	bool slave;
268	269	int signal;
269	270	unsigned mux_use;
	271	+ unsigned long waiting_at;
270	272	};
271	273
272	274	/**
@@ -875,6 +877,7 @@ static void pl08x_phy_alloc_and_start(struct pl08x_dma_chan *plchan) · 602 unmodified lines
875	877	if (!ch) {
876	878	dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
877	879	plchan->state = PL08X_CHAN_WAITING;
	880	+ plchan->waiting_at = jiffies;
878	881	return;
879	882	}
880	883
@@ -913,22 +916,29 @@ static void pl08x_phy_free(struct pl08x_dma_chan *plchan) · 32 unmodified lines
913	916	{
914	917	struct pl08x_driver_data *pl08x = plchan->host;
915	918	struct pl08x_dma_chan p, next;
916		−
	919	+ unsigned long waiting_at;
917	920	retry:
918	921	next = NULL;
	922	+ waiting_at = jiffies;
919	923
920		− /* Find a waiting virtual channel for the next transfer. */
	924	+ /*
	925	+ * Find a waiting virtual channel for the next transfer.
	926	+ * To be fair, time when each channel reached waiting state is compared
	927	+ * to select channel that is waiting for the longest time.
	928	+ */
921	929	list_for_each_entry(p, &pl08x->memcpy.channels, vc.chan.device_node)
922		− if (p->state == PL08X_CHAN_WAITING) {
	930	+ if (p->state == PL08X_CHAN_WAITING &&
	931	+ p->waiting_at <= waiting_at) {
923	932	next = p;
924		− break;
	933	+ waiting_at = p->waiting_at;
925	934	}
926	935
927	936	if (!next && pl08x->has_slave) {
928	937	list_for_each_entry(p, &pl08x->slave.channels, vc.chan.device_node)
929		− if (p->state == PL08X_CHAN_WAITING) {
	938	+ if (p->state == PL08X_CHAN_WAITING &&
	939	+ p->waiting_at <= waiting_at) {
930	940	next = p;
931		− break;
	941	+ waiting_at = p->waiting_at;
932	942	}
933	943	}
934	944

drivers/dma/at_xdmac.c+59−8

@@ -308,6 +308,11 @@ static inline int at_xdmac_csize(u32 maxburst) · 307 unmodified lines
308	308	return csize;
309	309	};
310	310
	311	+static inline bool at_xdmac_chan_is_peripheral_xfer(u32 cfg)
	312	+{
	313	+ return cfg & AT_XDMAC_CC_TYPE_PER_TRAN;
	314	+}
	315	+
311	316	static inline u8 at_xdmac_get_dwidth(u32 cfg)
312	317	{
313	318	return (cfg & AT_XDMAC_CC_DWIDTH_MASK) >> AT_XDMAC_CC_DWIDTH_OFFSET;
@@ -389,7 +394,13 @@ static void at_xdmac_start_xfer(struct at_xdmac_chan *atchan, · 75 unmodified lines
389	394	at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
390	395
391	396	at_xdmac_chan_write(atchan, AT_XDMAC_CID, 0xffffffff);
392		− reg = AT_XDMAC_CIE_RBEIE \| AT_XDMAC_CIE_WBEIE \| AT_XDMAC_CIE_ROIE;
	397	+ reg = AT_XDMAC_CIE_RBEIE \| AT_XDMAC_CIE_WBEIE;
	398	+ /*
	399	+ * Request Overflow Error is only for peripheral synchronized transfers
	400	+ */
	401	+ if (at_xdmac_chan_is_peripheral_xfer(first->lld.mbr_cfg))
	402	+ reg \|= AT_XDMAC_CIE_ROIE;
	403	+
393	404	/*
394	405	* There is no end of list when doing cyclic dma, we need to get
395	406	* an interrupt after each periods.
@@ -1575,6 +1586,46 @@ static void at_xdmac_handle_cyclic(struct at_xdmac_chan *atchan) · 1179 unmodified lines
1575	1586	dmaengine_desc_get_callback_invoke(txd, NULL);
1576	1587	}
1577	1588
	1589	+static void at_xdmac_handle_error(struct at_xdmac_chan *atchan)
	1590	+{
	1591	+ struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
	1592	+ struct at_xdmac_desc *bad_desc;
	1593	+
	1594	+ /*
	1595	+ * The descriptor currently at the head of the active list is
	1596	+ * broken. Since we don't have any way to report errors, we'll
	1597	+ * just have to scream loudly and try to continue with other
	1598	+ * descriptors queued (if any).
	1599	+ */
	1600	+ if (atchan->irq_status & AT_XDMAC_CIS_RBEIS)
	1601	+ dev_err(chan2dev(&atchan->chan), "read bus error!!!");
	1602	+ if (atchan->irq_status & AT_XDMAC_CIS_WBEIS)
	1603	+ dev_err(chan2dev(&atchan->chan), "write bus error!!!");
	1604	+ if (atchan->irq_status & AT_XDMAC_CIS_ROIS)
	1605	+ dev_err(chan2dev(&atchan->chan), "request overflow error!!!");
	1606	+
	1607	+ spin_lock_bh(&atchan->lock);
	1608	+
	1609	+ /* Channel must be disabled first as it's not done automatically */
	1610	+ at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask);
	1611	+ while (at_xdmac_read(atxdmac, AT_XDMAC_GS) & atchan->mask)
	1612	+ cpu_relax();
	1613	+
	1614	+ bad_desc = list_first_entry(&atchan->xfers_list,
	1615	+ struct at_xdmac_desc,
	1616	+ xfer_node);
	1617	+
	1618	+ spin_unlock_bh(&atchan->lock);
	1619	+
	1620	+ /* Print bad descriptor's details if needed */
	1621	+ dev_dbg(chan2dev(&atchan->chan),
	1622	+ "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
	1623	+ __func__, &bad_desc->lld.mbr_sa, &bad_desc->lld.mbr_da,
	1624	+ bad_desc->lld.mbr_ubc);
	1625	+
	1626	+ /* Then continue with usual descriptor management */
	1627	+}
	1628	+
1578	1629	static void at_xdmac_tasklet(unsigned long data)
1579	1630	{
1580	1631	struct at_xdmac_chan atchan = (struct at_xdmac_chan )data;
@@ -1594,19 +1645,19 @@ static void at_xdmac_tasklet(unsigned long data) · 13 unmodified lines
1594	1645	\|\| (atchan->irq_status & error_mask)) {
1595	1646	struct dma_async_tx_descriptor *txd;
1596	1647
1597		− if (atchan->irq_status & AT_XDMAC_CIS_RBEIS)
1598		− dev_err(chan2dev(&atchan->chan), "read bus error!!!");
1599		− if (atchan->irq_status & AT_XDMAC_CIS_WBEIS)
1600		− dev_err(chan2dev(&atchan->chan), "write bus error!!!");
1601		− if (atchan->irq_status & AT_XDMAC_CIS_ROIS)
1602		− dev_err(chan2dev(&atchan->chan), "request overflow error!!!");
	1648	+ if (atchan->irq_status & error_mask)
	1649	+ at_xdmac_handle_error(atchan);
1603	1650
1604	1651	spin_lock(&atchan->lock);
1605	1652	desc = list_first_entry(&atchan->xfers_list,
1606	1653	struct at_xdmac_desc,
1607	1654	xfer_node);
1608	1655	dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
1609		− BUG_ON(!desc->active_xfer);
	1656	+ if (!desc->active_xfer) {
	1657	+ dev_err(chan2dev(&atchan->chan), "Xfer not active: exiting");
	1658	+ spin_unlock(&atchan->lock);
	1659	+ return;
	1660	+ }
1610	1661
1611	1662	txd = &desc->tx_dma_desc;
1612	1663

drivers/dma/bcm-sba-raid.c+1−2

@@ -1459,8 +1459,7 @@ static void sba_receive_message(struct mbox_client cl, void msg) · 1458 unmodified lines
1459	1459
1460	1460	static int sba_debugfs_stats_show(struct seq_file file, void offset)
1461	1461	{
1462		− struct platform_device *pdev = to_platform_device(file->private);
1463		− struct sba_device *sba = platform_get_drvdata(pdev);
	1462	+ struct sba_device *sba = dev_get_drvdata(file->private);
1464	1463
1465	1464	/* Write stats in file */
1466	1465	sba_write_stats_in_seqfile(sba, file);

drivers/dma/bcm2835-dma.c+0−1

@@ -891,7 +891,6 @@ static int bcm2835_dma_probe(struct platform_device *pdev) · 890 unmodified lines
891	891	dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
892	892	dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask);
893	893	dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
894		− dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
895	894	dma_cap_set(DMA_MEMCPY, od->ddev.cap_mask);
896	895	od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources;
897	896	od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources;

drivers/dma/dma-axi-dmac.c+83−33

@@ -166,7 +166,7 @@ static int axi_dmac_dest_is_mem(struct axi_dmac_chan *chan) · 165 unmodified lines
166	166
167	167	static bool axi_dmac_check_len(struct axi_dmac_chan *chan, unsigned int len)
168	168	{
169		− if (len == 0 \|\| len > chan->max_length)
	169	+ if (len == 0)
170	170	return false;
171	171	if ((len & chan->align_mask) != 0) /* Not aligned */
172	172	return false;
@@ -379,6 +379,49 @@ static struct axi_dmac_desc *axi_dmac_alloc_desc(unsigned int num_sgs) · 206 unmodified lines
379	379	return desc;
380	380	}
381	381
	382	+static struct axi_dmac_sg axi_dmac_fill_linear_sg(struct axi_dmac_chan chan,
	383	+ enum dma_transfer_direction direction, dma_addr_t addr,
	384	+ unsigned int num_periods, unsigned int period_len,
	385	+ struct axi_dmac_sg *sg)
	386	+{
	387	+ unsigned int num_segments, i;
	388	+ unsigned int segment_size;
	389	+ unsigned int len;
	390	+
	391	+ /* Split into multiple equally sized segments if necessary */
	392	+ num_segments = DIV_ROUND_UP(period_len, chan->max_length);
	393	+ segment_size = DIV_ROUND_UP(period_len, num_segments);
	394	+ /* Take care of alignment */
	395	+ segment_size = ((segment_size - 1) \| chan->align_mask) + 1;
	396	+
	397	+ for (i = 0; i < num_periods; i++) {
	398	+ len = period_len;
	399	+
	400	+ while (len > segment_size) {
	401	+ if (direction == DMA_DEV_TO_MEM)
	402	+ sg->dest_addr = addr;
	403	+ else
	404	+ sg->src_addr = addr;
	405	+ sg->x_len = segment_size;
	406	+ sg->y_len = 1;
	407	+ sg++;
	408	+ addr += segment_size;
	409	+ len -= segment_size;
	410	+ }
	411	+
	412	+ if (direction == DMA_DEV_TO_MEM)
	413	+ sg->dest_addr = addr;
	414	+ else
	415	+ sg->src_addr = addr;
	416	+ sg->x_len = len;
	417	+ sg->y_len = 1;
	418	+ sg++;
	419	+ addr += len;
	420	+ }
	421	+
	422	+ return sg;
	423	+}
	424	+
382	425	static struct dma_async_tx_descriptor *axi_dmac_prep_slave_sg(
383	426	struct dma_chan c, struct scatterlist sgl,
384	427	unsigned int sg_len, enum dma_transfer_direction direction,
@@ -386,16 +429,24 @@ static struct dma_async_tx_descriptor *axi_dmac_prep_slave_sg( · 1 unmodified line
386	429	{
387	430	struct axi_dmac_chan *chan = to_axi_dmac_chan(c);
388	431	struct axi_dmac_desc *desc;
	432	+ struct axi_dmac_sg *dsg;
389	433	struct scatterlist *sg;
	434	+ unsigned int num_sgs;
390	435	unsigned int i;
391	436
392	437	if (direction != chan->direction)
393	438	return NULL;
394	439
395		− desc = axi_dmac_alloc_desc(sg_len);
	440	+ num_sgs = 0;
	441	+ for_each_sg(sgl, sg, sg_len, i)
	442	+ num_sgs += DIV_ROUND_UP(sg_dma_len(sg), chan->max_length);
	443	+
	444	+ desc = axi_dmac_alloc_desc(num_sgs);
396	445	if (!desc)
397	446	return NULL;
398	447
	448	+ dsg = desc->sg;
	449	+
399	450	for_each_sg(sgl, sg, sg_len, i) {
400	451	if (!axi_dmac_check_addr(chan, sg_dma_address(sg)) \|\|
401	452	!axi_dmac_check_len(chan, sg_dma_len(sg))) {
@@ -403,12 +454,8 @@ static struct dma_async_tx_descriptor *axi_dmac_prep_slave_sg( · 1 unmodified line
403	454	return NULL;
404	455	}
405	456
406		− if (direction == DMA_DEV_TO_MEM)
407		− desc->sg[i].dest_addr = sg_dma_address(sg);
408		− else
409		− desc->sg[i].src_addr = sg_dma_address(sg);
410		− desc->sg[i].x_len = sg_dma_len(sg);
411		− desc->sg[i].y_len = 1;
	457	+ dsg = axi_dmac_fill_linear_sg(chan, direction, sg_dma_address(sg), 1,
	458	+ sg_dma_len(sg), dsg);
412	459	}
413	460
414	461	desc->cyclic = false;
@@ -423,7 +470,7 @@ static struct dma_async_tx_descriptor *axi_dmac_prep_dma_cyclic( · 8 unmodified lines
423	470	{
424	471	struct axi_dmac_chan *chan = to_axi_dmac_chan(c);
425	472	struct axi_dmac_desc *desc;
426		− unsigned int num_periods, i;
	473	+ unsigned int num_periods, num_segments;
427	474
428	475	if (direction != chan->direction)
429	476	return NULL;
@@ -436,20 +483,14 @@ static struct dma_async_tx_descriptor *axi_dmac_prep_dma_cyclic( · 6 unmodified lines
436	483	return NULL;
437	484
438	485	num_periods = buf_len / period_len;
	486	+ num_segments = DIV_ROUND_UP(period_len, chan->max_length);
439	487
440		− desc = axi_dmac_alloc_desc(num_periods);
	488	+ desc = axi_dmac_alloc_desc(num_periods * num_segments);
441	489	if (!desc)
442	490	return NULL;
443	491
444		− for (i = 0; i < num_periods; i++) {
445		− if (direction == DMA_DEV_TO_MEM)
446		− desc->sg[i].dest_addr = buf_addr;
447		− else
448		− desc->sg[i].src_addr = buf_addr;
449		− desc->sg[i].x_len = period_len;
450		− desc->sg[i].y_len = 1;
451		− buf_addr += period_len;
452		− }
	492	+ axi_dmac_fill_linear_sg(chan, direction, buf_addr, num_periods,
	493	+ period_len, desc->sg);
453	494
454	495	desc->cyclic = true;
455	496
@@ -485,7 +526,7 @@ static struct dma_async_tx_descriptor *axi_dmac_prep_interleaved( · 29 unmodified lines
485	526
486	527	if (chan->hw_2d) {
487	528	if (!axi_dmac_check_len(chan, xt->sgl[0].size) \|\|
488		− !axi_dmac_check_len(chan, xt->numf))
	529	+ xt->numf == 0)
489	530	return NULL;
490	531	if (xt->sgl[0].size + dst_icg > chan->max_length \|\|
491	532	xt->sgl[0].size + src_icg > chan->max_length)
@@ -577,15 +618,6 @@ static int axi_dmac_parse_chan_dt(struct device_node *of_chan, · 85 unmodified lines
577	618	return ret;
578	619	chan->dest_width = val / 8;
579	620
580		− ret = of_property_read_u32(of_chan, "adi,length-width", &val);
581		− if (ret)
582		− return ret;
583		−
584		− if (val >= 32)
585		− chan->max_length = UINT_MAX;
586		− else
587		− chan->max_length = (1ULL << val) - 1;
588		−
589	621	chan->align_mask = max(chan->dest_width, chan->src_width) - 1;
590	622
591	623	if (axi_dmac_dest_is_mem(chan) && axi_dmac_src_is_mem(chan))
@@ -597,12 +629,27 @@ static int axi_dmac_parse_chan_dt(struct device_node *of_chan, · 5 unmodified lines
597	629	else
598	630	chan->direction = DMA_DEV_TO_DEV;
599	631
600		− chan->hw_cyclic = of_property_read_bool(of_chan, "adi,cyclic");
601		− chan->hw_2d = of_property_read_bool(of_chan, "adi,2d");
602		−
603	632	return 0;
604	633	}
605	634
	635	+static void axi_dmac_detect_caps(struct axi_dmac *dmac)
	636	+{
	637	+ struct axi_dmac_chan *chan = &dmac->chan;
	638	+
	639	+ axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, AXI_DMAC_FLAG_CYCLIC);
	640	+ if (axi_dmac_read(dmac, AXI_DMAC_REG_FLAGS) == AXI_DMAC_FLAG_CYCLIC)
	641	+ chan->hw_cyclic = true;
	642	+
	643	+ axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 1);
	644	+ if (axi_dmac_read(dmac, AXI_DMAC_REG_Y_LENGTH) == 1)
	645	+ chan->hw_2d = true;
	646	+
	647	+ axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, 0xffffffff);
	648	+ chan->max_length = axi_dmac_read(dmac, AXI_DMAC_REG_X_LENGTH);
	649	+ if (chan->max_length != UINT_MAX)
	650	+ chan->max_length++;
	651	+}
	652	+
606	653	static int axi_dmac_probe(struct platform_device *pdev)
607	654	{
608	655	struct device_node of_channels, of_chan;
@@ -647,11 +694,12 @@ static int axi_dmac_probe(struct platform_device *pdev) · 38 unmodified lines
647	694	of_node_put(of_channels);
648	695
649	696	pdev->dev.dma_parms = &dmac->dma_parms;
650		− dma_set_max_seg_size(&pdev->dev, dmac->chan.max_length);
	697	+ dma_set_max_seg_size(&pdev->dev, UINT_MAX);
651	698
652	699	dma_dev = &dmac->dma_dev;
653	700	dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
654	701	dma_cap_set(DMA_CYCLIC, dma_dev->cap_mask);
	702	+ dma_cap_set(DMA_INTERLEAVE, dma_dev->cap_mask);
655	703	dma_dev->device_free_chan_resources = axi_dmac_free_chan_resources;
656	704	dma_dev->device_tx_status = dma_cookie_status;
657	705	dma_dev->device_issue_pending = axi_dmac_issue_pending;
@@ -675,6 +723,8 @@ static int axi_dmac_probe(struct platform_device *pdev) · 17 unmodified lines
675	723	if (ret < 0)
676	724	return ret;
677	725
	726	+ axi_dmac_detect_caps(dmac);
	727	+
678	728	axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_MASK, 0x00);
679	729
680	730	ret = dma_async_device_register(dma_dev);

drivers/dma/fsl-edma-common.h+1−1

@@ -136,7 +136,7 @@ struct fsl_edma_desc { · 135 unmodified lines
136	136	};
137	137
138	138	enum edma_version {
139		− v1, /* 32ch, Vybdir, mpc57x, etc */
	139	+ v1, /* 32ch, Vybrid, mpc57x, etc */
140	140	v2, /* 64ch Coldfire */
141	141	};
142	142

drivers/dma/fsl-edma.c+3−3

@@ -144,21 +144,21 @@ fsl_edma_irq_init(struct platform_device pdev, struct fsl_edma_engine fsl_edma · 143 unmodified lines
144	144	fsl_edma_irq_handler, 0, "eDMA", fsl_edma);
145	145	if (ret) {
146	146	dev_err(&pdev->dev, "Can't register eDMA IRQ.\n");
147		− return ret;
	147	+ return ret;
148	148	}
149	149	} else {
150	150	ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
151	151	fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma);
152	152	if (ret) {
153	153	dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n");
154		− return ret;
	154	+ return ret;
155	155	}
156	156
157	157	ret = devm_request_irq(&pdev->dev, fsl_edma->errirq,
158	158	fsl_edma_err_handler, 0, "eDMA err", fsl_edma);
159	159	if (ret) {
160	160	dev_err(&pdev->dev, "Can't register eDMA err IRQ.\n");
161		− return ret;
	161	+ return ret;
162	162	}
163	163	}
164	164

drivers/dma/idma64.c+8−7

@@ -19,10 +19,9 @@ · 18 unmodified lines
19	19	#include <linux/platform_device.h>
20	20	#include <linux/slab.h>
21	21
22		−#include "idma64.h"
	22	+#include <linux/dma/idma64.h>
23	23
24		−/* Platform driver name */
25		−#define DRV_NAME "idma64"
	24	+#include "idma64.h"
26	25
27	26	/* For now we support only two channels */
28	27	#define IDMA64_NR_CHAN 2
@@ -592,7 +591,7 @@ static int idma64_probe(struct idma64_chip *chip) · 563 unmodified lines
592	591	idma64->dma.directions = BIT(DMA_DEV_TO_MEM) \| BIT(DMA_MEM_TO_DEV);
593	592	idma64->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
594	593
595		− idma64->dma.dev = chip->dev;
	594	+ idma64->dma.dev = chip->sysdev;
596	595
597	596	dma_set_max_seg_size(idma64->dma.dev, IDMA64C_CTLH_BLOCK_TS_MASK);
598	597
@@ -632,6 +631,7 @@ static int idma64_platform_probe(struct platform_device *pdev) · 33 unmodified lines
632	631	{
633	632	struct idma64_chip *chip;
634	633	struct device *dev = &pdev->dev;
	634	+ struct device *sysdev = dev->parent;
635	635	struct resource *mem;
636	636	int ret;
637	637
@@ -648,11 +648,12 @@ static int idma64_platform_probe(struct platform_device *pdev) · 10 unmodified lines
648	648	if (IS_ERR(chip->regs))
649	649	return PTR_ERR(chip->regs);
650	650
651		− ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
	651	+ ret = dma_coerce_mask_and_coherent(sysdev, DMA_BIT_MASK(64));
652	652	if (ret)
653	653	return ret;
654	654
655	655	chip->dev = dev;
	656	+ chip->sysdev = sysdev;
656	657
657	658	ret = idma64_probe(chip);
658	659	if (ret)
@@ -697,7 +698,7 @@ static struct platform_driver idma64_platform_driver = { · 38 unmodified lines
697	698	.probe = idma64_platform_probe,
698	699	.remove = idma64_platform_remove,
699	700	.driver = {
700		− .name = DRV_NAME,
	701	+ .name = LPSS_IDMA64_DRIVER_NAME,
701	702	.pm = &idma64_dev_pm_ops,
702	703	},
703	704	};
@@ -707,4 +708,4 @@ module_platform_driver(idma64_platform_driver); · 3 unmodified lines
707	708	MODULE_LICENSE("GPL v2");
708	709	MODULE_DESCRIPTION("iDMA64 core driver");
709	710	MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
710		−MODULE_ALIAS("platform:" DRV_NAME);
	711	+MODULE_ALIAS("platform:" LPSS_IDMA64_DRIVER_NAME);

drivers/dma/idma64.h+2−0

@@ -216,12 +216,14 @@ static inline void idma64_writel(struct idma64 *idma64, int offset, u32 value) · 215 unmodified lines
216	216	/**
217	217	* struct idma64_chip - representation of iDMA 64-bit controller hardware
218	218	* @dev: struct device of the DMA controller
	219	+ * @sysdev: struct device of the physical device that does DMA
219	220	* @irq: irq line
220	221	* @regs: memory mapped I/O space
221	222	* @idma64: struct idma64 that is filed by idma64_probe()
222	223	*/
223	224	struct idma64_chip {
224	225	struct device *dev;
	226	+ struct device *sysdev;
225	227	int irq;
226	228	void __iomem *regs;
227	229	struct idma64 *idma64;

drivers/dma/imx-sdma.c+14−1

@@ -419,6 +419,7 @@ struct sdma_driver_data { · 418 unmodified lines
419	419	int chnenbl0;
420	420	int num_events;
421	421	struct sdma_script_start_addrs *script_addrs;
	422	+ bool check_ratio;
422	423	};
423	424
424	425	struct sdma_engine {
@@ -557,6 +558,13 @@ static struct sdma_driver_data sdma_imx7d = { · 132 unmodified lines
557	558	.script_addrs = &sdma_script_imx7d,
558	559	};
559	560
	561	+static struct sdma_driver_data sdma_imx8mq = {
	562	+ .chnenbl0 = SDMA_CHNENBL0_IMX35,
	563	+ .num_events = 48,
	564	+ .script_addrs = &sdma_script_imx7d,
	565	+ .check_ratio = 1,
	566	+};
	567	+
560	568	static const struct platform_device_id sdma_devtypes[] = {
561	569	{
562	570	.name = "imx25-sdma",
@@ -579,6 +587,9 @@ static const struct platform_device_id sdma_devtypes[] = { · 16 unmodified lines
579	587	}, {
580	588	.name = "imx7d-sdma",
581	589	.driver_data = (unsigned long)&sdma_imx7d,
	590	+ }, {
	591	+ .name = "imx8mq-sdma",
	592	+ .driver_data = (unsigned long)&sdma_imx8mq,
582	593	}, {
583	594	/* sentinel */
584	595	}
@@ -593,6 +604,7 @@ static const struct of_device_id sdma_dt_ids[] = { · 8 unmodified lines
593	604	{ .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
594	605	{ .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
595	606	{ .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
	607	+ { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, },
596	608	{ /* sentinel */ }
597	609	};
598	610	MODULE_DEVICE_TABLE(of, sdma_dt_ids);
@@ -1852,7 +1864,8 @@ static int sdma_init(struct sdma_engine *sdma) · 1253 unmodified lines
1852	1864	if (ret)
1853	1865	goto disable_clk_ipg;
1854	1866
1855		− if (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg))
	1867	+ if (sdma->drvdata->check_ratio &&
	1868	+ (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg)))
1856	1869	sdma->clk_ratio = 1;
1857	1870
1858	1871	/* Be sure SDMA has not started yet */

drivers/dma/nbpfaxi.c+2−2

@@ -1491,14 +1491,14 @@ MODULE_DEVICE_TABLE(platform, nbpf_ids); · 1490 unmodified lines
1491	1491	#ifdef CONFIG_PM
1492	1492	static int nbpf_runtime_suspend(struct device *dev)
1493	1493	{
1494		− struct nbpf_device *nbpf = platform_get_drvdata(to_platform_device(dev));
	1494	+ struct nbpf_device *nbpf = dev_get_drvdata(dev);
1495	1495	clk_disable_unprepare(nbpf->clk);
1496	1496	return 0;
1497	1497	}
1498	1498
1499	1499	static int nbpf_runtime_resume(struct device *dev)
1500	1500	{
1501		− struct nbpf_device *nbpf = platform_get_drvdata(to_platform_device(dev));
	1501	+ struct nbpf_device *nbpf = dev_get_drvdata(dev);
1502	1502	return clk_prepare_enable(nbpf->clk);
1503	1503	}
1504	1504	#endif

drivers/dma/pl330.c+58−3

@@ -11,6 +11,7 @@ · 10 unmodified lines
11	11	* (at your option) any later version.
12	12	*/
13	13
	14	+#include <linux/debugfs.h>
14	15	#include <linux/kernel.h>
15	16	#include <linux/io.h>
16	17	#include <linux/init.h>
@@ -966,6 +967,7 @@ static void _stop(struct pl330_thread *thrd) · 949 unmodified lines
966	967	{
967	968	void __iomem *regs = thrd->dmac->base;
968	969	u8 insn[6] = {0, 0, 0, 0, 0, 0};
	970	+ u32 inten = readl(regs + INTEN);
969	971
970	972	if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
971	973	UNTIL(thrd, PL330_STATE_FAULTING \| PL330_STATE_KILLING);
@@ -978,10 +980,13 @@ static void _stop(struct pl330_thread *thrd) · 6 unmodified lines
978	980
979	981	_emit_KILL(0, insn);
980	982
981		− /* Stop generating interrupts for SEV */
982		− writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN);
983		−
984	983	_execute_DBGINSN(thrd, insn, is_manager(thrd));
	984	+
	985	+ /* clear the event */
	986	+ if (inten & (1 << thrd->ev))
	987	+ writel(1 << thrd->ev, regs + INTCLR);
	988	+ /* Stop generating interrupts for SEV */
	989	+ writel(inten & ~(1 << thrd->ev), regs + INTEN);
985	990	}
986	991
987	992	/* Start doing req 'idx' of thread 'thrd' */
@@ -2896,6 +2901,55 @@ static irqreturn_t pl330_irq_handler(int irq, void *data) · 1908 unmodified lines
2896	2901	BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) \| \
2897	2902	BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2898	2903
	2904	+#ifdef CONFIG_DEBUG_FS
	2905	+static int pl330_debugfs_show(struct seq_file s, void data)
	2906	+{
	2907	+ struct pl330_dmac *pl330 = s->private;
	2908	+ int chans, pchs, ch, pr;
	2909	+
	2910	+ chans = pl330->pcfg.num_chan;
	2911	+ pchs = pl330->num_peripherals;
	2912	+
	2913	+ seq_puts(s, "PL330 physical channels:\n");
	2914	+ seq_puts(s, "THREAD:\t\tCHANNEL:\n");
	2915	+ seq_puts(s, "--------\t-----\n");
	2916	+ for (ch = 0; ch < chans; ch++) {
	2917	+ struct pl330_thread *thrd = &pl330->channels[ch];
	2918	+ int found = -1;
	2919	+
	2920	+ for (pr = 0; pr < pchs; pr++) {
	2921	+ struct dma_pl330_chan *pch = &pl330->peripherals[pr];
	2922	+
	2923	+ if (!pch->thread \|\| thrd->id != pch->thread->id)
	2924	+ continue;
	2925	+
	2926	+ found = pr;
	2927	+ }
	2928	+
	2929	+ seq_printf(s, "%d\t\t", thrd->id);
	2930	+ if (found == -1)
	2931	+ seq_puts(s, "--\n");
	2932	+ else
	2933	+ seq_printf(s, "%d\n", found);
	2934	+ }
	2935	+
	2936	+ return 0;
	2937	+}
	2938	+
	2939	+DEFINE_SHOW_ATTRIBUTE(pl330_debugfs);
	2940	+
	2941	+static inline void init_pl330_debugfs(struct pl330_dmac *pl330)
	2942	+{
	2943	+ debugfs_create_file(dev_name(pl330->ddma.dev),
	2944	+ S_IFREG \| 0444, NULL, pl330,
	2945	+ &pl330_debugfs_fops);
	2946	+}
	2947	+#else
	2948	+static inline void init_pl330_debugfs(struct pl330_dmac *pl330)
	2949	+{
	2950	+}
	2951	+#endif
	2952	+
2899	2953	/*
2900	2954	* Runtime PM callbacks are provided by amba/bus.c driver.
2901	2955	*
@@ -3082,6 +3136,7 @@ pl330_probe(struct amba_device adev, const struct amba_id id) · 180 unmodified lines
3082	3136	dev_err(&adev->dev, "unable to set the seg size\n");
3083	3137
3084	3138
	3139	+ init_pl330_debugfs(pl330);
3085	3140	dev_info(&adev->dev,
3086	3141	"Loaded driver for PL330 DMAC-%x\n", adev->periphid);
3087	3142	dev_info(&adev->dev,

drivers/dma/sh/rcar-dmac.c+2−2

@@ -1,8 +1,8 @@
1	1	// SPDX-License-Identifier: GPL-2.0
2	2	/*
3		− * Renesas R-Car Gen2 DMA Controller Driver
	3	+ * Renesas R-Car Gen2/Gen3 DMA Controller Driver
4	4	*
5		− * Copyright (C) 2014 Renesas Electronics Inc.
	5	+ * Copyright (C) 2014-2019 Renesas Electronics Inc.
6	6	*
7	7	* Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
8	8	*/

drivers/dma/stm32-dma.c+85−18

@@ -1042,33 +1042,97 @@ static u32 stm32_dma_get_remaining_bytes(struct stm32_dma_chan *chan) · 1041 unmodified lines
1042	1042	return ndtr << width;
1043	1043	}
1044	1044
	1045	+/**
	1046	+ * stm32_dma_is_current_sg - check that expected sg_req is currently transferred
	1047	+ * @chan: dma channel
	1048	+ *
	1049	+ * This function called when IRQ are disable, checks that the hardware has not
	1050	+ * switched on the next transfer in double buffer mode. The test is done by
	1051	+ * comparing the next_sg memory address with the hardware related register
	1052	+ * (based on CT bit value).
	1053	+ *
	1054	+ * Returns true if expected current transfer is still running or double
	1055	+ * buffer mode is not activated.
	1056	+ */
	1057	+static bool stm32_dma_is_current_sg(struct stm32_dma_chan *chan)
	1058	+{
	1059	+ struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
	1060	+ struct stm32_dma_sg_req *sg_req;
	1061	+ u32 dma_scr, dma_smar, id;
	1062	+
	1063	+ id = chan->id;
	1064	+ dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
	1065	+
	1066	+ if (!(dma_scr & STM32_DMA_SCR_DBM))
	1067	+ return true;
	1068	+
	1069	+ sg_req = &chan->desc->sg_req[chan->next_sg];
	1070	+
	1071	+ if (dma_scr & STM32_DMA_SCR_CT) {
	1072	+ dma_smar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(id));
	1073	+ return (dma_smar == sg_req->chan_reg.dma_sm0ar);
	1074	+ }
	1075	+
	1076	+ dma_smar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(id));
	1077	+
	1078	+ return (dma_smar == sg_req->chan_reg.dma_sm1ar);
	1079	+}
	1080	+
1045	1081	static size_t stm32_dma_desc_residue(struct stm32_dma_chan *chan,
1046	1082	struct stm32_dma_desc *desc,
1047	1083	u32 next_sg)
1048	1084	{
1049	1085	u32 modulo, burst_size;
1050		− u32 residue = 0;
	1086	+ u32 residue;
	1087	+ u32 n_sg = next_sg;
	1088	+ struct stm32_dma_sg_req *sg_req = &chan->desc->sg_req[chan->next_sg];
1051	1089	int i;
1052	1090
1053	1091	/*
1054		− * In cyclic mode, for the last period, residue = remaining bytes from
1055		− * NDTR
	1092	+ * Calculate the residue means compute the descriptors
	1093	+ * information:
	1094	+ * - the sg_req currently transferred
	1095	+ * - the Hardware remaining position in this sg (NDTR bits field).
	1096	+ *
	1097	+ * A race condition may occur if DMA is running in cyclic or double
	1098	+ * buffer mode, since the DMA register are automatically reloaded at end
	1099	+ * of period transfer. The hardware may have switched to the next
	1100	+ * transfer (CT bit updated) just before the position (SxNDTR reg) is
	1101	+ * read.
	1102	+ * In this case the SxNDTR reg could (or not) correspond to the new
	1103	+ * transfer position, and not the expected one.
	1104	+ * The strategy implemented in the stm32 driver is to:
	1105	+ * - read the SxNDTR register
	1106	+ * - crosscheck that hardware is still in current transfer.
	1107	+ * In case of switch, we can assume that the DMA is at the beginning of
	1108	+ * the next transfer. So we approximate the residue in consequence, by
	1109	+ * pointing on the beginning of next transfer.
	1110	+ *
	1111	+ * This race condition doesn't apply for none cyclic mode, as double
	1112	+ * buffer is not used. In such situation registers are updated by the
	1113	+ * software.
1056	1114	*/
1057		− if (chan->desc->cyclic && next_sg == 0) {
1058		− residue = stm32_dma_get_remaining_bytes(chan);
1059		− goto end;
	1115	+
	1116	+ residue = stm32_dma_get_remaining_bytes(chan);
	1117	+
	1118	+ if (!stm32_dma_is_current_sg(chan)) {
	1119	+ n_sg++;
	1120	+ if (n_sg == chan->desc->num_sgs)
	1121	+ n_sg = 0;
	1122	+ residue = sg_req->len;
1060	1123	}
1061	1124
1062	1125	/*
1063		− * For all other periods in cyclic mode, and in sg mode,
1064		− * residue = remaining bytes from NDTR + remaining periods/sg to be
1065		− * transferred
	1126	+ * In cyclic mode, for the last period, residue = remaining bytes
	1127	+ * from NDTR,
	1128	+ * else for all other periods in cyclic mode, and in sg mode,
	1129	+ * residue = remaining bytes from NDTR + remaining
	1130	+ * periods/sg to be transferred
1066	1131	*/
1067		− for (i = next_sg; i < desc->num_sgs; i++)
1068		− residue += desc->sg_req[i].len;
1069		− residue += stm32_dma_get_remaining_bytes(chan);
	1132	+ if (!chan->desc->cyclic \|\| n_sg != 0)
	1133	+ for (i = n_sg; i < desc->num_sgs; i++)
	1134	+ residue += desc->sg_req[i].len;
1070	1135
1071		−end:
1072	1136	if (!chan->mem_burst)
1073	1137	return residue;
1074	1138
@@ -1302,13 +1366,16 @@ static int stm32_dma_probe(struct platform_device *pdev) · 227 unmodified lines
1302	1366
1303	1367	for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) {
1304	1368	chan = &dmadev->chan[i];
1305		− res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1306		− if (!res) {
1307		− ret = -EINVAL;
1308		− dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
	1369	+ chan->irq = platform_get_irq(pdev, i);
	1370	+ ret = platform_get_irq(pdev, i);
	1371	+ if (ret < 0) {
	1372	+ if (ret != -EPROBE_DEFER)
	1373	+ dev_err(&pdev->dev,
	1374	+ "No irq resource for chan %d\n", i);
1309	1375	goto err_unregister;
1310	1376	}
1311		− chan->irq = res->start;
	1377	+ chan->irq = ret;
	1378	+
1312	1379	ret = devm_request_irq(&pdev->dev, chan->irq,
1313	1380	stm32_dma_chan_irq, 0,
1314	1381	dev_name(chan2dev(chan)), chan);

drivers/dma/tegra210-adma.c+204−65

@@ -22,7 +22,6 @@ · 21 unmodified lines
22	22	#include <linux/of_device.h>
23	23	#include <linux/of_dma.h>
24	24	#include <linux/of_irq.h>
25		−#include <linux/pm_clock.h>
26	25	#include <linux/pm_runtime.h>
27	26	#include <linux/slab.h>
28	27
@@ -31,35 +30,33 @@ · 2 unmodified lines
31	30	#define ADMA_CH_CMD 0x00
32	31	#define ADMA_CH_STATUS 0x0c
33	32	#define ADMA_CH_STATUS_XFER_EN BIT(0)
	33	+#define ADMA_CH_STATUS_XFER_PAUSED BIT(1)
34	34
35	35	#define ADMA_CH_INT_STATUS 0x10
36	36	#define ADMA_CH_INT_STATUS_XFER_DONE BIT(0)
37	37
38	38	#define ADMA_CH_INT_CLEAR 0x1c
39	39	#define ADMA_CH_CTRL 0x24
40		−#define ADMA_CH_CTRL_TX_REQ(val) (((val) & 0xf) << 28)
41		−#define ADMA_CH_CTRL_TX_REQ_MAX 10
42		−#define ADMA_CH_CTRL_RX_REQ(val) (((val) & 0xf) << 24)
43		−#define ADMA_CH_CTRL_RX_REQ_MAX 10
44	40	#define ADMA_CH_CTRL_DIR(val) (((val) & 0xf) << 12)
45	41	#define ADMA_CH_CTRL_DIR_AHUB2MEM 2
46	42	#define ADMA_CH_CTRL_DIR_MEM2AHUB 4
47	43	#define ADMA_CH_CTRL_MODE_CONTINUOUS (2 << 8)
48	44	#define ADMA_CH_CTRL_FLOWCTRL_EN BIT(1)
	45	+#define ADMA_CH_CTRL_XFER_PAUSE_SHIFT 0
49	46
50	47	#define ADMA_CH_CONFIG 0x28
51	48	#define ADMA_CH_CONFIG_SRC_BUF(val) (((val) & 0x7) << 28)
52	49	#define ADMA_CH_CONFIG_TRG_BUF(val) (((val) & 0x7) << 24)
53		−#define ADMA_CH_CONFIG_BURST_SIZE(val) (((val) & 0x7) << 20)
54		−#define ADMA_CH_CONFIG_BURST_16 5
	50	+#define ADMA_CH_CONFIG_BURST_SIZE_SHIFT 20
	51	+#define ADMA_CH_CONFIG_MAX_BURST_SIZE 16
55	52	#define ADMA_CH_CONFIG_WEIGHT_FOR_WRR(val) ((val) & 0xf)
56	53	#define ADMA_CH_CONFIG_MAX_BUFS 8
57	54
58	55	#define ADMA_CH_FIFO_CTRL 0x2c
59	56	#define ADMA_CH_FIFO_CTRL_OVRFW_THRES(val) (((val) & 0xf) << 24)
60	57	#define ADMA_CH_FIFO_CTRL_STARV_THRES(val) (((val) & 0xf) << 16)
61		−#define ADMA_CH_FIFO_CTRL_TX_SIZE(val) (((val) & 0xf) << 8)
62		−#define ADMA_CH_FIFO_CTRL_RX_SIZE(val) ((val) & 0xf)
	58	+#define ADMA_CH_FIFO_CTRL_TX_FIFO_SIZE_SHIFT 8
	59	+#define ADMA_CH_FIFO_CTRL_RX_FIFO_SIZE_SHIFT 0
63	60
64	61	#define ADMA_CH_LOWER_SRC_ADDR 0x34
65	62	#define ADMA_CH_LOWER_TRG_ADDR 0x3c
@@ -69,25 +66,41 @@ · 3 unmodified lines
69	66	#define ADMA_CH_XFER_STATUS 0x54
70	67	#define ADMA_CH_XFER_STATUS_COUNT_MASK 0xffff
71	68
72		−#define ADMA_GLOBAL_CMD 0xc00
73		−#define ADMA_GLOBAL_SOFT_RESET 0xc04
74		−#define ADMA_GLOBAL_INT_CLEAR 0xc20
75		−#define ADMA_GLOBAL_CTRL 0xc24
	69	+#define ADMA_GLOBAL_CMD 0x00
	70	+#define ADMA_GLOBAL_SOFT_RESET 0x04
76	71
77		−#define ADMA_CH_REG_OFFSET(a) (a * 0x80)
	72	+#define TEGRA_ADMA_BURST_COMPLETE_TIME 20
78	73
79	74	#define ADMA_CH_FIFO_CTRL_DEFAULT (ADMA_CH_FIFO_CTRL_OVRFW_THRES(1) \| \
80		− ADMA_CH_FIFO_CTRL_STARV_THRES(1) \| \
81		− ADMA_CH_FIFO_CTRL_TX_SIZE(3) \| \
82		− ADMA_CH_FIFO_CTRL_RX_SIZE(3))
	75	+ ADMA_CH_FIFO_CTRL_STARV_THRES(1))
	76	+
	77	+#define ADMA_CH_REG_FIELD_VAL(val, mask, shift) (((val) & mask) << shift)
	78	+
83	79	struct tegra_adma;
84	80
85	81	/*
86	82	* struct tegra_adma_chip_data - Tegra chip specific data
	83	+ * @global_reg_offset: Register offset of DMA global register.
	84	+ * @global_int_clear: Register offset of DMA global interrupt clear.
	85	+ * @ch_req_tx_shift: Register offset for AHUB transmit channel select.
	86	+ * @ch_req_rx_shift: Register offset for AHUB receive channel select.
	87	+ * @ch_base_offset: Reister offset of DMA channel registers.
	88	+ * @ch_req_mask: Mask for Tx or Rx channel select.
	89	+ * @ch_req_max: Maximum number of Tx or Rx channels available.
	90	+ * @ch_reg_size: Size of DMA channel register space.
87	91	* @nr_channels: Number of DMA channels available.
88	92	*/
89	93	struct tegra_adma_chip_data {
90		− int nr_channels;
	94	+ unsigned int (*adma_get_burst_config)(unsigned int burst_size);
	95	+ unsigned int global_reg_offset;
	96	+ unsigned int global_int_clear;
	97	+ unsigned int ch_req_tx_shift;
	98	+ unsigned int ch_req_rx_shift;
	99	+ unsigned int ch_base_offset;
	100	+ unsigned int ch_req_mask;
	101	+ unsigned int ch_req_max;
	102	+ unsigned int ch_reg_size;
	103	+ unsigned int nr_channels;
91	104	};
92	105
93	106	/*
@@ -99,6 +112,7 @@ struct tegra_adma_chan_regs { · 5 unmodified lines
99	112	unsigned int src_addr;
100	113	unsigned int trg_addr;
101	114	unsigned int fifo_ctrl;
	115	+ unsigned int cmd;
102	116	unsigned int tc;
103	117	};
104	118
@@ -128,6 +142,7 @@ struct tegra_adma_chan { · 23 unmodified lines
128	142	enum dma_transfer_direction sreq_dir;
129	143	unsigned int sreq_index;
130	144	bool sreq_reserved;
	145	+ struct tegra_adma_chan_regs ch_regs;
131	146
132	147	/* Transfer count and position info */
133	148	unsigned int tx_buf_count;
@@ -141,6 +156,7 @@ struct tegra_adma { · 7 unmodified lines
141	156	struct dma_device dma_dev;
142	157	struct device *dev;
143	158	void __iomem *base_addr;
	159	+ struct clk *ahub_clk;
144	160	unsigned int nr_channels;
145	161	unsigned long rx_requests_reserved;
146	162	unsigned long tx_requests_reserved;
@@ -148,18 +164,20 @@ struct tegra_adma { · 1 unmodified line
148	164	/* Used to store global command register state when suspending */
149	165	unsigned int global_cmd;
150	166
	167	+ const struct tegra_adma_chip_data *cdata;
	168	+
151	169	/* Last member of the structure */
152	170	struct tegra_adma_chan channels[0];
153	171	};
154	172
155	173	static inline void tdma_write(struct tegra_adma *tdma, u32 reg, u32 val)
156	174	{
157		− writel(val, tdma->base_addr + reg);
	175	+ writel(val, tdma->base_addr + tdma->cdata->global_reg_offset + reg);
158	176	}
159	177
160	178	static inline u32 tdma_read(struct tegra_adma *tdma, u32 reg)
161	179	{
162		− return readl(tdma->base_addr + reg);
	180	+ return readl(tdma->base_addr + tdma->cdata->global_reg_offset + reg);
163	181	}
164	182
165	183	static inline void tdma_ch_write(struct tegra_adma_chan *tdc, u32 reg, u32 val)
@@ -209,14 +227,16 @@ static int tegra_adma_init(struct tegra_adma *tdma) · 43 unmodified lines
209	227	int ret;
210	228
211	229	/* Clear any interrupts */
212		− tdma_write(tdma, ADMA_GLOBAL_INT_CLEAR, 0x1);
	230	+ tdma_write(tdma, tdma->cdata->global_int_clear, 0x1);
213	231
214	232	/* Assert soft reset */
215	233	tdma_write(tdma, ADMA_GLOBAL_SOFT_RESET, 0x1);
216	234
217	235	/* Wait for reset to clear */
218	236	ret = readx_poll_timeout(readl,
219		− tdma->base_addr + ADMA_GLOBAL_SOFT_RESET,
	237	+ tdma->base_addr +
	238	+ tdma->cdata->global_reg_offset +
	239	+ ADMA_GLOBAL_SOFT_RESET,
220	240	status, status == 0, 20, 10000);
221	241	if (ret)
222	242	return ret;
@@ -236,13 +256,13 @@ static int tegra_adma_request_alloc(struct tegra_adma_chan *tdc, · 13 unmodified lines
236	256	if (tdc->sreq_reserved)
237	257	return tdc->sreq_dir == direction ? 0 : -EINVAL;
238	258
	259	+ if (sreq_index > tdma->cdata->ch_req_max) {
	260	+ dev_err(tdma->dev, "invalid DMA request\n");
	261	+ return -EINVAL;
	262	+ }
	263	+
239	264	switch (direction) {
240	265	case DMA_MEM_TO_DEV:
241		− if (sreq_index > ADMA_CH_CTRL_TX_REQ_MAX) {
242		− dev_err(tdma->dev, "invalid DMA request\n");
243		− return -EINVAL;
244		− }
245		−
246	266	if (test_and_set_bit(sreq_index, &tdma->tx_requests_reserved)) {
247	267	dev_err(tdma->dev, "DMA request reserved\n");
248	268	return -EINVAL;
@@ -250,11 +270,6 @@ static int tegra_adma_request_alloc(struct tegra_adma_chan *tdc, · 1 unmodified line
250	270	break;
251	271
252	272	case DMA_DEV_TO_MEM:
253		− if (sreq_index > ADMA_CH_CTRL_RX_REQ_MAX) {
254		− dev_err(tdma->dev, "invalid DMA request\n");
255		− return -EINVAL;
256		− }
257		−
258	273	if (test_and_set_bit(sreq_index, &tdma->rx_requests_reserved)) {
259	274	dev_err(tdma->dev, "DMA request reserved\n");
260	275	return -EINVAL;
@@ -428,6 +443,51 @@ static void tegra_adma_issue_pending(struct dma_chan *dc) · 167 unmodified lines
428	443	spin_unlock_irqrestore(&tdc->vc.lock, flags);
429	444	}
430	445
	446	+static bool tegra_adma_is_paused(struct tegra_adma_chan *tdc)
	447	+{
	448	+ u32 csts;
	449	+
	450	+ csts = tdma_ch_read(tdc, ADMA_CH_STATUS);
	451	+ csts &= ADMA_CH_STATUS_XFER_PAUSED;
	452	+
	453	+ return csts ? true : false;
	454	+}
	455	+
	456	+static int tegra_adma_pause(struct dma_chan *dc)
	457	+{
	458	+ struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
	459	+ struct tegra_adma_desc *desc = tdc->desc;
	460	+ struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs;
	461	+ int dcnt = 10;
	462	+
	463	+ ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL);
	464	+ ch_regs->ctrl \|= (1 << ADMA_CH_CTRL_XFER_PAUSE_SHIFT);
	465	+ tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
	466	+
	467	+ while (dcnt-- && !tegra_adma_is_paused(tdc))
	468	+ udelay(TEGRA_ADMA_BURST_COMPLETE_TIME);
	469	+
	470	+ if (dcnt < 0) {
	471	+ dev_err(tdc2dev(tdc), "unable to pause DMA channel\n");
	472	+ return -EBUSY;
	473	+ }
	474	+
	475	+ return 0;
	476	+}
	477	+
	478	+static int tegra_adma_resume(struct dma_chan *dc)
	479	+{
	480	+ struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
	481	+ struct tegra_adma_desc *desc = tdc->desc;
	482	+ struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs;
	483	+
	484	+ ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL);
	485	+ ch_regs->ctrl &= ~(1 << ADMA_CH_CTRL_XFER_PAUSE_SHIFT);
	486	+ tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl);
	487	+
	488	+ return 0;
	489	+}
	490	+
431	491	static int tegra_adma_terminate_all(struct dma_chan *dc)
432	492	{
433	493	struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc);
@@ -481,12 +541,29 @@ static enum dma_status tegra_adma_tx_status(struct dma_chan *dc, · 47 unmodified lines
481	541	return ret;
482	542	}
483	543
	544	+static unsigned int tegra210_adma_get_burst_config(unsigned int burst_size)
	545	+{
	546	+ if (!burst_size \|\| burst_size > ADMA_CH_CONFIG_MAX_BURST_SIZE)
	547	+ burst_size = ADMA_CH_CONFIG_MAX_BURST_SIZE;
	548	+
	549	+ return fls(burst_size) << ADMA_CH_CONFIG_BURST_SIZE_SHIFT;
	550	+}
	551	+
	552	+static unsigned int tegra186_adma_get_burst_config(unsigned int burst_size)
	553	+{
	554	+ if (!burst_size \|\| burst_size > ADMA_CH_CONFIG_MAX_BURST_SIZE)
	555	+ burst_size = ADMA_CH_CONFIG_MAX_BURST_SIZE;
	556	+
	557	+ return (burst_size - 1) << ADMA_CH_CONFIG_BURST_SIZE_SHIFT;
	558	+}
	559	+
484	560	static int tegra_adma_set_xfer_params(struct tegra_adma_chan *tdc,
485	561	struct tegra_adma_desc *desc,
486	562	dma_addr_t buf_addr,
487	563	enum dma_transfer_direction direction)
488	564	{
489	565	struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs;
	566	+ const struct tegra_adma_chip_data *cdata = tdc->tdma->cdata;
490	567	unsigned int burst_size, adma_dir;
491	568
492	569	if (desc->num_periods > ADMA_CH_CONFIG_MAX_BUFS)
@@ -495,17 +572,21 @@ static int tegra_adma_set_xfer_params(struct tegra_adma_chan *tdc, · 2 unmodified lines
495	572	switch (direction) {
496	573	case DMA_MEM_TO_DEV:
497	574	adma_dir = ADMA_CH_CTRL_DIR_MEM2AHUB;
498		− burst_size = fls(tdc->sconfig.dst_maxburst);
	575	+ burst_size = tdc->sconfig.dst_maxburst;
499	576	ch_regs->config = ADMA_CH_CONFIG_SRC_BUF(desc->num_periods - 1);
500		− ch_regs->ctrl = ADMA_CH_CTRL_TX_REQ(tdc->sreq_index);
	577	+ ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index,
	578	+ cdata->ch_req_mask,
	579	+ cdata->ch_req_tx_shift);
501	580	ch_regs->src_addr = buf_addr;
502	581	break;
503	582
504	583	case DMA_DEV_TO_MEM:
505	584	adma_dir = ADMA_CH_CTRL_DIR_AHUB2MEM;
506		− burst_size = fls(tdc->sconfig.src_maxburst);
	585	+ burst_size = tdc->sconfig.src_maxburst;
507	586	ch_regs->config = ADMA_CH_CONFIG_TRG_BUF(desc->num_periods - 1);
508		− ch_regs->ctrl = ADMA_CH_CTRL_RX_REQ(tdc->sreq_index);
	587	+ ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index,
	588	+ cdata->ch_req_mask,
	589	+ cdata->ch_req_rx_shift);
509	590	ch_regs->trg_addr = buf_addr;
510	591	break;
511	592
@@ -514,13 +595,10 @@ static int tegra_adma_set_xfer_params(struct tegra_adma_chan *tdc, · 2 unmodified lines
514	595	return -EINVAL;
515	596	}
516	597
517		− if (!burst_size \|\| burst_size > ADMA_CH_CONFIG_BURST_16)
518		− burst_size = ADMA_CH_CONFIG_BURST_16;
519		−
520	598	ch_regs->ctrl \|= ADMA_CH_CTRL_DIR(adma_dir) \|
521	599	ADMA_CH_CTRL_MODE_CONTINUOUS \|
522	600	ADMA_CH_CTRL_FLOWCTRL_EN;
523		− ch_regs->config \|= ADMA_CH_CONFIG_BURST_SIZE(burst_size);
	601	+ ch_regs->config \|= cdata->adma_get_burst_config(burst_size);
524	602	ch_regs->config \|= ADMA_CH_CONFIG_WEIGHT_FOR_WRR(1);
525	603	ch_regs->fifo_ctrl = ADMA_CH_FIFO_CTRL_DEFAULT;
526	604	ch_regs->tc = desc->period_len & ADMA_CH_TC_COUNT_MASK;
@@ -635,32 +713,99 @@ static struct dma_chan tegra_dma_of_xlate(struct of_phandle_args dma_spec, · 108 unmodified lines
635	713	static int tegra_adma_runtime_suspend(struct device *dev)
636	714	{
637	715	struct tegra_adma *tdma = dev_get_drvdata(dev);
	716	+ struct tegra_adma_chan_regs *ch_reg;
	717	+ struct tegra_adma_chan *tdc;
	718	+ int i;
638	719
639	720	tdma->global_cmd = tdma_read(tdma, ADMA_GLOBAL_CMD);
	721	+ if (!tdma->global_cmd)
	722	+ goto clk_disable;
	723	+
	724	+ for (i = 0; i < tdma->nr_channels; i++) {
	725	+ tdc = &tdma->channels[i];
	726	+ ch_reg = &tdc->ch_regs;
	727	+ ch_reg->cmd = tdma_ch_read(tdc, ADMA_CH_CMD);
	728	+ /* skip if channel is not active */
	729	+ if (!ch_reg->cmd)
	730	+ continue;
	731	+ ch_reg->tc = tdma_ch_read(tdc, ADMA_CH_TC);
	732	+ ch_reg->src_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_SRC_ADDR);
	733	+ ch_reg->trg_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_TRG_ADDR);
	734	+ ch_reg->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL);
	735	+ ch_reg->fifo_ctrl = tdma_ch_read(tdc, ADMA_CH_FIFO_CTRL);
	736	+ ch_reg->config = tdma_ch_read(tdc, ADMA_CH_CONFIG);
	737	+ }
	738	+
	739	+clk_disable:
	740	+ clk_disable_unprepare(tdma->ahub_clk);
640	741
641		− return pm_clk_suspend(dev);
	742	+ return 0;
642	743	}
643	744
644	745	static int tegra_adma_runtime_resume(struct device *dev)
645	746	{
646	747	struct tegra_adma *tdma = dev_get_drvdata(dev);
647		− int ret;
	748	+ struct tegra_adma_chan_regs *ch_reg;
	749	+ struct tegra_adma_chan *tdc;
	750	+ int ret, i;
648	751
649		− ret = pm_clk_resume(dev);
650		− if (ret)
	752	+ ret = clk_prepare_enable(tdma->ahub_clk);
	753	+ if (ret) {
	754	+ dev_err(dev, "ahub clk_enable failed: %d\n", ret);
651	755	return ret;
652		−
	756	+ }
653	757	tdma_write(tdma, ADMA_GLOBAL_CMD, tdma->global_cmd);
654	758
	759	+ if (!tdma->global_cmd)
	760	+ return 0;
	761	+
	762	+ for (i = 0; i < tdma->nr_channels; i++) {
	763	+ tdc = &tdma->channels[i];
	764	+ ch_reg = &tdc->ch_regs;
	765	+ /* skip if channel was not active earlier */
	766	+ if (!ch_reg->cmd)
	767	+ continue;
	768	+ tdma_ch_write(tdc, ADMA_CH_TC, ch_reg->tc);
	769	+ tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_reg->src_addr);
	770	+ tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_reg->trg_addr);
	771	+ tdma_ch_write(tdc, ADMA_CH_CTRL, ch_reg->ctrl);
	772	+ tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_reg->fifo_ctrl);
	773	+ tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_reg->config);
	774	+ tdma_ch_write(tdc, ADMA_CH_CMD, ch_reg->cmd);
	775	+ }
	776	+
655	777	return 0;
656	778	}
657	779
658	780	static const struct tegra_adma_chip_data tegra210_chip_data = {
659		− .nr_channels = 22,
	781	+ .adma_get_burst_config = tegra210_adma_get_burst_config,
	782	+ .global_reg_offset = 0xc00,
	783	+ .global_int_clear = 0x20,
	784	+ .ch_req_tx_shift = 28,
	785	+ .ch_req_rx_shift = 24,
	786	+ .ch_base_offset = 0,
	787	+ .ch_req_mask = 0xf,
	788	+ .ch_req_max = 10,
	789	+ .ch_reg_size = 0x80,
	790	+ .nr_channels = 22,
	791	+};
	792	+
	793	+static const struct tegra_adma_chip_data tegra186_chip_data = {
	794	+ .adma_get_burst_config = tegra186_adma_get_burst_config,
	795	+ .global_reg_offset = 0,
	796	+ .global_int_clear = 0x402c,
	797	+ .ch_req_tx_shift = 27,
	798	+ .ch_req_rx_shift = 22,
	799	+ .ch_base_offset = 0x10000,
	800	+ .ch_req_mask = 0x1f,
	801	+ .ch_req_max = 20,
	802	+ .ch_reg_size = 0x100,
	803	+ .nr_channels = 32,
660	804	};
661	805
662	806	static const struct of_device_id tegra_adma_of_match[] = {
663	807	{ .compatible = "nvidia,tegra210-adma", .data = &tegra210_chip_data },
	808	+ { .compatible = "nvidia,tegra186-adma", .data = &tegra186_chip_data },
664	809	{ },
665	810	};
666	811	MODULE_DEVICE_TABLE(of, tegra_adma_of_match);
@@ -685,6 +830,7 @@ static int tegra_adma_probe(struct platform_device *pdev) · 18 unmodified lines
685	830	return -ENOMEM;
686	831
687	832	tdma->dev = &pdev->dev;
	833	+ tdma->cdata = cdata;
688	834	tdma->nr_channels = cdata->nr_channels;
689	835	platform_set_drvdata(pdev, tdma);
690	836
@@ -693,13 +839,11 @@ static int tegra_adma_probe(struct platform_device *pdev) · 2 unmodified lines
693	839	if (IS_ERR(tdma->base_addr))
694	840	return PTR_ERR(tdma->base_addr);
695	841
696		− ret = pm_clk_create(&pdev->dev);
697		− if (ret)
698		− return ret;
699		−
700		− ret = of_pm_clk_add_clk(&pdev->dev, "d_audio");
701		− if (ret)
702		− goto clk_destroy;
	842	+ tdma->ahub_clk = devm_clk_get(&pdev->dev, "d_audio");
	843	+ if (IS_ERR(tdma->ahub_clk)) {
	844	+ dev_err(&pdev->dev, "Error: Missing ahub controller clock\n");
	845	+ return PTR_ERR(tdma->ahub_clk);
	846	+ }
703	847
704	848	pm_runtime_enable(&pdev->dev);
705	849
@@ -715,7 +859,8 @@ static int tegra_adma_probe(struct platform_device *pdev) · 9 unmodified lines
715	859	for (i = 0; i < tdma->nr_channels; i++) {
716	860	struct tegra_adma_chan *tdc = &tdma->channels[i];
717	861
718		− tdc->chan_addr = tdma->base_addr + ADMA_CH_REG_OFFSET(i);
	862	+ tdc->chan_addr = tdma->base_addr + cdata->ch_base_offset
	863	+ + (cdata->ch_reg_size * i);
719	864
720	865	tdc->irq = of_irq_get(pdev->dev.of_node, i);
721	866	if (tdc->irq <= 0) {
@@ -746,6 +891,8 @@ static int tegra_adma_probe(struct platform_device *pdev) · 24 unmodified lines
746	891	tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
747	892	tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) \| BIT(DMA_MEM_TO_DEV);
748	893	tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
	894	+ tdma->dma_dev.device_pause = tegra_adma_pause;
	895	+ tdma->dma_dev.device_resume = tegra_adma_resume;
749	896
750	897	ret = dma_async_device_register(&tdma->dma_dev);
751	898	if (ret < 0) {
@@ -776,8 +923,6 @@ rpm_put: · 24 unmodified lines
776	923	pm_runtime_put_sync(&pdev->dev);
777	924	rpm_disable:
778	925	pm_runtime_disable(&pdev->dev);
779		−clk_destroy:
780		− pm_clk_destroy(&pdev->dev);
781	926
782	927	return ret;
783	928	}
@@ -787,6 +932,7 @@ static int tegra_adma_remove(struct platform_device *pdev) · 3 unmodified lines
787	932	struct tegra_adma *tdma = platform_get_drvdata(pdev);
788	933	int i;
789	934
	935	+ of_dma_controller_free(pdev->dev.of_node);
790	936	dma_async_device_unregister(&tdma->dma_dev);
791	937
792	938	for (i = 0; i < tdma->nr_channels; ++i)
@@ -794,22 +940,15 @@ static int tegra_adma_remove(struct platform_device *pdev) · 1 unmodified line
794	940
795	941	pm_runtime_put_sync(&pdev->dev);
796	942	pm_runtime_disable(&pdev->dev);
797		− pm_clk_destroy(&pdev->dev);
798	943
799	944	return 0;
800	945	}
801	946
802		−#ifdef CONFIG_PM_SLEEP
803		−static int tegra_adma_pm_suspend(struct device *dev)
804		−{
805		− return pm_runtime_suspended(dev) == false;
806		−}
807		−#endif
808		−
809	947	static const struct dev_pm_ops tegra_adma_dev_pm_ops = {
810	948	SET_RUNTIME_PM_OPS(tegra_adma_runtime_suspend,
811	949	tegra_adma_runtime_resume, NULL)
812		− SET_SYSTEM_SLEEP_PM_OPS(tegra_adma_pm_suspend, NULL)
	950	+ SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
	951	+ pm_runtime_force_resume)
813	952	};
814	953
815	954	static struct platform_driver tegra_admac_driver = {

drivers/dma/xgene-dma.c+3−3

@@ -703,7 +703,7 @@ static void xgene_dma_cleanup_descriptors(struct xgene_dma_chan *chan) · 702 unmodified lines
703	703
704	704	INIT_LIST_HEAD(&ld_completed);
705	705
706		− spin_lock_bh(&chan->lock);
	706	+ spin_lock(&chan->lock);
707	707
708	708	/* Clean already completed and acked descriptors */
709	709	xgene_dma_clean_completed_descriptor(chan);
@@ -772,7 +772,7 @@ static void xgene_dma_cleanup_descriptors(struct xgene_dma_chan *chan) · 62 unmodified lines
772	772	*/
773	773	xgene_chan_xfer_ld_pending(chan);
774	774
775		− spin_unlock_bh(&chan->lock);
	775	+ spin_unlock(&chan->lock);
776	776
777	777	/* Run the callback for each descriptor, in order */
778	778	list_for_each_entry_safe(desc_sw, _desc_sw, &ld_completed, node) {
@@ -797,7 +797,7 @@ static int xgene_dma_alloc_chan_resources(struct dma_chan *dchan) · 18 unmodified lines
797	797	return -ENOMEM;
798	798	}
799	799
800		− chan_dbg(chan, "Allocate descripto pool\n");
	800	+ chan_dbg(chan, "Allocate descriptor pool\n");
801	801
802	802	return 1;
803	803	}

drivers/mfd/intel-lpss.c+2−2

@@ -28,6 +28,8 @@ · 27 unmodified lines
28	28	#include <linux/seq_file.h>
29	29	#include <linux/io-64-nonatomic-lo-hi.h>
30	30
	31	+#include <linux/dma/idma64.h>
	32	+
31	33	#include "intel-lpss.h"
32	34
33	35	#define LPSS_DEV_OFFSET 0x000
@@ -96,8 +98,6 @@ static const struct resource intel_lpss_idma64_resources[] = { · 62 unmodified lines
96	98	DEFINE_RES_IRQ(0),
97	99	};
98	100
99		−#define LPSS_IDMA64_DRIVER_NAME "idma64"
100		−
101	101	/*
102	102	* Cells needs to be ordered so that the iDMA is created first. This is
103	103	* because we need to be sure the DMA is available when the host controller

drivers/spi/spi-pxa2xx.c+1−6

@@ -1498,12 +1498,7 @@ static int pxa2xx_spi_get_port_id(struct acpi_device *adev) · 1497 unmodified lines
1498	1498
1499	1499	static bool pxa2xx_spi_idma_filter(struct dma_chan chan, void param)
1500	1500	{
1501		− struct device *dev = param;
1502		−
1503		− if (dev != chan->device->dev->parent)
1504		− return false;
1505		−
1506		− return true;
	1501	+ return param == chan->device->dev;
1507	1502	}
1508	1503
1509	1504	#endif /* CONFIG_PCI */

drivers/tty/serial/8250/8250_dw.c+2−2

@@ -365,7 +365,7 @@ static bool dw8250_fallback_dma_filter(struct dma_chan chan, void param) · 364 unmodified lines
365	365
366	366	static bool dw8250_idma_filter(struct dma_chan chan, void param)
367	367	{
368		− return param == chan->device->dev->parent;
	368	+ return param == chan->device->dev;
369	369	}
370	370
371	371	/*
@@ -434,7 +434,7 @@ static void dw8250_quirks(struct uart_port p, struct dw8250_data data) · 62 unmodified lines
434	434	data->uart_16550_compatible = true;
435	435	}
436	436
437		− /* Platforms with iDMA */
	437	+ /* Platforms with iDMA 64-bit */
438	438	if (platform_get_resource_byname(to_platform_device(p->dev),
439	439	IORESOURCE_MEM, "lpss_priv")) {
440	440	data->dma.rx_param = p->dev->parent;

include/linux/dma/idma64.h+14−0

@@ -0,0 +1,14 @@
	1	+/* SPDX-License-Identifier: GPL-2.0 */
	2	+/*
	3	+ * Definitions for the Intel integrated DMA 64-bit
	4	+ *
	5	+ * Copyright (C) 2019 Intel Corporation
	6	+ */
	7	+
	8	+#ifndef __LINUX_DMA_IDMA64_H__
	9	+#define __LINUX_DMA_IDMA64_H__
	10	+
	11	+/* Platform driver name */
	12	+#define LPSS_IDMA64_DRIVER_NAME "idma64"
	13	+
	14	+#endif /* __LINUX_DMA_IDMA64_H__ */

Merge tag 'dmaengine-5.2-rc1' of git://git.infradead.org/users/vkoul/slave-dma

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