Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull more clk updates from Stephen Boyd: "Here's some more updates that missed the last pull request because I happened to tag the tree at an earlier point in the history of clk-next. I must have fat fingered it and checked out an older version of clk-next on this second computer I'm using. This time it actually includes more code for Qualcomm SoCs, the AT91 major updates, and some Rockchip SoC clk driver updates as well. I've corrected this flow so this shouldn't happen again" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (83 commits) clk: bcm2835: Do not use prediv with bcm2711's PLLs clk: drop unused function __clk_get_flags clk: hsdk: Fix bad dependency on IOMEM dt-bindings: clock: Fix YAML schemas for LPASS clocks on SC7180 clk: mmp: avoid missing prototype warning clk: sparx5: Add Sparx5 SoC DPLL clock driver dt-bindings: clock: sparx5: Add bindings include file clk: qoriq: add LS1021A core pll mux options clk: clk-atlas6: fix return value check in atlas6_clk_init() clk: tegra: pll: Improve PLLM enable-state detection clk: X1000: Add support for calculat REFCLK of USB PHY. clk: JZ4780: Reformat the code to align it. clk: JZ4780: Add functions for enable and disable USB PHY. clk: Ingenic: Add RTC related clocks for Ingenic SoCs. dt-bindings: clock: Add tabs to align code. dt-bindings: clock: Add RTC related clocks for Ingenic SoCs. clk: davinci: Use fallthrough pseudo-keyword clk: imx: Use fallthrough pseudo-keyword clk: qcom: gcc-sdm660: Fix up gcc_mss_mnoc_bimc_axi_clk clk: qcom: gcc-sdm660: Add missing modem reset ...

Linus Torvalds committed 6 years ago

Commit 05a5b5d2 parents 4586039 dd9c69782 files · +4778 −871Browse files

Showing the changes to include (12 of 82 files). Show all

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12 files

include/dt-bindings/clock/actions,s500-cmu.h +6 −1
include/dt-bindings/clock/jz4780-cgu.h +73 −71
include/dt-bindings/clock/qcom,gcc-sc7180.h +1 −0
include/dt-bindings/clock/qcom,gcc-sdm660.h +1 −0
include/dt-bindings/clock/qcom,gpucc-sm8150.h +33 −0
include/dt-bindings/clock/qcom,gpucc-sm8250.h +34 −0
include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h +29 −0
include/dt-bindings/clock/x1000-cgu.h +2 −0
include/dt-bindings/clock/x1830-cgu.h +2 −0
include/dt-bindings/reset/actions,s500-reset.h +67 −0
include/linux/clk-provider.h +0 −1
include/linux/clk/at91_pmc.h +4 −0

include/dt-bindings/clock/actions,s500-cmu.h+6−1

@@ -72,7 +72,12 @@ · 71 unmodified lines
72	72	#define CLK_NAND 52
73	73	#define CLK_ECC 53
74	74	#define CLK_RMII_REF 54
	75	+#define CLK_GPIO 55
75	76
76		−#define CLK_NR_CLKS (CLK_RMII_REF + 1)
	77	+/* system clock (part 2) */
	78	+#define CLK_APB 56
	79	+#define CLK_DMAC 57
	80	+
	81	+#define CLK_NR_CLKS (CLK_DMAC + 1)
77	82
78	83	#endif /* __DT_BINDINGS_CLOCK_S500_CMU_H */

include/dt-bindings/clock/jz4780-cgu.h+73−71

@@ -12,78 +12,80 @@ · 11 unmodified lines
12	12	#ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__
13	13	#define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__
14	14
15		−#define JZ4780_CLK_EXCLK 0
16		−#define JZ4780_CLK_RTCLK 1
17		−#define JZ4780_CLK_APLL 2
18		−#define JZ4780_CLK_MPLL 3
19		−#define JZ4780_CLK_EPLL 4
20		−#define JZ4780_CLK_VPLL 5
21		−#define JZ4780_CLK_OTGPHY 6
22		−#define JZ4780_CLK_SCLKA 7
23		−#define JZ4780_CLK_CPUMUX 8
24		−#define JZ4780_CLK_CPU 9
25		−#define JZ4780_CLK_L2CACHE 10
26		−#define JZ4780_CLK_AHB0 11
27		−#define JZ4780_CLK_AHB2PMUX 12
28		−#define JZ4780_CLK_AHB2 13
29		−#define JZ4780_CLK_PCLK 14
30		−#define JZ4780_CLK_DDR 15
31		−#define JZ4780_CLK_VPU 16
32		−#define JZ4780_CLK_I2SPLL 17
33		−#define JZ4780_CLK_I2S 18
	15	+#define JZ4780_CLK_EXCLK 0
	16	+#define JZ4780_CLK_RTCLK 1
	17	+#define JZ4780_CLK_APLL 2
	18	+#define JZ4780_CLK_MPLL 3
	19	+#define JZ4780_CLK_EPLL 4
	20	+#define JZ4780_CLK_VPLL 5
	21	+#define JZ4780_CLK_OTGPHY 6
	22	+#define JZ4780_CLK_SCLKA 7
	23	+#define JZ4780_CLK_CPUMUX 8
	24	+#define JZ4780_CLK_CPU 9
	25	+#define JZ4780_CLK_L2CACHE 10
	26	+#define JZ4780_CLK_AHB0 11
	27	+#define JZ4780_CLK_AHB2PMUX 12
	28	+#define JZ4780_CLK_AHB2 13
	29	+#define JZ4780_CLK_PCLK 14
	30	+#define JZ4780_CLK_DDR 15
	31	+#define JZ4780_CLK_VPU 16
	32	+#define JZ4780_CLK_I2SPLL 17
	33	+#define JZ4780_CLK_I2S 18
34	34	#define JZ4780_CLK_LCD0PIXCLK 19
35	35	#define JZ4780_CLK_LCD1PIXCLK 20
36		−#define JZ4780_CLK_MSCMUX 21
37		−#define JZ4780_CLK_MSC0 22
38		−#define JZ4780_CLK_MSC1 23
39		−#define JZ4780_CLK_MSC2 24
40		−#define JZ4780_CLK_UHC 25
41		−#define JZ4780_CLK_SSIPLL 26
42		−#define JZ4780_CLK_SSI 27
43		−#define JZ4780_CLK_CIMMCLK 28
44		−#define JZ4780_CLK_PCMPLL 29
45		−#define JZ4780_CLK_PCM 30
46		−#define JZ4780_CLK_GPU 31
47		−#define JZ4780_CLK_HDMI 32
48		−#define JZ4780_CLK_BCH 33
49		−#define JZ4780_CLK_NEMC 34
50		−#define JZ4780_CLK_OTG0 35
51		−#define JZ4780_CLK_SSI0 36
52		−#define JZ4780_CLK_SMB0 37
53		−#define JZ4780_CLK_SMB1 38
54		−#define JZ4780_CLK_SCC 39
55		−#define JZ4780_CLK_AIC 40
56		−#define JZ4780_CLK_TSSI0 41
57		−#define JZ4780_CLK_OWI 42
58		−#define JZ4780_CLK_KBC 43
59		−#define JZ4780_CLK_SADC 44
60		−#define JZ4780_CLK_UART0 45
61		−#define JZ4780_CLK_UART1 46
62		−#define JZ4780_CLK_UART2 47
63		−#define JZ4780_CLK_UART3 48
64		−#define JZ4780_CLK_SSI1 49
65		−#define JZ4780_CLK_SSI2 50
66		−#define JZ4780_CLK_PDMA 51
67		−#define JZ4780_CLK_GPS 52
68		−#define JZ4780_CLK_MAC 53
69		−#define JZ4780_CLK_SMB2 54
70		−#define JZ4780_CLK_CIM 55
71		−#define JZ4780_CLK_LCD 56
72		−#define JZ4780_CLK_TVE 57
73		−#define JZ4780_CLK_IPU 58
74		−#define JZ4780_CLK_DDR0 59
75		−#define JZ4780_CLK_DDR1 60
76		−#define JZ4780_CLK_SMB3 61
77		−#define JZ4780_CLK_TSSI1 62
78		−#define JZ4780_CLK_COMPRESS 63
79		−#define JZ4780_CLK_AIC1 64
80		−#define JZ4780_CLK_GPVLC 65
81		−#define JZ4780_CLK_OTG1 66
82		−#define JZ4780_CLK_UART4 67
83		−#define JZ4780_CLK_AHBMON 68
84		−#define JZ4780_CLK_SMB4 69
85		−#define JZ4780_CLK_DES 70
86		−#define JZ4780_CLK_X2D 71
87		−#define JZ4780_CLK_CORE1 72
	36	+#define JZ4780_CLK_MSCMUX 21
	37	+#define JZ4780_CLK_MSC0 22
	38	+#define JZ4780_CLK_MSC1 23
	39	+#define JZ4780_CLK_MSC2 24
	40	+#define JZ4780_CLK_UHC 25
	41	+#define JZ4780_CLK_SSIPLL 26
	42	+#define JZ4780_CLK_SSI 27
	43	+#define JZ4780_CLK_CIMMCLK 28
	44	+#define JZ4780_CLK_PCMPLL 29
	45	+#define JZ4780_CLK_PCM 30
	46	+#define JZ4780_CLK_GPU 31
	47	+#define JZ4780_CLK_HDMI 32
	48	+#define JZ4780_CLK_BCH 33
	49	+#define JZ4780_CLK_NEMC 34
	50	+#define JZ4780_CLK_OTG0 35
	51	+#define JZ4780_CLK_SSI0 36
	52	+#define JZ4780_CLK_SMB0 37
	53	+#define JZ4780_CLK_SMB1 38
	54	+#define JZ4780_CLK_SCC 39
	55	+#define JZ4780_CLK_AIC 40
	56	+#define JZ4780_CLK_TSSI0 41
	57	+#define JZ4780_CLK_OWI 42
	58	+#define JZ4780_CLK_KBC 43
	59	+#define JZ4780_CLK_SADC 44
	60	+#define JZ4780_CLK_UART0 45
	61	+#define JZ4780_CLK_UART1 46
	62	+#define JZ4780_CLK_UART2 47
	63	+#define JZ4780_CLK_UART3 48
	64	+#define JZ4780_CLK_SSI1 49
	65	+#define JZ4780_CLK_SSI2 50
	66	+#define JZ4780_CLK_PDMA 51
	67	+#define JZ4780_CLK_GPS 52
	68	+#define JZ4780_CLK_MAC 53
	69	+#define JZ4780_CLK_SMB2 54
	70	+#define JZ4780_CLK_CIM 55
	71	+#define JZ4780_CLK_LCD 56
	72	+#define JZ4780_CLK_TVE 57
	73	+#define JZ4780_CLK_IPU 58
	74	+#define JZ4780_CLK_DDR0 59
	75	+#define JZ4780_CLK_DDR1 60
	76	+#define JZ4780_CLK_SMB3 61
	77	+#define JZ4780_CLK_TSSI1 62
	78	+#define JZ4780_CLK_COMPRESS 63
	79	+#define JZ4780_CLK_AIC1 64
	80	+#define JZ4780_CLK_GPVLC 65
	81	+#define JZ4780_CLK_OTG1 66
	82	+#define JZ4780_CLK_UART4 67
	83	+#define JZ4780_CLK_AHBMON 68
	84	+#define JZ4780_CLK_SMB4 69
	85	+#define JZ4780_CLK_DES 70
	86	+#define JZ4780_CLK_X2D 71
	87	+#define JZ4780_CLK_CORE1 72
	88	+#define JZ4780_CLK_EXCLK_DIV512 73
	89	+#define JZ4780_CLK_RTC 74
88	90
89	91	#endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */

include/dt-bindings/clock/qcom,gcc-sc7180.h+1−0

@@ -138,6 +138,7 @@ · 137 unmodified lines
138	138	#define GCC_MSS_Q6_MEMNOC_AXI_CLK 128
139	139	#define GCC_MSS_SNOC_AXI_CLK 129
140	140	#define GCC_SEC_CTRL_CLK_SRC 130
	141	+#define GCC_LPASS_CFG_NOC_SWAY_CLK 131
141	142
142	143	/* GCC resets */
143	144	#define GCC_QUSB2PHY_PRIM_BCR 0

include/dt-bindings/clock/qcom,gcc-sdm660.h+1−0

@@ -152,5 +152,6 @@ · 151 unmodified lines
152	152	#define GCC_USB_20_BCR 6
153	153	#define GCC_USB_30_BCR 7
154	154	#define GCC_USB_PHY_CFG_AHB2PHY_BCR 8
	155	+#define GCC_MSS_RESTART 9
155	156
156	157	#endif

include/dt-bindings/clock/qcom,gpucc-sm8150.h+33−0

@@ -0,0 +1,33 @@
	1	+/* SPDX-License-Identifier: GPL-2.0 */
	2	+/*
	3	+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
	4	+ */
	5	+
	6	+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8150_H
	7	+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8150_H
	8	+
	9	+/* GPU_CC clock registers */
	10	+#define GPU_CC_AHB_CLK 0
	11	+#define GPU_CC_CRC_AHB_CLK 1
	12	+#define GPU_CC_CX_APB_CLK 2
	13	+#define GPU_CC_CX_GMU_CLK 3
	14	+#define GPU_CC_CX_SNOC_DVM_CLK 4
	15	+#define GPU_CC_CXO_AON_CLK 5
	16	+#define GPU_CC_CXO_CLK 6
	17	+#define GPU_CC_GMU_CLK_SRC 7
	18	+#define GPU_CC_GX_GMU_CLK 8
	19	+#define GPU_CC_PLL1 9
	20	+
	21	+/* GPU_CC Resets */
	22	+#define GPUCC_GPU_CC_CX_BCR 0
	23	+#define GPUCC_GPU_CC_GFX3D_AON_BCR 1
	24	+#define GPUCC_GPU_CC_GMU_BCR 2
	25	+#define GPUCC_GPU_CC_GX_BCR 3
	26	+#define GPUCC_GPU_CC_SPDM_BCR 4
	27	+#define GPUCC_GPU_CC_XO_BCR 5
	28	+
	29	+/* GPU_CC GDSCRs */
	30	+#define GPU_CX_GDSC 0
	31	+#define GPU_GX_GDSC 1
	32	+
	33	+#endif

include/dt-bindings/clock/qcom,gpucc-sm8250.h+34−0

@@ -0,0 +1,34 @@
	1	+/* SPDX-License-Identifier: GPL-2.0 */
	2	+/*
	3	+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
	4	+ */
	5	+
	6	+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H
	7	+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H
	8	+
	9	+/* GPU_CC clock registers */
	10	+#define GPU_CC_AHB_CLK 0
	11	+#define GPU_CC_CRC_AHB_CLK 1
	12	+#define GPU_CC_CX_APB_CLK 2
	13	+#define GPU_CC_CX_GMU_CLK 3
	14	+#define GPU_CC_CX_SNOC_DVM_CLK 4
	15	+#define GPU_CC_CXO_AON_CLK 5
	16	+#define GPU_CC_CXO_CLK 6
	17	+#define GPU_CC_GMU_CLK_SRC 7
	18	+#define GPU_CC_GX_GMU_CLK 8
	19	+#define GPU_CC_PLL1 9
	20	+#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 10
	21	+
	22	+/* GPU_CC Resets */
	23	+#define GPUCC_GPU_CC_ACD_BCR 0
	24	+#define GPUCC_GPU_CC_CX_BCR 1
	25	+#define GPUCC_GPU_CC_GFX3D_AON_BCR 2
	26	+#define GPUCC_GPU_CC_GMU_BCR 3
	27	+#define GPUCC_GPU_CC_GX_BCR 4
	28	+#define GPUCC_GPU_CC_XO_BCR 5
	29	+
	30	+/* GPU_CC GDSCRs */
	31	+#define GPU_CX_GDSC 0
	32	+#define GPU_GX_GDSC 1
	33	+
	34	+#endif

include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h+29−0

@@ -0,0 +1,29 @@
	1	+/* SPDX-License-Identifier: GPL-2.0-only */
	2	+/*
	3	+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
	4	+ */
	5	+
	6	+#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7180_H
	7	+#define _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7180_H
	8	+
	9	+/* LPASS_CORE_CC clocks */
	10	+#define LPASS_LPAAUDIO_DIG_PLL 0
	11	+#define LPASS_LPAAUDIO_DIG_PLL_OUT_ODD 1
	12	+#define CORE_CLK_SRC 2
	13	+#define EXT_MCLK0_CLK_SRC 3
	14	+#define LPAIF_PRI_CLK_SRC 4
	15	+#define LPAIF_SEC_CLK_SRC 5
	16	+#define LPASS_AUDIO_CORE_CORE_CLK 6
	17	+#define LPASS_AUDIO_CORE_EXT_MCLK0_CLK 7
	18	+#define LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK 8
	19	+#define LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK 9
	20	+#define LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK 10
	21	+
	22	+/* LPASS Core power domains */
	23	+#define LPASS_CORE_HM_GDSCR 0
	24	+
	25	+/* LPASS Audio power domains */
	26	+#define LPASS_AUDIO_HM_GDSCR 0
	27	+#define LPASS_PDC_HM_GDSCR 1
	28	+
	29	+#endif

include/dt-bindings/clock/x1000-cgu.h+2−0

@@ -48,5 +48,7 @@ · 47 unmodified lines
48	48	#define X1000_CLK_SSI 33
49	49	#define X1000_CLK_OST 34
50	50	#define X1000_CLK_PDMA 35
	51	+#define X1000_CLK_EXCLK_DIV512 36
	52	+#define X1000_CLK_RTC 37
51	53
52	54	#endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */

include/dt-bindings/clock/x1830-cgu.h+2−0

@@ -51,5 +51,7 @@ · 50 unmodified lines
51	51	#define X1830_CLK_TCU 36
52	52	#define X1830_CLK_DTRNG 37
53	53	#define X1830_CLK_OST 38
	54	+#define X1830_CLK_EXCLK_DIV512 39
	55	+#define X1830_CLK_RTC 40
54	56
55	57	#endif /* __DT_BINDINGS_CLOCK_X1830_CGU_H__ */

include/dt-bindings/reset/actions,s500-reset.h+67−0

@@ -0,0 +1,67 @@
	1	+/* SPDX-License-Identifier: GPL-2.0+ */
	2	+/*
	3	+ * Device Tree binding constants for Actions Semi S500 Reset Management Unit
	4	+ *
	5	+ * Copyright (c) 2014 Actions Semi Inc.
	6	+ * Copyright (c) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
	7	+ */
	8	+
	9	+#ifndef __DT_BINDINGS_ACTIONS_S500_RESET_H
	10	+#define __DT_BINDINGS_ACTIONS_S500_RESET_H
	11	+
	12	+#define RESET_DMAC 0
	13	+#define RESET_NORIF 1
	14	+#define RESET_DDR 2
	15	+#define RESET_NANDC 3
	16	+#define RESET_SD0 4
	17	+#define RESET_SD1 5
	18	+#define RESET_PCM1 6
	19	+#define RESET_DE 7
	20	+#define RESET_LCD 8
	21	+#define RESET_SD2 9
	22	+#define RESET_DSI 10
	23	+#define RESET_CSI 11
	24	+#define RESET_BISP 12
	25	+#define RESET_KEY 13
	26	+#define RESET_GPIO 14
	27	+#define RESET_AUDIO 15
	28	+#define RESET_PCM0 16
	29	+#define RESET_VDE 17
	30	+#define RESET_VCE 18
	31	+#define RESET_GPU3D 19
	32	+#define RESET_NIC301 20
	33	+#define RESET_LENS 21
	34	+#define RESET_PERIPHRESET 22
	35	+#define RESET_USB2_0 23
	36	+#define RESET_TVOUT 24
	37	+#define RESET_HDMI 25
	38	+#define RESET_HDCP2TX 26
	39	+#define RESET_UART6 27
	40	+#define RESET_UART0 28
	41	+#define RESET_UART1 29
	42	+#define RESET_UART2 30
	43	+#define RESET_SPI0 31
	44	+#define RESET_SPI1 32
	45	+#define RESET_SPI2 33
	46	+#define RESET_SPI3 34
	47	+#define RESET_I2C0 35
	48	+#define RESET_I2C1 36
	49	+#define RESET_USB3 37
	50	+#define RESET_UART3 38
	51	+#define RESET_UART4 39
	52	+#define RESET_UART5 40
	53	+#define RESET_I2C2 41
	54	+#define RESET_I2C3 42
	55	+#define RESET_ETHERNET 43
	56	+#define RESET_CHIPID 44
	57	+#define RESET_USB2_1 45
	58	+#define RESET_WD0RESET 46
	59	+#define RESET_WD1RESET 47
	60	+#define RESET_WD2RESET 48
	61	+#define RESET_WD3RESET 49
	62	+#define RESET_DBG0RESET 50
	63	+#define RESET_DBG1RESET 51
	64	+#define RESET_DBG2RESET 52
	65	+#define RESET_DBG3RESET 53
	66	+
	67	+#endif /* __DT_BINDINGS_ACTIONS_S500_RESET_H */

include/linux/clk-provider.h+0−1

@@ -1096,7 +1096,6 @@ int clk_hw_get_parent_index(struct clk_hw *hw); · 1095 unmodified lines
1096	1096	int clk_hw_set_parent(struct clk_hw hw, struct clk_hw new_parent);
1097	1097	unsigned int __clk_get_enable_count(struct clk *clk);
1098	1098	unsigned long clk_hw_get_rate(const struct clk_hw *hw);
1099		−unsigned long __clk_get_flags(struct clk *clk);
1100	1099	unsigned long clk_hw_get_flags(const struct clk_hw *hw);
1101	1100	#define clk_hw_can_set_rate_parent(hw) \
1102	1101	(clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)

include/linux/clk/at91_pmc.h+4−0

@@ -59,6 +59,7 @@ · 58 unmodified lines
59	59	#define AT91_PMC_PLL_UPDT 0x1C /* PMC PLL update register [for SAM9X60] */
60	60	#define AT91_PMC_PLL_UPDT_UPDATE (1 << 8) /* Update PLL settings */
61	61	#define AT91_PMC_PLL_UPDT_ID (1 << 0) /* PLL ID */
	62	+#define AT91_PMC_PLL_UPDT_ID_MSK (0xf) /* PLL ID mask */
62	63	#define AT91_PMC_PLL_UPDT_STUPTIM (0xff << 16) /* Startup time */
63	64
64	65	#define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */
@@ -136,6 +137,8 @@ · 71 unmodified lines
136	137	#define AT91_PMC_PLLADIV2_ON (1 << 12)
137	138	#define AT91_PMC_H32MXDIV BIT(24)
138	139
	140	+#define AT91_PMC_XTALF 0x34 /* Main XTAL Frequency Register [SAMA7G5 only] */
	141	+
139	142	#define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */
140	143	#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */
141	144	#define AT91_PMC_USBS_PLLA (0 << 0)
@@ -174,6 +177,7 @@ · 32 unmodified lines
174	177	#define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */
175	178	#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */
176	179	#define AT91_PMC_GCKRDY (1 << 24) /* Generated Clocks */
	180	+#define AT91_PMC_MCKXRDY (1 << 26) /* Master Clock x [x=1..4] Ready Status */
177	181	#define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */
178	182
179	183	#define AT91_PMC_FSMR 0x70 /* Fast Startup Mode Register */