Pull more clk updates from Stephen Boyd: "Here's some more updates that missed the last pull request because I happened to tag the tree at an earlier point in the history of clk-next. I must have fat fingered it and checked out an older version of clk-next on this second computer I'm using. This time it actually includes more code for Qualcomm SoCs, the AT91 major updates, and some Rockchip SoC clk driver updates as well. I've corrected this flow so this shouldn't happen again" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (83 commits) clk: bcm2835: Do not use prediv with bcm2711's PLLs clk: drop unused function __clk_get_flags clk: hsdk: Fix bad dependency on IOMEM dt-bindings: clock: Fix YAML schemas for LPASS clocks on SC7180 clk: mmp: avoid missing prototype warning clk: sparx5: Add Sparx5 SoC DPLL clock driver dt-bindings: clock: sparx5: Add bindings include file clk: qoriq: add LS1021A core pll mux options clk: clk-atlas6: fix return value check in atlas6_clk_init() clk: tegra: pll: Improve PLLM enable-state detection clk: X1000: Add support for calculat REFCLK of USB PHY. clk: JZ4780: Reformat the code to align it. clk: JZ4780: Add functions for enable and disable USB PHY. clk: Ingenic: Add RTC related clocks for Ingenic SoCs. dt-bindings: clock: Add tabs to align code. dt-bindings: clock: Add RTC related clocks for Ingenic SoCs. clk: davinci: Use fallthrough pseudo-keyword clk: imx: Use fallthrough pseudo-keyword clk: qcom: gcc-sdm660: Fix up gcc_mss_mnoc_bimc_axi_clk clk: qcom: gcc-sdm660: Add missing modem reset ...
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| @@ -1096,7 +1096,6 @@ int clk_hw_get_parent_index(struct clk_hw *hw); · 1095 unmodified lines | ||
| 1096 | 1096 | int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent); |
| 1097 | 1097 | unsigned int __clk_get_enable_count(struct clk *clk); |
| 1098 | 1098 | unsigned long clk_hw_get_rate(const struct clk_hw *hw); |
| 1099 | −unsigned long __clk_get_flags(struct clk *clk); | |
| 1100 | 1099 | unsigned long clk_hw_get_flags(const struct clk_hw *hw); |
| 1101 | 1100 | #define clk_hw_can_set_rate_parent(hw) \ |
| 1102 | 1101 | (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT) |
| @@ -59,6 +59,7 @@ · 58 unmodified lines | ||
| 59 | 59 | #define AT91_PMC_PLL_UPDT 0x1C /* PMC PLL update register [for SAM9X60] */ |
| 60 | 60 | #define AT91_PMC_PLL_UPDT_UPDATE (1 << 8) /* Update PLL settings */ |
| 61 | 61 | #define AT91_PMC_PLL_UPDT_ID (1 << 0) /* PLL ID */ |
| 62 | +#define AT91_PMC_PLL_UPDT_ID_MSK (0xf) /* PLL ID mask */ | |
| 62 | 63 | #define AT91_PMC_PLL_UPDT_STUPTIM (0xff << 16) /* Startup time */ |
| 63 | 64 | |
| 64 | 65 | #define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */ |
| @@ -136,6 +137,8 @@ · 71 unmodified lines | ||
| 136 | 137 | #define AT91_PMC_PLLADIV2_ON (1 << 12) |
| 137 | 138 | #define AT91_PMC_H32MXDIV BIT(24) |
| 138 | 139 | |
| 140 | +#define AT91_PMC_XTALF 0x34 /* Main XTAL Frequency Register [SAMA7G5 only] */ | |
| 141 | + | |
| 139 | 142 | #define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */ |
| 140 | 143 | #define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */ |
| 141 | 144 | #define AT91_PMC_USBS_PLLA (0 << 0) |
| @@ -174,6 +177,7 @@ · 32 unmodified lines | ||
| 174 | 177 | #define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */ |
| 175 | 178 | #define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */ |
| 176 | 179 | #define AT91_PMC_GCKRDY (1 << 24) /* Generated Clocks */ |
| 180 | +#define AT91_PMC_MCKXRDY (1 << 26) /* Master Clock x [x=1..4] Ready Status */ | |
| 177 | 181 | #define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */ |
| 178 | 182 | |
| 179 | 183 | #define AT91_PMC_FSMR 0x70 /* Fast Startup Mode Register */ |