Commit 2a7fade7e03 ("hwmon: lis3: Power on corrections") caused a regression on HP laptops with 8bit chip. Writing CTRL2_BOOT_8B bit seems clearing the BIOS setup, and no proper interrupt for DriveGuard will be triggered any more. Since the init code there is basically only for embedded devices, put a pdata check so that the problematic initialization will be skipped for hp_accel stuff.
Unified · Split
| @@ -375,12 +375,14 @@ void lis3lv02d_poweron(struct lis3lv02d *lis3) · 374 unmodified lines | ||
| 375 | 375 | * both have been read. So the value read will always be correct. |
| 376 | 376 | * Set BOOT bit to refresh factory tuning values. |
| 377 | 377 | */ |
| 378 | − lis3->read(lis3, CTRL_REG2, ®); | |
| 379 | − if (lis3->whoami == WAI_12B) | |
| 380 | − reg |= CTRL2_BDU | CTRL2_BOOT; | |
| 381 | − else | |
| 382 | − reg |= CTRL2_BOOT_8B; | |
| 383 | − lis3->write(lis3, CTRL_REG2, reg); | |
| 378 | + if (lis3->pdata) { | |
| 379 | + lis3->read(lis3, CTRL_REG2, ®); | |
| 380 | + if (lis3->whoami == WAI_12B) | |
| 381 | + reg |= CTRL2_BDU | CTRL2_BOOT; | |
| 382 | + else | |
| 383 | + reg |= CTRL2_BOOT_8B; | |
| 384 | + lis3->write(lis3, CTRL_REG2, reg); | |
| 385 | + } | |
| 384 | 386 | |
| 385 | 387 | /* LIS3 power on delay is quite long */ |
| 386 | 388 | msleep(lis3->pwron_delay / lis3lv02d_get_odr()); |