Merge tag 'fixes-for-3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull arm-soc fixes from Arnd Bergmann: "Bug fixes for a number of ARM platforms, mostly OMAP, imx and at91. These come a little later than I had hoped but unfortunately we had a few of these patches cause regressions themselves and had to work out how to deal with those in the meantime." * tag 'fixes-for-3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (38 commits) Revert "ARM i.MX25: Fix PWM per clock lookups" ARM: versatile: fix versatile_defconfig ARM: mvebu: update defconfig with 3.7 changes ARM: at91: fix at91x40 build ARM: socfpga: Fix socfpga compilation with early_printk() enabled ARM: SPEAr: Remove unused empty files MAINTAINERS: Add arm-soc tree entry ARM: dts: mxs: add the "clock-names" for gpmi-nand ARM: ux500: Correct SDI5 address and add some format changes ARM: ux500: Specify AMBA Primecell IDs for Nomadik I2C in DT ARM: ux500: Fix build error relating to IRQCHIP_SKIP_SET_WAKE ARM: at91: drop duplicated config SOC_AT91SAM9 entry ARM: at91/i2c: change id to let i2c-at91 work ARM: at91/i2c: change id to let i2c-gpio work ARM: at91/dts: at91sam9g20ek_common: Fix typos in buttons labels. ARM: at91: fix external interrupt specification in board code ARM: at91: fix external interrupts in non-DT case ARM: at91: at91sam9g10: fix SOC type detection ARM: at91/tc: fix typo in the DT document ARM: AM33XX: Fix configuration of dmtimer parent clock by dmtimer driverDate:Wed, 17 Oct 2012 13:55:55 -0500 ...

Linus Torvalds committed 14 years ago

Commit 065c8012 parents 1a25b1c 943bb4856 files · +225 −87Browse files

Unified · Split

56 files

Documentation/devicetree/bindings/arm/atmel-at91.txt +1 −1
MAINTAINERS +7 −0
arch/arm/boot/dts/at91sam9g20ek_common.dtsi +2 −2
arch/arm/boot/dts/dbx5x0.dtsi +16 −1
arch/arm/boot/dts/exynos4210-trats.dts +4 −2
arch/arm/boot/dts/imx23.dtsi +1 −0
arch/arm/boot/dts/imx28.dtsi +1 −0
arch/arm/boot/dts/omap3.dtsi +2 −2
arch/arm/configs/imx_v6_v7_defconfig +2 −0
arch/arm/configs/mvebu_defconfig +7 −3
arch/arm/configs/versatile_defconfig +1 −0
arch/arm/include/debug/8250_32.S +27 −0
arch/arm/include/debug/picoxcell.S +1 −17
arch/arm/include/debug/socfpga.S +5 −0
arch/arm/mach-at91/Kconfig +2 −8
arch/arm/mach-at91/at91rm9200.c +1 −1
arch/arm/mach-at91/at91rm9200_devices.c +2 −2
arch/arm/mach-at91/at91sam9260.c +2 −2
arch/arm/mach-at91/at91sam9260_devices.c +2 −2
arch/arm/mach-at91/at91sam9261.c +2 −2
arch/arm/mach-at91/at91sam9261_devices.c +2 −2
arch/arm/mach-at91/at91sam9263.c +1 −1
arch/arm/mach-at91/at91sam9263_devices.c +2 −2
arch/arm/mach-at91/at91sam9rl_devices.c +2 −2
arch/arm/mach-at91/at91x40.c +1 −1
arch/arm/mach-at91/board-neocore926.c +1 −1
arch/arm/mach-at91/board-sam9261ek.c +1 −1
arch/arm/mach-at91/board-sam9263ek.c +1 −1
arch/arm/mach-at91/generic.h +2 −1
arch/arm/mach-at91/irq.c +7 −2
arch/arm/mach-at91/setup.c +2 −2
arch/arm/mach-exynos/common.c +5 −0
arch/arm/mach-exynos/mach-exynos4-dt.c +1 −0
arch/arm/mach-imx/clk-busy.c +1 −1
arch/arm/mach-imx/clk-imx25.c +2 −2
arch/arm/mach-imx/clk-imx27.c +2 −2
arch/arm/mach-imx/mm-imx3.c +2 −3
arch/arm/mach-omap2/Kconfig +0 −1
arch/arm/mach-omap2/board-omap3beagle.c +13 −9
arch/arm/mach-omap2/clock33xx_data.c +2 −0
arch/arm/mach-omap2/mux34xx.c +4 −4
arch/arm/mach-omap2/pm.h +1 −0
arch/arm/mach-omap2/pm34xx.c +28 −2
arch/arm/mach-omap2/serial.c +5 −0
arch/arm/mach-s3c24xx/s3c2416.c +2 −0
arch/arm/mach-s3c24xx/s3c2443.c +4 −0
arch/arm/mach-s5p64x0/common.c +3 −0
arch/arm/mach-s5pc100/common.c +3 −0
arch/arm/mach-s5pv210/common.c +3 −0
arch/arm/mach-shmobile/setup-r8a7779.c +1 −1
arch/arm/mach-spear13xx/include/mach/spear1310_misc_regs.h +0 −0
arch/arm/mach-spear13xx/include/mach/spear1340_misc_regs.h +0 −0
arch/arm/mach-ux500/cpu.c +1 −0
arch/arm/plat-mxc/devices/platform-mxc-mmc.c +1 −1
arch/arm/plat-omap/Kconfig +1 −0
arch/arm/plat-samsung/include/plat/spi-core.h +30 −0

Documentation/devicetree/bindings/arm/atmel-at91.txt+1−1

@@ -8,7 +8,7 @@ PIT Timer required properties: · 7 unmodified lines
8	8	shared across all System Controller members.
9	9
10	10	TC/TCLIB Timer required properties:
11		−- compatible: Should be "atmel,<chip>-pit".
	11	+- compatible: Should be "atmel,<chip>-tcb".
12	12	<chip> can be "at91rm9200" or "at91sam9x5"
13	13	- reg: Should contain registers location and length
14	14	- interrupts: Should contain all interrupts for the TC block

MAINTAINERS+7−0

@@ -637,6 +637,13 @@ W: http://www.arm.linux.org.uk/ · 636 unmodified lines
637	637	S: Maintained
638	638	F: arch/arm/
639	639
	640	+ARM SUB-ARCHITECTURES
	641	+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
	642	+S: MAINTAINED
	643	+F: arch/arm/mach-*/
	644	+F: arch/arm/plat-*/
	645	+T: git git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
	646	+
640	647	ARM PRIMECELL AACI PL041 DRIVER
641	648	M: Russell King <linux@arm.linux.org.uk>
642	649	S: Maintained

arch/arm/boot/dts/at91sam9g20ek_common.dtsi+2−2

@@ -126,14 +126,14 @@ · 125 unmodified lines
126	126	#size-cells = <0>;
127	127
128	128	btn3 {
129		− label = "Buttin 3";
	129	+ label = "Button 3";
130	130	gpios = <&pioA 30 1>;
131	131	linux,code = <0x103>;
132	132	gpio-key,wakeup;
133	133	};
134	134
135	135	btn4 {
136		− label = "Buttin 4";
	136	+ label = "Button 4";
137	137	gpios = <&pioA 31 1>;
138	138	linux,code = <0x104>;
139	139	gpio-key,wakeup;

arch/arm/boot/dts/dbx5x0.dtsi+16−1

@@ -483,6 +483,8 @@ · 482 unmodified lines
483	483	compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
484	484	reg = <0x80004000 0x1000>;
485	485	interrupts = <0 21 0x4>;
	486	+ arm,primecell-periphid = <0x180024>;
	487	+
486	488	#address-cells = <1>;
487	489	#size-cells = <0>;
488	490	v-i2c-supply = <&db8500_vape_reg>;
@@ -494,6 +496,8 @@ · 5 unmodified lines
494	496	compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
495	497	reg = <0x80122000 0x1000>;
496	498	interrupts = <0 22 0x4>;
	499	+ arm,primecell-periphid = <0x180024>;
	500	+
497	501	#address-cells = <1>;
498	502	#size-cells = <0>;
499	503	v-i2c-supply = <&db8500_vape_reg>;
@@ -505,6 +509,8 @@ · 5 unmodified lines
505	509	compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
506	510	reg = <0x80128000 0x1000>;
507	511	interrupts = <0 55 0x4>;
	512	+ arm,primecell-periphid = <0x180024>;
	513	+
508	514	#address-cells = <1>;
509	515	#size-cells = <0>;
510	516	v-i2c-supply = <&db8500_vape_reg>;
@@ -516,6 +522,8 @@ · 5 unmodified lines
516	522	compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
517	523	reg = <0x80110000 0x1000>;
518	524	interrupts = <0 12 0x4>;
	525	+ arm,primecell-periphid = <0x180024>;
	526	+
519	527	#address-cells = <1>;
520	528	#size-cells = <0>;
521	529	v-i2c-supply = <&db8500_vape_reg>;
@@ -527,6 +535,8 @@ · 5 unmodified lines
527	535	compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
528	536	reg = <0x8012a000 0x1000>;
529	537	interrupts = <0 51 0x4>;
	538	+ arm,primecell-periphid = <0x180024>;
	539	+
530	540	#address-cells = <1>;
531	541	#size-cells = <0>;
532	542	v-i2c-supply = <&db8500_vape_reg>;
@@ -573,33 +583,38 @@ · 40 unmodified lines
573	583	interrupts = <0 60 0x4>;
574	584	status = "disabled";
575	585	};
	586	+
576	587	sdi@80118000 {
577	588	compatible = "arm,pl18x", "arm,primecell";
578	589	reg = <0x80118000 0x1000>;
579	590	interrupts = <0 50 0x4>;
580	591	status = "disabled";
581	592	};
	593	+
582	594	sdi@80005000 {
583	595	compatible = "arm,pl18x", "arm,primecell";
584	596	reg = <0x80005000 0x1000>;
585	597	interrupts = <0 41 0x4>;
586	598	status = "disabled";
587	599	};
	600	+
588	601	sdi@80119000 {
589	602	compatible = "arm,pl18x", "arm,primecell";
590	603	reg = <0x80119000 0x1000>;
591	604	interrupts = <0 59 0x4>;
592	605	status = "disabled";
593	606	};
	607	+
594	608	sdi@80114000 {
595	609	compatible = "arm,pl18x", "arm,primecell";
596	610	reg = <0x80114000 0x1000>;
597	611	interrupts = <0 99 0x4>;
598	612	status = "disabled";
599	613	};
	614	+
600	615	sdi@80008000 {
601	616	compatible = "arm,pl18x", "arm,primecell";
602		− reg = <0x80114000 0x1000>;
	617	+ reg = <0x80008000 0x1000>;
603	618	interrupts = <0 100 0x4>;
604	619	status = "disabled";
605	620	};

arch/arm/boot/dts/exynos4210-trats.dts+4−2

@@ -20,8 +20,10 @@ · 19 unmodified lines
20	20	compatible = "samsung,trats", "samsung,exynos4210";
21	21
22	22	memory {
23		− reg = <0x40000000 0x20000000
24		− 0x60000000 0x20000000>;
	23	+ reg = <0x40000000 0x10000000
	24	+ 0x50000000 0x10000000
	25	+ 0x60000000 0x10000000
	26	+ 0x70000000 0x10000000>;
25	27	};
26	28
27	29	chosen {

arch/arm/boot/dts/imx23.dtsi+1−0

@@ -69,6 +69,7 @@ · 68 unmodified lines
69	69	interrupts = <13>, <56>;
70	70	interrupt-names = "gpmi-dma", "bch";
71	71	clocks = <&clks 34>;
	72	+ clock-names = "gpmi_io";
72	73	fsl,gpmi-dma-channel = <4>;
73	74	status = "disabled";
74	75	};

arch/arm/boot/dts/imx28.dtsi+1−0

@@ -85,6 +85,7 @@ · 84 unmodified lines
85	85	interrupts = <88>, <41>;
86	86	interrupt-names = "gpmi-dma", "bch";
87	87	clocks = <&clks 50>;
	88	+ clock-names = "gpmi_io";
88	89	fsl,gpmi-dma-channel = <4>;
89	90	status = "disabled";
90	91	};

arch/arm/boot/dts/omap3.dtsi+2−2

@@ -257,7 +257,7 @@ · 256 unmodified lines
257	257	interrupt-names = "common", "tx", "rx", "sidetone";
258	258	interrupt-parent = <&intc>;
259	259	ti,buffer-size = <1280>;
260		− ti,hwmods = "mcbsp2";
	260	+ ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
261	261	};
262	262
263	263	mcbsp3: mcbsp@49024000 {
@@ -272,7 +272,7 @@ · 8 unmodified lines
272	272	interrupt-names = "common", "tx", "rx", "sidetone";
273	273	interrupt-parent = <&intc>;
274	274	ti,buffer-size = <128>;
275		− ti,hwmods = "mcbsp3";
	275	+ ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
276	276	};
277	277
278	278	mcbsp4: mcbsp@49026000 {

arch/arm/configs/imx_v6_v7_defconfig+2−0

@@ -139,6 +139,7 @@ CONFIG_I2C_IMX=y · 138 unmodified lines
139	139	CONFIG_SPI=y
140	140	CONFIG_SPI_IMX=y
141	141	CONFIG_GPIO_SYSFS=y
	142	+CONFIG_GPIO_MC9S08DZ60=y
142	143	# CONFIG_HWMON is not set
143	144	CONFIG_WATCHDOG=y
144	145	CONFIG_IMX2_WDT=y
@@ -155,6 +156,7 @@ CONFIG_SOC_CAMERA=y · 10 unmodified lines
155	156	CONFIG_SOC_CAMERA_OV2640=y
156	157	CONFIG_VIDEO_MX3=y
157	158	CONFIG_FB=y
	159	+CONFIG_LCD_PLATFORM=y
158	160	CONFIG_BACKLIGHT_LCD_SUPPORT=y
159	161	CONFIG_LCD_CLASS_DEVICE=y
160	162	CONFIG_LCD_L4F00242T03=y

arch/arm/configs/mvebu_defconfig+7−3

@@ -1,6 +1,6 @@
1	1	CONFIG_EXPERIMENTAL=y
2	2	CONFIG_SYSVIPC=y
3		−CONFIG_NO_HZ=y
	3	+CONFIG_IRQ_DOMAIN_DEBUG=y
4	4	CONFIG_HIGH_RES_TIMERS=y
5	5	CONFIG_LOG_BUF_SHIFT=14
6	6	CONFIG_BLK_DEV_INITRD=y
@@ -9,10 +9,12 @@ CONFIG_SLAB=y · 2 unmodified lines
9	9	CONFIG_MODULES=y
10	10	CONFIG_MODULE_UNLOAD=y
11	11	CONFIG_ARCH_MVEBU=y
12		−CONFIG_MACH_ARMADA_370_XP=y
	12	+CONFIG_MACH_ARMADA_370=y
	13	+CONFIG_MACH_ARMADA_XP=y
	14	+# CONFIG_CACHE_L2X0 is not set
13	15	CONFIG_AEABI=y
14	16	CONFIG_HIGHMEM=y
15		−CONFIG_USE_OF=y
	17	+# CONFIG_COMPACTION is not set
16	18	CONFIG_ZBOOT_ROM_TEXT=0x0
17	19	CONFIG_ZBOOT_ROM_BSS=0x0
18	20	CONFIG_ARM_APPENDED_DTB=y
@@ -23,6 +25,8 @@ CONFIG_SERIAL_8250_CONSOLE=y · 4 unmodified lines
23	25	CONFIG_SERIAL_OF_PLATFORM=y
24	26	CONFIG_GPIOLIB=y
25	27	CONFIG_GPIO_SYSFS=y
	28	+# CONFIG_USB_SUPPORT is not set
	29	+# CONFIG_IOMMU_SUPPORT is not set
26	30	CONFIG_EXT2_FS=y
27	31	CONFIG_EXT3_FS=y
28	32	# CONFIG_EXT3_FS_XATTR is not set

arch/arm/configs/versatile_defconfig+1−0

@@ -1,3 +1,4 @@
	1	+CONFIG_ARCH_VERSATILE=y
1	2	CONFIG_EXPERIMENTAL=y
2	3	# CONFIG_LOCALVERSION_AUTO is not set
3	4	CONFIG_SYSVIPC=y

arch/arm/include/debug/8250_32.S+27−0

@@ -0,0 +1,27 @@
	1	+/*
	2	+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
	3	+ *
	4	+ * This program is free software; you can redistribute it and/or modify
	5	+ * it under the terms of the GNU General Public License version 2 as
	6	+ * published by the Free Software Foundation.
	7	+ *
	8	+ * Derived from arch/arm/mach-davinci/include/mach/debug-macro.S to use 32-bit
	9	+ * accesses to the 8250.
	10	+ */
	11	+
	12	+#include <linux/serial_reg.h>
	13	+
	14	+ .macro senduart,rd,rx
	15	+ str \rd, [\rx, #UART_TX << UART_SHIFT]
	16	+ .endm
	17	+
	18	+ .macro busyuart,rd,rx
	19	+1002: ldr \rd, [\rx, #UART_LSR << UART_SHIFT]
	20	+ and \rd, \rd, #UART_LSR_TEMT \| UART_LSR_THRE
	21	+ teq \rd, #UART_LSR_TEMT \| UART_LSR_THRE
	22	+ bne 1002b
	23	+ .endm
	24	+
	25	+ /* The UART's don't have any flow control IO's wired up. */
	26	+ .macro waituart,rd,rx
	27	+ .endm

arch/arm/include/debug/picoxcell.S+1−17

@@ -5,10 +5,7 @@ · 4 unmodified lines
5	5	* it under the terms of the GNU General Public License version 2 as
6	6	* published by the Free Software Foundation.
7	7	*
8		− * Derived from arch/arm/mach-davinci/include/mach/debug-macro.S to use 32-bit
9		− * accesses to the 8250.
10	8	*/
11		−#include <linux/serial_reg.h>
12	9
13	10	#define UART_SHIFT 2
14	11	#define PICOXCELL_UART1_BASE 0x80230000
@@ -19,17 +16,4 @@ · 4 unmodified lines
19	16	ldr \rp, =PICOXCELL_UART1_BASE
20	17	.endm
21	18
22		− .macro senduart,rd,rx
23		− str \rd, [\rx, #UART_TX << UART_SHIFT]
24		− .endm
25		−
26		− .macro busyuart,rd,rx
27		−1002: ldr \rd, [\rx, #UART_LSR << UART_SHIFT]
28		− and \rd, \rd, #UART_LSR_TEMT \| UART_LSR_THRE
29		− teq \rd, #UART_LSR_TEMT \| UART_LSR_THRE
30		− bne 1002b
31		− .endm
32		−
33		− /* The UART's don't have any flow control IO's wired up. */
34		− .macro waituart,rd,rx
35		− .endm
	19	+#include "8250_32.S"

arch/arm/include/debug/socfpga.S+5−0

@@ -7,6 +7,9 @@ · 6 unmodified lines
7	7	* published by the Free Software Foundation.
8	8	*/
9	9
	10	+#define UART_SHIFT 2
	11	+#define DEBUG_LL_UART_OFFSET 0x00002000
	12	+
10	13	.macro addruart, rp, rv, tmp
11	14	mov \rp, #DEBUG_LL_UART_OFFSET
12	15	orr \rp, \rp, #0x00c00000
@@ -14,3 +17,5 @@ · 1 unmodified line
14	17	orr \rp, \rp, #0xff000000 @ physical base
15	18	.endm
16	19
	20	+#include "8250_32.S"
	21	+

arch/arm/mach-at91/Kconfig+2−8

@@ -21,19 +21,13 @@ config SOC_AT91SAM9 · 20 unmodified lines
21	21	bool
22	22	select CPU_ARM926T
23	23	select GENERIC_CLOCKEVENTS
	24	+ select MULTI_IRQ_HANDLER
	25	+ select SPARSE_IRQ
24	26
25	27	menu "Atmel AT91 System-on-Chip"
26	28
27	29	comment "Atmel AT91 Processor"
28	30
29		−config SOC_AT91SAM9
30		− bool
31		− select AT91_SAM9_SMC
32		− select AT91_SAM9_TIME
33		− select CPU_ARM926T
34		− select MULTI_IRQ_HANDLER
35		− select SPARSE_IRQ
36		−
37	31	config SOC_AT91RM9200
38	32	bool "AT91RM9200"
39	33	select CPU_ARM920T

arch/arm/mach-at91/at91rm9200.c+1−1

@@ -187,7 +187,7 @@ static struct clk_lookup periph_clocks_lookups[] = { · 186 unmodified lines
187	187	CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
188	188	CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
189	189	CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
190		− CLKDEV_CON_DEV_ID(NULL, "i2c-at91rm9200", &twi_clk),
	190	+ CLKDEV_CON_DEV_ID(NULL, "i2c-at91rm9200.0", &twi_clk),
191	191	/* fake hclk clock */
192	192	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
193	193	CLKDEV_CON_ID("pioA", &pioA_clk),

arch/arm/mach-at91/at91rm9200_devices.c+2−2

@@ -479,7 +479,7 @@ static struct i2c_gpio_platform_data pdata = { · 478 unmodified lines
479	479
480	480	static struct platform_device at91rm9200_twi_device = {
481	481	.name = "i2c-gpio",
482		− .id = -1,
	482	+ .id = 0,
483	483	.dev.platform_data = &pdata,
484	484	};
485	485
@@ -512,7 +512,7 @@ static struct resource twi_resources[] = { · 26 unmodified lines
512	512
513	513	static struct platform_device at91rm9200_twi_device = {
514	514	.name = "i2c-at91rm9200",
515		− .id = -1,
	515	+ .id = 0,
516	516	.resource = twi_resources,
517	517	.num_resources = ARRAY_SIZE(twi_resources),
518	518	};

arch/arm/mach-at91/at91sam9260.c+2−2

@@ -211,8 +211,8 @@ static struct clk_lookup periph_clocks_lookups[] = { · 210 unmodified lines
211	211	CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
212	212	CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
213	213	CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk),
214		− CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260", &twi_clk),
215		− CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20", &twi_clk),
	214	+ CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
	215	+ CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi_clk),
216	216	/* more usart lookup table for DT entries */
217	217	CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
218	218	CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),

arch/arm/mach-at91/at91sam9260_devices.c+2−2

@@ -389,7 +389,7 @@ static struct i2c_gpio_platform_data pdata = { · 388 unmodified lines
389	389
390	390	static struct platform_device at91sam9260_twi_device = {
391	391	.name = "i2c-gpio",
392		− .id = -1,
	392	+ .id = 0,
393	393	.dev.platform_data = &pdata,
394	394	};
395	395
@@ -421,7 +421,7 @@ static struct resource twi_resources[] = { · 25 unmodified lines
421	421	};
422	422
423	423	static struct platform_device at91sam9260_twi_device = {
424		− .id = -1,
	424	+ .id = 0,
425	425	.resource = twi_resources,
426	426	.num_resources = ARRAY_SIZE(twi_resources),
427	427	};

arch/arm/mach-at91/at91sam9261.c+2−2

@@ -178,8 +178,8 @@ static struct clk_lookup periph_clocks_lookups[] = { · 177 unmodified lines
178	178	CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
179	179	CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
180	180	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
181		− CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9261", &twi_clk),
182		− CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10", &twi_clk),
	181	+ CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9261.0", &twi_clk),
	182	+ CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi_clk),
183	183	CLKDEV_CON_ID("pioA", &pioA_clk),
184	184	CLKDEV_CON_ID("pioB", &pioB_clk),
185	185	CLKDEV_CON_ID("pioC", &pioC_clk),

arch/arm/mach-at91/at91sam9261_devices.c+2−2

@@ -285,7 +285,7 @@ static struct i2c_gpio_platform_data pdata = { · 284 unmodified lines
285	285
286	286	static struct platform_device at91sam9261_twi_device = {
287	287	.name = "i2c-gpio",
288		− .id = -1,
	288	+ .id = 0,
289	289	.dev.platform_data = &pdata,
290	290	};
291	291
@@ -317,7 +317,7 @@ static struct resource twi_resources[] = { · 25 unmodified lines
317	317	};
318	318
319	319	static struct platform_device at91sam9261_twi_device = {
320		− .id = -1,
	320	+ .id = 0,
321	321	.resource = twi_resources,
322	322	.num_resources = ARRAY_SIZE(twi_resources),
323	323	};

arch/arm/mach-at91/at91sam9263.c+1−1

@@ -193,7 +193,7 @@ static struct clk_lookup periph_clocks_lookups[] = { · 192 unmodified lines
193	193	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
194	194	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
195	195	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
196		− CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260", &twi_clk),
	196	+ CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
197	197	/* fake hclk clock */
198	198	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
199	199	CLKDEV_CON_ID("pioA", &pioA_clk),

arch/arm/mach-at91/at91sam9263_devices.c+2−2

@@ -567,7 +567,7 @@ static struct i2c_gpio_platform_data pdata = { · 566 unmodified lines
567	567
568	568	static struct platform_device at91sam9263_twi_device = {
569	569	.name = "i2c-gpio",
570		− .id = -1,
	570	+ .id = 0,
571	571	.dev.platform_data = &pdata,
572	572	};
573	573
@@ -600,7 +600,7 @@ static struct resource twi_resources[] = { · 26 unmodified lines
600	600
601	601	static struct platform_device at91sam9263_twi_device = {
602	602	.name = "i2c-at91sam9260",
603		− .id = -1,
	603	+ .id = 0,
604	604	.resource = twi_resources,
605	605	.num_resources = ARRAY_SIZE(twi_resources),
606	606	};

arch/arm/mach-at91/at91sam9rl_devices.c+2−2

@@ -314,7 +314,7 @@ static struct i2c_gpio_platform_data pdata = { · 313 unmodified lines
314	314
315	315	static struct platform_device at91sam9rl_twi_device = {
316	316	.name = "i2c-gpio",
317		− .id = -1,
	317	+ .id = 0,
318	318	.dev.platform_data = &pdata,
319	319	};
320	320
@@ -347,7 +347,7 @@ static struct resource twi_resources[] = { · 26 unmodified lines
347	347
348	348	static struct platform_device at91sam9rl_twi_device = {
349	349	.name = "i2c-at91sam9g20",
350		− .id = -1,
	350	+ .id = 0,
351	351	.resource = twi_resources,
352	352	.num_resources = ARRAY_SIZE(twi_resources),
353	353	};

arch/arm/mach-at91/at91x40.c+1−1

@@ -88,6 +88,6 @@ void __init at91x40_init_interrupts(unsigned int priority[NR_AIC_IRQS]) · 87 unmodified lines
88	88	if (!priority)
89	89	priority = at91x40_default_irq_priority;
90	90
91		− at91_aic_init(priority);
	91	+ at91_aic_init(priority, at91_extern_irq);
92	92	}
93	93

arch/arm/mach-at91/board-neocore926.c+1−1

@@ -129,7 +129,7 @@ static struct spi_board_info neocore926_spi_devices[] = { · 128 unmodified lines
129	129	.max_speed_hz = 125000 * 16,
130	130	.bus_num = 0,
131	131	.platform_data = &ads_info,
132		− .irq = AT91SAM9263_ID_IRQ1,
	132	+ .irq = NR_IRQS_LEGACY + AT91SAM9263_ID_IRQ1,
133	133	},
134	134	#endif
135	135	};

arch/arm/mach-at91/board-sam9261ek.c+1−1

@@ -309,7 +309,7 @@ static struct spi_board_info ek_spi_devices[] = { · 308 unmodified lines
309	309	.max_speed_hz = 125000 * 26, /* (max sample rate @ 3V) * (cmd + data + overhead) */
310	310	.bus_num = 0,
311	311	.platform_data = &ads_info,
312		− .irq = AT91SAM9261_ID_IRQ0,
	312	+ .irq = NR_IRQS_LEGACY + AT91SAM9261_ID_IRQ0,
313	313	.controller_data = (void ) AT91_PIN_PA28, / CS pin */
314	314	},
315	315	#endif

arch/arm/mach-at91/board-sam9263ek.c+1−1

@@ -132,7 +132,7 @@ static struct spi_board_info ek_spi_devices[] = { · 131 unmodified lines
132	132	.max_speed_hz = 125000 * 26, /* (max sample rate @ 3V) * (cmd + data + overhead) */
133	133	.bus_num = 0,
134	134	.platform_data = &ads_info,
135		− .irq = AT91SAM9263_ID_IRQ1,
	135	+ .irq = NR_IRQS_LEGACY + AT91SAM9263_ID_IRQ1,
136	136	},
137	137	#endif
138	138	};

arch/arm/mach-at91/generic.h+2−1

@@ -26,7 +26,8 @@ extern void __init at91_dt_initialize(void); · 25 unmodified lines
26	26	extern void __init at91_init_irq_default(void);
27	27	extern void __init at91_init_interrupts(unsigned int priority[]);
28	28	extern void __init at91x40_init_interrupts(unsigned int priority[]);
29		−extern void __init at91_aic_init(unsigned int priority[]);
	29	+extern void __init at91_aic_init(unsigned int priority[],
	30	+ unsigned int ext_irq_mask);
30	31	extern int __init at91_aic_of_init(struct device_node *node,
31	32	struct device_node *parent);
32	33	extern int __init at91_aic5_of_init(struct device_node *node,

arch/arm/mach-at91/irq.c+7−2

@@ -502,14 +502,19 @@ int __init at91_aic5_of_init(struct device_node *node, · 501 unmodified lines
502	502	/*
503	503	* Initialize the AIC interrupt controller.
504	504	*/
505		−void __init at91_aic_init(unsigned int *priority)
	505	+void __init at91_aic_init(unsigned int *priority, unsigned int ext_irq_mask)
506	506	{
507	507	unsigned int i;
508	508	int irq_base;
509	509
510		− if (at91_aic_pm_init())
	510	+ at91_extern_irq = kzalloc(BITS_TO_LONGS(n_irqs)
	511	+ * sizeof(*at91_extern_irq), GFP_KERNEL);
	512	+
	513	+ if (at91_aic_pm_init() \|\| at91_extern_irq == NULL)
511	514	panic("Unable to allocate bit maps\n");
512	515
	516	+ *at91_extern_irq = ext_irq_mask;
	517	+
513	518	at91_aic_base = ioremap(AT91_AIC, 512);
514	519	if (!at91_aic_base)
515	520	panic("Unable to ioremap AIC registers\n");

arch/arm/mach-at91/setup.c+2−2

@@ -47,7 +47,7 @@ void __init at91_init_irq_default(void) · 46 unmodified lines
47	47	void __init at91_init_interrupts(unsigned int *priority)
48	48	{
49	49	/* Initialize the AIC interrupt controller */
50		− at91_aic_init(priority);
	50	+ at91_aic_init(priority, at91_extern_irq);
51	51
52	52	/* Enable GPIO interrupts */
53	53	at91_gpio_irq_setup();
@@ -151,7 +151,7 @@ static void __init soc_detect(u32 dbgu_base) · 97 unmodified lines
151	151	}
152	152
153	153	/* at91sam9g10 */
154		− if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
	154	+ if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
155	155	at91_soc_initdata.type = AT91_SOC_SAM9G10;
156	156	at91_boot_soc = at91sam9261_soc;
157	157	}

arch/arm/mach-exynos/common.c+5−0

@@ -47,6 +47,7 @@ · 46 unmodified lines
47	47	#include <plat/fimc-core.h>
48	48	#include <plat/iic-core.h>
49	49	#include <plat/tv-core.h>
	50	+#include <plat/spi-core.h>
50	51	#include <plat/regs-serial.h>
51	52
52	53	#include "common.h"
@@ -346,6 +347,8 @@ static void __init exynos4_map_io(void) · 293 unmodified lines
346	347
347	348	s5p_fb_setname(0, "exynos4-fb");
348	349	s5p_hdmi_setname("exynos4-hdmi");
	350	+
	351	+ s3c64xx_spi_setname("exynos4210-spi");
349	352	}
350	353
351	354	static void __init exynos5_map_io(void)
@@ -366,6 +369,8 @@ static void __init exynos5_map_io(void) · 14 unmodified lines
366	369	s3c_i2c0_setname("s3c2440-i2c");
367	370	s3c_i2c1_setname("s3c2440-i2c");
368	371	s3c_i2c2_setname("s3c2440-i2c");
	372	+
	373	+ s3c64xx_spi_setname("exynos4210-spi");
369	374	}
370	375
371	376	static void __init exynos4_init_clocks(int xtal)

arch/arm/mach-exynos/mach-exynos4-dt.c+1−0

@@ -99,6 +99,7 @@ static char const *exynos4_dt_compat[] __initdata = { · 98 unmodified lines
99	99
100	100	DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
101	101	/* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
	102	+ .smp = smp_ops(exynos_smp_ops),
102	103	.init_irq = exynos4_init_irq,
103	104	.map_io = exynos4_dt_map_io,
104	105	.handle_irq = gic_handle_irq,

arch/arm/mach-imx/clk-busy.c+1−1

@@ -108,7 +108,7 @@ struct clk imx_clk_busy_divider(const char name, const char *parent_name, · 107 unmodified lines
108	108	busy->div.hw.init = &init;
109	109
110	110	clk = clk_register(NULL, &busy->div.hw);
111		− if (!clk)
	111	+ if (IS_ERR(clk))
112	112	kfree(busy);
113	113
114	114	return clk;

arch/arm/mach-imx/clk-imx25.c+2−2

@@ -127,8 +127,8 @@ int __init mx25_clocks_init(void) · 126 unmodified lines
127	127	clk[esdhc2_ipg_per] = imx_clk_gate("esdhc2_ipg_per", "per4", ccm(CCM_CGCR0), 4);
128	128	clk[gpt_ipg_per] = imx_clk_gate("gpt_ipg_per", "per5", ccm(CCM_CGCR0), 5);
129	129	clk[i2c_ipg_per] = imx_clk_gate("i2c_ipg_per", "per6", ccm(CCM_CGCR0), 6);
130		− clk[lcdc_ipg_per] = imx_clk_gate("lcdc_ipg_per", "per8", ccm(CCM_CGCR0), 7);
131		− clk[nfc_ipg_per] = imx_clk_gate("nfc_ipg_per", "ipg_per", ccm(CCM_CGCR0), 8);
	130	+ clk[lcdc_ipg_per] = imx_clk_gate("lcdc_ipg_per", "per7", ccm(CCM_CGCR0), 7);
	131	+ clk[nfc_ipg_per] = imx_clk_gate("nfc_ipg_per", "per8", ccm(CCM_CGCR0), 8);
132	132	clk[ssi1_ipg_per] = imx_clk_gate("ssi1_ipg_per", "per13", ccm(CCM_CGCR0), 13);
133	133	clk[ssi2_ipg_per] = imx_clk_gate("ssi2_ipg_per", "per14", ccm(CCM_CGCR0), 14);
134	134	clk[uart_ipg_per] = imx_clk_gate("uart_ipg_per", "per15", ccm(CCM_CGCR0), 15);

arch/arm/mach-imx/clk-imx27.c+2−2

@@ -109,7 +109,7 @@ int __init mx27_clocks_init(unsigned long fref) · 108 unmodified lines
109	109	clk[per3_div] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6);
110	110	clk[per4_div] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);
111	111	clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));
112		− clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 3);
	112	+ clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6);
113	113	clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 28, 3);
114	114	clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
115	115	clk[clko_sel] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
@@ -121,7 +121,7 @@ int __init mx27_clocks_init(unsigned long fref) · 5 unmodified lines
121	121	clk[ssi1_sel] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
122	122	clk[ssi2_sel] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
123	123	clk[ssi1_div] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
124		− clk[ssi2_div] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 3);
	124	+ clk[ssi2_div] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);
125	125	clk[clko_en] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0);
126	126	clk[ssi2_ipg_gate] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0);
127	127	clk[ssi1_ipg_gate] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1);

arch/arm/mach-imx/mm-imx3.c+2−3

@@ -108,9 +108,8 @@ void __init imx3_init_l2x0(void) · 107 unmodified lines
108	108	}
109	109
110	110	l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
111		− if (IS_ERR(l2x0_base)) {
112		− printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
113		− PTR_ERR(l2x0_base));
	111	+ if (!l2x0_base) {
	112	+ printk(KERN_ERR "remapping L2 cache area failed\n");
114	113	return;
115	114	}
116	115

arch/arm/mach-omap2/Kconfig+0−1

@@ -11,7 +11,6 @@ config ARCH_OMAP2PLUS_TYPICAL · 10 unmodified lines
11	11	select I2C_OMAP
12	12	select MENELAUS if ARCH_OMAP2
13	13	select NEON if ARCH_OMAP3 \|\| ARCH_OMAP4 \|\| SOC_OMAP5
14		− select PINCTRL
15	14	select PM_RUNTIME
16	15	select REGULATOR
17	16	select SERIAL_OMAP

arch/arm/mach-omap2/board-omap3beagle.c+13−9

@@ -24,6 +24,7 @@ · 23 unmodified lines
24	24	#include <linux/input.h>
25	25	#include <linux/gpio_keys.h>
26	26	#include <linux/opp.h>
	27	+#include <linux/cpu.h>
27	28
28	29	#include <linux/mtd/mtd.h>
29	30	#include <linux/mtd/partitions.h>
@@ -444,27 +445,31 @@ static struct omap_board_mux board_mux[] __initdata = { · 414 unmodified lines
444	445	};
445	446	#endif
446	447
447		−static void __init beagle_opp_init(void)
	448	+static int __init beagle_opp_init(void)
448	449	{
449	450	int r = 0;
450	451
451		− /* Initialize the omap3 opp table */
452		− if (omap3_opp_init()) {
	452	+ if (!machine_is_omap3_beagle())
	453	+ return 0;
	454	+
	455	+ /* Initialize the omap3 opp table if not already created. */
	456	+ r = omap3_opp_init();
	457	+ if (IS_ERR_VALUE(r) && (r != -EEXIST)) {
453	458	pr_err("%s: opp default init failed\n", __func__);
454		− return;
	459	+ return r;
455	460	}
456	461
457	462	/* Custom OPP enabled for all xM versions */
458	463	if (cpu_is_omap3630()) {
459	464	struct device mpu_dev, iva_dev;
460	465
461		− mpu_dev = omap_device_get_by_hwmod_name("mpu");
	466	+ mpu_dev = get_cpu_device(0);
462	467	iva_dev = omap_device_get_by_hwmod_name("iva");
463	468
464	469	if (IS_ERR(mpu_dev) \|\| IS_ERR(iva_dev)) {
465	470	pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n",
466	471	__func__, mpu_dev, iva_dev);
467		− return;
	472	+ return -ENODEV;
468	473	}
469	474	/* Enable MPU 1GHz and lower opps */
470	475	r = opp_enable(mpu_dev, 800000000);
@@ -484,8 +489,9 @@ static void __init beagle_opp_init(void) · 13 unmodified lines
484	489	opp_disable(iva_dev, 660000000);
485	490	}
486	491	}
487		− return;
	492	+ return 0;
488	493	}
	494	+device_initcall(beagle_opp_init);
489	495
490	496	static void __init omap3_beagle_init(void)
491	497	{
@@ -522,8 +528,6 @@ static void __init omap3_beagle_init(void) · 30 unmodified lines
522	528	/* Ensure SDRC pins are mux'd for self-refresh */
523	529	omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
524	530	omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
525		−
526		− beagle_opp_init();
527	531	}
528	532
529	533	MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")

arch/arm/mach-omap2/clock33xx_data.c+2−0

@@ -1073,6 +1073,8 @@ static struct omap_clk am33xx_clks[] = { · 1072 unmodified lines
1073	1073	CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck, CK_AM33XX),
1074	1074	CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck, CK_AM33XX),
1075	1075	CLK(NULL, "clkout2_ck", &clkout2_ck, CK_AM33XX),
	1076	+ CLK(NULL, "timer_32k_ck", &clkdiv32k_ick, CK_AM33XX),
	1077	+ CLK(NULL, "timer_sys_ck", &sys_clkin_ck, CK_AM33XX),
1076	1078	};
1077	1079
1078	1080	int __init am33xx_clk_init(void)

arch/arm/mach-omap2/mux34xx.c+4−4

@@ -614,16 +614,16 @@ static struct omap_mux __initdata omap3_muxmodes[] = { · 613 unmodified lines
614	614	"sys_off_mode", NULL, NULL, NULL,
615	615	"gpio_9", NULL, NULL, "safe_mode"),
616	616	_OMAP3_MUXENTRY(UART1_CTS, 150,
617		− "uart1_cts", NULL, NULL, NULL,
	617	+ "uart1_cts", "ssi1_rdy_tx", NULL, NULL,
618	618	"gpio_150", "hsusb3_tll_clk", NULL, "safe_mode"),
619	619	_OMAP3_MUXENTRY(UART1_RTS, 149,
620		− "uart1_rts", NULL, NULL, NULL,
	620	+ "uart1_rts", "ssi1_flag_tx", NULL, NULL,
621	621	"gpio_149", NULL, NULL, "safe_mode"),
622	622	_OMAP3_MUXENTRY(UART1_RX, 151,
623		− "uart1_rx", NULL, "mcbsp1_clkr", "mcspi4_clk",
	623	+ "uart1_rx", "ss1_wake_tx", "mcbsp1_clkr", "mcspi4_clk",
624	624	"gpio_151", NULL, NULL, "safe_mode"),
625	625	_OMAP3_MUXENTRY(UART1_TX, 148,
626		− "uart1_tx", NULL, NULL, NULL,
	626	+ "uart1_tx", "ssi1_dat_tx", NULL, NULL,
627	627	"gpio_148", NULL, NULL, "safe_mode"),
628	628	_OMAP3_MUXENTRY(UART2_CTS, 144,
629	629	"uart2_cts", "mcbsp3_dx", "gpt9_pwm_evt", NULL,

arch/arm/mach-omap2/pm.h+1−0

@@ -91,6 +91,7 @@ extern void omap3_save_scratchpad_contents(void); · 90 unmodified lines
91	91
92	92	#define PM_RTA_ERRATUM_i608 (1 << 0)
93	93	#define PM_SDRC_WAKEUP_ERRATUM_i583 (1 << 1)
	94	+#define PM_PER_MEMORIES_ERRATUM_i582 (1 << 2)
94	95
95	96	#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
96	97	extern u16 pm34xx_errata;

arch/arm/mach-omap2/pm34xx.c+28−2

@@ -652,14 +652,17 @@ static void __init pm_errata_configure(void) · 651 unmodified lines
652	652	/* Enable the l2 cache toggling in sleep logic */
653	653	enable_omap3630_toggle_l2_on_restore();
654	654	if (omap_rev() < OMAP3630_REV_ES1_2)
655		− pm34xx_errata \|= PM_SDRC_WAKEUP_ERRATUM_i583;
	655	+ pm34xx_errata \|= (PM_SDRC_WAKEUP_ERRATUM_i583 \|
	656	+ PM_PER_MEMORIES_ERRATUM_i582);
	657	+ } else if (cpu_is_omap34xx()) {
	658	+ pm34xx_errata \|= PM_PER_MEMORIES_ERRATUM_i582;
656	659	}
657	660	}
658	661
659	662	int __init omap3_pm_init(void)
660	663	{
661	664	struct power_state pwrst, tmp;
662		− struct clockdomain neon_clkdm, mpu_clkdm;
	665	+ struct clockdomain neon_clkdm, mpu_clkdm, per_clkdm, wkup_clkdm;
663	666	int ret;
664	667
665	668	if (!omap3_has_io_chain_ctrl())
@@ -711,6 +714,8 @@ int __init omap3_pm_init(void) · 45 unmodified lines
711	714
712	715	neon_clkdm = clkdm_lookup("neon_clkdm");
713	716	mpu_clkdm = clkdm_lookup("mpu_clkdm");
	717	+ per_clkdm = clkdm_lookup("per_clkdm");
	718	+ wkup_clkdm = clkdm_lookup("wkup_clkdm");
714	719
715	720	#ifdef CONFIG_SUSPEND
716	721	omap_pm_suspend = omap3_pm_suspend;
@@ -727,6 +732,27 @@ int __init omap3_pm_init(void) · 10 unmodified lines
727	732	if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
728	733	omap3630_ctrl_disable_rta();
729	734
	735	+ /*
	736	+ * The UART3/4 FIFO and the sidetone memory in McBSP2/3 are
	737	+ * not correctly reset when the PER powerdomain comes back
	738	+ * from OFF or OSWR when the CORE powerdomain is kept active.
	739	+ * See OMAP36xx Erratum i582 "PER Domain reset issue after
	740	+ * Domain-OFF/OSWR Wakeup". This wakeup dependency is not a
	741	+ * complete workaround. The kernel must also prevent the PER
	742	+ * powerdomain from going to OSWR/OFF while the CORE
	743	+ * powerdomain is not going to OSWR/OFF. And if PER last
	744	+ * power state was off while CORE last power state was ON, the
	745	+ * UART3/4 and McBSP2/3 SIDETONE devices need to run a
	746	+ * self-test using their loopback tests; if that fails, those
	747	+ * devices are unusable until the PER/CORE can complete a transition
	748	+ * from ON to OSWR/OFF and then back to ON.
	749	+ *
	750	+ * XXX Technically this workaround is only needed if off-mode
	751	+ * or OSWR is enabled.
	752	+ */
	753	+ if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582))
	754	+ clkdm_add_wkdep(per_clkdm, wkup_clkdm);
	755	+
730	756	clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
731	757	if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
732	758	omap3_secure_ram_storage =

arch/arm/mach-omap2/serial.c+5−0

@@ -329,6 +329,11 @@ void __init omap_serial_init_port(struct omap_board_data *bdata, · 328 unmodified lines
329	329
330	330	oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
331	331
	332	+ if (console_uart_id == bdata->id) {
	333	+ omap_device_enable(pdev);
	334	+ pm_runtime_set_active(&pdev->dev);
	335	+ }
	336	+
332	337	oh->dev_attr = uart;
333	338
334	339	if (((cpu_is_omap34xx() \|\| cpu_is_omap44xx()) && bdata->pads)

arch/arm/mach-s3c24xx/s3c2416.c+2−0

@@ -61,6 +61,7 @@ · 60 unmodified lines
61	61	#include <plat/nand-core.h>
62	62	#include <plat/adc-core.h>
63	63	#include <plat/rtc-core.h>
	64	+#include <plat/spi-core.h>
64	65
65	66	static struct map_desc s3c2416_iodesc[] __initdata = {
66	67	IODESC_ENT(WATCHDOG),
@@ -132,6 +133,7 @@ void __init s3c2416_map_io(void) · 65 unmodified lines
132	133	/* initialize device information early */
133	134	s3c2416_default_sdhci0();
134	135	s3c2416_default_sdhci1();
	136	+ s3c64xx_spi_setname("s3c2443-spi");
135	137
136	138	iotable_init(s3c2416_iodesc, ARRAY_SIZE(s3c2416_iodesc));
137	139	}

arch/arm/mach-s3c24xx/s3c2443.c+4−0

@@ -43,6 +43,7 @@ · 42 unmodified lines
43	43	#include <plat/nand-core.h>
44	44	#include <plat/adc-core.h>
45	45	#include <plat/rtc-core.h>
	46	+#include <plat/spi-core.h>
46	47
47	48	static struct map_desc s3c2443_iodesc[] __initdata = {
48	49	IODESC_ENT(WATCHDOG),
@@ -100,6 +101,9 @@ void __init s3c2443_map_io(void) · 51 unmodified lines
100	101	s3c24xx_gpiocfg_default.set_pull = s3c2443_gpio_setpull;
101	102	s3c24xx_gpiocfg_default.get_pull = s3c2443_gpio_getpull;
102	103
	104	+ /* initialize device information early */
	105	+ s3c64xx_spi_setname("s3c2443-spi");
	106	+
103	107	iotable_init(s3c2443_iodesc, ARRAY_SIZE(s3c2443_iodesc));
104	108	}
105	109

arch/arm/mach-s5p64x0/common.c+3−0

@@ -44,6 +44,7 @@ · 43 unmodified lines
44	44	#include <plat/sdhci.h>
45	45	#include <plat/adc-core.h>
46	46	#include <plat/fb-core.h>
	47	+#include <plat/spi-core.h>
47	48	#include <plat/gpio-cfg.h>
48	49	#include <plat/regs-irqtype.h>
49	50	#include <plat/regs-serial.h>
@@ -179,6 +180,7 @@ void __init s5p6440_map_io(void) · 129 unmodified lines
179	180	/* initialize any device information early */
180	181	s3c_adc_setname("s3c64xx-adc");
181	182	s3c_fb_setname("s5p64x0-fb");
	183	+ s3c64xx_spi_setname("s5p64x0-spi");
182	184
183	185	s5p64x0_default_sdhci0();
184	186	s5p64x0_default_sdhci1();
@@ -193,6 +195,7 @@ void __init s5p6450_map_io(void) · 8 unmodified lines
193	195	/* initialize any device information early */
194	196	s3c_adc_setname("s3c64xx-adc");
195	197	s3c_fb_setname("s5p64x0-fb");
	198	+ s3c64xx_spi_setname("s5p64x0-spi");
196	199
197	200	s5p64x0_default_sdhci0();
198	201	s5p64x0_default_sdhci1();

arch/arm/mach-s5pc100/common.c+3−0

@@ -45,6 +45,7 @@ · 44 unmodified lines
45	45	#include <plat/fb-core.h>
46	46	#include <plat/iic-core.h>
47	47	#include <plat/onenand-core.h>
	48	+#include <plat/spi-core.h>
48	49	#include <plat/regs-serial.h>
49	50	#include <plat/watchdog-reset.h>
50	51
@@ -165,6 +166,8 @@ void __init s5pc100_map_io(void) · 114 unmodified lines
165	166	s3c_onenand_setname("s5pc100-onenand");
166	167	s3c_fb_setname("s5pc100-fb");
167	168	s3c_cfcon_setname("s5pc100-pata");
	169	+
	170	+ s3c64xx_spi_setname("s5pc100-spi");
168	171	}
169	172
170	173	void __init s5pc100_init_clocks(int xtal)

arch/arm/mach-s5pv210/common.c+3−0

@@ -43,6 +43,7 @@ · 42 unmodified lines
43	43	#include <plat/iic-core.h>
44	44	#include <plat/keypad-core.h>
45	45	#include <plat/tv-core.h>
	46	+#include <plat/spi-core.h>
46	47	#include <plat/regs-serial.h>
47	48
48	49	#include "common.h"
@@ -196,6 +197,8 @@ void __init s5pv210_map_io(void) · 147 unmodified lines
196	197
197	198	/* setup TV devices */
198	199	s5p_hdmi_setname("s5pv210-hdmi");
	200	+
	201	+ s3c64xx_spi_setname("s5pv210-spi");
199	202	}
200	203
201	204	void __init s5pv210_init_clocks(int xtal)

arch/arm/mach-shmobile/setup-r8a7779.c+1−1

@@ -247,7 +247,7 @@ void __init r8a7779_add_standard_devices(void) · 246 unmodified lines
247	247	{
248	248	#ifdef CONFIG_CACHE_L2X0
249	249	/* Early BRESP enable, Shared attribute override enable, 64K16way /
250		− l2x0_init((void __iomem __force *)(0xf0100000), 0x40470000, 0x82000fff);
	250	+ l2x0_init(IOMEM(0xf0100000), 0x40470000, 0x82000fff);
251	251	#endif
252	252	r8a7779_pm_init();
253	253

arch/arm/mach-spear13xx/include/mach/spear1310_misc_regs.h+0−0

Empty file deleted.

arch/arm/mach-spear13xx/include/mach/spear1340_misc_regs.h+0−0

Empty file deleted.

arch/arm/mach-ux500/cpu.c+1−0

@@ -16,6 +16,7 @@ · 15 unmodified lines
16	16	#include <linux/stat.h>
17	17	#include <linux/of.h>
18	18	#include <linux/of_irq.h>
	19	+#include <linux/irq.h>
19	20	#include <linux/platform_data/clk-ux500.h>
20	21
21	22	#include <asm/hardware/gic.h>

arch/arm/plat-mxc/devices/platform-mxc-mmc.c+1−1

@@ -55,7 +55,7 @@ struct platform_device *__init imx_add_mxc_mmc( · 54 unmodified lines
55	55	struct resource res[] = {
56	56	{
57	57	.start = data->iobase,
58		− .end = data->iobase + SZ_4K - 1,
	58	+ .end = data->iobase + data->iosize - 1,
59	59	.flags = IORESOURCE_MEM,
60	60	}, {
61	61	.start = data->irq,

arch/arm/plat-omap/Kconfig+1−0

@@ -26,6 +26,7 @@ config ARCH_OMAP2PLUS · 25 unmodified lines
26	26	select CLKDEV_LOOKUP
27	27	select GENERIC_IRQ_CHIP
28	28	select OMAP_DM_TIMER
	29	+ select PINCTRL
29	30	select PROC_DEVICETREE if PROC_FS
30	31	select SPARSE_IRQ
31	32	select USE_OF

arch/arm/plat-samsung/include/plat/spi-core.h+30−0

@@ -0,0 +1,30 @@
	1	+/*
	2	+ * Copyright (C) 2012 Heiko Stuebner <heiko@sntech.de>
	3	+ *
	4	+ * This program is free software; you can redistribute it and/or modify
	5	+ * it under the terms of the GNU General Public License version 2 as
	6	+ * published by the Free Software Foundation.
	7	+ */
	8	+
	9	+#ifndef __PLAT_S3C_SPI_CORE_H
	10	+#define __PLAT_S3C_SPI_CORE_H
	11	+
	12	+/* These functions are only for use with the core support code, such as
	13	+ * the cpu specific initialisation code
	14	+ */
	15	+
	16	+/* re-define device name depending on support. */
	17	+static inline void s3c64xx_spi_setname(char *name)
	18	+{
	19	+#ifdef CONFIG_S3C64XX_DEV_SPI0
	20	+ s3c64xx_device_spi0.name = name;
	21	+#endif
	22	+#ifdef CONFIG_S3C64XX_DEV_SPI1
	23	+ s3c64xx_device_spi1.name = name;
	24	+#endif
	25	+#ifdef CONFIG_S3C64XX_DEV_SPI2
	26	+ s3c64xx_device_spi2.name = name;
	27	+#endif
	28	+}
	29	+
	30	+#endif /* __PLAT_S3C_SPI_CORE_H */