History

Merge branch 'etnaviv/next' of https://git.pengutronix.de/git/lst/linux into drm-next

- remove redundant NULL checks by various people - fix sparse checker warnings from Marc - expose more GPU ID values to userspace from Christian - add HWDB entry for GPU found on i.MX8MP from Sascha - rework of the linear window calculation to better deal with systems with large regions of reserved RAM

Dave Airlie committed 5 years ago

Commit 0666cba2 parents c707b73 989c9da6 files · +82 −43Browse files

Unified · Split

6 files
  1. drivers/gpu/drm/etnaviv/etnaviv_dump.c +4 −4
  2. drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c +1 −2
  3. drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c +4 −8
  4. drivers/gpu/drm/etnaviv/etnaviv_gpu.c +39 −29
  5. drivers/gpu/drm/etnaviv/etnaviv_hwdb.c +31 −0
  6. include/uapi/drm/etnaviv_drm.h +3 −0
drivers/gpu/drm/etnaviv/etnaviv_dump.c+4−4
@@ -75,7 +75,7 @@ static void etnaviv_core_dump_header(struct core_dump_iterator *iter, · 74 unmodified lines
7575 hdr->file_size = cpu_to_le32(data_end - iter->data);
7676
7777 iter->hdr++;
78− iter->data += hdr->file_size;
78+ iter->data += le32_to_cpu(hdr->file_size);
7979 }
8080
8181 static void etnaviv_core_dump_registers(struct core_dump_iterator *iter,
@@ -85,8 +85,8 @@ static void etnaviv_core_dump_registers(struct core_dump_iterator *iter, · 3 unmodified lines
8585 unsigned int i;
8686
8787 for (i = 0; i < ARRAY_SIZE(etnaviv_dump_registers); i++, reg++) {
88− reg->reg = etnaviv_dump_registers[i];
89− reg->value = gpu_read(gpu, etnaviv_dump_registers[i]);
88+ reg->reg = cpu_to_le32(etnaviv_dump_registers[i]);
89+ reg->value = cpu_to_le32(gpu_read(gpu, etnaviv_dump_registers[i]));
9090 }
9191
9292 etnaviv_core_dump_header(iter, ETDUMP_BUF_REG, reg);
@@ -207,7 +207,7 @@ void etnaviv_core_dump(struct etnaviv_gem_submit *submit) · 114 unmodified lines
207207 if (!IS_ERR(pages)) {
208208 int j;
209209
210− iter.hdr->data[0] = bomap - bomap_start;
210+ iter.hdr->data[0] = cpu_to_le32((bomap - bomap_start));
211211
212212 for (j = 0; j < obj->base.size >> PAGE_SHIFT; j++)
213213 *bomap++ = cpu_to_le64(page_to_phys(*pages++));
drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c+1−2
@@ -80,8 +80,7 @@ static void etnaviv_gem_prime_release(struct etnaviv_gem_object *etnaviv_obj) · 79 unmodified lines
8080 /* Don't drop the pages for imported dmabuf, as they are not
8181 * ours, just free the array we allocated:
8282 */
83− if (etnaviv_obj->pages)
84− kvfree(etnaviv_obj->pages);
83+ kvfree(etnaviv_obj->pages);
8584
8685 drm_prime_gem_destroy(&etnaviv_obj->base, etnaviv_obj->sgt);
8786 }
drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c+4−8
@@ -612,14 +612,10 @@ err_submit_ww_acquire: · 611 unmodified lines
612612 err_submit_cmds:
613613 if (ret && (out_fence_fd >= 0))
614614 put_unused_fd(out_fence_fd);
615− if (stream)
616− kvfree(stream);
617− if (bos)
618− kvfree(bos);
619− if (relocs)
620− kvfree(relocs);
621− if (pmrs)
622− kvfree(pmrs);
615+ kvfree(stream);
616+ kvfree(bos);
617+ kvfree(relocs);
618+ kvfree(pmrs);
623619
624620 return ret;
625621 }
drivers/gpu/drm/etnaviv/etnaviv_gpu.c+39−29
@@ -27,10 +27,6 @@ · 26 unmodified lines
2727 #include "state_hi.xml.h"
2828 #include "cmdstream.xml.h"
2929
30−#ifndef PHYS_OFFSET
31−#define PHYS_OFFSET 0
32−#endif
33−
3430 static const struct platform_device_id gpu_ids[] = {
3531 { .name = "etnaviv-gpu,2d" },
3632 { },
@@ -156,6 +152,18 @@ int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) · 119 unmodified lines
156152 *value = ~0ULL;
157153 break;
158154
155+ case ETNAVIV_PARAM_GPU_PRODUCT_ID:
156+ *value = gpu->identity.product_id;
157+ break;
158+
159+ case ETNAVIV_PARAM_GPU_CUSTOMER_ID:
160+ *value = gpu->identity.customer_id;
161+ break;
162+
163+ case ETNAVIV_PARAM_GPU_ECO_ID:
164+ *value = gpu->identity.eco_id;
165+ break;
166+
159167 default:
160168 DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
161169 return -EINVAL;
@@ -724,6 +732,7 @@ static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu) · 562 unmodified lines
724732 int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
725733 {
726734 struct etnaviv_drm_private *priv = gpu->drm->dev_private;
735+ dma_addr_t cmdbuf_paddr;
727736 int ret, i;
728737
729738 ret = pm_runtime_get_sync(gpu->dev);
@@ -766,28 +775,6 @@ int etnaviv_gpu_init(struct etnaviv_gpu *gpu) · 36 unmodified lines
766775 if (ret)
767776 goto fail;
768777
769− /*
770− * Set the GPU linear window to be at the end of the DMA window, where
771− * the CMA area is likely to reside. This ensures that we are able to
772− * map the command buffers while having the linear window overlap as
773− * much RAM as possible, so we can optimize mappings for other buffers.
774− *
775− * For 3D cores only do this if MC2.0 is present, as with MC1.0 it leads
776− * to different views of the memory on the individual engines.
777− */
778− if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
779− (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {
780− u32 dma_mask = (u32)dma_get_required_mask(gpu->dev);
781− if (dma_mask < PHYS_OFFSET + SZ_2G)
782− priv->mmu_global->memory_base = PHYS_OFFSET;
783− else
784− priv->mmu_global->memory_base = dma_mask - SZ_2G + 1;
785− } else if (PHYS_OFFSET >= SZ_2G) {
786− dev_info(gpu->dev, "Need to move linear window on MC1.0, disabling TS\n");
787− priv->mmu_global->memory_base = PHYS_OFFSET;
788− gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
789− }
790−
791778 /*
792779 * If the GPU is part of a system with DMA addressing limitations,
793780 * request pages for our SHM backend buffers from the DMA32 zone to
@@ -804,6 +791,31 @@ int etnaviv_gpu_init(struct etnaviv_gpu *gpu) · 10 unmodified lines
804791 goto fail;
805792 }
806793
794+ /*
795+ * Set the GPU linear window to cover the cmdbuf region, as the GPU
796+ * won't be able to start execution otherwise. The alignment to 128M is
797+ * chosen arbitrarily but helps in debugging, as the MMU offset
798+ * calculations are much more straight forward this way.
799+ *
800+ * On MC1.0 cores the linear window offset is ignored by the TS engine,
801+ * leading to inconsistent memory views. Avoid using the offset on those
802+ * cores if possible, otherwise disable the TS feature.
803+ */
804+ cmdbuf_paddr = ALIGN_DOWN(etnaviv_cmdbuf_get_pa(&gpu->buffer), SZ_128M);
805+
806+ if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
807+ (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {
808+ if (cmdbuf_paddr >= SZ_2G)
809+ priv->mmu_global->memory_base = SZ_2G;
810+ else
811+ priv->mmu_global->memory_base = cmdbuf_paddr;
812+ } else if (cmdbuf_paddr + SZ_128M >= SZ_2G) {
813+ dev_info(gpu->dev,
814+ "Need to move linear window on MC1.0, disabling TS\n");
815+ gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
816+ priv->mmu_global->memory_base = SZ_2G;
817+ }
818+
807819 /* Setup event management */
808820 spin_lock_init(&gpu->event_spinlock);
809821 init_completion(&gpu->event_free);
@@ -1771,10 +1783,8 @@ static int etnaviv_gpu_platform_probe(struct platform_device *pdev) · 961 unmodified lines
17711783
17721784 /* Get Interrupt: */
17731785 gpu->irq = platform_get_irq(pdev, 0);
1774− if (gpu->irq < 0) {
1775− dev_err(dev, "failed to get irq: %d\n", gpu->irq);
1786+ if (gpu->irq < 0)
17761787 return gpu->irq;
1777− }
17781788
17791789 err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
17801790 dev_name(gpu->dev), gpu);
drivers/gpu/drm/etnaviv/etnaviv_hwdb.c+31−0
@@ -37,6 +37,37 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = { · 36 unmodified lines
3737 .minor_features10 = 0x0,
3838 .minor_features11 = 0x0,
3939 },
40+ {
41+ .model = 0x7000,
42+ .revision = 0x6204,
43+ .product_id = ~0U,
44+ .customer_id = ~0U,
45+ .eco_id = 0,
46+ .stream_count = 16,
47+ .register_max = 64,
48+ .thread_count = 512,
49+ .shader_core_count = 2,
50+ .vertex_cache_size = 16,
51+ .vertex_output_buffer_size = 1024,
52+ .pixel_pipes = 1,
53+ .instruction_count = 512,
54+ .num_constants = 320,
55+ .buffer_size = 0,
56+ .varyings_count = 16,
57+ .features = 0xe0287c8d,
58+ .minor_features0 = 0xc1589eff,
59+ .minor_features1 = 0xfefbfad9,
60+ .minor_features2 = 0xeb9d4fbf,
61+ .minor_features3 = 0xedfffced,
62+ .minor_features4 = 0xdb0dafc7,
63+ .minor_features5 = 0x3b5ac333,
64+ .minor_features6 = 0xfcce6000,
65+ .minor_features7 = 0xfffbfa6f,
66+ .minor_features8 = 0x00e10ef3,
67+ .minor_features9 = 0x04c8003c,
68+ .minor_features10 = 0x00004060,
69+ .minor_features11 = 0x00000024,
70+ },
4071 {
4172 .model = 0x7000,
4273 .revision = 0x6214,
include/uapi/drm/etnaviv_drm.h+3−0
@@ -74,6 +74,9 @@ struct drm_etnaviv_timespec { · 73 unmodified lines
7474 #define ETNAVIV_PARAM_GPU_NUM_CONSTANTS 0x19
7575 #define ETNAVIV_PARAM_GPU_NUM_VARYINGS 0x1a
7676 #define ETNAVIV_PARAM_SOFTPIN_START_ADDR 0x1b
77+#define ETNAVIV_PARAM_GPU_PRODUCT_ID 0x1c
78+#define ETNAVIV_PARAM_GPU_CUSTOMER_ID 0x1d
79+#define ETNAVIV_PARAM_GPU_ECO_ID 0x1e
7780
7881 #define ETNA_MAX_PIPES 4
7982