History

Merge tag 'drm-intel-fixes-2019-10-03-1' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes

- Fix DP-MST crtc_mask - Fix dsc dpp calculations - Fix g4x sprite scaling stride check with GTT remapping Signed-off-by: Dave Airlie <airlied@redhat.com>

Dave Airlie committed 7 years ago

Commit 07bba342 parents 63c4cec 485f6826 files · +111 −102Browse files

Unified · Split

6 files
  1. drivers/gpu/drm/i915/display/intel_display.c +8 −4
  2. drivers/gpu/drm/i915/display/intel_display.h +1 −1
  3. drivers/gpu/drm/i915/display/intel_dp.c +95 −89
  4. drivers/gpu/drm/i915/display/intel_dp.h +2 −4
  5. drivers/gpu/drm/i915/display/intel_dp_mst.c +2 −2
  6. drivers/gpu/drm/i915/display/intel_sprite.c +3 −2
drivers/gpu/drm/i915/display/intel_display.c+8−4
@@ -7261,7 +7261,7 @@ retry: · 7260 unmodified lines
72617261 pipe_config->fdi_lanes = lane;
72627262
72637263 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7264− link_bw, &pipe_config->fdi_m_n, false);
7264+ link_bw, &pipe_config->fdi_m_n, false, false);
72657265
72667266 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
72677267 if (ret == -EDEADLK)
@@ -7508,11 +7508,15 @@ void · 240 unmodified lines
75087508 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
75097509 int pixel_clock, int link_clock,
75107510 struct intel_link_m_n *m_n,
7511− bool constant_n)
7511+ bool constant_n, bool fec_enable)
75127512 {
7513− m_n->tu = 64;
7513+ u32 data_clock = bits_per_pixel * pixel_clock;
7514+
7515+ if (fec_enable)
7516+ data_clock = intel_dp_mode_to_fec_clock(data_clock);
75147517
7515− compute_m_n(bits_per_pixel * pixel_clock,
7518+ m_n->tu = 64;
7519+ compute_m_n(data_clock,
75167520 link_clock * nlanes * 8,
75177521 &m_n->gmch_m, &m_n->gmch_n,
75187522 constant_n);
drivers/gpu/drm/i915/display/intel_display.h+1−1
@@ -414,7 +414,7 @@ enum phy_fia { · 413 unmodified lines
414414 void intel_link_compute_m_n(u16 bpp, int nlanes,
415415 int pixel_clock, int link_clock,
416416 struct intel_link_m_n *m_n,
417− bool constant_n);
417+ bool constant_n, bool fec_enable);
418418 bool is_ccs_modifier(u64 modifier);
419419 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
420420 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
drivers/gpu/drm/i915/display/intel_dp.c+95−89
@@ -78,8 +78,8 @@ · 77 unmodified lines
7878 #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
7979 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000
8080
81−/* DP DSC FEC Overhead factor = (100 - 2.4)/100 */
82−#define DP_DSC_FEC_OVERHEAD_FACTOR 976
81+/* DP DSC FEC Overhead factor = 1/(0.972261) */
82+#define DP_DSC_FEC_OVERHEAD_FACTOR 972261
8383
8484 /* Compliance test status bits */
8585 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0
@@ -494,6 +494,97 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, · 408 unmodified lines
494494 return 0;
495495 }
496496
497+u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
498+{
499+ return div_u64(mul_u32_u32(mode_clock, 1000000U),
500+ DP_DSC_FEC_OVERHEAD_FACTOR);
501+}
502+
503+static u16 intel_dp_dsc_get_output_bpp(u32 link_clock, u32 lane_count,
504+ u32 mode_clock, u32 mode_hdisplay)
505+{
506+ u32 bits_per_pixel, max_bpp_small_joiner_ram;
507+ int i;
508+
509+ /*
510+ * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
511+ * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
512+ * for SST -> TimeSlotsPerMTP is 1,
513+ * for MST -> TimeSlotsPerMTP has to be calculated
514+ */
515+ bits_per_pixel = (link_clock * lane_count * 8) /
516+ intel_dp_mode_to_fec_clock(mode_clock);
517+ DRM_DEBUG_KMS("Max link bpp: %u\n", bits_per_pixel);
518+
519+ /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
520+ max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER / mode_hdisplay;
521+ DRM_DEBUG_KMS("Max small joiner bpp: %u\n", max_bpp_small_joiner_ram);
522+
523+ /*
524+ * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
525+ * check, output bpp from small joiner RAM check)
526+ */
527+ bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
528+
529+ /* Error out if the max bpp is less than smallest allowed valid bpp */
530+ if (bits_per_pixel < valid_dsc_bpp[0]) {
531+ DRM_DEBUG_KMS("Unsupported BPP %u, min %u\n",
532+ bits_per_pixel, valid_dsc_bpp[0]);
533+ return 0;
534+ }
535+
536+ /* Find the nearest match in the array of known BPPs from VESA */
537+ for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
538+ if (bits_per_pixel < valid_dsc_bpp[i + 1])
539+ break;
540+ }
541+ bits_per_pixel = valid_dsc_bpp[i];
542+
543+ /*
544+ * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
545+ * fractional part is 0
546+ */
547+ return bits_per_pixel << 4;
548+}
549+
550+static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
551+ int mode_clock, int mode_hdisplay)
552+{
553+ u8 min_slice_count, i;
554+ int max_slice_width;
555+
556+ if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
557+ min_slice_count = DIV_ROUND_UP(mode_clock,
558+ DP_DSC_MAX_ENC_THROUGHPUT_0);
559+ else
560+ min_slice_count = DIV_ROUND_UP(mode_clock,
561+ DP_DSC_MAX_ENC_THROUGHPUT_1);
562+
563+ max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
564+ if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
565+ DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n",
566+ max_slice_width);
567+ return 0;
568+ }
569+ /* Also take into account max slice width */
570+ min_slice_count = min_t(u8, min_slice_count,
571+ DIV_ROUND_UP(mode_hdisplay,
572+ max_slice_width));
573+
574+ /* Find the closest match to the valid slice count values */
575+ for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
576+ if (valid_dsc_slicecount[i] >
577+ drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
578+ false))
579+ break;
580+ if (min_slice_count <= valid_dsc_slicecount[i])
581+ return valid_dsc_slicecount[i];
582+ }
583+
584+ DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count);
585+ return 0;
586+}
587+
497588 static enum drm_mode_status
498589 intel_dp_mode_valid(struct drm_connector *connector,
499590 struct drm_display_mode *mode)
@@ -2226,7 +2317,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, · 1726 unmodified lines
22262317 adjusted_mode->crtc_clock,
22272318 pipe_config->port_clock,
22282319 &pipe_config->dp_m_n,
2229− constant_n);
2320+ constant_n, pipe_config->fec_enable);
22302321
22312322 if (intel_connector->panel.downclock_mode != NULL &&
22322323 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
@@ -2236,7 +2327,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, · 3 unmodified lines
22362327 intel_connector->panel.downclock_mode->clock,
22372328 pipe_config->port_clock,
22382329 &pipe_config->dp_m2_n2,
2239− constant_n);
2330+ constant_n, pipe_config->fec_enable);
22402331 }
22412332
22422333 if (!HAS_DDI(dev_priv))
@@ -4323,91 +4414,6 @@ intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) · 2080 unmodified lines
43234414 DP_DPRX_ESI_LEN;
43244415 }
43254416
4326−u16 intel_dp_dsc_get_output_bpp(int link_clock, u8 lane_count,
4327− int mode_clock, int mode_hdisplay)
4328−{
4329− u16 bits_per_pixel, max_bpp_small_joiner_ram;
4330− int i;
4331−
4332− /*
4333− * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
4334− * (LinkSymbolClock)* 8 * ((100-FECOverhead)/100)*(TimeSlotsPerMTP)
4335− * FECOverhead = 2.4%, for SST -> TimeSlotsPerMTP is 1,
4336− * for MST -> TimeSlotsPerMTP has to be calculated
4337− */
4338− bits_per_pixel = (link_clock * lane_count * 8 *
4339− DP_DSC_FEC_OVERHEAD_FACTOR) /
4340− mode_clock;
4341−
4342− /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
4343− max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER /
4344− mode_hdisplay;
4345−
4346− /*
4347− * Greatest allowed DSC BPP = MIN (output BPP from avaialble Link BW
4348− * check, output bpp from small joiner RAM check)
4349− */
4350− bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
4351−
4352− /* Error out if the max bpp is less than smallest allowed valid bpp */
4353− if (bits_per_pixel < valid_dsc_bpp[0]) {
4354− DRM_DEBUG_KMS("Unsupported BPP %d\n", bits_per_pixel);
4355− return 0;
4356− }
4357−
4358− /* Find the nearest match in the array of known BPPs from VESA */
4359− for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
4360− if (bits_per_pixel < valid_dsc_bpp[i + 1])
4361− break;
4362− }
4363− bits_per_pixel = valid_dsc_bpp[i];
4364−
4365− /*
4366− * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
4367− * fractional part is 0
4368− */
4369− return bits_per_pixel << 4;
4370−}
4371−
4372−u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
4373− int mode_clock,
4374− int mode_hdisplay)
4375−{
4376− u8 min_slice_count, i;
4377− int max_slice_width;
4378−
4379− if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
4380− min_slice_count = DIV_ROUND_UP(mode_clock,
4381− DP_DSC_MAX_ENC_THROUGHPUT_0);
4382− else
4383− min_slice_count = DIV_ROUND_UP(mode_clock,
4384− DP_DSC_MAX_ENC_THROUGHPUT_1);
4385−
4386− max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
4387− if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
4388− DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n",
4389− max_slice_width);
4390− return 0;
4391− }
4392− /* Also take into account max slice width */
4393− min_slice_count = min_t(u8, min_slice_count,
4394− DIV_ROUND_UP(mode_hdisplay,
4395− max_slice_width));
4396−
4397− /* Find the closest match to the valid slice count values */
4398− for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
4399− if (valid_dsc_slicecount[i] >
4400− drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
4401− false))
4402− break;
4403− if (min_slice_count <= valid_dsc_slicecount[i])
4404− return valid_dsc_slicecount[i];
4405− }
4406−
4407− DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count);
4408− return 0;
4409−}
4410−
44114417 static void
44124418 intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp,
44134419 const struct intel_crtc_state *crtc_state)
drivers/gpu/drm/i915/display/intel_dp.h+2−4
@@ -102,10 +102,6 @@ bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp); · 101 unmodified lines
102102 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
103103 bool
104104 intel_dp_get_link_status(struct intel_dp *intel_dp, u8 *link_status);
105−u16 intel_dp_dsc_get_output_bpp(int link_clock, u8 lane_count,
106− int mode_clock, int mode_hdisplay);
107−u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
108− int mode_hdisplay);
109105
110106 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
111107 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp);
@@ -118,4 +114,6 @@ static inline unsigned int intel_dp_unused_lane_mask(int lane_count) · 6 unmodified lines
118114 return ~((1 << lane_count) - 1) & 0xf;
119115 }
120116
117+u32 intel_dp_mode_to_fec_clock(u32 mode_clock);
118+
121119 #endif /* __INTEL_DP_H__ */
drivers/gpu/drm/i915/display/intel_dp_mst.c+2−2
@@ -81,7 +81,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, · 80 unmodified lines
8181 adjusted_mode->crtc_clock,
8282 crtc_state->port_clock,
8383 &crtc_state->dp_m_n,
84− constant_n);
84+ constant_n, crtc_state->fec_enable);
8585 crtc_state->dp_m_n.tu = slots;
8686
8787 return 0;
@@ -615,7 +615,7 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum · 527 unmodified lines
615615 intel_encoder->type = INTEL_OUTPUT_DP_MST;
616616 intel_encoder->power_domain = intel_dig_port->base.power_domain;
617617 intel_encoder->port = intel_dig_port->base.port;
618− intel_encoder->crtc_mask = BIT(pipe);
618+ intel_encoder->crtc_mask = 0x7;
619619 intel_encoder->cloneable = 0;
620620
621621 intel_encoder->compute_config = intel_dp_mst_compute_config;
drivers/gpu/drm/i915/display/intel_sprite.c+3−2
@@ -1528,6 +1528,7 @@ g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state, · 1527 unmodified lines
15281528 int src_x, src_w, src_h, crtc_w, crtc_h;
15291529 const struct drm_display_mode *adjusted_mode =
15301530 &crtc_state->base.adjusted_mode;
1531+ unsigned int stride = plane_state->color_plane[0].stride;
15311532 unsigned int cpp = fb->format->cpp[0];
15321533 unsigned int width_bytes;
15331534 int min_width, min_height;
@@ -1569,9 +1570,9 @@ g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state, · 35 unmodified lines
15691570 return -EINVAL;
15701571 }
15711572
1572− if (width_bytes > 4096 || fb->pitches[0] > 4096) {
1573+ if (stride > 4096) {
15731574 DRM_DEBUG_KMS("Stride (%u) exceeds hardware max with scaling (%u)\n",
1574− fb->pitches[0], 4096);
1575+ stride, 4096);
15751576 return -EINVAL;
15761577 }
15771578

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