History

net/mlx5: Introduce EQ polling budget

Multiple EQs may share the same irq in subsequent patches. To avoid starvation, a budget is set per EQ's interrupt handler. Because of this change, it is no longer required to check that MLX5_NUM_SPARE_EQE eqes were polled (to detect that arm is required). It is guaranteed that MLX5_NUM_SPARE_EQE > budget, therefore the handler will arm and exit the handler before all the entries in the eq are polled. In the scenario where the handler is out of budget and there are more EQEs to poll, arming the EQ guarantees that the HW will send another interrupt and the handler will be called again.

Yuval Avnery committed 7 years ago

Commit 081cc2d1 parent 86eec501 file · +27 −28Browse files

Unified · Split

drivers/net/ethernet/mellanox/mlx5/core/eq.c+27−28
@@ -61,6 +61,16 @@ enum { · 60 unmodified lines
6161 MLX5_EQ_DOORBEL_OFFSET = 0x40,
6262 };
6363
64+/* budget must be smaller than MLX5_NUM_SPARE_EQE to guarantee that we update
65+ * the ci before we polled all the entries in the EQ. MLX5_NUM_SPARE_EQE is
66+ * used to set the EQ size, budget must be smaller than the EQ size.
67+ */
68+enum {
69+ MLX5_EQ_POLLING_BUDGET = 128,
70+};
71+
72+static_assert(MLX5_EQ_POLLING_BUDGET <= MLX5_NUM_SPARE_EQE);
73+
6474 struct mlx5_irq_info {
6575 cpumask_var_t mask;
6676 char name[MLX5_MAX_IRQ_NAME];
@@ -129,11 +139,16 @@ static irqreturn_t mlx5_eq_comp_int(int irq, void *eq_ptr) · 62 unmodified lines
129139 struct mlx5_eq_comp *eq_comp = eq_ptr;
130140 struct mlx5_eq *eq = eq_ptr;
131141 struct mlx5_eqe *eqe;
132− int set_ci = 0;
142+ int num_eqes = 0;
133143 u32 cqn = -1;
134144
135− while ((eqe = next_eqe_sw(eq))) {
145+ eqe = next_eqe_sw(eq);
146+ if (!eqe)
147+ goto out;
148+
149+ do {
136150 struct mlx5_core_cq *cq;
151+
137152 /* Make sure we read EQ entry contents after we've
138153 * checked the ownership bit.
139154 */
@@ -151,20 +166,10 @@ static irqreturn_t mlx5_eq_comp_int(int irq, void *eq_ptr) · 11 unmodified lines
151166 }
152167
153168 ++eq->cons_index;
154− ++set_ci;
155169
156− /* The HCA will think the queue has overflowed if we
157− * don't tell it we've been processing events. We
158− * create our EQs with MLX5_NUM_SPARE_EQE extra
159− * entries, so we must update our consumer index at
160− * least that often.
161− */
162− if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) {
163− eq_update_ci(eq, 0);
164− set_ci = 0;
165− }
166− }
170+ } while ((++num_eqes < MLX5_EQ_POLLING_BUDGET) && (eqe = next_eqe_sw(eq)));
167171
172+out:
168173 eq_update_ci(eq, 1);
169174
170175 if (cqn != -1)
@@ -197,12 +202,16 @@ static irqreturn_t mlx5_eq_async_int(int irq, void *eq_ptr) · 26 unmodified lines
197202 struct mlx5_eq_table *eqt;
198203 struct mlx5_core_dev *dev;
199204 struct mlx5_eqe *eqe;
200− int set_ci = 0;
205+ int num_eqes = 0;
201206
202207 dev = eq->dev;
203208 eqt = dev->priv.eq_table;
204209
205− while ((eqe = next_eqe_sw(eq))) {
210+ eqe = next_eqe_sw(eq);
211+ if (!eqe)
212+ goto out;
213+
214+ do {
206215 /*
207216 * Make sure we read EQ entry contents after we've
208217 * checked the ownership bit.
@@ -217,20 +226,10 @@ static irqreturn_t mlx5_eq_async_int(int irq, void *eq_ptr) · 8 unmodified lines
217226 atomic_notifier_call_chain(&eqt->nh[MLX5_EVENT_TYPE_NOTIFY_ANY], eqe->type, eqe);
218227
219228 ++eq->cons_index;
220− ++set_ci;
221229
222− /* The HCA will think the queue has overflowed if we
223− * don't tell it we've been processing events. We
224− * create our EQs with MLX5_NUM_SPARE_EQE extra
225− * entries, so we must update our consumer index at
226− * least that often.
227− */
228− if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) {
229− eq_update_ci(eq, 0);
230− set_ci = 0;
231− }
232− }
230+ } while ((++num_eqes < MLX5_EQ_POLLING_BUDGET) && (eqe = next_eqe_sw(eq)));
233231
232+out:
234233 eq_update_ci(eq, 1);
235234
236235 return IRQ_HANDLED;

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