lael-labs/linux

Documentation/devicetree/bindings/i2c/i2c-st.txt+1−1

@@ -31,7 +31,7 @@ i2c0: i2c@fed40000 { · 30 unmodified lines
31	compatible = "st,comms-ssc4-i2c";	31	compatible = "st,comms-ssc4-i2c";
32	reg = <0xfed40000 0x110>;	32	reg = <0xfed40000 0x110>;
33	interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;	33	interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
34	clocks = <&CLK_S_ICN_REG_0>;	34	clocks = <&clk_s_a0_ls CLK_ICN_REG>;
35	clock-names = "ssc";	35	clock-names = "ssc";
36	clock-frequency = <400000>;	36	clock-frequency = <400000>;
37	pinctrl-names = "default";	37	pinctrl-names = "default";

Documentation/devicetree/bindings/i2c/trivial-devices.txt+1−0

@@ -47,6 +47,7 @@ dallas,ds3232 Extremely Accurate I²C RTC with Integrated Crystal and SRAM · 46 unmodified lines
47	dallas,ds4510 CPU Supervisor with Nonvolatile Memory and Programmable I/O	47	dallas,ds4510 CPU Supervisor with Nonvolatile Memory and Programmable I/O
48	dallas,ds75 Digital Thermometer and Thermostat	48	dallas,ds75 Digital Thermometer and Thermostat
49	dlg,da9053 DA9053: flexible system level PMIC with multicore support	49	dlg,da9053 DA9053: flexible system level PMIC with multicore support
		50	dlg,da9063 DA9063: system PMIC for quad-core application processors
50	epson,rx8025 High-Stability. I2C-Bus INTERFACE REAL TIME CLOCK MODULE	51	epson,rx8025 High-Stability. I2C-Bus INTERFACE REAL TIME CLOCK MODULE
51	epson,rx8581 I2C-BUS INTERFACE REAL TIME CLOCK MODULE	52	epson,rx8581 I2C-BUS INTERFACE REAL TIME CLOCK MODULE
52	fsl,mag3110 MAG3110: Xtrinsic High Accuracy, 3D Magnetometer	53	fsl,mag3110 MAG3110: Xtrinsic High Accuracy, 3D Magnetometer

MAINTAINERS+21−0

@@ -708,6 +708,16 @@ X: drivers/iio//adjd · 707 unmodified lines
708	F: drivers/staging/iio//ad	708	F: drivers/staging/iio//ad
709	F: staging/iio/trigger/iio-trig-bfin-timer.c	709	F: staging/iio/trigger/iio-trig-bfin-timer.c
710		710
		711	ANDROID DRIVERS
		712	M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
		713	M: Arve Hj�nnev�g <arve@android.com>
		714	M: Riley Andrews <riandrews@android.com>
		715	T: git git://git.kernel.org/pub/scm/linux/kernel/gregkh/staging.git
		716	L: devel@driverdev.osuosl.org
		717	S: Supported
		718	F: drivers/android/
		719	F: drivers/staging/android/
		720
711	AOA (Apple Onboard Audio) ALSA DRIVER	721	AOA (Apple Onboard Audio) ALSA DRIVER
712	M: Johannes Berg <johannes@sipsolutions.net>	722	M: Johannes Berg <johannes@sipsolutions.net>
713	L: linuxppc-dev@lists.ozlabs.org	723	L: linuxppc-dev@lists.ozlabs.org
@@ -4943,6 +4953,16 @@ F: Documentation/input/multi-touch-protocol.txt · 4229 unmodified lines
4943	F: drivers/input/input-mt.c	4953	F: drivers/input/input-mt.c
4944	K: \b(ABS\|SYN)_MT_	4954	K: \b(ABS\|SYN)_MT_
4945		4955
		4956	INTEL ASoC BDW/HSW DRIVERS
		4957	M: Jie Yang <yang.jie@linux.intel.com>
		4958	L: alsa-devel@alsa-project.org
		4959	S: Supported
		4960	F: sound/soc/intel/sst-haswell*
		4961	F: sound/soc/intel/sst-dsp*
		4962	F: sound/soc/intel/sst-firmware.c
		4963	F: sound/soc/intel/broadwell.c
		4964	F: sound/soc/intel/haswell.c
		4965
4946	INTEL C600 SERIES SAS CONTROLLER DRIVER	4966	INTEL C600 SERIES SAS CONTROLLER DRIVER
4947	M: Intel SCU Linux support <intel-linux-scu@intel.com>	4967	M: Intel SCU Linux support <intel-linux-scu@intel.com>
4948	M: Artur Paszkiewicz <artur.paszkiewicz@intel.com>	4968	M: Artur Paszkiewicz <artur.paszkiewicz@intel.com>
@@ -10166,6 +10186,7 @@ USERSPACE I/O (UIO) · 5217 unmodified lines
10166	M: "Hans J. Koch" <hjk@hansjkoch.de>	10186	M: "Hans J. Koch" <hjk@hansjkoch.de>
10167	M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>	10187	M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
10168	S: Maintained	10188	S: Maintained
		10189	T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git
10169	F: Documentation/DocBook/uio-howto.tmpl	10190	F: Documentation/DocBook/uio-howto.tmpl
10170	F: drivers/uio/	10191	F: drivers/uio/
10171	F: include/linux/uio*.h	10192	F: include/linux/uio*.h

Makefile+1−1

@@ -1,7 +1,7 @@
1	VERSION = 3	1	VERSION = 3
2	PATCHLEVEL = 19	2	PATCHLEVEL = 19
3	SUBLEVEL = 0	3	SUBLEVEL = 0
4	EXTRAVERSION = -rc6	4	EXTRAVERSION = -rc7
5	NAME = Diseased Newt	5	NAME = Diseased Newt
6		6
7	# DOCUMENTATION	7	# DOCUMENTATION

arch/alpha/mm/fault.c+2−0

 	if (unlikely(fault & VM_FAULT_ERROR)) {
 		if (fault & VM_FAULT_OOM)
 			goto out_of_memory;
+		else if (fault & VM_FAULT_SIGSEGV)
+			goto bad_area;
 		else if (fault & VM_FAULT_SIGBUS)
 			goto do_sigbus;
 		BUG();

arch/arc/mm/fault.c+2−0

@@ -161,6 +161,8 @@ good_area: · 160 unmodified lines
161		161
162	if (fault & VM_FAULT_OOM)	162	if (fault & VM_FAULT_OOM)
163	goto out_of_memory;	163	goto out_of_memory;
		164	else if (fault & VM_FAULT_SIGSEGV)
		165	goto bad_area;
164	else if (fault & VM_FAULT_SIGBUS)	166	else if (fault & VM_FAULT_SIGBUS)
165	goto do_sigbus;	167	goto do_sigbus;
166		168

arch/arm/boot/dts/exynos4.dtsi+2−2

@@ -368,7 +368,7 @@ · 367 unmodified lines
368	};	368	};
369		369
370	i2s1: i2s@13960000 {	370	i2s1: i2s@13960000 {
371	compatible = "samsung,s5pv210-i2s";	371	compatible = "samsung,s3c6410-i2s";
372	reg = <0x13960000 0x100>;	372	reg = <0x13960000 0x100>;
373	clocks = <&clock CLK_I2S1>;	373	clocks = <&clock CLK_I2S1>;
374	clock-names = "iis";	374	clock-names = "iis";
@@ -378,7 +378,7 @@ · 3 unmodified lines
378	};	378	};
379		379
380	i2s2: i2s@13970000 {	380	i2s2: i2s@13970000 {
381	compatible = "samsung,s5pv210-i2s";	381	compatible = "samsung,s3c6410-i2s";
382	reg = <0x13970000 0x100>;	382	reg = <0x13970000 0x100>;
383	clocks = <&clock CLK_I2S2>;	383	clocks = <&clock CLK_I2S2>;
384	clock-names = "iis";	384	clock-names = "iis";

arch/arm/boot/dts/imx6sx-sdb.dts+4−4

@@ -166,12 +166,12 @@ · 165 unmodified lines
166	#address-cells = <1>;	166	#address-cells = <1>;
167	#size-cells = <0>;	167	#size-cells = <0>;
168		168
169	ethphy1: ethernet-phy@0 {	169	ethphy1: ethernet-phy@1 {
170	reg = <0>;	170	reg = <1>;
171	};	171	};
172		172
173	ethphy2: ethernet-phy@1 {	173	ethphy2: ethernet-phy@2 {
174	reg = <1>;	174	reg = <2>;
175	};	175	};
176	};	176	};
177	};	177	};

arch/arm/boot/dts/sun4i-a10.dtsi+10−10

 	aliases {
 		ethernet0 = &emac;
-		serial0 = &uart0;
-		serial1 = &uart1;
-		serial2 = &uart2;
-		serial3 = &uart3;
-		serial4 = &uart4;
-		serial5 = &uart5;
-		serial6 = &uart6;
-		serial7 = &uart7;
 	};
 	chosen {
 				 <&ahb_gates 44>;
 			status = "disabled";
 		};
+		framebuffer@1 {
+			compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
+			allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
+			clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
+				 <&ahb_gates 44>, <&ahb_gates 46>;
+			status = "disabled";
+		};
 	};
 	cpus {
 			reg-names = "phy_ctrl", "pmu1", "pmu2";
 			clocks = <&usb_clk 8>;
 			clock-names = "usb_phy";
-			resets = <&usb_clk 1>, <&usb_clk 2>;
+			resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
-			reset-names = "usb1_reset", "usb2_reset";
+			reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
 			status = "disabled";
 		};

arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts+6−0

 	model = "Olimex A10s-Olinuxino Micro";
 	compatible = "olimex,a10s-olinuxino-micro", "allwinner,sun5i-a10s";
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart2;
+		serial2 = &uart3;
+	};
 	soc@01c00000 {
 		emac: ethernet@01c0b000 {
 			pinctrl-names = "default";

arch/arm/boot/dts/sun5i-a10s.dtsi+2−6

 	aliases {
 		ethernet0 = &emac;
-		serial0 = &uart0;
-		serial1 = &uart1;
-		serial2 = &uart2;
-		serial3 = &uart3;
 	};
 	chosen {
 			reg-names = "phy_ctrl", "pmu1";
 			clocks = <&usb_clk 8>;
 			clock-names = "usb_phy";
-			resets = <&usb_clk 1>;
+			resets = <&usb_clk 0>, <&usb_clk 1>;
-			reset-names = "usb1_reset";
+			reset-names = "usb0_reset", "usb1_reset";
 			status = "disabled";
 		};

arch/arm/boot/dts/sun5i-a13-hsg-h702.dts+4−0

 	model = "HSG H702";
 	compatible = "hsg,h702", "allwinner,sun5i-a13";
+	aliases {
+		serial0 = &uart1;
+	};
 	soc@01c00000 {
 		mmc0: mmc@01c0f000 {
 			pinctrl-names = "default";

arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts+4−0

 	model = "Olimex A13-Olinuxino Micro";
 	compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13";
+	aliases {
+		serial0 = &uart1;
+	};
 	soc@01c00000 {
 		mmc0: mmc@01c0f000 {
 			pinctrl-names = "default";

arch/arm/boot/dts/sun5i-a13-olinuxino.dts+4−0

 	model = "Olimex A13-Olinuxino";
 	compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13";
+	aliases {
+		serial0 = &uart1;
+	};
 	soc@01c00000 {
 		mmc0: mmc@01c0f000 {
 			pinctrl-names = "default";

arch/arm/boot/dts/sun5i-a13.dtsi+2−7

 / {
 	interrupt-parent = <&intc>;
-	aliases {
-		serial0 = &uart1;
-		serial1 = &uart3;
-	};
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
 			reg-names = "phy_ctrl", "pmu1";
 			clocks = <&usb_clk 8>;
 			clock-names = "usb_phy";
-			resets = <&usb_clk 1>;
+			resets = <&usb_clk 0>, <&usb_clk 1>;
-			reset-names = "usb1_reset";
+			reset-names = "usb0_reset", "usb1_reset";
 			status = "disabled";
 		};

arch/arm/boot/dts/sun6i-a31.dtsi+0−6

 	interrupt-parent = <&gic>;
 	aliases {
-		serial0 = &uart0;
-		serial1 = &uart1;
-		serial2 = &uart2;
-		serial3 = &uart3;
-		serial4 = &uart4;
-		serial5 = &uart5;
 		ethernet0 = &gmac;
 	};

arch/arm/boot/dts/sun7i-a20-bananapi.dts+6−0

 	model = "LeMaker Banana Pi";
 	compatible = "lemaker,bananapi", "allwinner,sun7i-a20";
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart3;
+		serial2 = &uart7;
+	};
 	soc@01c00000 {
 		spi0: spi@01c05000 {
 			pinctrl-names = "default";

arch/arm/boot/dts/sun7i-a20-hummingbird.dts+8−0

@@ -19,6 +19,14 @@ · 18 unmodified lines
19	model = "Merrii A20 Hummingbird";	19	model = "Merrii A20 Hummingbird";
20	compatible = "merrii,a20-hummingbird", "allwinner,sun7i-a20";	20	compatible = "merrii,a20-hummingbird", "allwinner,sun7i-a20";
21		21
		22	aliases {
		23	serial0 = &uart0;
		24	serial1 = &uart2;
		25	serial2 = &uart3;
		26	serial3 = &uart4;
		27	serial4 = &uart5;
		28	};
		29
22	soc@01c00000 {	30	soc@01c00000 {
23	mmc0: mmc@01c0f000 {	31	mmc0: mmc@01c0f000 {
24	pinctrl-names = "default";	32	pinctrl-names = "default";

arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts+3−0

 	compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20";
 	aliases {
+		serial0 = &uart0;
+		serial1 = &uart6;
+		serial2 = &uart7;
 		spi0 = &spi1;
 		spi1 = &spi2;
 	};

arch/arm/boot/dts/sun7i-a20.dtsi+0−8

@@ -54,14 +54,6 @@ · 53 unmodified lines
54		54
55	aliases {	55	aliases {
56	ethernet0 = &gmac;	56	ethernet0 = &gmac;
57	serial0 = &uart0;
58	serial1 = &uart1;
59	serial2 = &uart2;
60	serial3 = &uart3;
61	serial4 = &uart4;
62	serial5 = &uart5;
63	serial6 = &uart6;
64	serial7 = &uart7;
65	};	57	};
66		58
67	chosen {	59	chosen {

arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts+4−0

 	model = "Ippo Q8H Dual Core Tablet (v5)";
 	compatible = "ippo,q8h-v5", "allwinner,sun8i-a23";
+	aliases {
+		serial0 = &r_uart;
+	};
 	chosen {
 		bootargs = "earlyprintk console=ttyS0,115200";
 	};

arch/arm/boot/dts/sun8i-a23.dtsi+0−9

@@ -52,15 +52,6 @@ · 51 unmodified lines
52	/ {	52	/ {
53	interrupt-parent = <&gic>;	53	interrupt-parent = <&gic>;
54		54
55	aliases {
56	serial0 = &uart0;
57	serial1 = &uart1;
58	serial2 = &uart2;
59	serial3 = &uart3;
60	serial4 = &uart4;
61	serial5 = &r_uart;
62	};
63
64	cpus {	55	cpus {
65	#address-cells = <1>;	56	#address-cells = <1>;
66	#size-cells = <0>;	57	#size-cells = <0>;

arch/arm/boot/dts/sun9i-a80-optimus.dts+5−0

 	model = "Merrii A80 Optimus Board";
 	compatible = "merrii,a80-optimus", "allwinner,sun9i-a80";
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart4;
+	};
 	chosen {
 		bootargs = "earlyprintk console=ttyS0,115200";
 	};

arch/arm/boot/dts/sun9i-a80.dtsi+0−10

@@ -52,16 +52,6 @@ · 51 unmodified lines
52	/ {	52	/ {
53	interrupt-parent = <&gic>;	53	interrupt-parent = <&gic>;
54		54
55	aliases {
56	serial0 = &uart0;
57	serial1 = &uart1;
58	serial2 = &uart2;
59	serial3 = &uart3;
60	serial4 = &uart4;
61	serial5 = &uart5;
62	serial6 = &r_uart;
63	};
64
65	cpus {	55	cpus {
66	#address-cells = <1>;	56	#address-cells = <1>;
67	#size-cells = <0>;	57	#size-cells = <0>;

arch/arm/include/asm/kvm_emulate.h+10−0

@@ -38,6 +38,16 @@ static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu) · 37 unmodified lines
38	vcpu->arch.hcr = HCR_GUEST_MASK;	38	vcpu->arch.hcr = HCR_GUEST_MASK;
39	}	39	}
40		40
		41	static inline unsigned long vcpu_get_hcr(struct kvm_vcpu *vcpu)
		42	{
		43	return vcpu->arch.hcr;
		44	}
		45
		46	static inline void vcpu_set_hcr(struct kvm_vcpu *vcpu, unsigned long hcr)
		47	{
		48	vcpu->arch.hcr = hcr;
		49	}
		50
41	static inline bool vcpu_mode_is_32bit(struct kvm_vcpu *vcpu)	51	static inline bool vcpu_mode_is_32bit(struct kvm_vcpu *vcpu)
42	{	52	{
43	return 1;	53	return 1;

arch/arm/include/asm/kvm_host.h+0−3

 	 * Anything that is not used directly from assembly code goes
 	 * here.
 	 */
-	/* dcache set/way operation pending */
-	int last_pcpu;
-	cpumask_t require_dcache_flush;
 	/* Don't run the guest on this vcpu */
 	bool pause;

arch/arm/include/asm/kvm_mmu.h+67−10

@@ -44,6 +44,7 @@ · 43 unmodified lines
44		44
45	#ifndef __ASSEMBLY__	45	#ifndef __ASSEMBLY__
46		46
		47	#include <linux/highmem.h>
47	#include <asm/cacheflush.h>	48	#include <asm/cacheflush.h>
48	#include <asm/pgalloc.h>	49	#include <asm/pgalloc.h>
49		50
@@ -161,13 +162,10 @@ static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu) · 111 unmodified lines
161	return (vcpu->arch.cp15[c1_SCTLR] & 0b101) == 0b101;	162	return (vcpu->arch.cp15[c1_SCTLR] & 0b101) == 0b101;
162	}	163	}
163		164
164	static inline void coherent_cache_guest_page(struct kvm_vcpu *vcpu, hva_t hva,	165	static inline void __coherent_cache_guest_page(struct kvm_vcpu *vcpu, pfn_t pfn,
165	unsigned long size,	166	unsigned long size,
166	bool ipa_uncached)	167	bool ipa_uncached)
167	{	168	{
168	if (!vcpu_has_cache_enabled(vcpu) \|\| ipa_uncached)
169	kvm_flush_dcache_to_poc((void *)hva, size);
170
171	/*	169	/*
172	* If we are going to insert an instruction page and the icache is	170	* If we are going to insert an instruction page and the icache is
173	* either VIPT or PIPT, there is a potential problem where the host	171	* either VIPT or PIPT, there is a potential problem where the host
@@ -179,18 +177,77 @@ static inline void coherent_cache_guest_page(struct kvm_vcpu *vcpu, hva_t hva, · 5 unmodified lines
179	*	177	*
180	* VIVT caches are tagged using both the ASID and the VMID and doesn't	178	* VIVT caches are tagged using both the ASID and the VMID and doesn't
181	* need any kind of flushing (DDI 0406C.b - Page B3-1392).	179	* need any kind of flushing (DDI 0406C.b - Page B3-1392).
		180	*
		181	* We need to do this through a kernel mapping (using the
		182	* user-space mapping has proved to be the wrong
		183	* solution). For that, we need to kmap one page at a time,
		184	* and iterate over the range.
182	*/	185	*/
183	if (icache_is_pipt()) {	186
184	__cpuc_coherent_user_range(hva, hva + size);	187	bool need_flush = !vcpu_has_cache_enabled(vcpu) \|\| ipa_uncached;
185	} else if (!icache_is_vivt_asid_tagged()) {	188
		189	VM_BUG_ON(size & PAGE_MASK);
		190
		191	if (!need_flush && !icache_is_pipt())
		192	goto vipt_cache;
		193
		194	while (size) {
		195	void *va = kmap_atomic_pfn(pfn);
		196
		197	if (need_flush)
		198	kvm_flush_dcache_to_poc(va, PAGE_SIZE);
		199
		200	if (icache_is_pipt())
		201	__cpuc_coherent_user_range((unsigned long)va,
		202	(unsigned long)va + PAGE_SIZE);
		203
		204	size -= PAGE_SIZE;
		205	pfn++;
		206
		207	kunmap_atomic(va);
		208	}
		209
		210	vipt_cache:
		211	if (!icache_is_pipt() && !icache_is_vivt_asid_tagged()) {
186	/* any kind of VIPT cache */	212	/* any kind of VIPT cache */
187	__flush_icache_all();	213	__flush_icache_all();
188	}	214	}
189	}	215	}
190		216
		217	static inline void __kvm_flush_dcache_pte(pte_t pte)
		218	{
		219	void *va = kmap_atomic(pte_page(pte));
		220
		221	kvm_flush_dcache_to_poc(va, PAGE_SIZE);
		222
		223	kunmap_atomic(va);
		224	}
		225
		226	static inline void __kvm_flush_dcache_pmd(pmd_t pmd)
		227	{
		228	unsigned long size = PMD_SIZE;
		229	pfn_t pfn = pmd_pfn(pmd);
		230
		231	while (size) {
		232	void *va = kmap_atomic_pfn(pfn);
		233
		234	kvm_flush_dcache_to_poc(va, PAGE_SIZE);
		235
		236	pfn++;
		237	size -= PAGE_SIZE;
		238
		239	kunmap_atomic(va);
		240	}
		241	}
		242
		243	static inline void __kvm_flush_dcache_pud(pud_t pud)
		244	{
		245	}
		246
191	#define kvm_virt_to_phys(x) virt_to_idmap((unsigned long)(x))	247	#define kvm_virt_to_phys(x) virt_to_idmap((unsigned long)(x))
192		248
193	void stage2_flush_vm(struct kvm *kvm);	249	void kvm_set_way_flush(struct kvm_vcpu *vcpu);
		250	void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled);
194		251
195	#endif /* !__ASSEMBLY__ */	252	#endif /* !__ASSEMBLY__ */
196		253

arch/arm/kvm/arm.c+0−10

 	vcpu->cpu = cpu;
 	vcpu->arch.host_cpu_context = this_cpu_ptr(kvm_host_cpu_state);
-	/*
-	 * Check whether this vcpu requires the cache to be flushed on
-	 * this physical CPU. This is a consequence of doing dcache
-	 * operations by set/way on this vcpu. We do it here to be in
-	 * a non-preemptible section.
-	 */
-	if (cpumask_test_and_clear_cpu(cpu, &vcpu->arch.require_dcache_flush))
-		flush_cache_all(); /* We'd really want v7_flush_dcache_all() */
 	kvm_arm_set_running_vcpu(vcpu);
 }
 		ret = kvm_call_hyp(__kvm_vcpu_run, vcpu);
 		vcpu->mode = OUTSIDE_GUEST_MODE;
-		vcpu->arch.last_pcpu = smp_processor_id();
 		kvm_guest_exit();
 		trace_kvm_exit(*vcpu_pc(vcpu));
 		/*

arch/arm/kvm/coproc.c+14−56

@@ -189,82 +189,40 @@ static bool access_l2ectlr(struct kvm_vcpu *vcpu, · 188 unmodified lines
189	return true;	189	return true;
190	}	190	}
191		191
192	/* See note at ARM ARM B1.14.4 */	192	/*
		193	* See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
		194	*/
193	static bool access_dcsw(struct kvm_vcpu *vcpu,	195	static bool access_dcsw(struct kvm_vcpu *vcpu,
194	const struct coproc_params *p,	196	const struct coproc_params *p,
195	const struct coproc_reg *r)	197	const struct coproc_reg *r)
196	{	198	{
197	unsigned long val;
198	int cpu;
199
200	if (!p->is_write)	199	if (!p->is_write)
201	return read_from_write_only(vcpu, p);	200	return read_from_write_only(vcpu, p);
202		201
203	cpu = get_cpu();	202	kvm_set_way_flush(vcpu);
204
205	cpumask_setall(&vcpu->arch.require_dcache_flush);
206	cpumask_clear_cpu(cpu, &vcpu->arch.require_dcache_flush);
207
208	/* If we were already preempted, take the long way around */
209	if (cpu != vcpu->arch.last_pcpu) {
210	flush_cache_all();
211	goto done;
212	}
213
214	val = *vcpu_reg(vcpu, p->Rt1);
215
216	switch (p->CRm) {
217	case 6: /* Upgrade DCISW to DCCISW, as per HCR.SWIO */
218	case 14: /* DCCISW */
219	asm volatile("mcr p15, 0, %0, c7, c14, 2" : : "r" (val));
220	break;
221
222	case 10: /* DCCSW */
223	asm volatile("mcr p15, 0, %0, c7, c10, 2" : : "r" (val));
224	break;
225	}
226
227	done:
228	put_cpu();
229
230	return true;	203	return true;
231	}	204	}
232		205
233	/*	206	/*
234	* Generic accessor for VM registers. Only called as long as HCR_TVM	207	* Generic accessor for VM registers. Only called as long as HCR_TVM
235	* is set.	208	* is set. If the guest enables the MMU, we stop trapping the VM
		209	* sys_regs and leave it in complete control of the caches.
		210	*
		211	* Used by the cpu-specific code.
236	*/	212	*/
237	static bool access_vm_reg(struct kvm_vcpu *vcpu,	213	bool access_vm_reg(struct kvm_vcpu *vcpu,
238	const struct coproc_params *p,	214	const struct coproc_params *p,
239	const struct coproc_reg *r)	215	const struct coproc_reg *r)
240	{	216	{
		217	bool was_enabled = vcpu_has_cache_enabled(vcpu);
		218
241	BUG_ON(!p->is_write);	219	BUG_ON(!p->is_write);
242		220
243	vcpu->arch.cp15[r->reg] = *vcpu_reg(vcpu, p->Rt1);	221	vcpu->arch.cp15[r->reg] = *vcpu_reg(vcpu, p->Rt1);
244	if (p->is_64bit)	222	if (p->is_64bit)
245	vcpu->arch.cp15[r->reg + 1] = *vcpu_reg(vcpu, p->Rt2);	223	vcpu->arch.cp15[r->reg + 1] = *vcpu_reg(vcpu, p->Rt2);
246		224
247	return true;	225	kvm_toggle_cache(vcpu, was_enabled);
248	}
249
250	/*
251	* SCTLR accessor. Only called as long as HCR_TVM is set. If the
252	* guest enables the MMU, we stop trapping the VM sys_regs and leave
253	* it in complete control of the caches.
254	*
255	* Used by the cpu-specific code.
256	*/
257	bool access_sctlr(struct kvm_vcpu *vcpu,
258	const struct coproc_params *p,
259	const struct coproc_reg *r)
260	{
261	access_vm_reg(vcpu, p, r);
262
263	if (vcpu_has_cache_enabled(vcpu)) { /* MMU+Caches enabled? */
264	vcpu->arch.hcr &= ~HCR_TVM;
265	stage2_flush_vm(vcpu->kvm);
266	}
267
268	return true;	226	return true;
269	}	227	}
270		228

arch/arm/kvm/coproc.h+3−3

@@ -153,8 +153,8 @@ static inline int cmp_reg(const struct coproc_reg *i1, · 152 unmodified lines
153	#define is64 .is_64 = true	153	#define is64 .is_64 = true
154	#define is32 .is_64 = false	154	#define is32 .is_64 = false
155		155
156	bool access_sctlr(struct kvm_vcpu *vcpu,	156	bool access_vm_reg(struct kvm_vcpu *vcpu,
157	const struct coproc_params *p,	157	const struct coproc_params *p,
158	const struct coproc_reg *r);	158	const struct coproc_reg *r);
159		159
160	#endif /* __ARM_KVM_COPROC_LOCAL_H__ */	160	#endif /* __ARM_KVM_COPROC_LOCAL_H__ */

arch/arm/kvm/coproc_a15.c+1−1

@@ -34,7 +34,7 @@ · 33 unmodified lines
34	static const struct coproc_reg a15_regs[] = {	34	static const struct coproc_reg a15_regs[] = {
35	/* SCTLR: swapped by interrupt.S. */	35	/* SCTLR: swapped by interrupt.S. */
36	{ CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32,	36	{ CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32,
37	access_sctlr, reset_val, c1_SCTLR, 0x00C50078 },	37	access_vm_reg, reset_val, c1_SCTLR, 0x00C50078 },
38	};	38	};
39		39
40	static struct kvm_coproc_target_table a15_target_table = {	40	static struct kvm_coproc_target_table a15_target_table = {

arch/arm/kvm/coproc_a7.c+1−1

@@ -37,7 +37,7 @@ · 36 unmodified lines
37	static const struct coproc_reg a7_regs[] = {	37	static const struct coproc_reg a7_regs[] = {
38	/* SCTLR: swapped by interrupt.S. */	38	/* SCTLR: swapped by interrupt.S. */
39	{ CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32,	39	{ CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32,
40	access_sctlr, reset_val, c1_SCTLR, 0x00C50878 },	40	access_vm_reg, reset_val, c1_SCTLR, 0x00C50878 },
41	};	41	};
42		42
43	static struct kvm_coproc_target_table a7_target_table = {	43	static struct kvm_coproc_target_table a7_target_table = {

arch/arm/kvm/mmu.c+144−20

@@ -58,6 +58,26 @@ static void kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa) · 57 unmodified lines
58	kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, kvm, ipa);	58	kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, kvm, ipa);
59	}	59	}
60		60
		61	/*
		62	* D-Cache management functions. They take the page table entries by
		63	* value, as they are flushing the cache using the kernel mapping (or
		64	* kmap on 32bit).
		65	*/
		66	static void kvm_flush_dcache_pte(pte_t pte)
		67	{
		68	__kvm_flush_dcache_pte(pte);
		69	}
		70
		71	static void kvm_flush_dcache_pmd(pmd_t pmd)
		72	{
		73	__kvm_flush_dcache_pmd(pmd);
		74	}
		75
		76	static void kvm_flush_dcache_pud(pud_t pud)
		77	{
		78	__kvm_flush_dcache_pud(pud);
		79	}
		80
61	static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,	81	static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
62	int min, int max)	82	int min, int max)
63	{	83	{
@@ -119,6 +139,26 @@ static void clear_pmd_entry(struct kvm kvm, pmd_t pmd, phys_addr_t addr) · 55 unmodified lines
119	put_page(virt_to_page(pmd));	139	put_page(virt_to_page(pmd));
120	}	140	}
121		141
		142	/*
		143	* Unmapping vs dcache management:
		144	*
		145	* If a guest maps certain memory pages as uncached, all writes will
		146	* bypass the data cache and go directly to RAM. However, the CPUs
		147	* can still speculate reads (not writes) and fill cache lines with
		148	* data.
		149	*
		150	* Those cache lines will be clean cache lines though, so a
		151	* clean+invalidate operation is equivalent to an invalidate
		152	* operation, because no cache lines are marked dirty.
		153	*
		154	* Those clean cache lines could be filled prior to an uncached write
		155	* by the guest, and the cache coherent IO subsystem would therefore
		156	* end up writing old data to disk.
		157	*
		158	* This is why right after unmapping a page/section and invalidating
		159	* the corresponding TLBs, we call kvm_flush_dcache_p*() to make sure
		160	* the IO subsystem will never hit in the cache.
		161	*/
122	static void unmap_ptes(struct kvm kvm, pmd_t pmd,	162	static void unmap_ptes(struct kvm kvm, pmd_t pmd,
123	phys_addr_t addr, phys_addr_t end)	163	phys_addr_t addr, phys_addr_t end)
124	{	164	{
@@ -128,9 +168,16 @@ static void unmap_ptes(struct kvm kvm, pmd_t pmd, · 3 unmodified lines
128	start_pte = pte = pte_offset_kernel(pmd, addr);	168	start_pte = pte = pte_offset_kernel(pmd, addr);
129	do {	169	do {
130	if (!pte_none(*pte)) {	170	if (!pte_none(*pte)) {
		171	pte_t old_pte = *pte;
		172
131	kvm_set_pte(pte, __pte(0));	173	kvm_set_pte(pte, __pte(0));
132	put_page(virt_to_page(pte));
133	kvm_tlb_flush_vmid_ipa(kvm, addr);	174	kvm_tlb_flush_vmid_ipa(kvm, addr);
		175
		176	/* No need to invalidate the cache for device mappings */
		177	if ((pte_val(old_pte) & PAGE_S2_DEVICE) != PAGE_S2_DEVICE)
		178	kvm_flush_dcache_pte(old_pte);
		179
		180	put_page(virt_to_page(pte));
134	}	181	}
135	} while (pte++, addr += PAGE_SIZE, addr != end);	182	} while (pte++, addr += PAGE_SIZE, addr != end);
136		183
@@ -149,8 +196,13 @@ static void unmap_pmds(struct kvm kvm, pud_t pud, · 12 unmodified lines
149	next = kvm_pmd_addr_end(addr, end);	196	next = kvm_pmd_addr_end(addr, end);
150	if (!pmd_none(*pmd)) {	197	if (!pmd_none(*pmd)) {
151	if (kvm_pmd_huge(*pmd)) {	198	if (kvm_pmd_huge(*pmd)) {
		199	pmd_t old_pmd = *pmd;
		200
152	pmd_clear(pmd);	201	pmd_clear(pmd);
153	kvm_tlb_flush_vmid_ipa(kvm, addr);	202	kvm_tlb_flush_vmid_ipa(kvm, addr);
		203
		204	kvm_flush_dcache_pmd(old_pmd);
		205
154	put_page(virt_to_page(pmd));	206	put_page(virt_to_page(pmd));
155	} else {	207	} else {
156	unmap_ptes(kvm, pmd, addr, next);	208	unmap_ptes(kvm, pmd, addr, next);
@@ -173,8 +225,13 @@ static void unmap_puds(struct kvm kvm, pgd_t pgd, · 16 unmodified lines
173	next = kvm_pud_addr_end(addr, end);	225	next = kvm_pud_addr_end(addr, end);
174	if (!pud_none(*pud)) {	226	if (!pud_none(*pud)) {
175	if (pud_huge(*pud)) {	227	if (pud_huge(*pud)) {
		228	pud_t old_pud = *pud;
		229
176	pud_clear(pud);	230	pud_clear(pud);
177	kvm_tlb_flush_vmid_ipa(kvm, addr);	231	kvm_tlb_flush_vmid_ipa(kvm, addr);
		232
		233	kvm_flush_dcache_pud(old_pud);
		234
178	put_page(virt_to_page(pud));	235	put_page(virt_to_page(pud));
179	} else {	236	} else {
180	unmap_pmds(kvm, pud, addr, next);	237	unmap_pmds(kvm, pud, addr, next);
@@ -209,10 +266,9 @@ static void stage2_flush_ptes(struct kvm kvm, pmd_t pmd, · 28 unmodified lines
209		266
210	pte = pte_offset_kernel(pmd, addr);	267	pte = pte_offset_kernel(pmd, addr);
211	do {	268	do {
212	if (!pte_none(*pte)) {	269	if (!pte_none(*pte) &&
213	hva_t hva = gfn_to_hva(kvm, addr >> PAGE_SHIFT);	270	(pte_val(*pte) & PAGE_S2_DEVICE) != PAGE_S2_DEVICE)
214	kvm_flush_dcache_to_poc((void*)hva, PAGE_SIZE);	271	kvm_flush_dcache_pte(*pte);
215	}
216	} while (pte++, addr += PAGE_SIZE, addr != end);	272	} while (pte++, addr += PAGE_SIZE, addr != end);
217	}	273	}
218		274
@@ -226,12 +282,10 @@ static void stage2_flush_pmds(struct kvm kvm, pud_t pud, · 7 unmodified lines
226	do {	282	do {
227	next = kvm_pmd_addr_end(addr, end);	283	next = kvm_pmd_addr_end(addr, end);
228	if (!pmd_none(*pmd)) {	284	if (!pmd_none(*pmd)) {
229	if (kvm_pmd_huge(*pmd)) {	285	if (kvm_pmd_huge(*pmd))
230	hva_t hva = gfn_to_hva(kvm, addr >> PAGE_SHIFT);	286	kvm_flush_dcache_pmd(*pmd);
231	kvm_flush_dcache_to_poc((void*)hva, PMD_SIZE);	287	else
232	} else {
233	stage2_flush_ptes(kvm, pmd, addr, next);	288	stage2_flush_ptes(kvm, pmd, addr, next);
234	}
235	}	289	}
236	} while (pmd++, addr = next, addr != end);	290	} while (pmd++, addr = next, addr != end);
237	}	291	}
@@ -246,12 +300,10 @@ static void stage2_flush_puds(struct kvm kvm, pgd_t pgd, · 8 unmodified lines
246	do {	300	do {
247	next = kvm_pud_addr_end(addr, end);	301	next = kvm_pud_addr_end(addr, end);
248	if (!pud_none(*pud)) {	302	if (!pud_none(*pud)) {
249	if (pud_huge(*pud)) {	303	if (pud_huge(*pud))
250	hva_t hva = gfn_to_hva(kvm, addr >> PAGE_SHIFT);	304	kvm_flush_dcache_pud(*pud);
251	kvm_flush_dcache_to_poc((void*)hva, PUD_SIZE);	305	else
252	} else {
253	stage2_flush_pmds(kvm, pud, addr, next);	306	stage2_flush_pmds(kvm, pud, addr, next);
254	}
255	}	307	}
256	} while (pud++, addr = next, addr != end);	308	} while (pud++, addr = next, addr != end);
257	}	309	}
@@ -278,7 +330,7 @@ static void stage2_flush_memslot(struct kvm *kvm, · 20 unmodified lines
278	* Go through the stage 2 page tables and invalidate any cache lines	330	* Go through the stage 2 page tables and invalidate any cache lines
279	* backing memory already mapped to the VM.	331	* backing memory already mapped to the VM.
280	*/	332	*/
281	void stage2_flush_vm(struct kvm *kvm)	333	static void stage2_flush_vm(struct kvm *kvm)
282	{	334	{
283	struct kvm_memslots *slots;	335	struct kvm_memslots *slots;
284	struct kvm_memory_slot *memslot;	336	struct kvm_memory_slot *memslot;
@@ -905,6 +957,12 @@ static bool kvm_is_device_pfn(unsigned long pfn) · 620 unmodified lines
905	return !pfn_valid(pfn);	957	return !pfn_valid(pfn);
906	}	958	}
907		959
		960	static void coherent_cache_guest_page(struct kvm_vcpu *vcpu, pfn_t pfn,
		961	unsigned long size, bool uncached)
		962	{
		963	__coherent_cache_guest_page(vcpu, pfn, size, uncached);
		964	}
		965
908	static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,	966	static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
909	struct kvm_memory_slot *memslot, unsigned long hva,	967	struct kvm_memory_slot *memslot, unsigned long hva,
910	unsigned long fault_status)	968	unsigned long fault_status)
@@ -994,8 +1052,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, · 83 unmodified lines
994	kvm_set_s2pmd_writable(&new_pmd);	1052	kvm_set_s2pmd_writable(&new_pmd);
995	kvm_set_pfn_dirty(pfn);	1053	kvm_set_pfn_dirty(pfn);
996	}	1054	}
997	coherent_cache_guest_page(vcpu, hva & PMD_MASK, PMD_SIZE,	1055	coherent_cache_guest_page(vcpu, pfn, PMD_SIZE, fault_ipa_uncached);
998	fault_ipa_uncached);
999	ret = stage2_set_pmd_huge(kvm, memcache, fault_ipa, &new_pmd);	1056	ret = stage2_set_pmd_huge(kvm, memcache, fault_ipa, &new_pmd);
1000	} else {	1057	} else {
1001	pte_t new_pte = pfn_pte(pfn, mem_type);	1058	pte_t new_pte = pfn_pte(pfn, mem_type);
@@ -1003,8 +1060,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, · 1 unmodified line
1003	kvm_set_s2pte_writable(&new_pte);	1060	kvm_set_s2pte_writable(&new_pte);
1004	kvm_set_pfn_dirty(pfn);	1061	kvm_set_pfn_dirty(pfn);
1005	}	1062	}
1006	coherent_cache_guest_page(vcpu, hva, PAGE_SIZE,	1063	coherent_cache_guest_page(vcpu, pfn, PAGE_SIZE, fault_ipa_uncached);
1007	fault_ipa_uncached);
1008	ret = stage2_set_pte(kvm, memcache, fault_ipa, &new_pte,	1064	ret = stage2_set_pte(kvm, memcache, fault_ipa, &new_pte,
1009	pgprot_val(mem_type) == pgprot_val(PAGE_S2_DEVICE));	1065	pgprot_val(mem_type) == pgprot_val(PAGE_S2_DEVICE));
1010	}	1066	}
@@ -1411,3 +1467,71 @@ void kvm_arch_flush_shadow_memslot(struct kvm *kvm, · 400 unmodified lines
1411	unmap_stage2_range(kvm, gpa, size);	1467	unmap_stage2_range(kvm, gpa, size);
1412	spin_unlock(&kvm->mmu_lock);	1468	spin_unlock(&kvm->mmu_lock);
1413	}	1469	}
		1470
		1471	/*
		1472	* See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
		1473	*
		1474	* Main problems:
		1475	* - S/W ops are local to a CPU (not broadcast)
		1476	* - We have line migration behind our back (speculation)
		1477	* - System caches don't support S/W at all (damn!)
		1478	*
		1479	* In the face of the above, the best we can do is to try and convert
		1480	* S/W ops to VA ops. Because the guest is not allowed to infer the
		1481	* S/W to PA mapping, it can only use S/W to nuke the whole cache,
		1482	* which is a rather good thing for us.
		1483	*
		1484	* Also, it is only used when turning caches on/off ("The expected
		1485	* usage of the cache maintenance instructions that operate by set/way
		1486	* is associated with the cache maintenance instructions associated
		1487	* with the powerdown and powerup of caches, if this is required by
		1488	* the implementation.").
		1489	*
		1490	* We use the following policy:
		1491	*
		1492	* - If we trap a S/W operation, we enable VM trapping to detect
		1493	* caches being turned on/off, and do a full clean.
		1494	*
		1495	* - We flush the caches on both caches being turned on and off.
		1496	*
		1497	* - Once the caches are enabled, we stop trapping VM ops.
		1498	*/
		1499	void kvm_set_way_flush(struct kvm_vcpu *vcpu)
		1500	{
		1501	unsigned long hcr = vcpu_get_hcr(vcpu);
		1502
		1503	/*
		1504	* If this is the first time we do a S/W operation
		1505	* (i.e. HCR_TVM not set) flush the whole memory, and set the
		1506	* VM trapping.
		1507	*
		1508	* Otherwise, rely on the VM trapping to wait for the MMU +
		1509	* Caches to be turned off. At that point, we'll be able to
		1510	* clean the caches again.
		1511	*/
		1512	if (!(hcr & HCR_TVM)) {
		1513	trace_kvm_set_way_flush(*vcpu_pc(vcpu),
		1514	vcpu_has_cache_enabled(vcpu));
		1515	stage2_flush_vm(vcpu->kvm);
		1516	vcpu_set_hcr(vcpu, hcr \| HCR_TVM);
		1517	}
		1518	}
		1519
		1520	void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled)
		1521	{
		1522	bool now_enabled = vcpu_has_cache_enabled(vcpu);
		1523
		1524	/*
		1525	* If switching the MMU+caches on, need to invalidate the caches.
		1526	* If switching it off, need to clean the caches.
		1527	* Clean + invalidate does the trick always.
		1528	*/
		1529	if (now_enabled != was_enabled)
		1530	stage2_flush_vm(vcpu->kvm);
		1531
		1532	/* Caches are now on, stop trapping VM ops (until a S/W op) */
		1533	if (now_enabled)
		1534	vcpu_set_hcr(vcpu, vcpu_get_hcr(vcpu) & ~HCR_TVM);
		1535
		1536	trace_kvm_toggle_cache(*vcpu_pc(vcpu), was_enabled, now_enabled);
		1537	}

arch/arm/kvm/trace.h+39−0

@@ -223,6 +223,45 @@ TRACE_EVENT(kvm_hvc, · 222 unmodified lines
223	__entry->vcpu_pc, __entry->r0, __entry->imm)	223	__entry->vcpu_pc, __entry->r0, __entry->imm)
224	);	224	);
225		225
		226	TRACE_EVENT(kvm_set_way_flush,
		227	TP_PROTO(unsigned long vcpu_pc, bool cache),
		228	TP_ARGS(vcpu_pc, cache),
		229
		230	TP_STRUCT__entry(
		231	__field( unsigned long, vcpu_pc )
		232	__field( bool, cache )
		233	),
		234
		235	TP_fast_assign(
		236	__entry->vcpu_pc = vcpu_pc;
		237	__entry->cache = cache;
		238	),
		239
		240	TP_printk("S/W flush at 0x%016lx (cache %s)",
		241	__entry->vcpu_pc, __entry->cache ? "on" : "off")
		242	);
		243
		244	TRACE_EVENT(kvm_toggle_cache,
		245	TP_PROTO(unsigned long vcpu_pc, bool was, bool now),
		246	TP_ARGS(vcpu_pc, was, now),
		247
		248	TP_STRUCT__entry(
		249	__field( unsigned long, vcpu_pc )
		250	__field( bool, was )
		251	__field( bool, now )
		252	),
		253
		254	TP_fast_assign(
		255	__entry->vcpu_pc = vcpu_pc;
		256	__entry->was = was;
		257	__entry->now = now;
		258	),
		259
		260	TP_printk("VM op at 0x%016lx (cache was %s, now %s)",
		261	__entry->vcpu_pc, __entry->was ? "on" : "off",
		262	__entry->now ? "on" : "off")
		263	);
		264
226	#endif /* _TRACE_KVM_H */	265	#endif /* _TRACE_KVM_H */
227		266
228	#undef TRACE_INCLUDE_PATH	267	#undef TRACE_INCLUDE_PATH

arch/arm/mach-mvebu/coherency.c+7−0

@@ -189,6 +189,13 @@ static void __init armada_375_380_coherency_init(struct device_node *np) · 188 unmodified lines
189	coherency_cpu_base = of_iomap(np, 0);	189	coherency_cpu_base = of_iomap(np, 0);
190	arch_ioremap_caller = armada_pcie_wa_ioremap_caller;	190	arch_ioremap_caller = armada_pcie_wa_ioremap_caller;
191		191
		192	/*
		193	* We should switch the PL310 to I/O coherency mode only if
		194	* I/O coherency is actually enabled.
		195	*/
		196	if (!coherency_available())
		197	return;
		198
192	/*	199	/*
193	* Add the PL310 property "arm,io-coherent". This makes sure the	200	* Add the PL310 property "arm,io-coherent". This makes sure the
194	* outer sync operation is not used, which allows to	201	* outer sync operation is not used, which allows to

arch/arm/mach-shmobile/board-ape6evm.c+20−0

@@ -18,6 +18,8 @@ · 17 unmodified lines
18	#include <linux/gpio_keys.h>	18	#include <linux/gpio_keys.h>
19	#include <linux/input.h>	19	#include <linux/input.h>
20	#include <linux/interrupt.h>	20	#include <linux/interrupt.h>
		21	#include <linux/irqchip.h>
		22	#include <linux/irqchip/arm-gic.h>
21	#include <linux/kernel.h>	23	#include <linux/kernel.h>
22	#include <linux/mfd/tmio.h>	24	#include <linux/mfd/tmio.h>
23	#include <linux/mmc/host.h>	25	#include <linux/mmc/host.h>
@@ -273,6 +275,22 @@ static void __init ape6evm_add_standard_devices(void) · 249 unmodified lines
273	sizeof(ape6evm_leds_pdata));	275	sizeof(ape6evm_leds_pdata));
274	}	276	}
275		277
		278	static void __init ape6evm_legacy_init_time(void)
		279	{
		280	/* Do not invoke DT-based timers via clocksource_of_init() */
		281	}
		282
		283	static void __init ape6evm_legacy_init_irq(void)
		284	{
		285	void __iomem *gic_dist_base = ioremap_nocache(0xf1001000, 0x1000);
		286	void __iomem *gic_cpu_base = ioremap_nocache(0xf1002000, 0x1000);
		287
		288	gic_init(0, 29, gic_dist_base, gic_cpu_base);
		289
		290	/* Do not invoke DT-based interrupt code via irqchip_init() */
		291	}
		292
		293
276	static const char *ape6evm_boards_compat_dt[] __initdata = {	294	static const char *ape6evm_boards_compat_dt[] __initdata = {
277	"renesas,ape6evm",	295	"renesas,ape6evm",
278	NULL,	296	NULL,
@@ -280,7 +298,9 @@ static const char *ape6evm_boards_compat_dt[] __initdata = { · 1 unmodified line
280		298
281	DT_MACHINE_START(APE6EVM_DT, "ape6evm")	299	DT_MACHINE_START(APE6EVM_DT, "ape6evm")
282	.init_early = shmobile_init_delay,	300	.init_early = shmobile_init_delay,
		301	.init_irq = ape6evm_legacy_init_irq,
283	.init_machine = ape6evm_add_standard_devices,	302	.init_machine = ape6evm_add_standard_devices,
284	.init_late = shmobile_init_late,	303	.init_late = shmobile_init_late,
285	.dt_compat = ape6evm_boards_compat_dt,	304	.dt_compat = ape6evm_boards_compat_dt,
		305	.init_time = ape6evm_legacy_init_time,
286	MACHINE_END	306	MACHINE_END

arch/arm/mach-shmobile/board-lager.c+13−0

 #include <linux/input.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/arm-gic.h>
 #include <linux/kernel.h>
 #include <linux/leds.h>
 #include <linux/mfd/tmio.h>
 					  lager_ksz8041_fixup);
 }
+static void __init lager_legacy_init_irq(void)
+{
+	void __iomem *gic_dist_base = ioremap_nocache(0xf1001000, 0x1000);
+	void __iomem *gic_cpu_base = ioremap_nocache(0xf1002000, 0x1000);
+	gic_init(0, 29, gic_dist_base, gic_cpu_base);
+	/* Do not invoke DT-based interrupt code via irqchip_init() */
+}
 static const char * const lager_boards_compat_dt[] __initconst = {
 	"renesas,lager",
 	NULL,
 DT_MACHINE_START(LAGER_DT, "lager")
 	.smp		= smp_ops(r8a7790_smp_ops),
 	.init_early	= shmobile_init_delay,
+	.init_irq	= lager_legacy_init_irq,
 	.init_time	= rcar_gen2_timer_init,
 	.init_machine	= lager_init,
 	.init_late	= shmobile_init_late,

arch/arm/mach-shmobile/setup-rcar-gen2.c+2−0

 #ifdef CONFIG_COMMON_CLK
 	rcar_gen2_clocks_init(mode);
 #endif
+#ifdef CONFIG_ARCH_SHMOBILE_MULTI
 	clocksource_of_init();
+#endif
 }
 struct memory_reserve_config {

arch/arm/mach-shmobile/timer.c+12−0

@@ -70,6 +70,18 @@ void __init shmobile_init_delay(void) · 69 unmodified lines
70	if (!max_freq)	70	if (!max_freq)
71	return;	71	return;
72		72
		73	#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
		74	/* Non-multiplatform r8a73a4 SoC cannot use arch timer due
		75	* to GIC being initialized from C and arch timer via DT */
		76	if (of_machine_is_compatible("renesas,r8a73a4"))
		77	has_arch_timer = false;
		78
		79	/* Non-multiplatform r8a7790 SoC cannot use arch timer due
		80	* to GIC being initialized from C and arch timer via DT */
		81	if (of_machine_is_compatible("renesas,r8a7790"))
		82	has_arch_timer = false;
		83	#endif
		84
73	if (!has_arch_timer \|\| !IS_ENABLED(CONFIG_ARM_ARCH_TIMER)) {	85	if (!has_arch_timer \|\| !IS_ENABLED(CONFIG_ARM_ARCH_TIMER)) {
74	if (is_a7_a8_a9)	86	if (is_a7_a8_a9)
75	shmobile_setup_delay_hz(max_freq, 1, 3);	87	shmobile_setup_delay_hz(max_freq, 1, 3);

arch/arm/mm/dma-mapping.c+38−15

 }
 EXPORT_SYMBOL_GPL(arm_iommu_release_mapping);
+static int __arm_iommu_attach_device(struct device *dev,
+				     struct dma_iommu_mapping *mapping)
+{
+	int err;
+	err = iommu_attach_device(mapping->domain, dev);
+	if (err)
+		return err;
+	kref_get(&mapping->kref);
+	dev->archdata.mapping = mapping;
+	pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev));
+	return 0;
+}
 /**
  * arm_iommu_attach_device
  * @dev: valid struct device pointer
  * @mapping: io address space mapping structure (returned from
  *	arm_iommu_create_mapping)
  *
- * Attaches specified io address space mapping to the provided device,
+ * Attaches specified io address space mapping to the provided device.
+ * This replaces the dma operations (dma_map_ops pointer) with the
+ * IOMMU aware version.
+ *
  * More than one client might be attached to the same io address space
  * mapping.
  */
 {
 	int err;
-	err = iommu_attach_device(mapping->domain, dev);
+	err = __arm_iommu_attach_device(dev, mapping);
 	if (err)
 		return err;
-	kref_get(&mapping->kref);
+	set_dma_ops(dev, &iommu_ops);
-	dev->archdata.mapping = mapping;
-	pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev));
 	return 0;
 }
 EXPORT_SYMBOL_GPL(arm_iommu_attach_device);
-/**
+static void __arm_iommu_detach_device(struct device *dev)
- * arm_iommu_detach_device
- * @dev: valid struct device pointer
- *
- * Detaches the provided device from a previously attached map.
- */
-void arm_iommu_detach_device(struct device *dev)
 {
 	struct dma_iommu_mapping *mapping;
 	pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev));
 }
+/**
+ * arm_iommu_detach_device
+ * @dev: valid struct device pointer
+ *
+ * Detaches the provided device from a previously attached map.
+ * This voids the dma operations (dma_map_ops pointer)
+ */
+void arm_iommu_detach_device(struct device *dev)
+{
+	__arm_iommu_detach_device(dev);
+	set_dma_ops(dev, NULL);
+}
 EXPORT_SYMBOL_GPL(arm_iommu_detach_device);
 static struct dma_map_ops *arm_get_iommu_dma_map_ops(bool coherent)
 		return false;
 	}
-	if (arm_iommu_attach_device(dev, mapping)) {
+	if (__arm_iommu_attach_device(dev, mapping)) {
 		pr_warn("Failed to attached device %s to IOMMU_mapping\n",
 				dev_name(dev));
 		arm_iommu_release_mapping(mapping);
 {
 	struct dma_iommu_mapping *mapping = dev->archdata.mapping;
-	arm_iommu_detach_device(dev);
+	__arm_iommu_detach_device(dev);
 	arm_iommu_release_mapping(mapping);
 }

arch/arm64/include/asm/kvm_emulate.h+10−0

@@ -45,6 +45,16 @@ static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu) · 44 unmodified lines
45	vcpu->arch.hcr_el2 &= ~HCR_RW;	45	vcpu->arch.hcr_el2 &= ~HCR_RW;
46	}	46	}
47		47
		48	static inline unsigned long vcpu_get_hcr(struct kvm_vcpu *vcpu)
		49	{
		50	return vcpu->arch.hcr_el2;
		51	}
		52
		53	static inline void vcpu_set_hcr(struct kvm_vcpu *vcpu, unsigned long hcr)
		54	{
		55	vcpu->arch.hcr_el2 = hcr;
		56	}
		57
48	static inline unsigned long vcpu_pc(const struct kvm_vcpu vcpu)	58	static inline unsigned long vcpu_pc(const struct kvm_vcpu vcpu)
49	{	59	{
50	return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pc;	60	return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pc;

arch/arm64/include/asm/kvm_host.h+0−3

 	 * Anything that is not used directly from assembly code goes
 	 * here.
 	 */
-	/* dcache set/way operation pending */
-	int last_pcpu;
-	cpumask_t require_dcache_flush;
 	/* Don't run the guest */
 	bool pause;

arch/arm64/include/asm/kvm_mmu.h+28−6

 	return (vcpu_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101;
 }
-static inline void coherent_cache_guest_page(struct kvm_vcpu *vcpu, hva_t hva,
+static inline void __coherent_cache_guest_page(struct kvm_vcpu *vcpu, pfn_t pfn,
-					     unsigned long size,
+					       unsigned long size,
-					     bool ipa_uncached)
+					       bool ipa_uncached)
 {
+	void *va = page_address(pfn_to_page(pfn));
 	if (!vcpu_has_cache_enabled(vcpu) || ipa_uncached)
-		kvm_flush_dcache_to_poc((void *)hva, size);
+		kvm_flush_dcache_to_poc(va, size);
 	if (!icache_is_aliasing()) {		/* PIPT */
-		flush_icache_range(hva, hva + size);
+		flush_icache_range((unsigned long)va,
+				   (unsigned long)va + size);
 	} else if (!icache_is_aivivt()) {	/* non ASID-tagged VIVT */
 		/* any kind of VIPT cache */
 		__flush_icache_all();
 	}
 }
+static inline void __kvm_flush_dcache_pte(pte_t pte)
+{
+	struct page *page = pte_page(pte);
+	kvm_flush_dcache_to_poc(page_address(page), PAGE_SIZE);
+}
+static inline void __kvm_flush_dcache_pmd(pmd_t pmd)
+{
+	struct page *page = pmd_page(pmd);
+	kvm_flush_dcache_to_poc(page_address(page), PMD_SIZE);
+}
+static inline void __kvm_flush_dcache_pud(pud_t pud)
+{
+	struct page *page = pud_page(pud);
+	kvm_flush_dcache_to_poc(page_address(page), PUD_SIZE);
+}
 #define kvm_virt_to_phys(x)		__virt_to_phys((unsigned long)(x))
-void stage2_flush_vm(struct kvm *kvm);
+void kvm_set_way_flush(struct kvm_vcpu *vcpu);
+void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled);
 #endif /* __ASSEMBLY__ */
 #endif /* __ARM64_KVM_MMU_H__ */

arch/arm64/kvm/sys_regs.c+10−65

@@ -69,68 +69,31 @@ static u32 get_ccsidr(u32 csselr) · 68 unmodified lines
69	return ccsidr;	69	return ccsidr;
70	}	70	}
71		71
72	static void do_dc_cisw(u32 val)	72	/*
73	{	73	* See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
74	asm volatile("dc cisw, %x0" : : "r" (val));	74	*/
75	dsb(ish);
76	}
77
78	static void do_dc_csw(u32 val)
79	{
80	asm volatile("dc csw, %x0" : : "r" (val));
81	dsb(ish);
82	}
83
84	/* See note at ARM ARM B1.14.4 */
85	static bool access_dcsw(struct kvm_vcpu *vcpu,	75	static bool access_dcsw(struct kvm_vcpu *vcpu,
86	const struct sys_reg_params *p,	76	const struct sys_reg_params *p,
87	const struct sys_reg_desc *r)	77	const struct sys_reg_desc *r)
88	{	78	{
89	unsigned long val;
90	int cpu;
91
92	if (!p->is_write)	79	if (!p->is_write)
93	return read_from_write_only(vcpu, p);	80	return read_from_write_only(vcpu, p);
94		81
95	cpu = get_cpu();	82	kvm_set_way_flush(vcpu);
96
97	cpumask_setall(&vcpu->arch.require_dcache_flush);
98	cpumask_clear_cpu(cpu, &vcpu->arch.require_dcache_flush);
99
100	/* If we were already preempted, take the long way around */
101	if (cpu != vcpu->arch.last_pcpu) {
102	flush_cache_all();
103	goto done;
104	}
105
106	val = *vcpu_reg(vcpu, p->Rt);
107
108	switch (p->CRm) {
109	case 6: /* Upgrade DCISW to DCCISW, as per HCR.SWIO */
110	case 14: /* DCCISW */
111	do_dc_cisw(val);
112	break;
113
114	case 10: /* DCCSW */
115	do_dc_csw(val);
116	break;
117	}
118
119	done:
120	put_cpu();
121
122	return true;	83	return true;
123	}	84	}
124		85
125	/*	86	/*
126	* Generic accessor for VM registers. Only called as long as HCR_TVM	87	* Generic accessor for VM registers. Only called as long as HCR_TVM
127	* is set.	88	* is set. If the guest enables the MMU, we stop trapping the VM
		89	* sys_regs and leave it in complete control of the caches.
128	*/	90	*/
129	static bool access_vm_reg(struct kvm_vcpu *vcpu,	91	static bool access_vm_reg(struct kvm_vcpu *vcpu,
130	const struct sys_reg_params *p,	92	const struct sys_reg_params *p,
131	const struct sys_reg_desc *r)	93	const struct sys_reg_desc *r)
132	{	94	{
133	unsigned long val;	95	unsigned long val;
		96	bool was_enabled = vcpu_has_cache_enabled(vcpu);
134		97
135	BUG_ON(!p->is_write);	98	BUG_ON(!p->is_write);
136		99
@@ -143,25 +106,7 @@ static bool access_vm_reg(struct kvm_vcpu *vcpu, · 6 unmodified lines
143	vcpu_cp15_64_low(vcpu, r->reg) = val & 0xffffffffUL;	106	vcpu_cp15_64_low(vcpu, r->reg) = val & 0xffffffffUL;
144	}	107	}
145		108
146	return true;	109	kvm_toggle_cache(vcpu, was_enabled);
147	}
148
149	/*
150	* SCTLR_EL1 accessor. Only called as long as HCR_TVM is set. If the
151	* guest enables the MMU, we stop trapping the VM sys_regs and leave
152	* it in complete control of the caches.
153	*/
154	static bool access_sctlr(struct kvm_vcpu *vcpu,
155	const struct sys_reg_params *p,
156	const struct sys_reg_desc *r)
157	{
158	access_vm_reg(vcpu, p, r);
159
160	if (vcpu_has_cache_enabled(vcpu)) { /* MMU+Caches enabled? */
161	vcpu->arch.hcr_el2 &= ~HCR_TVM;
162	stage2_flush_vm(vcpu->kvm);
163	}
164
165	return true;	110	return true;
166	}	111	}
167		112
@@ -377,7 +322,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { · 209 unmodified lines
377	NULL, reset_mpidr, MPIDR_EL1 },	322	NULL, reset_mpidr, MPIDR_EL1 },
378	/* SCTLR_EL1 */	323	/* SCTLR_EL1 */
379	{ Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),	324	{ Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
380	access_sctlr, reset_val, SCTLR_EL1, 0x00C50078 },	325	access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
381	/* CPACR_EL1 */	326	/* CPACR_EL1 */
382	{ Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b010),	327	{ Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b010),
383	NULL, reset_val, CPACR_EL1, 0 },	328	NULL, reset_val, CPACR_EL1, 0 },
@@ -657,7 +602,7 @@ static const struct sys_reg_desc cp14_64_regs[] = { · 273 unmodified lines
657	* register).	602	* register).
658	*/	603	*/
659	static const struct sys_reg_desc cp15_regs[] = {	604	static const struct sys_reg_desc cp15_regs[] = {
660	{ Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_sctlr, NULL, c1_SCTLR },	605	{ Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR },
661	{ Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },	606	{ Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
662	{ Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },	607	{ Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
663	{ Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },	608	{ Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },

arch/avr32/mm/fault.c+2−0

 	if (unlikely(fault & VM_FAULT_ERROR)) {
 		if (fault & VM_FAULT_OOM)
 			goto out_of_memory;
+		else if (fault & VM_FAULT_SIGSEGV)
+			goto bad_area;
 		else if (fault & VM_FAULT_SIGBUS)
 			goto do_sigbus;
 		BUG();

arch/cris/mm/fault.c+2−0

 	if (unlikely(fault & VM_FAULT_ERROR)) {
 		if (fault & VM_FAULT_OOM)
 			goto out_of_memory;
+		else if (fault & VM_FAULT_SIGSEGV)
+			goto bad_area;
 		else if (fault & VM_FAULT_SIGBUS)
 			goto do_sigbus;
 		BUG();

arch/frv/mm/fault.c+2−0

 	if (unlikely(fault & VM_FAULT_ERROR)) {
 		if (fault & VM_FAULT_OOM)
 			goto out_of_memory;
+		else if (fault & VM_FAULT_SIGSEGV)
+			goto bad_area;
 		else if (fault & VM_FAULT_SIGBUS)
 			goto do_sigbus;
 		BUG();

arch/ia64/mm/fault.c+2−0

 		 */
 		if (fault & VM_FAULT_OOM) {
 			goto out_of_memory;
+		} else if (fault & VM_FAULT_SIGSEGV) {
+			goto bad_area;
 		} else if (fault & VM_FAULT_SIGBUS) {
 			signal = SIGBUS;
 			goto bad_area;

arch/m32r/mm/fault.c+2−0

 	if (unlikely(fault & VM_FAULT_ERROR)) {
 		if (fault & VM_FAULT_OOM)
 			goto out_of_memory;
+		else if (fault & VM_FAULT_SIGSEGV)
+			goto bad_area;
 		else if (fault & VM_FAULT_SIGBUS)
 			goto do_sigbus;
 		BUG();

arch/m68k/mm/fault.c+2−0

 	if (unlikely(fault & VM_FAULT_ERROR)) {
 		if (fault & VM_FAULT_OOM)
 			goto out_of_memory;
+		else if (fault & VM_FAULT_SIGSEGV)
+			goto map_err;
 		else if (fault & VM_FAULT_SIGBUS)
 			goto bus_err;
 		BUG();

arch/metag/mm/fault.c+2−0

 	if (unlikely(fault & VM_FAULT_ERROR)) {
 		if (fault & VM_FAULT_OOM)
 			goto out_of_memory;
+		else if (fault & VM_FAULT_SIGSEGV)
+			goto bad_area;
 		else if (fault & VM_FAULT_SIGBUS)
 			goto do_sigbus;
 		BUG();

arch/microblaze/mm/fault.c+2−0

 	if (unlikely(fault & VM_FAULT_ERROR)) {
 		if (fault & VM_FAULT_OOM)
 			goto out_of_memory;
+		else if (fault & VM_FAULT_SIGSEGV)
+			goto bad_area;
 		else if (fault & VM_FAULT_SIGBUS)
 			goto do_sigbus;
 		BUG();

arch/mips/mm/fault.c+2−0

 	if (unlikely(fault & VM_FAULT_ERROR)) {
 		if (fault & VM_FAULT_OOM)
 			goto out_of_memory;
+		else if (fault & VM_FAULT_SIGSEGV)
+			goto bad_area;
 		else if (fault & VM_FAULT_SIGBUS)
 			goto do_sigbus;
 		BUG();

arch/mn10300/mm/fault.c+2−0

 	if (unlikely(fault & VM_FAULT_ERROR)) {
 		if (fault & VM_FAULT_OOM)
 			goto out_of_memory;
+		else if (fault & VM_FAULT_SIGSEGV)
+			goto bad_area;
 		else if (fault & VM_FAULT_SIGBUS)
 			goto do_sigbus;
 		BUG();

arch/nios2/mm/fault.c+2−0

 	if (unlikely(fault & VM_FAULT_ERROR)) {
 		if (fault & VM_FAULT_OOM)
 			goto out_of_memory;
+		else if (fault & VM_FAULT_SIGSEGV)
+			goto bad_area;
 		else if (fault & VM_FAULT_SIGBUS)
 			goto do_sigbus;
 		BUG();

arch/openrisc/mm/fault.c+2−0

 	if (unlikely(fault & VM_FAULT_ERROR)) {
 		if (fault & VM_FAULT_OOM)
 			goto out_of_memory;
+		else if (fault & VM_FAULT_SIGSEGV)
+			goto bad_area;
 		else if (fault & VM_FAULT_SIGBUS)
 			goto do_sigbus;
 		BUG();

arch/parisc/mm/fault.c+2−0

 		 */
 		if (fault & VM_FAULT_OOM)
 			goto out_of_memory;
+		else if (fault & VM_FAULT_SIGSEGV)
+			goto bad_area;
 		else if (fault & VM_FAULT_SIGBUS)
 			goto bad_area;
 		BUG();

arch/powerpc/mm/copro_fault.c+1−1

@@ -76,7 +76,7 @@ int copro_handle_mm_fault(struct mm_struct *mm, unsigned long ea, · 75 unmodified lines
76	if (*flt & VM_FAULT_OOM) {	76	if (*flt & VM_FAULT_OOM) {
77	ret = -ENOMEM;	77	ret = -ENOMEM;
78	goto out_unlock;	78	goto out_unlock;
79	} else if (*flt & VM_FAULT_SIGBUS) {	79	} else if (*flt & (VM_FAULT_SIGBUS \| VM_FAULT_SIGSEGV)) {
80	ret = -EFAULT;	80	ret = -EFAULT;
81	goto out_unlock;	81	goto out_unlock;
82	}	82	}

arch/powerpc/mm/fault.c+2−0

 	 */
 	fault = handle_mm_fault(mm, vma, address, flags);
 	if (unlikely(fault & (VM_FAULT_RETRY|VM_FAULT_ERROR))) {
+		if (fault & VM_FAULT_SIGSEGV)
+			goto bad_area;
 		rc = mm_fault_error(regs, address, fault);
 		if (rc >= MM_FAULT_RETURN)
 			goto bail;

arch/powerpc/platforms/powernv/setup.c+1−1

@@ -304,7 +304,7 @@ int pnv_save_sprs_for_winkle(void) · 303 unmodified lines
304	* all cpus at boot. Get these reg values of current cpu and use the	304	* all cpus at boot. Get these reg values of current cpu and use the
305	* same accross all cpus.	305	* same accross all cpus.
306	*/	306	*/
307	uint64_t lpcr_val = mfspr(SPRN_LPCR);	307	uint64_t lpcr_val = mfspr(SPRN_LPCR) & ~(u64)LPCR_PECE1;
308	uint64_t hid0_val = mfspr(SPRN_HID0);	308	uint64_t hid0_val = mfspr(SPRN_HID0);
309	uint64_t hid1_val = mfspr(SPRN_HID1);	309	uint64_t hid1_val = mfspr(SPRN_HID1);
310	uint64_t hid4_val = mfspr(SPRN_HID4);	310	uint64_t hid4_val = mfspr(SPRN_HID4);

arch/powerpc/xmon/xmon.c+1−0

@@ -337,6 +337,7 @@ static inline void disable_surveillance(void) · 336 unmodified lines
337	args.token = rtas_token("set-indicator");	337	args.token = rtas_token("set-indicator");
338	if (args.token == RTAS_UNKNOWN_SERVICE)	338	if (args.token == RTAS_UNKNOWN_SERVICE)
339	return;	339	return;
		340	args.token = cpu_to_be32(args.token);
340	args.nargs = cpu_to_be32(3);	341	args.nargs = cpu_to_be32(3);
341	args.nret = cpu_to_be32(1);	342	args.nret = cpu_to_be32(1);
342	args.rets = &args.args[3];	343	args.rets = &args.args[3];

arch/s390/mm/fault.c+6−0

 				do_no_context(regs);
 			else
 				pagefault_out_of_memory();
+		} else if (fault & VM_FAULT_SIGSEGV) {
+			/* Kernel mode? Handle exceptions or die */
+			if (!user_mode(regs))
+				do_no_context(regs);
+			else
+				do_sigsegv(regs, SEGV_MAPERR);
 		} else if (fault & VM_FAULT_SIGBUS) {
 			/* Kernel mode? Handle exceptions or die */
 			if (!user_mode(regs))

arch/score/mm/fault.c+2−0

 	if (unlikely(fault & VM_FAULT_ERROR)) {
 		if (fault & VM_FAULT_OOM)
 			goto out_of_memory;
+		else if (fault & VM_FAULT_SIGSEGV)
+			goto bad_area;
 		else if (fault & VM_FAULT_SIGBUS)
 			goto do_sigbus;
 		BUG();

arch/sh/mm/fault.c+2−0

 	} else {
 		if (fault & VM_FAULT_SIGBUS)
 			do_sigbus(regs, error_code, address);
+		else if (fault & VM_FAULT_SIGSEGV)
+			bad_area(regs, error_code, address);
 		else
 			BUG();
 	}

arch/sparc/mm/fault_32.c+2−0

 	if (unlikely(fault & VM_FAULT_ERROR)) {
 		if (fault & VM_FAULT_OOM)
 			goto out_of_memory;
+		else if (fault & VM_FAULT_SIGSEGV)
+			goto bad_area;
 		else if (fault & VM_FAULT_SIGBUS)
 			goto do_sigbus;
 		BUG();

arch/sparc/mm/fault_64.c+2−0

 	if (unlikely(fault & VM_FAULT_ERROR)) {
 		if (fault & VM_FAULT_OOM)
 			goto out_of_memory;
+		else if (fault & VM_FAULT_SIGSEGV)
+			goto bad_area;
 		else if (fault & VM_FAULT_SIGBUS)
 			goto do_sigbus;
 		BUG();

arch/tile/mm/fault.c+2−0

 	if (unlikely(fault & VM_FAULT_ERROR)) {
 		if (fault & VM_FAULT_OOM)
 			goto out_of_memory;
+		else if (fault & VM_FAULT_SIGSEGV)
+			goto bad_area;
 		else if (fault & VM_FAULT_SIGBUS)
 			goto do_sigbus;
 		BUG();

arch/um/kernel/trap.c+2−0

 		if (unlikely(fault & VM_FAULT_ERROR)) {
 			if (fault & VM_FAULT_OOM) {
 				goto out_of_memory;
+			} else if (fault & VM_FAULT_SIGSEGV) {
+				goto out;
 			} else if (fault & VM_FAULT_SIGBUS) {
 				err = -EACCES;
 				goto out;

arch/x86/boot/compressed/Makefile+1−1

@@ -90,7 +90,7 @@ suffix-$(CONFIG_KERNEL_LZO) := lzo · 89 unmodified lines
90	suffix-$(CONFIG_KERNEL_LZ4) := lz4	90	suffix-$(CONFIG_KERNEL_LZ4) := lz4
91		91
92	RUN_SIZE = $(shell $(OBJDUMP) -h vmlinux \| \	92	RUN_SIZE = $(shell $(OBJDUMP) -h vmlinux \| \
93	perl $(srctree)/arch/x86/tools/calc_run_size.pl)	93	$(CONFIG_SHELL) $(srctree)/arch/x86/tools/calc_run_size.sh)
94	quiet_cmd_mkpiggy = MKPIGGY $@	94	quiet_cmd_mkpiggy = MKPIGGY $@
95	cmd_mkpiggy = $(obj)/mkpiggy $< $(RUN_SIZE) > $@ \|\| ( rm -f $@ ; false )	95	cmd_mkpiggy = $(obj)/mkpiggy $< $(RUN_SIZE) > $@ \|\| ( rm -f $@ ; false )
96		96

arch/x86/kernel/cpu/perf_event_intel.c+1−0

@@ -2431,6 +2431,7 @@ __init int intel_pmu_init(void) · 2430 unmodified lines
2431	break;	2431	break;
2432		2432
2433	case 55: /* 22nm Atom "Silvermont" */	2433	case 55: /* 22nm Atom "Silvermont" */
		2434	case 76: /* 14nm Atom "Airmont" */
2434	case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */	2435	case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
2435	memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,	2436	memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
2436	sizeof(hw_cache_event_ids));	2437	sizeof(hw_cache_event_ids));

arch/x86/kernel/cpu/perf_event_intel_rapl.c+1−1

@@ -142,7 +142,7 @@ static inline u64 rapl_scale(u64 v) · 141 unmodified lines
142	* or use ldexp(count, -32).	142	* or use ldexp(count, -32).
143	* Watts = Joules/Time delta	143	* Watts = Joules/Time delta
144	*/	144	*/
145	return v << (32 - __this_cpu_read(rapl_pmu->hw_unit));	145	return v << (32 - __this_cpu_read(rapl_pmu)->hw_unit);
146	}	146	}
147		147
148	static u64 rapl_event_update(struct perf_event *event)	148	static u64 rapl_event_update(struct perf_event *event)

arch/x86/kernel/cpu/perf_event_intel_uncore.c+2−7

 	box->phys_id = phys_id;
 	box->pci_dev = pdev;
 	box->pmu = pmu;
-	uncore_box_init(box);
 	pci_set_drvdata(pdev, box);
 	raw_spin_lock(&uncore_box_lock);
 			pmu = &type->pmus[j];
 			box = *per_cpu_ptr(pmu->box, cpu);
 			/* called by uncore_cpu_init? */
-			if (box && box->phys_id >= 0) {
+			if (box && box->phys_id >= 0)
-				uncore_box_init(box);
 				continue;
-			}
 			for_each_online_cpu(k) {
 				exist = *per_cpu_ptr(pmu->box, k);
 				}
 			}
-			if (box) {
+			if (box)
 				box->phys_id = phys_id;
-				uncore_box_init(box);
-			}
 		}
 	}
 	return 0;

arch/x86/kernel/cpu/perf_event_intel_uncore.h+10−8

 	return box->pmu->type->num_counters;
 }
+static inline void uncore_box_init(struct intel_uncore_box *box)
+{
+	if (!test_and_set_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
+		if (box->pmu->type->ops->init_box)
+			box->pmu->type->ops->init_box(box);
+	}
+}
 static inline void uncore_disable_box(struct intel_uncore_box *box)
 {
 	if (box->pmu->type->ops->disable_box)
 static inline void uncore_enable_box(struct intel_uncore_box *box)
 {
+	uncore_box_init(box);
 	if (box->pmu->type->ops->enable_box)
 		box->pmu->type->ops->enable_box(box);
 }
 	return box->pmu->type->ops->read_counter(box, event);
 }
-static inline void uncore_box_init(struct intel_uncore_box *box)
-{
-	if (!test_and_set_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
-		if (box->pmu->type->ops->init_box)
-			box->pmu->type->ops->init_box(box);
-	}
-}
 static inline bool uncore_box_is_fake(struct intel_uncore_box *box)
 {
 	return (box->phys_id < 0);

arch/x86/kvm/lapic.c+3−0

@@ -192,6 +192,9 @@ static void recalculate_apic_map(struct kvm *kvm) · 191 unmodified lines
192	u16 cid, lid;	192	u16 cid, lid;
193	u32 ldr, aid;	193	u32 ldr, aid;
194		194
		195	if (!kvm_apic_present(vcpu))
		196	continue;
		197
195	aid = kvm_apic_id(apic);	198	aid = kvm_apic_id(apic);
196	ldr = kvm_apic_get_reg(apic, APIC_LDR);	199	ldr = kvm_apic_get_reg(apic, APIC_LDR);
197	cid = apic_cluster_id(new, ldr);	200	cid = apic_cluster_id(new, ldr);

arch/x86/mm/fault.c+2−0

 		if (fault & (VM_FAULT_SIGBUS|VM_FAULT_HWPOISON|
 			     VM_FAULT_HWPOISON_LARGE))
 			do_sigbus(regs, error_code, address, fault);
+		else if (fault & VM_FAULT_SIGSEGV)
+			bad_area_nosemaphore(regs, error_code, address);
 		else
 			BUG();
 	}

arch/x86/tools/calc_run_size.pl+0−39

@@ -1,39 +0,0 @@
1	#!/usr/bin/perl
2	#
3	# Calculate the amount of space needed to run the kernel, including room for
4	# the .bss and .brk sections.
5	#
6	# Usage:
7	# objdump -h a.out \| perl calc_run_size.pl
8	use strict;
9
10	my $mem_size = 0;
11	my $file_offset = 0;
12
13	my $sections=" *[0-9]+ \.(?:bss\|brk) +";
14	while (<>) {
15	if (/^$sections([0-9a-f]+) +(?:[0-9a-f]+ +){2}([0-9a-f]+)/) {
16	my $size = hex($1);
17	my $offset = hex($2);
18	$mem_size += $size;
19	if ($file_offset == 0) {
20	$file_offset = $offset;
21	} elsif ($file_offset != $offset) {
22	# BFD linker shows the same file offset in ELF.
23	# Gold linker shows them as consecutive.
24	next if ($file_offset + $mem_size == $offset + $size);
25
26	printf STDERR "file_offset: 0x%lx\n", $file_offset;
27	printf STDERR "mem_size: 0x%lx\n", $mem_size;
28	printf STDERR "offset: 0x%lx\n", $offset;
29	printf STDERR "size: 0x%lx\n", $size;
30
31	die ".bss and .brk are non-contiguous\n";
32	}
33	}
34	}
35
36	if ($file_offset == 0) {
37	die "Never found .bss or .brk file offset\n";
38	}
39	printf("%d\n", $mem_size + $file_offset);

arch/x86/tools/calc_run_size.sh+42−0

@@ -0,0 +1,42 @@
	1	#!/bin/sh
	2	#
	3	# Calculate the amount of space needed to run the kernel, including room for
	4	# the .bss and .brk sections.
	5	#
	6	# Usage:
	7	# objdump -h a.out \| sh calc_run_size.sh
	8
	9	NUM='$[0-9a-fA-F][ \t]$'
	10	OUT=$(sed -n 's/^[ \t0-9].b[sr][sk][ \t]'"$NUM$NUM$NUM$NUM"'.*/\1\4/p')
	11	if [ -z "$OUT" ] ; then
	12	echo "Never found .bss or .brk file offset" >&2
	13	exit 1
	14	fi
	15
	16	OUT=$(echo ${OUT# })
	17	sizeA=$(printf "%d" 0x${OUT%% *})
	18	OUT=${OUT#* }
	19	offsetA=$(printf "%d" 0x${OUT%% *})
	20	OUT=${OUT#* }
	21	sizeB=$(printf "%d" 0x${OUT%% *})
	22	OUT=${OUT#* }
	23	offsetB=$(printf "%d" 0x${OUT%% *})
	24
	25	run_size=$(( $offsetA + $sizeA + $sizeB ))
	26
	27	# BFD linker shows the same file offset in ELF.
	28	if [ "$offsetA" -ne "$offsetB" ] ; then
	29	# Gold linker shows them as consecutive.
	30	endB=$(( $offsetB + $sizeB ))
	31	if [ "$endB" != "$run_size" ] ; then
	32	printf "sizeA: 0x%x\n" $sizeA >&2
	33	printf "offsetA: 0x%x\n" $offsetA >&2
	34	printf "sizeB: 0x%x\n" $sizeB >&2
	35	printf "offsetB: 0x%x\n" $offsetB >&2
	36	echo ".bss and .brk are non-contiguous" >&2
	37	exit 1
	38	fi
	39	fi
	40
	41	printf "%d\n" $run_size
	42	exit 0

arch/xtensa/mm/fault.c+2−0

 	if (unlikely(fault & VM_FAULT_ERROR)) {
 		if (fault & VM_FAULT_OOM)
 			goto out_of_memory;
+		else if (fault & VM_FAULT_SIGSEGV)
+			goto bad_area;
 		else if (fault & VM_FAULT_SIGBUS)
 			goto do_sigbus;
 		BUG();

drivers/Kconfig+0−2

@@ -134,8 +134,6 @@ source "drivers/staging/Kconfig" · 133 unmodified lines
134		134
135	source "drivers/platform/Kconfig"	135	source "drivers/platform/Kconfig"
136		136
137	source "drivers/soc/Kconfig"
138
139	source "drivers/clk/Kconfig"	137	source "drivers/clk/Kconfig"
140		138
141	source "drivers/hwspinlock/Kconfig"	139	source "drivers/hwspinlock/Kconfig"

drivers/block/rbd.c+7−18

@@ -2098,32 +2098,26 @@ static void rbd_dev_parent_put(struct rbd_device *rbd_dev) · 2097 unmodified lines
2098	* If an image has a non-zero parent overlap, get a reference to its	2098	* If an image has a non-zero parent overlap, get a reference to its
2099	* parent.	2099	* parent.
2100	*	2100	*
2101	* We must get the reference before checking for the overlap to
2102	* coordinate properly with zeroing the parent overlap in
2103	* rbd_dev_v2_parent_info() when an image gets flattened. We
2104	* drop it again if there is no overlap.
2105	*
2106	* Returns true if the rbd device has a parent with a non-zero	2101	* Returns true if the rbd device has a parent with a non-zero
2107	* overlap and a reference for it was successfully taken, or	2102	* overlap and a reference for it was successfully taken, or
2108	* false otherwise.	2103	* false otherwise.
2109	*/	2104	*/
2110	static bool rbd_dev_parent_get(struct rbd_device *rbd_dev)	2105	static bool rbd_dev_parent_get(struct rbd_device *rbd_dev)
2111	{	2106	{
2112	int counter;	2107	int counter = 0;
2113		2108
2114	if (!rbd_dev->parent_spec)	2109	if (!rbd_dev->parent_spec)
2115	return false;	2110	return false;
2116		2111
2117	counter = atomic_inc_return_safe(&rbd_dev->parent_ref);	2112	down_read(&rbd_dev->header_rwsem);
2118	if (counter > 0 && rbd_dev->parent_overlap)	2113	if (rbd_dev->parent_overlap)
2119	return true;	2114	counter = atomic_inc_return_safe(&rbd_dev->parent_ref);
2120		2115	up_read(&rbd_dev->header_rwsem);
2121	/* Image was flattened, but parent is not yet torn down */
2122		2116
2123	if (counter < 0)	2117	if (counter < 0)
2124	rbd_warn(rbd_dev, "parent reference overflow");	2118	rbd_warn(rbd_dev, "parent reference overflow");
2125		2119
2126	return false;	2120	return counter > 0;
2127	}	2121	}
2128		2122
2129	/*	2123	/*
@@ -4239,7 +4233,6 @@ static int rbd_dev_v2_parent_info(struct rbd_device *rbd_dev) · 2109 unmodified lines
4239	*/	4233	*/
4240	if (rbd_dev->parent_overlap) {	4234	if (rbd_dev->parent_overlap) {
4241	rbd_dev->parent_overlap = 0;	4235	rbd_dev->parent_overlap = 0;
4242	smp_mb();
4243	rbd_dev_parent_put(rbd_dev);	4236	rbd_dev_parent_put(rbd_dev);
4244	pr_info("%s: clone image has been flattened\n",	4237	pr_info("%s: clone image has been flattened\n",
4245	rbd_dev->disk->disk_name);	4238	rbd_dev->disk->disk_name);
@@ -4285,7 +4278,6 @@ static int rbd_dev_v2_parent_info(struct rbd_device *rbd_dev) · 39 unmodified lines
4285	* treat it specially.	4278	* treat it specially.
4286	*/	4279	*/
4287	rbd_dev->parent_overlap = overlap;	4280	rbd_dev->parent_overlap = overlap;
4288	smp_mb();
4289	if (!overlap) {	4281	if (!overlap) {
4290		4282
4291	/* A null parent_spec indicates it's the initial probe */	4283	/* A null parent_spec indicates it's the initial probe */
@@ -5114,10 +5106,7 @@ static void rbd_dev_unprobe(struct rbd_device *rbd_dev) · 822 unmodified lines
5114	{	5106	{
5115	struct rbd_image_header *header;	5107	struct rbd_image_header *header;
5116		5108
5117	/* Drop parent reference unless it's already been done (or none) */	5109	rbd_dev_parent_put(rbd_dev);
5118
5119	if (rbd_dev->parent_overlap)
5120	rbd_dev_parent_put(rbd_dev);
5121		5110
5122	/* Free dynamic fields from the header, then zero it out */	5111	/* Free dynamic fields from the header, then zero it out */
5123		5112

drivers/gpu/drm/amd/amdkfd/kfd_device.c+3−3

 #include <linux/slab.h>
 #include "kfd_priv.h"
 #include "kfd_device_queue_manager.h"
+#include "kfd_pm4_headers.h"
 #define MQD_SIZE_ALIGNED 768
 	kfd->shared_resources = *gpu_resources;
 	/* calculate max size of mqds needed for queues */
-	size = max_num_of_processes *
+	size = max_num_of_queues_per_device *
-		max_num_of_queues_per_process *
+			kfd->device_info->mqd_size_aligned;
-		kfd->device_info->mqd_size_aligned;
 	/* add another 512KB for all other allocations on gart */
 	size += 512 * 1024;

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c+76−2

@@ -183,6 +183,13 @@ static int create_queue_nocpsch(struct device_queue_manager *dqm, · 182 unmodified lines
183		183
184	mutex_lock(&dqm->lock);	184	mutex_lock(&dqm->lock);
185		185
		186	if (dqm->total_queue_count >= max_num_of_queues_per_device) {
		187	pr_warn("amdkfd: Can't create new usermode queue because %d queues were already created\n",
		188	dqm->total_queue_count);
		189	mutex_unlock(&dqm->lock);
		190	return -EPERM;
		191	}
		192
186	if (list_empty(&qpd->queues_list)) {	193	if (list_empty(&qpd->queues_list)) {
187	retval = allocate_vmid(dqm, qpd, q);	194	retval = allocate_vmid(dqm, qpd, q);
188	if (retval != 0) {	195	if (retval != 0) {
@@ -207,6 +214,14 @@ static int create_queue_nocpsch(struct device_queue_manager *dqm, · 18 unmodified lines
207	list_add(&q->list, &qpd->queues_list);	214	list_add(&q->list, &qpd->queues_list);
208	dqm->queue_count++;	215	dqm->queue_count++;
209		216
		217	/*
		218	* Unconditionally increment this counter, regardless of the queue's
		219	* type or whether the queue is active.
		220	*/
		221	dqm->total_queue_count++;
		222	pr_debug("Total of %d queues are accountable so far\n",
		223	dqm->total_queue_count);
		224
210	mutex_unlock(&dqm->lock);	225	mutex_unlock(&dqm->lock);
211	return 0;	226	return 0;
212	}	227	}
@@ -326,6 +341,15 @@ static int destroy_queue_nocpsch(struct device_queue_manager *dqm, · 113 unmodified lines
326	if (list_empty(&qpd->queues_list))	341	if (list_empty(&qpd->queues_list))
327	deallocate_vmid(dqm, qpd, q);	342	deallocate_vmid(dqm, qpd, q);
328	dqm->queue_count--;	343	dqm->queue_count--;
		344
		345	/*
		346	* Unconditionally decrement this counter, regardless of the queue's
		347	* type
		348	*/
		349	dqm->total_queue_count--;
		350	pr_debug("Total of %d queues are accountable so far\n",
		351	dqm->total_queue_count);
		352
329	out:	353	out:
330	mutex_unlock(&dqm->lock);	354	mutex_unlock(&dqm->lock);
331	return retval;	355	return retval;
@@ -541,10 +565,14 @@ static int init_pipelines(struct device_queue_manager *dqm, · 209 unmodified lines
541		565
542	for (i = 0; i < pipes_num; i++) {	566	for (i = 0; i < pipes_num; i++) {
543	inx = i + first_pipe;	567	inx = i + first_pipe;
		568	/*
		569	* HPD buffer on GTT is allocated by amdkfd, no need to waste
		570	* space in GTT for pipelines we don't initialize
		571	*/
544	pipe_hpd_addr = dqm->pipelines_addr + i * CIK_HPD_EOP_BYTES;	572	pipe_hpd_addr = dqm->pipelines_addr + i * CIK_HPD_EOP_BYTES;
545	pr_debug("kfd: pipeline address %llX\n", pipe_hpd_addr);	573	pr_debug("kfd: pipeline address %llX\n", pipe_hpd_addr);
546	/* = log2(bytes/4)-1 */	574	/* = log2(bytes/4)-1 */
547	kfd2kgd->init_pipeline(dqm->dev->kgd, i,	575	kfd2kgd->init_pipeline(dqm->dev->kgd, inx,
548	CIK_HPD_EOP_BYTES_LOG2 - 3, pipe_hpd_addr);	576	CIK_HPD_EOP_BYTES_LOG2 - 3, pipe_hpd_addr);
549	}	577	}
550		578
@@ -560,7 +588,7 @@ static int init_scheduler(struct device_queue_manager *dqm) · 9 unmodified lines
560		588
561	pr_debug("kfd: In %s\n", __func__);	589	pr_debug("kfd: In %s\n", __func__);
562		590
563	retval = init_pipelines(dqm, get_pipes_num(dqm), KFD_DQM_FIRST_PIPE);	591	retval = init_pipelines(dqm, get_pipes_num(dqm), get_first_pipe(dqm));
564	if (retval != 0)	592	if (retval != 0)
565	return retval;	593	return retval;
566		594
@@ -752,6 +780,21 @@ static int create_kernel_queue_cpsch(struct device_queue_manager *dqm, · 185 unmodified lines
752	pr_debug("kfd: In func %s\n", __func__);	780	pr_debug("kfd: In func %s\n", __func__);
753		781
754	mutex_lock(&dqm->lock);	782	mutex_lock(&dqm->lock);
		783	if (dqm->total_queue_count >= max_num_of_queues_per_device) {
		784	pr_warn("amdkfd: Can't create new kernel queue because %d queues were already created\n",
		785	dqm->total_queue_count);
		786	mutex_unlock(&dqm->lock);
		787	return -EPERM;
		788	}
		789
		790	/*
		791	* Unconditionally increment this counter, regardless of the queue's
		792	* type or whether the queue is active.
		793	*/
		794	dqm->total_queue_count++;
		795	pr_debug("Total of %d queues are accountable so far\n",
		796	dqm->total_queue_count);
		797
755	list_add(&kq->list, &qpd->priv_queue_list);	798	list_add(&kq->list, &qpd->priv_queue_list);
756	dqm->queue_count++;	799	dqm->queue_count++;
757	qpd->is_debug = true;	800	qpd->is_debug = true;
@@ -775,6 +818,13 @@ static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm, · 17 unmodified lines
775	dqm->queue_count--;	818	dqm->queue_count--;
776	qpd->is_debug = false;	819	qpd->is_debug = false;
777	execute_queues_cpsch(dqm, false);	820	execute_queues_cpsch(dqm, false);
		821	/*
		822	* Unconditionally decrement this counter, regardless of the queue's
		823	* type.
		824	*/
		825	dqm->total_queue_count++;
		826	pr_debug("Total of %d queues are accountable so far\n",
		827	dqm->total_queue_count);
778	mutex_unlock(&dqm->lock);	828	mutex_unlock(&dqm->lock);
779	}	829	}
780		830
@@ -793,6 +843,13 @@ static int create_queue_cpsch(struct device_queue_manager dqm, struct queue q, · 12 unmodified lines
793		843
794	mutex_lock(&dqm->lock);	844	mutex_lock(&dqm->lock);
795		845
		846	if (dqm->total_queue_count >= max_num_of_queues_per_device) {
		847	pr_warn("amdkfd: Can't create new usermode queue because %d queues were already created\n",
		848	dqm->total_queue_count);
		849	retval = -EPERM;
		850	goto out;
		851	}
		852
796	mqd = dqm->get_mqd_manager(dqm, KFD_MQD_TYPE_CIK_CP);	853	mqd = dqm->get_mqd_manager(dqm, KFD_MQD_TYPE_CIK_CP);
797	if (mqd == NULL) {	854	if (mqd == NULL) {
798	mutex_unlock(&dqm->lock);	855	mutex_unlock(&dqm->lock);
@@ -810,6 +867,15 @@ static int create_queue_cpsch(struct device_queue_manager dqm, struct queue q, · 11 unmodified lines
810	retval = execute_queues_cpsch(dqm, false);	867	retval = execute_queues_cpsch(dqm, false);
811	}	868	}
812		869
		870	/*
		871	* Unconditionally increment this counter, regardless of the queue's
		872	* type or whether the queue is active.
		873	*/
		874	dqm->total_queue_count++;
		875
		876	pr_debug("Total of %d queues are accountable so far\n",
		877	dqm->total_queue_count);
		878
813	out:	879	out:
814	mutex_unlock(&dqm->lock);	880	mutex_unlock(&dqm->lock);
815	return retval;	881	return retval;
@@ -930,6 +996,14 @@ static int destroy_queue_cpsch(struct device_queue_manager *dqm, · 114 unmodified lines
930		996
931	mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj);	997	mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj);
932		998
		999	/*
		1000	* Unconditionally decrement this counter, regardless of the queue's
		1001	* type
		1002	*/
		1003	dqm->total_queue_count--;
		1004	pr_debug("Total of %d queues are accountable so far\n",
		1005	dqm->total_queue_count);
		1006
933	mutex_unlock(&dqm->lock);	1007	mutex_unlock(&dqm->lock);
934		1008
935	return 0;	1009	return 0;

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h+1−0

@@ -130,6 +130,7 @@ struct device_queue_manager { · 129 unmodified lines
130	struct list_head queues;	130	struct list_head queues;
131	unsigned int processes_count;	131	unsigned int processes_count;
132	unsigned int queue_count;	132	unsigned int queue_count;
		133	unsigned int total_queue_count;
133	unsigned int next_pipe_to_allocate;	134	unsigned int next_pipe_to_allocate;
134	unsigned int *allocated_queues;	135	unsigned int *allocated_queues;
135	unsigned int vmid_bitmap;	136	unsigned int vmid_bitmap;

drivers/gpu/drm/amd/amdkfd/kfd_module.c+8−19

 MODULE_PARM_DESC(sched_policy,
 	"Kernel cmdline parameter that defines the amdkfd scheduling policy");
-int max_num_of_processes = KFD_MAX_NUM_OF_PROCESSES_DEFAULT;
+int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
-module_param(max_num_of_processes, int, 0444);
+module_param(max_num_of_queues_per_device, int, 0444);
-MODULE_PARM_DESC(max_num_of_processes,
+MODULE_PARM_DESC(max_num_of_queues_per_device,
-	"Kernel cmdline parameter that defines the amdkfd maximum number of supported processes");
+	"Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
-int max_num_of_queues_per_process = KFD_MAX_NUM_OF_QUEUES_PER_PROCESS_DEFAULT;
-module_param(max_num_of_queues_per_process, int, 0444);
-MODULE_PARM_DESC(max_num_of_queues_per_process,
-	"Kernel cmdline parameter that defines the amdkfd maximum number of supported queues per process");
 bool kgd2kfd_init(unsigned interface_version,
 		  const struct kfd2kgd_calls *f2g,
 	}
 	/* Verify module parameters */
-	if ((max_num_of_processes < 0) ||
+	if ((max_num_of_queues_per_device < 0) ||
-		(max_num_of_processes > KFD_MAX_NUM_OF_PROCESSES)) {
+		(max_num_of_queues_per_device >
-		pr_err("kfd: max_num_of_processes must be between 0 to KFD_MAX_NUM_OF_PROCESSES\n");
+			KFD_MAX_NUM_OF_QUEUES_PER_DEVICE)) {
-		return -1;
+		pr_err("kfd: max_num_of_queues_per_device must be between 0 to KFD_MAX_NUM_OF_QUEUES_PER_DEVICE\n");
-	}
-	if ((max_num_of_queues_per_process < 0) ||
-		(max_num_of_queues_per_process >
-			KFD_MAX_NUM_OF_QUEUES_PER_PROCESS)) {
-		pr_err("kfd: max_num_of_queues_per_process must be between 0 to KFD_MAX_NUM_OF_QUEUES_PER_PROCESS\n");
 		return -1;
 	}

drivers/gpu/drm/amd/amdkfd/kfd_pasid.c+1−1

@@ -30,7 +30,7 @@ static DEFINE_MUTEX(pasid_mutex); · 29 unmodified lines
30		30
31	int kfd_pasid_init(void)	31	int kfd_pasid_init(void)
32	{	32	{
33	pasid_limit = max_num_of_processes;	33	pasid_limit = KFD_MAX_NUM_OF_PROCESSES;
34		34
35	pasid_bitmap = kcalloc(BITS_TO_LONGS(pasid_limit), sizeof(long), GFP_KERNEL);	35	pasid_bitmap = kcalloc(BITS_TO_LONGS(pasid_limit), sizeof(long), GFP_KERNEL);
36	if (!pasid_bitmap)	36	if (!pasid_bitmap)

drivers/gpu/drm/amd/amdkfd/kfd_priv.h+8−9

 #define kfd_alloc_struct(ptr_to_struct)	\
 	((typeof(ptr_to_struct)) kzalloc(sizeof(*ptr_to_struct), GFP_KERNEL))
-/* Kernel module parameter to specify maximum number of supported processes */
-extern int max_num_of_processes;
-#define KFD_MAX_NUM_OF_PROCESSES_DEFAULT 32
 #define KFD_MAX_NUM_OF_PROCESSES 512
+#define KFD_MAX_NUM_OF_QUEUES_PER_PROCESS 1024
 /*
- * Kernel module parameter to specify maximum number of supported queues
+ * Kernel module parameter to specify maximum number of supported queues per
- * per process
+ * device
  */
-extern int max_num_of_queues_per_process;
+extern int max_num_of_queues_per_device;
-#define KFD_MAX_NUM_OF_QUEUES_PER_PROCESS_DEFAULT 128
+#define KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT 4096
-#define KFD_MAX_NUM_OF_QUEUES_PER_PROCESS 1024
+#define KFD_MAX_NUM_OF_QUEUES_PER_DEVICE		\
+	(KFD_MAX_NUM_OF_PROCESSES *			\
+			KFD_MAX_NUM_OF_QUEUES_PER_PROCESS)
 #define KFD_KERNEL_QUEUE_SIZE 2048

drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c+8−4

 	pr_debug("kfd: in %s\n", __func__);
 	found = find_first_zero_bit(pqm->queue_slot_bitmap,
-			max_num_of_queues_per_process);
+			KFD_MAX_NUM_OF_QUEUES_PER_PROCESS);
 	pr_debug("kfd: the new slot id %lu\n", found);
-	if (found >= max_num_of_queues_per_process) {
+	if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) {
 		pr_info("amdkfd: Can not open more queues for process with pasid %d\n",
 				pqm->process->pasid);
 		return -ENOMEM;
 	INIT_LIST_HEAD(&pqm->queues);
 	pqm->queue_slot_bitmap =
-			kzalloc(DIV_ROUND_UP(max_num_of_queues_per_process,
+			kzalloc(DIV_ROUND_UP(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS,
 					BITS_PER_BYTE), GFP_KERNEL);
 	if (pqm->queue_slot_bitmap == NULL)
 		return -ENOMEM;
 		pqn->kq = NULL;
 		retval = dev->dqm->create_queue(dev->dqm, q, &pdd->qpd,
 						&q->properties.vmid);
+		pr_debug("DQM returned %d for create_queue\n", retval);
 		print_queue(q);
 		break;
 	case KFD_QUEUE_TYPE_DIQ:
 	}
 	if (retval != 0) {
-		pr_err("kfd: error dqm create queue\n");
+		pr_debug("Error dqm create queue\n");
 		goto err_create_queue;
 	}
 err_create_queue:
 	kfree(pqn);
 err_allocate_pqn:
+	/* check if queues list is empty unregister process from device */
 	clear_bit(*qid, pqm->queue_slot_bitmap);
+	if (list_empty(&pqm->queues))
+		dev->dqm->unregister_process(dev->dqm, &pdd->qpd);
 	return retval;
 }

drivers/gpu/drm/drm_fb_helper.c+30−0

@@ -145,6 +145,31 @@ int drm_fb_helper_add_one_connector(struct drm_fb_helper *fb_helper, struct drm_ · 144 unmodified lines
145	}	145	}
146	EXPORT_SYMBOL(drm_fb_helper_add_one_connector);	146	EXPORT_SYMBOL(drm_fb_helper_add_one_connector);
147		147
		148	static void remove_from_modeset(struct drm_mode_set *set,
		149	struct drm_connector *connector)
		150	{
		151	int i, j;
		152
		153	for (i = 0; i < set->num_connectors; i++) {
		154	if (set->connectors[i] == connector)
		155	break;
		156	}
		157
		158	if (i == set->num_connectors)
		159	return;
		160
		161	for (j = i + 1; j < set->num_connectors; j++) {
		162	set->connectors[j - 1] = set->connectors[j];
		163	}
		164	set->num_connectors--;
		165
		166	/* because i915 is pissy about this..
		167	* TODO maybe need to makes sure we set it back to !=NULL somewhere?
		168	*/
		169	if (set->num_connectors == 0)
		170	set->fb = NULL;
		171	}
		172
148	int drm_fb_helper_remove_one_connector(struct drm_fb_helper *fb_helper,	173	int drm_fb_helper_remove_one_connector(struct drm_fb_helper *fb_helper,
149	struct drm_connector *connector)	174	struct drm_connector *connector)
150	{	175	{
@@ -167,6 +192,11 @@ int drm_fb_helper_remove_one_connector(struct drm_fb_helper *fb_helper, · 16 unmodified lines
167	}	192	}
168	fb_helper->connector_count--;	193	fb_helper->connector_count--;
169	kfree(fb_helper_connector);	194	kfree(fb_helper_connector);
		195
		196	/* also cleanup dangling references to the connector: */
		197	for (i = 0; i < fb_helper->crtc_count; i++)
		198	remove_from_modeset(&fb_helper->crtc_info[i].mode_set, connector);
		199
170	return 0;	200	return 0;
171	}	201	}
172	EXPORT_SYMBOL(drm_fb_helper_remove_one_connector);	202	EXPORT_SYMBOL(drm_fb_helper_remove_one_connector);

drivers/gpu/drm/i2c/tda998x_drv.c+42−10

 struct tda998x_priv {
 	struct i2c_client *cec;
 	struct i2c_client *hdmi;
+	struct mutex mutex;
+	struct delayed_work dwork;
 	uint16_t rev;
 	uint8_t current_page;
 	int dpms;
 	uint8_t addr = REG2ADDR(reg);
 	int ret;
+	mutex_lock(&priv->mutex);
 	ret = set_page(priv, reg);
 	if (ret < 0)
-		return ret;
+		goto out;
 	ret = i2c_master_send(client, &addr, sizeof(addr));
 	if (ret < 0)
 	if (ret < 0)
 		goto fail;
-	return ret;
+	goto out;
 fail:
 	dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
+out:
+	mutex_unlock(&priv->mutex);
 	return ret;
 }
 	buf[0] = REG2ADDR(reg);
 	memcpy(&buf[1], p, cnt);
+	mutex_lock(&priv->mutex);
 	ret = set_page(priv, reg);
 	if (ret < 0)
-		return;
+		goto out;
 	ret = i2c_master_send(client, buf, cnt + 1);
 	if (ret < 0)
 		dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
+out:
+	mutex_unlock(&priv->mutex);
 }
 static int
 	uint8_t buf[] = {REG2ADDR(reg), val};
 	int ret;
+	mutex_lock(&priv->mutex);
 	ret = set_page(priv, reg);
 	if (ret < 0)
-		return;
+		goto out;
 	ret = i2c_master_send(client, buf, sizeof(buf));
 	if (ret < 0)
 		dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
+out:
+	mutex_unlock(&priv->mutex);
 }
 static void
 	uint8_t buf[] = {REG2ADDR(reg), val >> 8, val};
 	int ret;
+	mutex_lock(&priv->mutex);
 	ret = set_page(priv, reg);
 	if (ret < 0)
-		return;
+		goto out;
 	ret = i2c_master_send(client, buf, sizeof(buf));
 	if (ret < 0)
 		dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
+out:
+	mutex_unlock(&priv->mutex);
 }
 static void
 	reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
 }
+/* handle HDMI connect/disconnect */
+static void tda998x_hpd(struct work_struct *work)
+{
+	struct delayed_work *dwork = to_delayed_work(work);
+	struct tda998x_priv *priv =
+			container_of(dwork, struct tda998x_priv, dwork);
+	if (priv->encoder && priv->encoder->dev)
+		drm_kms_helper_hotplug_event(priv->encoder->dev);
+}
 /*
  * only 2 interrupts may occur: screen plug/unplug and EDID read
  */
 		priv->wq_edid_wait = 0;
 		wake_up(&priv->wq_edid);
 	} else if (cec != 0) {			/* HPD change */
-		if (priv->encoder && priv->encoder->dev)
+		schedule_delayed_work(&priv->dwork, HZ/10);
-			drm_helper_hpd_irq_event(priv->encoder->dev);
 	}
 	return IRQ_HANDLED;
 }
 	/* disable all IRQs and free the IRQ handler */
 	cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
 	reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
-	if (priv->hdmi->irq)
+	if (priv->hdmi->irq) {
 		free_irq(priv->hdmi->irq, priv);
+		cancel_delayed_work_sync(&priv->dwork);
+	}
 	i2c_unregister_device(priv->cec);
 }
 	struct device_node *np = client->dev.of_node;
 	u32 video;
 	int rev_lo, rev_hi, ret;
+	unsigned short cec_addr;
 	priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
 	priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
 	priv->current_page = 0xff;
 	priv->hdmi = client;
-	priv->cec = i2c_new_dummy(client->adapter, 0x34);
+	/* CEC I2C address bound to TDA998x I2C addr by configuration pins */
+	cec_addr = 0x34 + (client->addr & 0x03);
+	priv->cec = i2c_new_dummy(client->adapter, cec_addr);
 	if (!priv->cec)
 		return -ENODEV;
 	priv->dpms = DRM_MODE_DPMS_OFF;
+	mutex_init(&priv->mutex);	/* protect the page access */
 	/* wake up the device: */
 	cec_write(priv, REG_CEC_ENAMODS,
 			CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
 	if (client->irq) {
 		int irqf_trigger;
-		/* init read EDID waitqueue */
+		/* init read EDID waitqueue and HDP work */
 		init_waitqueue_head(&priv->wq_edid);
+		INIT_DELAYED_WORK(&priv->dwork, tda998x_hpd);
 		/* clear pending interrupts */
 		reg_read(priv, REG_INT_FLAGS_0);

drivers/gpu/drm/i915/i915_drv.c+4−10

 			} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_LPT;
 				DRM_DEBUG_KMS("Found LynxPoint PCH\n");
-				WARN_ON(!IS_HASWELL(dev));
+				WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
-				WARN_ON(IS_HSW_ULT(dev));
+				WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
-			} else if (IS_BROADWELL(dev)) {
-				dev_priv->pch_type = PCH_LPT;
-				dev_priv->pch_id =
-					INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
-				DRM_DEBUG_KMS("This is Broadwell, assuming "
-					      "LynxPoint LP PCH\n");
 			} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_LPT;
 				DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
-				WARN_ON(!IS_HASWELL(dev));
+				WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
-				WARN_ON(!IS_HSW_ULT(dev));
+				WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
 			} else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 				dev_priv->pch_type = PCH_SPT;
 				DRM_DEBUG_KMS("Found SunrisePoint PCH\n");

drivers/gpu/drm/i915/i915_drv.h+1−2

 #define IS_HSW_EARLY_SDV(dev)	(IS_HASWELL(dev) && \
 				 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
 #define IS_BDW_ULT(dev)		(IS_BROADWELL(dev) && \
-				 ((INTEL_DEVID(dev) & 0xf) == 0x2  || \
+				 ((INTEL_DEVID(dev) & 0xf) == 0x6 ||	\
-				 (INTEL_DEVID(dev) & 0xf) == 0x6 || \
 				 (INTEL_DEVID(dev) & 0xf) == 0xe))
 #define IS_BDW_GT3(dev)		(IS_BROADWELL(dev) && \
 				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)

drivers/gpu/drm/i915/i915_gem.c+13−13

 		u32 size = i915_gem_obj_ggtt_size(obj);
 		uint64_t val;
+		/* Adjust fence size to match tiled area */
+		if (obj->tiling_mode != I915_TILING_NONE) {
+			uint32_t row_size = obj->stride *
+				(obj->tiling_mode == I915_TILING_Y ? 32 : 8);
+			size = (size / row_size) * row_size;
+		}
 		val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
 				 0xfffff000) << 32;
 		val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
 	for (i = 0; i < NUM_L3_SLICES(dev); i++)
 		i915_gem_l3_remap(&dev_priv->ring[RCS], i);
-	/*
+	ret = i915_ppgtt_init_hw(dev);
-	 * XXX: Contexts should only be initialized once. Doing a switch to the
-	 * default context switch however is something we'd like to do after
-	 * reset or thaw (the latter may not actually be necessary for HW, but
-	 * goes with our code better). Context switching requires rings (for
-	 * the do_switch), but before enabling PPGTT. So don't move this.
-	 */
-	ret = i915_gem_context_enable(dev_priv);
 	if (ret && ret != -EIO) {
-		DRM_ERROR("Context enable failed %d\n", ret);
+		DRM_ERROR("PPGTT enable failed %d\n", ret);
 		i915_gem_cleanup_ringbuffer(dev);
-		return ret;
 	}
-	ret = i915_ppgtt_init_hw(dev);
+	ret = i915_gem_context_enable(dev_priv);
 	if (ret && ret != -EIO) {
-		DRM_ERROR("PPGTT enable failed %d\n", ret);
+		DRM_ERROR("Context enable failed %d\n", ret);
 		i915_gem_cleanup_ringbuffer(dev);
+		return ret;
 	}
 	return ret;

drivers/gpu/drm/i915/intel_panel.c+1−1

@@ -962,7 +962,7 @@ void intel_panel_enable_backlight(struct intel_connector *connector) · 961 unmodified lines
962		962
963	WARN_ON(panel->backlight.max == 0);	963	WARN_ON(panel->backlight.max == 0);
964		964
965	if (panel->backlight.level == 0) {	965	if (panel->backlight.level <= panel->backlight.min) {
966	panel->backlight.level = panel->backlight.max;	966	panel->backlight.level = panel->backlight.max;
967	if (panel->backlight.device)	967	if (panel->backlight.device)
968	panel->backlight.device->props.brightness =	968	panel->backlight.device->props.brightness =

drivers/gpu/drm/radeon/cik_sdma.c+0−1

@@ -816,7 +816,6 @@ void cik_sdma_vm_write_pages(struct radeon_device *rdev, · 815 unmodified lines
816	for (; ndw > 0; ndw -= 2, --count, pe += 8) {	816	for (; ndw > 0; ndw -= 2, --count, pe += 8) {
817	if (flags & R600_PTE_SYSTEM) {	817	if (flags & R600_PTE_SYSTEM) {
818	value = radeon_vm_map_gart(rdev, addr);	818	value = radeon_vm_map_gart(rdev, addr);
819	value &= 0xFFFFFFFFFFFFF000ULL;
820	} else if (flags & R600_PTE_VALID) {	819	} else if (flags & R600_PTE_VALID) {
821	value = addr;	820	value = addr;
822	} else {	821	} else {

drivers/gpu/drm/radeon/ni_dma.c+0−1

@@ -372,7 +372,6 @@ void cayman_dma_vm_write_pages(struct radeon_device *rdev, · 371 unmodified lines
372	for (; ndw > 0; ndw -= 2, --count, pe += 8) {	372	for (; ndw > 0; ndw -= 2, --count, pe += 8) {
373	if (flags & R600_PTE_SYSTEM) {	373	if (flags & R600_PTE_SYSTEM) {
374	value = radeon_vm_map_gart(rdev, addr);	374	value = radeon_vm_map_gart(rdev, addr);
375	value &= 0xFFFFFFFFFFFFF000ULL;
376	} else if (flags & R600_PTE_VALID) {	375	} else if (flags & R600_PTE_VALID) {
377	value = addr;	376	value = addr;
378	} else {	377	} else {

drivers/gpu/drm/radeon/r100.c+8−2

 		return r;
 	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 	rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
+	rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
 	rdev->asic->gart.set_page = &r100_pci_gart_set_page;
 	return radeon_gart_table_ram_alloc(rdev);
 }
 	WREG32(RADEON_AIC_HI_ADDR, 0);
 }
+uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags)
+{
+	return addr;
+}
 void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
-			    uint64_t addr, uint32_t flags)
+			    uint64_t entry)
 {
 	u32 *gtt = rdev->gart.ptr;
-	gtt[i] = cpu_to_le32(lower_32_bits(addr));
+	gtt[i] = cpu_to_le32(lower_32_bits(entry));
 }
 void r100_pci_gart_fini(struct radeon_device *rdev)

drivers/gpu/drm/radeon/r300.c+11−5

 #define R300_PTE_WRITEABLE (1 << 2)
 #define R300_PTE_READABLE  (1 << 3)
-void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i,
+uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags)
-			      uint64_t addr, uint32_t flags)
 {
-	void __iomem *ptr = rdev->gart.ptr;
 	addr = (lower_32_bits(addr) >> 8) |
 		((upper_32_bits(addr) & 0xff) << 24);
 	if (flags & RADEON_GART_PAGE_READ)
 		addr |= R300_PTE_WRITEABLE;
 	if (!(flags & RADEON_GART_PAGE_SNOOP))
 		addr |= R300_PTE_UNSNOOPED;
+	return addr;
+}
+void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i,
+			      uint64_t entry)
+{
+	void __iomem *ptr = rdev->gart.ptr;
 	/* on x86 we want this to be CPU endian, on powerpc
 	 * on powerpc without HW swappers, it'll get swapped on way
 	 * into VRAM - so no need for cpu_to_le32 on VRAM tables */
-	writel(addr, ((void __iomem *)ptr) + (i * 4));
+	writel(entry, ((void __iomem *)ptr) + (i * 4));
 }
 int rv370_pcie_gart_init(struct radeon_device *rdev)
 		DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
 	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 	rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
+	rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;
 	rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
 	return radeon_gart_table_vram_alloc(rdev);
 }

drivers/gpu/drm/radeon/radeon.h+6−3

  * Dummy page
  */
 struct radeon_dummy_page {
+	uint64_t	entry;
 	struct page	*page;
 	dma_addr_t	addr;
 };
 	unsigned			num_cpu_pages;
 	unsigned			table_size;
 	struct page			**pages;
-	dma_addr_t			*pages_addr;
+	uint64_t			*pages_entry;
 	bool				ready;
 };
 	/* gart */
 	struct {
 		void (*tlb_flush)(struct radeon_device *rdev);
+		uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
 		void (*set_page)(struct radeon_device *rdev, unsigned i,
-				 uint64_t addr, uint32_t flags);
+				 uint64_t entry);
 	} gart;
 	struct {
 		int (*init)(struct radeon_device *rdev);
 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
-#define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f))
+#define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
+#define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))

drivers/gpu/drm/radeon/radeon_asic.c+24−0

 		DRM_INFO("Forcing AGP to PCIE mode\n");
 		rdev->flags |= RADEON_IS_PCIE;
 		rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
+		rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;
 		rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
 	} else {
 		DRM_INFO("Forcing AGP to PCI mode\n");
 		rdev->flags |= RADEON_IS_PCI;
 		rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
+		rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
 		rdev->asic->gart.set_page = &r100_pci_gart_set_page;
 	}
 	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 	.mc_wait_for_idle = &r100_mc_wait_for_idle,
 	.gart = {
 		.tlb_flush = &r100_pci_gart_tlb_flush,
+		.get_page_entry = &r100_pci_gart_get_page_entry,
 		.set_page = &r100_pci_gart_set_page,
 	},
 	.ring = {
 	.mc_wait_for_idle = &r100_mc_wait_for_idle,
 	.gart = {
 		.tlb_flush = &r100_pci_gart_tlb_flush,
+		.get_page_entry = &r100_pci_gart_get_page_entry,
 		.set_page = &r100_pci_gart_set_page,
 	},
 	.ring = {
 	.mc_wait_for_idle = &r300_mc_wait_for_idle,
 	.gart = {
 		.tlb_flush = &r100_pci_gart_tlb_flush,
+		.get_page_entry = &r100_pci_gart_get_page_entry,
 		.set_page = &r100_pci_gart_set_page,
 	},
 	.ring = {
 	.mc_wait_for_idle = &r300_mc_wait_for_idle,
 	.gart = {
 		.tlb_flush = &rv370_pcie_gart_tlb_flush,
+		.get_page_entry = &rv370_pcie_gart_get_page_entry,
 		.set_page = &rv370_pcie_gart_set_page,
 	},
 	.ring = {
 	.mc_wait_for_idle = &r300_mc_wait_for_idle,
 	.gart = {
 		.tlb_flush = &rv370_pcie_gart_tlb_flush,
+		.get_page_entry = &rv370_pcie_gart_get_page_entry,
 		.set_page = &rv370_pcie_gart_set_page,
 	},
 	.ring = {
 	.mc_wait_for_idle = &rs400_mc_wait_for_idle,
 	.gart = {
 		.tlb_flush = &rs400_gart_tlb_flush,
+		.get_page_entry = &rs400_gart_get_page_entry,
 		.set_page = &rs400_gart_set_page,
 	},
 	.ring = {
 	.mc_wait_for_idle = &rs600_mc_wait_for_idle,
 	.gart = {
 		.tlb_flush = &rs600_gart_tlb_flush,
+		.get_page_entry = &rs600_gart_get_page_entry,
 		.set_page = &rs600_gart_set_page,
 	},
 	.ring = {
 	.mc_wait_for_idle = &rs690_mc_wait_for_idle,
 	.gart = {
 		.tlb_flush = &rs400_gart_tlb_flush,
+		.get_page_entry = &rs400_gart_get_page_entry,
 		.set_page = &rs400_gart_set_page,
 	},
 	.ring = {
 	.mc_wait_for_idle = &rv515_mc_wait_for_idle,
 	.gart = {
 		.tlb_flush = &rv370_pcie_gart_tlb_flush,
+		.get_page_entry = &rv370_pcie_gart_get_page_entry,
 		.set_page = &rv370_pcie_gart_set_page,
 	},
 	.ring = {
 	.mc_wait_for_idle = &r520_mc_wait_for_idle,
 	.gart = {
 		.tlb_flush = &rv370_pcie_gart_tlb_flush,
+		.get_page_entry = &rv370_pcie_gart_get_page_entry,
 		.set_page = &rv370_pcie_gart_set_page,
 	},
 	.ring = {
 	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
 	.gart = {
 		.tlb_flush = &r600_pcie_gart_tlb_flush,
+		.get_page_entry = &rs600_gart_get_page_entry,
 		.set_page = &rs600_gart_set_page,
 	},
 	.ring = {
 	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
 	.gart = {
 		.tlb_flush = &r600_pcie_gart_tlb_flush,
+		.get_page_entry = &rs600_gart_get_page_entry,
 		.set_page = &rs600_gart_set_page,
 	},
 	.ring = {
 	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
 	.gart = {
 		.tlb_flush = &r600_pcie_gart_tlb_flush,
+		.get_page_entry = &rs600_gart_get_page_entry,
 		.set_page = &rs600_gart_set_page,
 	},
 	.ring = {
 	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
 	.gart = {
 		.tlb_flush = &r600_pcie_gart_tlb_flush,
+		.get_page_entry = &rs600_gart_get_page_entry,
 		.set_page = &rs600_gart_set_page,
 	},
 	.ring = {
 	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
 	.gart = {
 		.tlb_flush = &evergreen_pcie_gart_tlb_flush,
+		.get_page_entry = &rs600_gart_get_page_entry,
 		.set_page = &rs600_gart_set_page,
 	},
 	.ring = {
 	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
 	.gart = {
 		.tlb_flush = &evergreen_pcie_gart_tlb_flush,
+		.get_page_entry = &rs600_gart_get_page_entry,
 		.set_page = &rs600_gart_set_page,
 	},
 	.ring = {
 	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
 	.gart = {
 		.tlb_flush = &evergreen_pcie_gart_tlb_flush,
+		.get_page_entry = &rs600_gart_get_page_entry,
 		.set_page = &rs600_gart_set_page,
 	},
 	.ring = {
 	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
 	.gart = {
 		.tlb_flush = &cayman_pcie_gart_tlb_flush,
+		.get_page_entry = &rs600_gart_get_page_entry,
 		.set_page = &rs600_gart_set_page,
 	},
 	.vm = {
 	.get_gpu_clock_counter = &r600_get_gpu_clock_counter,
 	.gart = {
 		.tlb_flush = &cayman_pcie_gart_tlb_flush,
+		.get_page_entry = &rs600_gart_get_page_entry,
 		.set_page = &rs600_gart_set_page,
 	},
 	.vm = {
 	.get_gpu_clock_counter = &si_get_gpu_clock_counter,
 	.gart = {
 		.tlb_flush = &si_pcie_gart_tlb_flush,
+		.get_page_entry = &rs600_gart_get_page_entry,
 		.set_page = &rs600_gart_set_page,
 	},
 	.vm = {
 	.get_gpu_clock_counter = &cik_get_gpu_clock_counter,
 	.gart = {
 		.tlb_flush = &cik_pcie_gart_tlb_flush,
+		.get_page_entry = &rs600_gart_get_page_entry,
 		.set_page = &rs600_gart_set_page,
 	},
 	.vm = {
 	.get_gpu_clock_counter = &cik_get_gpu_clock_counter,
 	.gart = {
 		.tlb_flush = &cik_pcie_gart_tlb_flush,
+		.get_page_entry = &rs600_gart_get_page_entry,
 		.set_page = &rs600_gart_set_page,
 	},
 	.vm = {

drivers/gpu/drm/radeon/radeon_asic.h+8−4

 int r100_asic_reset(struct radeon_device *rdev);
 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
 void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
+uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags);
 void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
-			    uint64_t addr, uint32_t flags);
+			    uint64_t entry);
 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
 int r100_irq_set(struct radeon_device *rdev);
 int r100_irq_process(struct radeon_device *rdev);
 				struct radeon_fence *fence);
 extern int r300_cs_parse(struct radeon_cs_parser *p);
 extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
+extern uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags);
 extern void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i,
-				     uint64_t addr, uint32_t flags);
+				     uint64_t entry);
 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
 extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
 extern void r300_set_reg_safe(struct radeon_device *rdev);
 extern int rs400_suspend(struct radeon_device *rdev);
 extern int rs400_resume(struct radeon_device *rdev);
 void rs400_gart_tlb_flush(struct radeon_device *rdev);
+uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags);
 void rs400_gart_set_page(struct radeon_device *rdev, unsigned i,
-			 uint64_t addr, uint32_t flags);
+			 uint64_t entry);
 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 int rs400_gart_init(struct radeon_device *rdev);
 void rs600_irq_disable(struct radeon_device *rdev);
 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
 void rs600_gart_tlb_flush(struct radeon_device *rdev);
+uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags);
 void rs600_gart_set_page(struct radeon_device *rdev, unsigned i,
-			 uint64_t addr, uint32_t flags);
+			 uint64_t entry);
 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 void rs600_bandwidth_update(struct radeon_device *rdev);

drivers/gpu/drm/radeon/radeon_device.c+2−0

@@ -774,6 +774,8 @@ int radeon_dummy_page_init(struct radeon_device *rdev) · 773 unmodified lines
774	rdev->dummy_page.page = NULL;	774	rdev->dummy_page.page = NULL;
775	return -ENOMEM;	775	return -ENOMEM;
776	}	776	}
		777	rdev->dummy_page.entry = radeon_gart_get_page_entry(rdev->dummy_page.addr,
		778	RADEON_GART_PAGE_DUMMY);
777	return 0;	779	return 0;
778	}	780	}
779		781

drivers/gpu/drm/radeon/radeon_gart.c+32−22

 		radeon_bo_unpin(rdev->gart.robj);
 	radeon_bo_unreserve(rdev->gart.robj);
 	rdev->gart.table_addr = gpu_addr;
+	if (!r) {
+		int i;
+		/* We might have dropped some GART table updates while it wasn't
+		 * mapped, restore all entries
+		 */
+		for (i = 0; i < rdev->gart.num_gpu_pages; i++)
+			radeon_gart_set_page(rdev, i, rdev->gart.pages_entry[i]);
+		mb();
+		radeon_gart_tlb_flush(rdev);
+	}
 	return r;
 }
 	unsigned t;
 	unsigned p;
 	int i, j;
-	u64 page_base;
 	if (!rdev->gart.ready) {
 		WARN(1, "trying to unbind memory from uninitialized GART !\n");
 	for (i = 0; i < pages; i++, p++) {
 		if (rdev->gart.pages[p]) {
 			rdev->gart.pages[p] = NULL;
-			rdev->gart.pages_addr[p] = rdev->dummy_page.addr;
-			page_base = rdev->gart.pages_addr[p];
 			for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
+				rdev->gart.pages_entry[t] = rdev->dummy_page.entry;
 				if (rdev->gart.ptr) {
-					radeon_gart_set_page(rdev, t, page_base,
+					radeon_gart_set_page(rdev, t,
-							     RADEON_GART_PAGE_DUMMY);
+							     rdev->dummy_page.entry);
 				}
-				page_base += RADEON_GPU_PAGE_SIZE;
 			}
 		}
 	}
 {
 	unsigned t;
 	unsigned p;
-	uint64_t page_base;
+	uint64_t page_base, page_entry;
 	int i, j;
 	if (!rdev->gart.ready) {
 	p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
 	for (i = 0; i < pages; i++, p++) {
-		rdev->gart.pages_addr[p] = dma_addr[i];
 		rdev->gart.pages[p] = pagelist[i];
-		if (rdev->gart.ptr) {
+		page_base = dma_addr[i];
-			page_base = rdev->gart.pages_addr[p];
+		for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
-			for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
+			page_entry = radeon_gart_get_page_entry(page_base, flags);
-				radeon_gart_set_page(rdev, t, page_base, flags);
+			rdev->gart.pages_entry[t] = page_entry;
-				page_base += RADEON_GPU_PAGE_SIZE;
+			if (rdev->gart.ptr) {
+				radeon_gart_set_page(rdev, t, page_entry);
 			}
+			page_base += RADEON_GPU_PAGE_SIZE;
 		}
 	}
 	mb();
 		radeon_gart_fini(rdev);
 		return -ENOMEM;
 	}
-	rdev->gart.pages_addr = vzalloc(sizeof(dma_addr_t) *
+	rdev->gart.pages_entry = vmalloc(sizeof(uint64_t) *
-					rdev->gart.num_cpu_pages);
+					 rdev->gart.num_gpu_pages);
-	if (rdev->gart.pages_addr == NULL) {
+	if (rdev->gart.pages_entry == NULL) {
 		radeon_gart_fini(rdev);
 		return -ENOMEM;
 	}
 	/* set GART entry to point to the dummy page by default */
-	for (i = 0; i < rdev->gart.num_cpu_pages; i++) {
+	for (i = 0; i < rdev->gart.num_gpu_pages; i++)
-		rdev->gart.pages_addr[i] = rdev->dummy_page.addr;
+		rdev->gart.pages_entry[i] = rdev->dummy_page.entry;
-	}
 	return 0;
 }
  */
 void radeon_gart_fini(struct radeon_device *rdev)
 {
-	if (rdev->gart.pages && rdev->gart.pages_addr && rdev->gart.ready) {
+	if (rdev->gart.ready) {
 		/* unbind pages */
 		radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages);
 	}
 	rdev->gart.ready = false;
 	vfree(rdev->gart.pages);
-	vfree(rdev->gart.pages_addr);
+	vfree(rdev->gart.pages_entry);
 	rdev->gart.pages = NULL;
-	rdev->gart.pages_addr = NULL;
+	rdev->gart.pages_entry = NULL;
 	radeon_dummy_page_fini(rdev);
 }

drivers/gpu/drm/radeon/radeon_kfd.c+1−1

@@ -436,7 +436,7 @@ static int kgd_init_memory(struct kgd_dev *kgd) · 435 unmodified lines
436	static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,	436	static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
437	uint32_t hpd_size, uint64_t hpd_gpu_addr)	437	uint32_t hpd_size, uint64_t hpd_gpu_addr)
438	{	438	{
439	uint32_t mec = (++pipe_id / CIK_PIPE_PER_MEC) + 1;	439	uint32_t mec = (pipe_id / CIK_PIPE_PER_MEC) + 1;
440	uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC);	440	uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC);
441		441
442	lock_srbm(kgd, mec, pipe, 0, 0);	442	lock_srbm(kgd, mec, pipe, 0, 0);

drivers/gpu/drm/radeon/radeon_vm.c+2−4

@@ -587,10 +587,8 @@ uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr) · 586 unmodified lines
587	uint64_t result;	587	uint64_t result;
588		588
589	/* page table offset */	589	/* page table offset */
590	result = rdev->gart.pages_addr[addr >> PAGE_SHIFT];	590	result = rdev->gart.pages_entry[addr >> RADEON_GPU_PAGE_SHIFT];
591		591	result &= ~RADEON_GPU_PAGE_MASK;
592	/* in case cpu page size != gpu page size*/
593	result \|= addr & (~PAGE_MASK);
594		592
595	return result;	593	return result;
596	}	594	}

drivers/gpu/drm/radeon/rs400.c+9−5

 #define RS400_PTE_WRITEABLE (1 << 2)
 #define RS400_PTE_READABLE  (1 << 3)
-void rs400_gart_set_page(struct radeon_device *rdev, unsigned i,
+uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags)
-			 uint64_t addr, uint32_t flags)
 {
 	uint32_t entry;
-	u32 *gtt = rdev->gart.ptr;
 	entry = (lower_32_bits(addr) & PAGE_MASK) |
 		((upper_32_bits(addr) & 0xff) << 4);
 		entry |= RS400_PTE_WRITEABLE;
 	if (!(flags & RADEON_GART_PAGE_SNOOP))
 		entry |= RS400_PTE_UNSNOOPED;
-	entry = cpu_to_le32(entry);
+	return entry;
-	gtt[i] = entry;
+}
+void rs400_gart_set_page(struct radeon_device *rdev, unsigned i,
+			 uint64_t entry)
+{
+	u32 *gtt = rdev->gart.ptr;
+	gtt[i] = cpu_to_le32(lower_32_bits(entry));
 }
 int rs400_mc_wait_for_idle(struct radeon_device *rdev)

drivers/gpu/drm/radeon/rs600.c+9−5

 	radeon_gart_table_vram_free(rdev);
 }
-void rs600_gart_set_page(struct radeon_device *rdev, unsigned i,
+uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags)
-			 uint64_t addr, uint32_t flags)
 {
-	void __iomem *ptr = (void *)rdev->gart.ptr;
 	addr = addr & 0xFFFFFFFFFFFFF000ULL;
 	addr |= R600_PTE_SYSTEM;
 	if (flags & RADEON_GART_PAGE_VALID)
 		addr |= R600_PTE_WRITEABLE;
 	if (flags & RADEON_GART_PAGE_SNOOP)
 		addr |= R600_PTE_SNOOPED;
-	writeq(addr, ptr + (i * 8));
+	return addr;
+}
+void rs600_gart_set_page(struct radeon_device *rdev, unsigned i,
+			 uint64_t entry)
+{
+	void __iomem *ptr = (void *)rdev->gart.ptr;
+	writeq(entry, ptr + (i * 8));
 }
 int rs600_irq_set(struct radeon_device *rdev)

drivers/gpu/drm/radeon/si_dma.c+0−1

@@ -123,7 +123,6 @@ void si_dma_vm_write_pages(struct radeon_device *rdev, · 122 unmodified lines
123	for (; ndw > 0; ndw -= 2, --count, pe += 8) {	123	for (; ndw > 0; ndw -= 2, --count, pe += 8) {
124	if (flags & R600_PTE_SYSTEM) {	124	if (flags & R600_PTE_SYSTEM) {
125	value = radeon_vm_map_gart(rdev, addr);	125	value = radeon_vm_map_gart(rdev, addr);
126	value &= 0xFFFFFFFFFFFFF000ULL;
127	} else if (flags & R600_PTE_VALID) {	126	} else if (flags & R600_PTE_VALID) {
128	value = addr;	127	value = addr;
129	} else {	128	} else {

drivers/gpu/drm/vmwgfx/vmwgfx_drv.c+5−23

 		if (unlikely(ret != 0))
 			--dev_priv->num_3d_resources;
 	} else if (unhide_svga) {
-		mutex_lock(&dev_priv->hw_mutex);
 		vmw_write(dev_priv, SVGA_REG_ENABLE,
 			  vmw_read(dev_priv, SVGA_REG_ENABLE) &
 			  ~SVGA_REG_ENABLE_HIDE);
-		mutex_unlock(&dev_priv->hw_mutex);
 	}
 	mutex_unlock(&dev_priv->release_mutex);
 	mutex_lock(&dev_priv->release_mutex);
 	if (unlikely(--dev_priv->num_3d_resources == 0))
 		vmw_release_device(dev_priv);
-	else if (hide_svga) {
+	else if (hide_svga)
-		mutex_lock(&dev_priv->hw_mutex);
 		vmw_write(dev_priv, SVGA_REG_ENABLE,
 			  vmw_read(dev_priv, SVGA_REG_ENABLE) |
 			  SVGA_REG_ENABLE_HIDE);
-		mutex_unlock(&dev_priv->hw_mutex);
-	}
 	n3d = (int32_t) dev_priv->num_3d_resources;
 	mutex_unlock(&dev_priv->release_mutex);
 	dev_priv->dev = dev;
 	dev_priv->vmw_chipset = chipset;
 	dev_priv->last_read_seqno = (uint32_t) -100;
-	mutex_init(&dev_priv->hw_mutex);
 	mutex_init(&dev_priv->cmdbuf_mutex);
 	mutex_init(&dev_priv->release_mutex);
 	mutex_init(&dev_priv->binding_mutex);
 	rwlock_init(&dev_priv->resource_lock);
 	ttm_lock_init(&dev_priv->reservation_sem);
+	spin_lock_init(&dev_priv->hw_lock);
+	spin_lock_init(&dev_priv->waiter_lock);
+	spin_lock_init(&dev_priv->cap_lock);
 	for (i = vmw_res_context; i < vmw_res_max; ++i) {
 		idr_init(&dev_priv->res_idr[i]);
 	dev_priv->enable_fb = enable_fbdev;
-	mutex_lock(&dev_priv->hw_mutex);
 	vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
 	svga_id = vmw_read(dev_priv, SVGA_REG_ID);
 	if (svga_id != SVGA_ID_2) {
 		ret = -ENOSYS;
 		DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
-		mutex_unlock(&dev_priv->hw_mutex);
 		goto out_err0;
 	}
 		dev_priv->prim_bb_mem = dev_priv->vram_size;
 	ret = vmw_dma_masks(dev_priv);
-	if (unlikely(ret != 0)) {
+	if (unlikely(ret != 0))
-		mutex_unlock(&dev_priv->hw_mutex);
 		goto out_err0;
-	}
 	/*
 	 * Limit back buffer size to VRAM size.  Remove this once
 	if (dev_priv->prim_bb_mem > dev_priv->vram_size)
 		dev_priv->prim_bb_mem = dev_priv->vram_size;
-	mutex_unlock(&dev_priv->hw_mutex);
 	vmw_print_capabilities(dev_priv->capabilities);
 	if (dev_priv->capabilities & SVGA_CAP_GMR2) {
 		if (unlikely(ret != 0))
 			return ret;
 		vmw_kms_save_vga(dev_priv);
-		mutex_lock(&dev_priv->hw_mutex);
 		vmw_write(dev_priv, SVGA_REG_TRACES, 0);
-		mutex_unlock(&dev_priv->hw_mutex);
 	}
 	if (active) {
 	if (!dev_priv->enable_fb) {
 		vmw_kms_restore_vga(dev_priv);
 		vmw_3d_resource_dec(dev_priv, true);
-		mutex_lock(&dev_priv->hw_mutex);
 		vmw_write(dev_priv, SVGA_REG_TRACES, 1);
-		mutex_unlock(&dev_priv->hw_mutex);
 	}
 	return ret;
 }
 			DRM_ERROR("Unable to clean VRAM on master drop.\n");
 		vmw_kms_restore_vga(dev_priv);
 		vmw_3d_resource_dec(dev_priv, true);
-		mutex_lock(&dev_priv->hw_mutex);
 		vmw_write(dev_priv, SVGA_REG_TRACES, 1);
-		mutex_unlock(&dev_priv->hw_mutex);
 	}
 	dev_priv->active_master = &dev_priv->fbdev_master;
 	struct drm_device *dev = pci_get_drvdata(pdev);
 	struct vmw_private *dev_priv = vmw_priv(dev);
-	mutex_lock(&dev_priv->hw_mutex);
 	vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
 	(void) vmw_read(dev_priv, SVGA_REG_ID);
-	mutex_unlock(&dev_priv->hw_mutex);
 	/**
 	 * Reclaim 3d reference held by fbdev and potentially

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h+21−4

 	uint32_t memory_size;
 	bool has_gmr;
 	bool has_mob;
-	struct mutex hw_mutex;
+	spinlock_t hw_lock;
+	spinlock_t cap_lock;
 	/*
 	 * VGA registers.
 	atomic_t marker_seq;
 	wait_queue_head_t fence_queue;
 	wait_queue_head_t fifo_queue;
-	int fence_queue_waiters; /* Protected by hw_mutex */
+	spinlock_t waiter_lock;
-	int goal_queue_waiters; /* Protected by hw_mutex */
+	int fence_queue_waiters; /* Protected by waiter_lock */
+	int goal_queue_waiters; /* Protected by waiter_lock */
 	atomic_t fifo_queue_waiters;
 	uint32_t last_read_seqno;
 	spinlock_t irq_lock;
 	return (struct vmw_master *) master->driver_priv;
 }
+/*
+ * The locking here is fine-grained, so that it is performed once
+ * for every read- and write operation. This is of course costly, but we
+ * don't perform much register access in the timing critical paths anyway.
+ * Instead we have the extra benefit of being sure that we don't forget
+ * the hw lock around register accesses.
+ */
 static inline void vmw_write(struct vmw_private *dev_priv,
 			     unsigned int offset, uint32_t value)
 {
+	unsigned long irq_flags;
+	spin_lock_irqsave(&dev_priv->hw_lock, irq_flags);
 	outl(offset, dev_priv->io_start + VMWGFX_INDEX_PORT);
 	outl(value, dev_priv->io_start + VMWGFX_VALUE_PORT);
+	spin_unlock_irqrestore(&dev_priv->hw_lock, irq_flags);
 }
 static inline uint32_t vmw_read(struct vmw_private *dev_priv,
 				unsigned int offset)
 {
-	uint32_t val;
+	unsigned long irq_flags;
+	u32 val;
+	spin_lock_irqsave(&dev_priv->hw_lock, irq_flags);
 	outl(offset, dev_priv->io_start + VMWGFX_INDEX_PORT);
 	val = inl(dev_priv->io_start + VMWGFX_VALUE_PORT);
+	spin_unlock_irqrestore(&dev_priv->hw_lock, irq_flags);
 	return val;
 }

drivers/gpu/drm/vmwgfx/vmwgfx_fence.c+2−16

 	struct vmw_private *dev_priv;
 	spinlock_t lock;
 	struct list_head fence_list;
-	struct work_struct work, ping_work;
+	struct work_struct work;
 	u32 user_fence_size;
 	u32 fence_size;
 	u32 event_fence_action_size;
 	return "svga";
 }
-static void vmw_fence_ping_func(struct work_struct *work)
-{
-	struct vmw_fence_manager *fman =
-		container_of(work, struct vmw_fence_manager, ping_work);
-	vmw_fifo_ping_host(fman->dev_priv, SVGA_SYNC_GENERIC);
-}
 static bool vmw_fence_enable_signaling(struct fence *f)
 {
 	struct vmw_fence_obj *fence =
 	if (seqno - fence->base.seqno < VMW_FENCE_WRAP)
 		return false;
-	if (mutex_trylock(&dev_priv->hw_mutex)) {
+	vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
-		vmw_fifo_ping_host_locked(dev_priv, SVGA_SYNC_GENERIC);
-		mutex_unlock(&dev_priv->hw_mutex);
-	} else
-		schedule_work(&fman->ping_work);
 	return true;
 }
 	INIT_LIST_HEAD(&fman->fence_list);
 	INIT_LIST_HEAD(&fman->cleanup_list);
 	INIT_WORK(&fman->work, &vmw_fence_work_func);
-	INIT_WORK(&fman->ping_work, &vmw_fence_ping_func);
 	fman->fifo_down = true;
 	fman->user_fence_size = ttm_round_pot(sizeof(struct vmw_user_fence));
 	fman->fence_size = ttm_round_pot(sizeof(struct vmw_fence_obj));
 	bool lists_empty;
 	(void) cancel_work_sync(&fman->work);
-	(void) cancel_work_sync(&fman->ping_work);
 	spin_lock_irqsave(&fman->lock, irq_flags);
 	lists_empty = list_empty(&fman->fence_list) &&

drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c+15−21

 		if (!dev_priv->has_mob)
 			return false;
-		mutex_lock(&dev_priv->hw_mutex);
+		spin_lock(&dev_priv->cap_lock);
 		vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_3D);
 		result = vmw_read(dev_priv, SVGA_REG_DEV_CAP);
-		mutex_unlock(&dev_priv->hw_mutex);
+		spin_unlock(&dev_priv->cap_lock);
 		return (result != 0);
 	}
 	DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT));
 	DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL));
-	mutex_lock(&dev_priv->hw_mutex);
 	dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
 	dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
 	dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
 	mb();
 	vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
-	mutex_unlock(&dev_priv->hw_mutex);
 	max = ioread32(fifo_mem + SVGA_FIFO_MAX);
 	min = ioread32(fifo_mem  + SVGA_FIFO_MIN);
 	return vmw_fifo_send_fence(dev_priv, &dummy);
 }
-void vmw_fifo_ping_host_locked(struct vmw_private *dev_priv, uint32_t reason)
+void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)
 {
 	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
+	static DEFINE_SPINLOCK(ping_lock);
+	unsigned long irq_flags;
+	/*
+	 * The ping_lock is needed because we don't have an atomic
+	 * test-and-set of the SVGA_FIFO_BUSY register.
+	 */
+	spin_lock_irqsave(&ping_lock, irq_flags);
 	if (unlikely(ioread32(fifo_mem + SVGA_FIFO_BUSY) == 0)) {
 		iowrite32(1, fifo_mem + SVGA_FIFO_BUSY);
 		vmw_write(dev_priv, SVGA_REG_SYNC, reason);
 	}
-}
+	spin_unlock_irqrestore(&ping_lock, irq_flags);
-void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)
-{
-	mutex_lock(&dev_priv->hw_mutex);
-	vmw_fifo_ping_host_locked(dev_priv, reason);
-	mutex_unlock(&dev_priv->hw_mutex);
 }
 void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
 {
 	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
-	mutex_lock(&dev_priv->hw_mutex);
 	vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
 	while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0)
 		;
 	vmw_write(dev_priv, SVGA_REG_TRACES,
 		  dev_priv->traces_state);
-	mutex_unlock(&dev_priv->hw_mutex);
 	vmw_marker_queue_takedown(&fifo->marker_queue);
 	if (likely(fifo->static_buffer != NULL)) {
 		return vmw_fifo_wait_noirq(dev_priv, bytes,
 					   interruptible, timeout);
-	mutex_lock(&dev_priv->hw_mutex);
+	spin_lock(&dev_priv->waiter_lock);
 	if (atomic_add_return(1, &dev_priv->fifo_queue_waiters) > 0) {
 		spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
 		outl(SVGA_IRQFLAG_FIFO_PROGRESS,
 		vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
 		spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
 	}
-	mutex_unlock(&dev_priv->hw_mutex);
+	spin_unlock(&dev_priv->waiter_lock);
 	if (interruptible)
 		ret = wait_event_interruptible_timeout
 	else if (likely(ret > 0))
 		ret = 0;
-	mutex_lock(&dev_priv->hw_mutex);
+	spin_lock(&dev_priv->waiter_lock);
 	if (atomic_dec_and_test(&dev_priv->fifo_queue_waiters)) {
 		spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
 		dev_priv->irq_mask &= ~SVGA_IRQFLAG_FIFO_PROGRESS;
 		vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
 		spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
 	}
-	mutex_unlock(&dev_priv->hw_mutex);
+	spin_unlock(&dev_priv->waiter_lock);
 	return ret;
 }

drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c+4−4

@@ -135,13 +135,13 @@ static int vmw_fill_compat_cap(struct vmw_private dev_priv, void bounce, · 134 unmodified lines
135	(pair_offset + max_size * sizeof(SVGA3dCapPair)) / sizeof(u32);	135	(pair_offset + max_size * sizeof(SVGA3dCapPair)) / sizeof(u32);
136	compat_cap->header.type = SVGA3DCAPS_RECORD_DEVCAPS;	136	compat_cap->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
137		137
138	mutex_lock(&dev_priv->hw_mutex);	138	spin_lock(&dev_priv->cap_lock);
139	for (i = 0; i < max_size; ++i) {	139	for (i = 0; i < max_size; ++i) {
140	vmw_write(dev_priv, SVGA_REG_DEV_CAP, i);	140	vmw_write(dev_priv, SVGA_REG_DEV_CAP, i);
141	compat_cap->pairs[i][0] = i;	141	compat_cap->pairs[i][0] = i;
142	compat_cap->pairs[i][1] = vmw_read(dev_priv, SVGA_REG_DEV_CAP);	142	compat_cap->pairs[i][1] = vmw_read(dev_priv, SVGA_REG_DEV_CAP);
143	}	143	}
144	mutex_unlock(&dev_priv->hw_mutex);	144	spin_unlock(&dev_priv->cap_lock);
145		145
146	return 0;	146	return 0;
147	}	147	}
@@ -191,12 +191,12 @@ int vmw_get_cap_3d_ioctl(struct drm_device dev, void data, · 43 unmodified lines
191	if (num > SVGA3D_DEVCAP_MAX)	191	if (num > SVGA3D_DEVCAP_MAX)
192	num = SVGA3D_DEVCAP_MAX;	192	num = SVGA3D_DEVCAP_MAX;
193		193
194	mutex_lock(&dev_priv->hw_mutex);	194	spin_lock(&dev_priv->cap_lock);
195	for (i = 0; i < num; ++i) {	195	for (i = 0; i < num; ++i) {
196	vmw_write(dev_priv, SVGA_REG_DEV_CAP, i);	196	vmw_write(dev_priv, SVGA_REG_DEV_CAP, i);
197	*bounce32++ = vmw_read(dev_priv, SVGA_REG_DEV_CAP);	197	*bounce32++ = vmw_read(dev_priv, SVGA_REG_DEV_CAP);
198	}	198	}
199	mutex_unlock(&dev_priv->hw_mutex);	199	spin_unlock(&dev_priv->cap_lock);
200	} else if (gb_objects) {	200	} else if (gb_objects) {
201	ret = vmw_fill_compat_cap(dev_priv, bounce, size);	201	ret = vmw_fill_compat_cap(dev_priv, bounce, size);
202	if (unlikely(ret != 0))	202	if (unlikely(ret != 0))

drivers/gpu/drm/vmwgfx/vmwgfx_irq.c+9−16

 static bool vmw_fifo_idle(struct vmw_private *dev_priv, uint32_t seqno)
 {
-	uint32_t busy;
-	mutex_lock(&dev_priv->hw_mutex);
+	return (vmw_read(dev_priv, SVGA_REG_BUSY) == 0);
-	busy = vmw_read(dev_priv, SVGA_REG_BUSY);
-	mutex_unlock(&dev_priv->hw_mutex);
-	return (busy == 0);
 }
 void vmw_update_seqno(struct vmw_private *dev_priv,
 void vmw_seqno_waiter_add(struct vmw_private *dev_priv)
 {
-	mutex_lock(&dev_priv->hw_mutex);
+	spin_lock(&dev_priv->waiter_lock);
 	if (dev_priv->fence_queue_waiters++ == 0) {
 		unsigned long irq_flags;
 		vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
 		spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
 	}
-	mutex_unlock(&dev_priv->hw_mutex);
+	spin_unlock(&dev_priv->waiter_lock);
 }
 void vmw_seqno_waiter_remove(struct vmw_private *dev_priv)
 {
-	mutex_lock(&dev_priv->hw_mutex);
+	spin_lock(&dev_priv->waiter_lock);
 	if (--dev_priv->fence_queue_waiters == 0) {
 		unsigned long irq_flags;
 		vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
 		spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
 	}
-	mutex_unlock(&dev_priv->hw_mutex);
+	spin_unlock(&dev_priv->waiter_lock);
 }
 void vmw_goal_waiter_add(struct vmw_private *dev_priv)
 {
-	mutex_lock(&dev_priv->hw_mutex);
+	spin_lock(&dev_priv->waiter_lock);
 	if (dev_priv->goal_queue_waiters++ == 0) {
 		unsigned long irq_flags;
 		vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
 		spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
 	}
-	mutex_unlock(&dev_priv->hw_mutex);
+	spin_unlock(&dev_priv->waiter_lock);
 }
 void vmw_goal_waiter_remove(struct vmw_private *dev_priv)
 {
-	mutex_lock(&dev_priv->hw_mutex);
+	spin_lock(&dev_priv->waiter_lock);
 	if (--dev_priv->goal_queue_waiters == 0) {
 		unsigned long irq_flags;
 		vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
 		spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
 	}
-	mutex_unlock(&dev_priv->hw_mutex);
+	spin_unlock(&dev_priv->waiter_lock);
 }
 int vmw_wait_seqno(struct vmw_private *dev_priv,
 	if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
 		return;
-	mutex_lock(&dev_priv->hw_mutex);
 	vmw_write(dev_priv, SVGA_REG_IRQMASK, 0);
-	mutex_unlock(&dev_priv->hw_mutex);
 	status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
 	outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c+0−2

@@ -1828,9 +1828,7 @@ vmw_du_connector_detect(struct drm_connector *connector, bool force) · 1827 unmodified lines
1828	struct vmw_private *dev_priv = vmw_priv(dev);	1828	struct vmw_private *dev_priv = vmw_priv(dev);
1829	struct vmw_display_unit *du = vmw_connector_to_du(connector);	1829	struct vmw_display_unit *du = vmw_connector_to_du(connector);
1830		1830
1831	mutex_lock(&dev_priv->hw_mutex);
1832	num_displays = vmw_read(dev_priv, SVGA_REG_NUM_DISPLAYS);	1831	num_displays = vmw_read(dev_priv, SVGA_REG_NUM_DISPLAYS);
1833	mutex_unlock(&dev_priv->hw_mutex);
1834		1832
1835	return ((vmw_connector_to_du(connector)->unit < num_displays &&	1833	return ((vmw_connector_to_du(connector)->unit < num_displays &&
1836	du->pref_active) ?	1834	du->pref_active) ?

drivers/i2c/busses/Kconfig+1−0

@@ -881,6 +881,7 @@ config I2C_XLR · 880 unmodified lines
881	config I2C_RCAR	881	config I2C_RCAR
882	tristate "Renesas R-Car I2C Controller"	882	tristate "Renesas R-Car I2C Controller"
883	depends on ARCH_SHMOBILE \|\| COMPILE_TEST	883	depends on ARCH_SHMOBILE \|\| COMPILE_TEST
		884	select I2C_SLAVE
884	help	885	help
885	If you say yes to this option, support will be included for the	886	If you say yes to this option, support will be included for the
886	R-Car I2C controller.	887	R-Car I2C controller.

drivers/i2c/busses/i2c-s3c2410.c+17−6

 	int ret;
 	pm_runtime_get_sync(&adap->dev);
-	clk_prepare_enable(i2c->clk);
+	ret = clk_enable(i2c->clk);
+	if (ret)
+		return ret;
 	for (retry = 0; retry < adap->retries; retry++) {
 		ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
 		if (ret != -EAGAIN) {
-			clk_disable_unprepare(i2c->clk);
+			clk_disable(i2c->clk);
 			pm_runtime_put(&adap->dev);
 			return ret;
 		}
 		udelay(100);
 	}
-	clk_disable_unprepare(i2c->clk);
+	clk_disable(i2c->clk);
 	pm_runtime_put(&adap->dev);
 	return -EREMOTEIO;
 }
 	clk_prepare_enable(i2c->clk);
 	ret = s3c24xx_i2c_init(i2c);
-	clk_disable_unprepare(i2c->clk);
+	clk_disable(i2c->clk);
 	if (ret != 0) {
 		dev_err(&pdev->dev, "I2C controller init failed\n");
 		return ret;
 		i2c->irq = ret = platform_get_irq(pdev, 0);
 		if (ret <= 0) {
 			dev_err(&pdev->dev, "cannot find IRQ\n");
+			clk_unprepare(i2c->clk);
 			return ret;
 		}
 		if (ret != 0) {
 			dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
+			clk_unprepare(i2c->clk);
 			return ret;
 		}
 	}
 	ret = s3c24xx_i2c_register_cpufreq(i2c);
 	if (ret < 0) {
 		dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
+		clk_unprepare(i2c->clk);
 		return ret;
 	}
 	if (ret < 0) {
 		dev_err(&pdev->dev, "failed to add bus to i2c core\n");
 		s3c24xx_i2c_deregister_cpufreq(i2c);
+		clk_unprepare(i2c->clk);
 		return ret;
 	}
 {
 	struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
+	clk_unprepare(i2c->clk);
 	pm_runtime_disable(&i2c->adap.dev);
 	pm_runtime_disable(&pdev->dev);
 {
 	struct platform_device *pdev = to_platform_device(dev);
 	struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
+	int ret;
 	if (!IS_ERR(i2c->sysreg))
 		regmap_write(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, i2c->sys_i2c_cfg);
-	clk_prepare_enable(i2c->clk);
+	ret = clk_enable(i2c->clk);
+	if (ret)
+		return ret;
 	s3c24xx_i2c_init(i2c);
-	clk_disable_unprepare(i2c->clk);
+	clk_disable(i2c->clk);
 	i2c->suspended = 0;
 	return 0;

drivers/i2c/busses/i2c-sh_mobile.c+11−1

 	int pos;
 	int sr;
 	bool send_stop;
+	bool stop_after_dma;
 	struct resource *res;
 	struct dma_chan *dma_tx;
 	if (pd->pos == pd->msg->len) {
 		/* Send stop if we haven't yet (DMA case) */
-		if (pd->send_stop && (iic_rd(pd, ICCR) & ICCR_BBSY))
+		if (pd->send_stop && pd->stop_after_dma)
 			i2c_op(pd, OP_TX_STOP, 0);
 		return 1;
 	}
 		real_pos = pd->pos - 2;
 		if (pd->pos == pd->msg->len) {
+			if (pd->stop_after_dma) {
+				/* Simulate PIO end condition after DMA transfer */
+				i2c_op(pd, OP_RX_STOP, 0);
+				pd->pos++;
+				break;
+			}
 			if (real_pos < 0) {
 				i2c_op(pd, OP_RX_STOP, 0);
 				break;
 	sh_mobile_i2c_dma_unmap(pd);
 	pd->pos = pd->msg->len;
+	pd->stop_after_dma = true;
 	iic_set_clr(pd, ICIC, 0, ICIC_TDMAE | ICIC_RDMAE);
 }
 		bool do_start = pd->send_stop || !i;
 		msg = &msgs[i];
 		pd->send_stop = i == num - 1 || msg->flags & I2C_M_STOP;
+		pd->stop_after_dma = false;
 		err = start_ch(pd, msg, do_start);
 		if (err)

drivers/i2c/i2c-core.c+2−0

 }
 EXPORT_SYMBOL(i2c_smbus_xfer);
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
 int i2c_slave_register(struct i2c_client *client, i2c_slave_cb_t slave_cb)
 {
 	int ret;
 	return ret;
 }
 EXPORT_SYMBOL_GPL(i2c_slave_unregister);
+#endif
 MODULE_AUTHOR("Simon G. Vogl <simon@tk.uni-linz.ac.at>");
 MODULE_DESCRIPTION("I2C-Bus main module");

drivers/i2c/i2c-slave-eeprom.c+2−2

@@ -74,7 +74,7 @@ static ssize_t i2c_slave_eeprom_bin_read(struct file filp, struct kobject kobj · 73 unmodified lines
74	struct eeprom_data *eeprom;	74	struct eeprom_data *eeprom;
75	unsigned long flags;	75	unsigned long flags;
76		76
77	if (off + count >= attr->size)	77	if (off + count > attr->size)
78	return -EFBIG;	78	return -EFBIG;
79		79
80	eeprom = dev_get_drvdata(container_of(kobj, struct device, kobj));	80	eeprom = dev_get_drvdata(container_of(kobj, struct device, kobj));
@@ -92,7 +92,7 @@ static ssize_t i2c_slave_eeprom_bin_write(struct file filp, struct kobject kob · 11 unmodified lines
92	struct eeprom_data *eeprom;	92	struct eeprom_data *eeprom;
93	unsigned long flags;	93	unsigned long flags;
94		94
95	if (off + count >= attr->size)	95	if (off + count > attr->size)
96	return -EFBIG;	96	return -EFBIG;
97		97
98	eeprom = dev_get_drvdata(container_of(kobj, struct device, kobj));	98	eeprom = dev_get_drvdata(container_of(kobj, struct device, kobj));

drivers/input/mouse/elantech.c+16−0

@@ -1097,6 +1097,8 @@ static int elantech_get_resolution_v4(struct psmouse *psmouse, · 1096 unmodified lines
1097	* Asus UX31 0x361f00 20, 15, 0e clickpad	1097	* Asus UX31 0x361f00 20, 15, 0e clickpad
1098	* Asus UX32VD 0x361f02 00, 15, 0e clickpad	1098	* Asus UX32VD 0x361f02 00, 15, 0e clickpad
1099	* Avatar AVIU-145A2 0x361f00 ? clickpad	1099	* Avatar AVIU-145A2 0x361f00 ? clickpad
		1100	* Fujitsu LIFEBOOK E544 0x470f00 d0, 12, 09 2 hw buttons
		1101	* Fujitsu LIFEBOOK E554 0x570f01 40, 14, 0c 2 hw buttons
1100	* Fujitsu H730 0x570f00 c0, 14, 0c 3 hw buttons (**)	1102	* Fujitsu H730 0x570f00 c0, 14, 0c 3 hw buttons (**)
1101	* Gigabyte U2442 0x450f01 58, 17, 0c 2 hw buttons	1103	* Gigabyte U2442 0x450f01 58, 17, 0c 2 hw buttons
1102	* Lenovo L430 0x350f02 b9, 15, 0c 2 hw buttons (*)	1104	* Lenovo L430 0x350f02 b9, 15, 0c 2 hw buttons (*)
@@ -1475,6 +1477,20 @@ static const struct dmi_system_id elantech_dmi_force_crc_enabled[] = { · 372 unmodified lines
1475	DMI_MATCH(DMI_PRODUCT_NAME, "CELSIUS H730"),	1477	DMI_MATCH(DMI_PRODUCT_NAME, "CELSIUS H730"),
1476	},	1478	},
1477	},	1479	},
		1480	{
		1481	/* Fujitsu LIFEBOOK E554 does not work with crc_enabled == 0 */
		1482	.matches = {
		1483	DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
		1484	DMI_MATCH(DMI_PRODUCT_NAME, "LIFEBOOK E554"),
		1485	},
		1486	},
		1487	{
		1488	/* Fujitsu LIFEBOOK E544 does not work with crc_enabled == 0 */
		1489	.matches = {
		1490	DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
		1491	DMI_MATCH(DMI_PRODUCT_NAME, "LIFEBOOK E544"),
		1492	},
		1493	},
1478	#endif	1494	#endif
1479	{ }	1495	{ }
1480	};	1496	};

drivers/input/mouse/synaptics.c+4−3

 		1232, 5710, 1156, 4696
 	},
 	{
-		(const char * const []){"LEN0034", "LEN0036", "LEN0039",
+		(const char * const []){"LEN0034", "LEN0036", "LEN0037",
-					"LEN2002", "LEN2004", NULL},
+					"LEN0039", "LEN2002", "LEN2004",
+					NULL},
 		1024, 5112, 2024, 4832
 	},
 	{
 	"LEN0034", /* T431s, L440, L540, T540, W540, X1 Carbon 2nd */
 	"LEN0035", /* X240 */
 	"LEN0036", /* T440 */
-	"LEN0037",
+	"LEN0037", /* X1 Carbon 2nd */
 	"LEN0038",
 	"LEN0039", /* T440s */
 	"LEN0041",

drivers/input/serio/i8042-x86ia64io.h+8−0

@@ -151,6 +151,14 @@ static const struct dmi_system_id __initconst i8042_dmi_noloop_table[] = { · 150 unmodified lines
151	DMI_MATCH(DMI_PRODUCT_VERSION, "5a"),	151	DMI_MATCH(DMI_PRODUCT_VERSION, "5a"),
152	},	152	},
153	},	153	},
		154	{
		155	/* Medion Akoya E7225 */
		156	.matches = {
		157	DMI_MATCH(DMI_SYS_VENDOR, "Medion"),
		158	DMI_MATCH(DMI_PRODUCT_NAME, "Akoya E7225"),
		159	DMI_MATCH(DMI_PRODUCT_VERSION, "1.0"),
		160	},
		161	},
154	{	162	{
155	/* Blue FB5601 */	163	/* Blue FB5601 */
156	.matches = {	164	.matches = {

drivers/iommu/tegra-gart.c+2−1

@@ -315,6 +315,7 @@ static const struct iommu_ops gart_iommu_ops = { · 314 unmodified lines
315	.attach_dev = gart_iommu_attach_dev,	315	.attach_dev = gart_iommu_attach_dev,
316	.detach_dev = gart_iommu_detach_dev,	316	.detach_dev = gart_iommu_detach_dev,
317	.map = gart_iommu_map,	317	.map = gart_iommu_map,
		318	.map_sg = default_iommu_map_sg,
318	.unmap = gart_iommu_unmap,	319	.unmap = gart_iommu_unmap,
319	.iova_to_phys = gart_iommu_iova_to_phys,	320	.iova_to_phys = gart_iommu_iova_to_phys,
320	.pgsize_bitmap = GART_IOMMU_PGSIZES,	321	.pgsize_bitmap = GART_IOMMU_PGSIZES,
@@ -395,7 +396,7 @@ static int tegra_gart_probe(struct platform_device *pdev) · 74 unmodified lines
395	do_gart_setup(gart, NULL);	396	do_gart_setup(gart, NULL);
396		397
397	gart_handle = gart;	398	gart_handle = gart;
398	bus_set_iommu(&platform_bus_type, &gart_iommu_ops);	399
399	return 0;	400	return 0;
400	}	401	}
401		402

drivers/md/dm-cache-metadata.c+5−4

@@ -683,7 +683,7 @@ static struct dm_cache_metadata metadata_open(struct block_device bdev, · 682 unmodified lines
683	cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);	683	cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
684	if (!cmd) {	684	if (!cmd) {
685	DMERR("could not allocate metadata struct");	685	DMERR("could not allocate metadata struct");
686	return NULL;	686	return ERR_PTR(-ENOMEM);
687	}	687	}
688		688
689	atomic_set(&cmd->ref_count, 1);	689	atomic_set(&cmd->ref_count, 1);
@@ -745,7 +745,7 @@ static struct dm_cache_metadata lookup_or_open(struct block_device bdev, · 55 unmodified lines
745	return cmd;	745	return cmd;
746		746
747	cmd = metadata_open(bdev, data_block_size, may_format_device, policy_hint_size);	747	cmd = metadata_open(bdev, data_block_size, may_format_device, policy_hint_size);
748	if (cmd) {	748	if (!IS_ERR(cmd)) {
749	mutex_lock(&table_lock);	749	mutex_lock(&table_lock);
750	cmd2 = lookup(bdev);	750	cmd2 = lookup(bdev);
751	if (cmd2) {	751	if (cmd2) {
@@ -780,9 +780,10 @@ struct dm_cache_metadata dm_cache_metadata_open(struct block_device bdev, · 28 unmodified lines
780	{	780	{
781	struct dm_cache_metadata *cmd = lookup_or_open(bdev, data_block_size,	781	struct dm_cache_metadata *cmd = lookup_or_open(bdev, data_block_size,
782	may_format_device, policy_hint_size);	782	may_format_device, policy_hint_size);
783	if (cmd && !same_params(cmd, data_block_size)) {	783
		784	if (!IS_ERR(cmd) && !same_params(cmd, data_block_size)) {
784	dm_cache_metadata_close(cmd);	785	dm_cache_metadata_close(cmd);
785	return NULL;	786	return ERR_PTR(-EINVAL);
786	}	787	}
787		788
788	return cmd;	789	return cmd;

drivers/md/dm-thin.c+6−0

 	struct pool_c *pt = ti->private;
 	struct pool *pool = pt->pool;
+	if (get_pool_mode(pool) >= PM_READ_ONLY) {
+		DMERR("%s: unable to service pool target messages in READ_ONLY or FAIL mode",
+		      dm_device_name(pool->pool_md));
+		return -EINVAL;
+	}
 	if (!strcasecmp(argv[0], "create_thin"))
 		r = process_create_thin_mesg(argc, argv, pool);

drivers/net/can/c_can/c_can.c+3−0

@@ -615,6 +615,9 @@ static void c_can_stop(struct net_device *dev) · 614 unmodified lines
615		615
616	c_can_irq_control(priv, false);	616	c_can_irq_control(priv, false);
617		617
		618	/* put ctrl to init on stop to end ongoing transmission */
		619	priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_INIT);
		620
618	/* deactivate pins */	621	/* deactivate pins */
619	pinctrl_pm_select_sleep_state(dev->dev.parent);	622	pinctrl_pm_select_sleep_state(dev->dev.parent);
620	priv->can.state = CAN_STATE_STOPPED;	623	priv->can.state = CAN_STATE_STOPPED;

drivers/net/can/usb/kvaser_usb.c+15−13

 			  usb_sndbulkpipe(dev->udev,
 					  dev->bulk_out->bEndpointAddress),
 			  buf, msg->len,
-			  kvaser_usb_simple_msg_callback, priv);
+			  kvaser_usb_simple_msg_callback, netdev);
 	usb_anchor_urb(urb, &priv->tx_submitted);
 	err = usb_submit_urb(urb, GFP_ATOMIC);
 	priv = dev->nets[channel];
 	stats = &priv->netdev->stats;
-	if (status & M16C_STATE_BUS_RESET) {
-		kvaser_usb_unlink_tx_urbs(priv);
-		return;
-	}
 	skb = alloc_can_err_skb(priv->netdev, &cf);
 	if (!skb) {
 		stats->rx_dropped++;
 	netdev_dbg(priv->netdev, "Error status: 0x%02x\n", status);
-	if (status & M16C_STATE_BUS_OFF) {
+	if (status & (M16C_STATE_BUS_OFF | M16C_STATE_BUS_RESET)) {
 		cf->can_id |= CAN_ERR_BUSOFF;
 		priv->can.can_stats.bus_off++;
 		}
 		new_state = CAN_STATE_ERROR_PASSIVE;
-	}
+	} else if (status & M16C_STATE_BUS_ERROR) {
-	if (status == M16C_STATE_BUS_ERROR) {
 		if ((priv->can.state < CAN_STATE_ERROR_WARNING) &&
 		    ((txerr >= 96) || (rxerr >= 96))) {
 			cf->can_id |= CAN_ERR_CRTL;
 			priv->can.can_stats.error_warning++;
 			new_state = CAN_STATE_ERROR_WARNING;
-		} else if (priv->can.state > CAN_STATE_ERROR_ACTIVE) {
+		} else if ((priv->can.state > CAN_STATE_ERROR_ACTIVE) &&
+			   ((txerr < 96) && (rxerr < 96))) {
 			cf->can_id |= CAN_ERR_PROT;
 			cf->data[2] = CAN_ERR_PROT_ACTIVE;
 {
 	struct kvaser_usb *dev;
 	int err = -ENOMEM;
-	int i;
+	int i, retry = 3;
 	dev = devm_kzalloc(&intf->dev, sizeof(*dev), GFP_KERNEL);
 	if (!dev)
 	usb_set_intfdata(intf, dev);
-	err = kvaser_usb_get_software_info(dev);
+	/* On some x86 laptops, plugging a Kvaser device again after
+	 * an unplug makes the firmware always ignore the very first
+	 * command. For such a case, provide some room for retries
+	 * instead of completely exiting the driver.
+	 */
+	do {
+		err = kvaser_usb_get_software_info(dev);
+	} while (--retry && err == -ETIMEDOUT);
 	if (err) {
 		dev_err(&intf->dev,
 			"Cannot get software infos, error %d\n", err);

drivers/net/ethernet/amd/xgbe/xgbe-common.h+5−4

 #define MTL_Q_RQOMR			0x40
 #define MTL_Q_RQMPOCR			0x44
 #define MTL_Q_RQDR			0x4c
+#define MTL_Q_RQFCR			0x50
 #define MTL_Q_IER			0x70
 #define MTL_Q_ISR			0x74
 /* MTL queue register entry bit positions and sizes */
+#define MTL_Q_RQFCR_RFA_INDEX		1
+#define MTL_Q_RQFCR_RFA_WIDTH		6
+#define MTL_Q_RQFCR_RFD_INDEX		17
+#define MTL_Q_RQFCR_RFD_WIDTH		6
 #define MTL_Q_RQOMR_EHFC_INDEX		7
 #define MTL_Q_RQOMR_EHFC_WIDTH		1
-#define MTL_Q_RQOMR_RFA_INDEX		8
-#define MTL_Q_RQOMR_RFA_WIDTH		3
-#define MTL_Q_RQOMR_RFD_INDEX		13
-#define MTL_Q_RQOMR_RFD_WIDTH		3
 #define MTL_Q_RQOMR_RQS_INDEX		16
 #define MTL_Q_RQOMR_RQS_WIDTH		9
 #define MTL_Q_RQOMR_RSF_INDEX		5

drivers/net/ethernet/amd/xgbe/xgbe-dev.c+2−2

@@ -2079,10 +2079,10 @@ static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata) · 2078 unmodified lines
2079		2079
2080	for (i = 0; i < pdata->rx_q_count; i++) {	2080	for (i = 0; i < pdata->rx_q_count; i++) {
2081	/* Activate flow control when less than 4k left in fifo */	2081	/* Activate flow control when less than 4k left in fifo */
2082	XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RFA, 2);	2082	XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFA, 2);
2083		2083
2084	/* De-activate flow control when more than 6k left in fifo */	2084	/* De-activate flow control when more than 6k left in fifo */
2085	XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RFD, 4);	2085	XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFD, 4);
2086	}	2086	}
2087	}	2087	}
2088		2088

drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c+1−1

@@ -3175,7 +3175,7 @@ static int bnx2x_poll(struct napi_struct *napi, int budget) · 3174 unmodified lines
3175	}	3175	}
3176	#endif	3176	#endif
3177	if (!bnx2x_fp_lock_napi(fp))	3177	if (!bnx2x_fp_lock_napi(fp))
3178	return work_done;	3178	return budget;
3179		3179
3180	for_each_cos_in_tx_queue(fp, cos)	3180	for_each_cos_in_tx_queue(fp, cos)
3181	if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos]))	3181	if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos]))

drivers/net/ethernet/cisco/enic/enic_main.c+1−1

@@ -1335,7 +1335,7 @@ static int enic_poll_msix_rq(struct napi_struct *napi, int budget) · 1334 unmodified lines
1335	int err;	1335	int err;
1336		1336
1337	if (!enic_poll_lock_napi(&enic->rq[rq]))	1337	if (!enic_poll_lock_napi(&enic->rq[rq]))
1338	return work_done;	1338	return budget;
1339	/* Service RQ	1339	/* Service RQ
1340	*/	1340	*/
1341		1341

drivers/net/ethernet/marvell/mv643xx_eth.c+49−10

@@ -192,6 +192,10 @@ static char mv643xx_eth_driver_version[] = "1.4"; · 191 unmodified lines
192	#define IS_TSO_HEADER(txq, addr) \	192	#define IS_TSO_HEADER(txq, addr) \
193	((addr >= txq->tso_hdrs_dma) && \	193	((addr >= txq->tso_hdrs_dma) && \
194	(addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))	194	(addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
		195
		196	#define DESC_DMA_MAP_SINGLE 0
		197	#define DESC_DMA_MAP_PAGE 1
		198
195	/*	199	/*
196	* RX/TX descriptors.	200	* RX/TX descriptors.
197	*/	201	*/
@@ -362,6 +366,7 @@ struct tx_queue { · 164 unmodified lines
362	dma_addr_t tso_hdrs_dma;	366	dma_addr_t tso_hdrs_dma;
363		367
364	struct tx_desc *tx_desc_area;	368	struct tx_desc *tx_desc_area;
		369	char tx_desc_mapping; / array to track the type of the dma mapping */
365	dma_addr_t tx_desc_dma;	370	dma_addr_t tx_desc_dma;
366	int tx_desc_area_size;	371	int tx_desc_area_size;
367		372
@@ -750,6 +755,7 @@ txq_put_data_tso(struct net_device dev, struct tx_queue txq, · 382 unmodified lines
750	if (txq->tx_curr_desc == txq->tx_ring_size)	755	if (txq->tx_curr_desc == txq->tx_ring_size)
751	txq->tx_curr_desc = 0;	756	txq->tx_curr_desc = 0;
752	desc = &txq->tx_desc_area[tx_index];	757	desc = &txq->tx_desc_area[tx_index];
		758	txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
753		759
754	desc->l4i_chk = 0;	760	desc->l4i_chk = 0;
755	desc->byte_cnt = length;	761	desc->byte_cnt = length;
@@ -879,14 +885,13 @@ static void txq_submit_frag_skb(struct tx_queue txq, struct sk_buff skb) · 123 unmodified lines
879	skb_frag_t *this_frag;	885	skb_frag_t *this_frag;
880	int tx_index;	886	int tx_index;
881	struct tx_desc *desc;	887	struct tx_desc *desc;
882	void *addr;
883		888
884	this_frag = &skb_shinfo(skb)->frags[frag];	889	this_frag = &skb_shinfo(skb)->frags[frag];
885	addr = page_address(this_frag->page.p) + this_frag->page_offset;
886	tx_index = txq->tx_curr_desc++;	890	tx_index = txq->tx_curr_desc++;
887	if (txq->tx_curr_desc == txq->tx_ring_size)	891	if (txq->tx_curr_desc == txq->tx_ring_size)
888	txq->tx_curr_desc = 0;	892	txq->tx_curr_desc = 0;
889	desc = &txq->tx_desc_area[tx_index];	893	desc = &txq->tx_desc_area[tx_index];
		894	txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_PAGE;
890		895
891	/*	896	/*
892	* The last fragment will generate an interrupt	897	* The last fragment will generate an interrupt
@@ -902,8 +907,9 @@ static void txq_submit_frag_skb(struct tx_queue txq, struct sk_buff skb) · 9 unmodified lines
902		907
903	desc->l4i_chk = 0;	908	desc->l4i_chk = 0;
904	desc->byte_cnt = skb_frag_size(this_frag);	909	desc->byte_cnt = skb_frag_size(this_frag);
905	desc->buf_ptr = dma_map_single(mp->dev->dev.parent, addr,	910	desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent,
906	desc->byte_cnt, DMA_TO_DEVICE);	911	this_frag, 0, desc->byte_cnt,
		912	DMA_TO_DEVICE);
907	}	913	}
908	}	914	}
909		915
@@ -936,6 +942,7 @@ static int txq_submit_skb(struct tx_queue txq, struct sk_buff skb, · 26 unmodified lines
936	if (txq->tx_curr_desc == txq->tx_ring_size)	942	if (txq->tx_curr_desc == txq->tx_ring_size)
937	txq->tx_curr_desc = 0;	943	txq->tx_curr_desc = 0;
938	desc = &txq->tx_desc_area[tx_index];	944	desc = &txq->tx_desc_area[tx_index];
		945	txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
939		946
940	if (nr_frags) {	947	if (nr_frags) {
941	txq_submit_frag_skb(txq, skb);	948	txq_submit_frag_skb(txq, skb);
@@ -1047,9 +1054,12 @@ static int txq_reclaim(struct tx_queue *txq, int budget, int force) · 105 unmodified lines
1047	int tx_index;	1054	int tx_index;
1048	struct tx_desc *desc;	1055	struct tx_desc *desc;
1049	u32 cmd_sts;	1056	u32 cmd_sts;
		1057	char desc_dma_map;
1050		1058
1051	tx_index = txq->tx_used_desc;	1059	tx_index = txq->tx_used_desc;
1052	desc = &txq->tx_desc_area[tx_index];	1060	desc = &txq->tx_desc_area[tx_index];
		1061	desc_dma_map = txq->tx_desc_mapping[tx_index];
		1062
1053	cmd_sts = desc->cmd_sts;	1063	cmd_sts = desc->cmd_sts;
1054		1064
1055	if (cmd_sts & BUFFER_OWNED_BY_DMA) {	1065	if (cmd_sts & BUFFER_OWNED_BY_DMA) {
@@ -1065,9 +1075,19 @@ static int txq_reclaim(struct tx_queue *txq, int budget, int force) · 9 unmodified lines
1065	reclaimed++;	1075	reclaimed++;
1066	txq->tx_desc_count--;	1076	txq->tx_desc_count--;
1067		1077
1068	if (!IS_TSO_HEADER(txq, desc->buf_ptr))	1078	if (!IS_TSO_HEADER(txq, desc->buf_ptr)) {
1069	dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr,	1079
1070	desc->byte_cnt, DMA_TO_DEVICE);	1080	if (desc_dma_map == DESC_DMA_MAP_PAGE)
		1081	dma_unmap_page(mp->dev->dev.parent,
		1082	desc->buf_ptr,
		1083	desc->byte_cnt,
		1084	DMA_TO_DEVICE);
		1085	else
		1086	dma_unmap_single(mp->dev->dev.parent,
		1087	desc->buf_ptr,
		1088	desc->byte_cnt,
		1089	DMA_TO_DEVICE);
		1090	}
1071		1091
1072	if (cmd_sts & TX_ENABLE_INTERRUPT) {	1092	if (cmd_sts & TX_ENABLE_INTERRUPT) {
1073	struct sk_buff *skb = __skb_dequeue(&txq->tx_skb);	1093	struct sk_buff *skb = __skb_dequeue(&txq->tx_skb);
@@ -1996,6 +2016,7 @@ static int txq_init(struct mv643xx_eth_private *mp, int index) · 922 unmodified lines
1996	struct tx_queue *txq = mp->txq + index;	2016	struct tx_queue *txq = mp->txq + index;
1997	struct tx_desc *tx_desc;	2017	struct tx_desc *tx_desc;
1998	int size;	2018	int size;
		2019	int ret;
1999	int i;	2020	int i;
2000		2021
2001	txq->index = index;	2022	txq->index = index;
@@ -2048,18 +2069,34 @@ static int txq_init(struct mv643xx_eth_private *mp, int index) · 46 unmodified lines
2048	nexti * sizeof(struct tx_desc);	2069	nexti * sizeof(struct tx_desc);
2049	}	2070	}
2050		2071
		2072	txq->tx_desc_mapping = kcalloc(txq->tx_ring_size, sizeof(char),
		2073	GFP_KERNEL);
		2074	if (!txq->tx_desc_mapping) {
		2075	ret = -ENOMEM;
		2076	goto err_free_desc_area;
		2077	}
		2078
2051	/* Allocate DMA buffers for TSO MAC/IP/TCP headers */	2079	/* Allocate DMA buffers for TSO MAC/IP/TCP headers */
2052	txq->tso_hdrs = dma_alloc_coherent(mp->dev->dev.parent,	2080	txq->tso_hdrs = dma_alloc_coherent(mp->dev->dev.parent,
2053	txq->tx_ring_size * TSO_HEADER_SIZE,	2081	txq->tx_ring_size * TSO_HEADER_SIZE,
2054	&txq->tso_hdrs_dma, GFP_KERNEL);	2082	&txq->tso_hdrs_dma, GFP_KERNEL);
2055	if (txq->tso_hdrs == NULL) {	2083	if (txq->tso_hdrs == NULL) {
2056	dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,	2084	ret = -ENOMEM;
2057	txq->tx_desc_area, txq->tx_desc_dma);	2085	goto err_free_desc_mapping;
2058	return -ENOMEM;
2059	}	2086	}
2060	skb_queue_head_init(&txq->tx_skb);	2087	skb_queue_head_init(&txq->tx_skb);
2061		2088
2062	return 0;	2089	return 0;
		2090
		2091	err_free_desc_mapping:
		2092	kfree(txq->tx_desc_mapping);
		2093	err_free_desc_area:
		2094	if (index == 0 && size <= mp->tx_desc_sram_size)
		2095	iounmap(txq->tx_desc_area);
		2096	else
		2097	dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
		2098	txq->tx_desc_area, txq->tx_desc_dma);
		2099	return ret;
2063	}	2100	}
2064		2101
2065	static void txq_deinit(struct tx_queue *txq)	2102	static void txq_deinit(struct tx_queue *txq)
@@ -2077,6 +2114,8 @@ static void txq_deinit(struct tx_queue *txq) · 11 unmodified lines
2077	else	2114	else
2078	dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,	2115	dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2079	txq->tx_desc_area, txq->tx_desc_dma);	2116	txq->tx_desc_area, txq->tx_desc_dma);
		2117	kfree(txq->tx_desc_mapping);
		2118
2080	if (txq->tso_hdrs)	2119	if (txq->tso_hdrs)
2081	dma_free_coherent(mp->dev->dev.parent,	2120	dma_free_coherent(mp->dev->dev.parent,
2082	txq->tx_ring_size * TSO_HEADER_SIZE,	2121	txq->tx_ring_size * TSO_HEADER_SIZE,

drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c+4−1

@@ -2388,7 +2388,10 @@ static int netxen_nic_poll(struct napi_struct *napi, int budget) · 2387 unmodified lines
2388		2388
2389	work_done = netxen_process_rcv_ring(sds_ring, budget);	2389	work_done = netxen_process_rcv_ring(sds_ring, budget);
2390		2390
2391	if ((work_done < budget) && tx_complete) {	2391	if (!tx_complete)
		2392	work_done = budget;
		2393
		2394	if (work_done < budget) {
2392	napi_complete(&sds_ring->napi);	2395	napi_complete(&sds_ring->napi);
2393	if (test_bit(__NX_DEV_UP, &adapter->state))	2396	if (test_bit(__NX_DEV_UP, &adapter->state))
2394	netxen_nic_enable_int(sds_ring);	2397	netxen_nic_enable_int(sds_ring);

drivers/net/ethernet/renesas/sh_eth.c+113−51

@@ -396,6 +396,9 @@ static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = { · 395 unmodified lines
396	[TSU_ADRL31] = 0x01fc,	396	[TSU_ADRL31] = 0x01fc,
397	};	397	};
398		398
		399	static void sh_eth_rcv_snd_disable(struct net_device *ndev);
		400	static struct net_device_stats sh_eth_get_stats(struct net_device ndev);
		401
399	static bool sh_eth_is_gether(struct sh_eth_private *mdp)	402	static bool sh_eth_is_gether(struct sh_eth_private *mdp)
400	{	403	{
401	return mdp->reg_offset == sh_eth_offset_gigabit;	404	return mdp->reg_offset == sh_eth_offset_gigabit;
@@ -1120,6 +1123,7 @@ static void sh_eth_ring_format(struct net_device *ndev) · 718 unmodified lines
1120	int rx_ringsize = sizeof(rxdesc) mdp->num_rx_ring;	1123	int rx_ringsize = sizeof(rxdesc) mdp->num_rx_ring;
1121	int tx_ringsize = sizeof(txdesc) mdp->num_tx_ring;	1124	int tx_ringsize = sizeof(txdesc) mdp->num_tx_ring;
1122	int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN - 1;	1125	int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN - 1;
		1126	dma_addr_t dma_addr;
1123		1127
1124	mdp->cur_rx = 0;	1128	mdp->cur_rx = 0;
1125	mdp->cur_tx = 0;	1129	mdp->cur_tx = 0;
@@ -1133,7 +1137,6 @@ static void sh_eth_ring_format(struct net_device *ndev) · 7 unmodified lines
1133	/* skb */	1137	/* skb */
1134	mdp->rx_skbuff[i] = NULL;	1138	mdp->rx_skbuff[i] = NULL;
1135	skb = netdev_alloc_skb(ndev, skbuff_size);	1139	skb = netdev_alloc_skb(ndev, skbuff_size);
1136	mdp->rx_skbuff[i] = skb;
1137	if (skb == NULL)	1140	if (skb == NULL)
1138	break;	1141	break;
1139	sh_eth_set_receive_align(skb);	1142	sh_eth_set_receive_align(skb);
@@ -1142,9 +1145,15 @@ static void sh_eth_ring_format(struct net_device *ndev) · 2 unmodified lines
1142	rxdesc = &mdp->rx_ring[i];	1145	rxdesc = &mdp->rx_ring[i];
1143	/* The size of the buffer is a multiple of 16 bytes. */	1146	/* The size of the buffer is a multiple of 16 bytes. */
1144	rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);	1147	rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1145	dma_map_single(&ndev->dev, skb->data, rxdesc->buffer_length,	1148	dma_addr = dma_map_single(&ndev->dev, skb->data,
1146	DMA_FROM_DEVICE);	1149	rxdesc->buffer_length,
1147	rxdesc->addr = virt_to_phys(skb->data);	1150	DMA_FROM_DEVICE);
		1151	if (dma_mapping_error(&ndev->dev, dma_addr)) {
		1152	kfree_skb(skb);
		1153	break;
		1154	}
		1155	mdp->rx_skbuff[i] = skb;
		1156	rxdesc->addr = dma_addr;
1148	rxdesc->status = cpu_to_edmac(mdp, RD_RACT \| RD_RFP);	1157	rxdesc->status = cpu_to_edmac(mdp, RD_RACT \| RD_RFP);
1149		1158
1150	/* Rx descriptor address set */	1159	/* Rx descriptor address set */
@@ -1316,8 +1325,10 @@ static int sh_eth_dev_init(struct net_device *ndev, bool start) · 165 unmodified lines
1316	RFLR);	1325	RFLR);
1317		1326
1318	sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);	1327	sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1319	if (start)	1328	if (start) {
		1329	mdp->irq_enabled = true;
1320	sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);	1330	sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
		1331	}
1321		1332
1322	/* PAUSE Prohibition */	1333	/* PAUSE Prohibition */
1323	val = (sh_eth_read(ndev, ECMR) & ECMR_DM) \|	1334	val = (sh_eth_read(ndev, ECMR) & ECMR_DM) \|
@@ -1356,6 +1367,33 @@ static int sh_eth_dev_init(struct net_device *ndev, bool start) · 32 unmodified lines
1356	return ret;	1367	return ret;
1357	}	1368	}
1358		1369
		1370	static void sh_eth_dev_exit(struct net_device *ndev)
		1371	{
		1372	struct sh_eth_private *mdp = netdev_priv(ndev);
		1373	int i;
		1374
		1375	/* Deactivate all TX descriptors, so DMA should stop at next
		1376	* packet boundary if it's currently running
		1377	*/
		1378	for (i = 0; i < mdp->num_tx_ring; i++)
		1379	mdp->tx_ring[i].status &= ~cpu_to_edmac(mdp, TD_TACT);
		1380
		1381	/* Disable TX FIFO egress to MAC */
		1382	sh_eth_rcv_snd_disable(ndev);
		1383
		1384	/* Stop RX DMA at next packet boundary */
		1385	sh_eth_write(ndev, 0, EDRRR);
		1386
		1387	/* Aside from TX DMA, we can't tell when the hardware is
		1388	* really stopped, so we need to reset to make sure.
		1389	* Before doing that, wait for long enough to probably
		1390	* finish transmitting the last packet and poll stats.
		1391	*/
		1392	msleep(2); /* max frame time at 10 Mbps < 1250 us */
		1393	sh_eth_get_stats(ndev);
		1394	sh_eth_reset(ndev);
		1395	}
		1396
1359	/* free Tx skb function */	1397	/* free Tx skb function */
1360	static int sh_eth_txfree(struct net_device *ndev)	1398	static int sh_eth_txfree(struct net_device *ndev)
1361	{	1399	{
@@ -1400,6 +1438,7 @@ static int sh_eth_rx(struct net_device ndev, u32 intr_status, int quota) · 38 unmodified lines
1400	u16 pkt_len = 0;	1438	u16 pkt_len = 0;
1401	u32 desc_status;	1439	u32 desc_status;
1402	int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN - 1;	1440	int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN - 1;
		1441	dma_addr_t dma_addr;
1403		1442
1404	boguscnt = min(boguscnt, *quota);	1443	boguscnt = min(boguscnt, *quota);
1405	limit = boguscnt;	1444	limit = boguscnt;
@@ -1447,9 +1486,9 @@ static int sh_eth_rx(struct net_device ndev, u32 intr_status, int quota) · 41 unmodified lines
1447	mdp->rx_skbuff[entry] = NULL;	1486	mdp->rx_skbuff[entry] = NULL;
1448	if (mdp->cd->rpadir)	1487	if (mdp->cd->rpadir)
1449	skb_reserve(skb, NET_IP_ALIGN);	1488	skb_reserve(skb, NET_IP_ALIGN);
1450	dma_sync_single_for_cpu(&ndev->dev, rxdesc->addr,	1489	dma_unmap_single(&ndev->dev, rxdesc->addr,
1451	ALIGN(mdp->rx_buf_sz, 16),	1490	ALIGN(mdp->rx_buf_sz, 16),
1452	DMA_FROM_DEVICE);	1491	DMA_FROM_DEVICE);
1453	skb_put(skb, pkt_len);	1492	skb_put(skb, pkt_len);
1454	skb->protocol = eth_type_trans(skb, ndev);	1493	skb->protocol = eth_type_trans(skb, ndev);
1455	netif_receive_skb(skb);	1494	netif_receive_skb(skb);
@@ -1469,15 +1508,20 @@ static int sh_eth_rx(struct net_device ndev, u32 intr_status, int quota) · 13 unmodified lines
1469		1508
1470	if (mdp->rx_skbuff[entry] == NULL) {	1509	if (mdp->rx_skbuff[entry] == NULL) {
1471	skb = netdev_alloc_skb(ndev, skbuff_size);	1510	skb = netdev_alloc_skb(ndev, skbuff_size);
1472	mdp->rx_skbuff[entry] = skb;
1473	if (skb == NULL)	1511	if (skb == NULL)
1474	break; /* Better luck next round. */	1512	break; /* Better luck next round. */
1475	sh_eth_set_receive_align(skb);	1513	sh_eth_set_receive_align(skb);
1476	dma_map_single(&ndev->dev, skb->data,	1514	dma_addr = dma_map_single(&ndev->dev, skb->data,
1477	rxdesc->buffer_length, DMA_FROM_DEVICE);	1515	rxdesc->buffer_length,
		1516	DMA_FROM_DEVICE);
		1517	if (dma_mapping_error(&ndev->dev, dma_addr)) {
		1518	kfree_skb(skb);
		1519	break;
		1520	}
		1521	mdp->rx_skbuff[entry] = skb;
1478		1522
1479	skb_checksum_none_assert(skb);	1523	skb_checksum_none_assert(skb);
1480	rxdesc->addr = virt_to_phys(skb->data);	1524	rxdesc->addr = dma_addr;
1481	}	1525	}
1482	if (entry >= mdp->num_rx_ring - 1)	1526	if (entry >= mdp->num_rx_ring - 1)
1483	rxdesc->status \|=	1527	rxdesc->status \|=
@@ -1573,7 +1617,6 @@ ignore_link: · 89 unmodified lines
1573	if (intr_status & EESR_RFRMER) {	1617	if (intr_status & EESR_RFRMER) {
1574	/* Receive Frame Overflow int */	1618	/* Receive Frame Overflow int */
1575	ndev->stats.rx_frame_errors++;	1619	ndev->stats.rx_frame_errors++;
1576	netif_err(mdp, rx_err, ndev, "Receive Abort\n");
1577	}	1620	}
1578	}	1621	}
1579		1622
@@ -1592,13 +1635,11 @@ ignore_link: · 12 unmodified lines
1592	if (intr_status & EESR_RDE) {	1635	if (intr_status & EESR_RDE) {
1593	/* Receive Descriptor Empty int */	1636	/* Receive Descriptor Empty int */
1594	ndev->stats.rx_over_errors++;	1637	ndev->stats.rx_over_errors++;
1595	netif_err(mdp, rx_err, ndev, "Receive Descriptor Empty\n");
1596	}	1638	}
1597		1639
1598	if (intr_status & EESR_RFE) {	1640	if (intr_status & EESR_RFE) {
1599	/* Receive FIFO Overflow int */	1641	/* Receive FIFO Overflow int */
1600	ndev->stats.rx_fifo_errors++;	1642	ndev->stats.rx_fifo_errors++;
1601	netif_err(mdp, rx_err, ndev, "Receive FIFO Overflow\n");
1602	}	1643	}
1603		1644
1604	if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {	1645	if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
@@ -1653,7 +1694,12 @@ static irqreturn_t sh_eth_interrupt(int irq, void *netdev) · 48 unmodified lines
1653	if (intr_status & (EESR_RX_CHECK \| cd->tx_check \| cd->eesr_err_check))	1694	if (intr_status & (EESR_RX_CHECK \| cd->tx_check \| cd->eesr_err_check))
1654	ret = IRQ_HANDLED;	1695	ret = IRQ_HANDLED;
1655	else	1696	else
1656	goto other_irq;	1697	goto out;
		1698
		1699	if (!likely(mdp->irq_enabled)) {
		1700	sh_eth_write(ndev, 0, EESIPR);
		1701	goto out;
		1702	}
1657		1703
1658	if (intr_status & EESR_RX_CHECK) {	1704	if (intr_status & EESR_RX_CHECK) {
1659	if (napi_schedule_prep(&mdp->napi)) {	1705	if (napi_schedule_prep(&mdp->napi)) {
@@ -1684,7 +1730,7 @@ static irqreturn_t sh_eth_interrupt(int irq, void *netdev) · 24 unmodified lines
1684	sh_eth_error(ndev, intr_status);	1730	sh_eth_error(ndev, intr_status);
1685	}	1731	}
1686		1732
1687	other_irq:	1733	out:
1688	spin_unlock(&mdp->lock);	1734	spin_unlock(&mdp->lock);
1689		1735
1690	return ret;	1736	return ret;
@@ -1712,7 +1758,8 @@ static int sh_eth_poll(struct napi_struct *napi, int budget) · 21 unmodified lines
1712	napi_complete(napi);	1758	napi_complete(napi);
1713		1759
1714	/* Reenable Rx interrupts */	1760	/* Reenable Rx interrupts */
1715	sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);	1761	if (mdp->irq_enabled)
		1762	sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1716	out:	1763	out:
1717	return budget - quota;	1764	return budget - quota;
1718	}	1765	}
@@ -1968,40 +2015,50 @@ static int sh_eth_set_ringparam(struct net_device *ndev, · 249 unmodified lines
1968	return -EINVAL;	2015	return -EINVAL;
1969		2016
1970	if (netif_running(ndev)) {	2017	if (netif_running(ndev)) {
		2018	netif_device_detach(ndev);
1971	netif_tx_disable(ndev);	2019	netif_tx_disable(ndev);
1972	/* Disable interrupts by clearing the interrupt mask. */	2020
1973	sh_eth_write(ndev, 0x0000, EESIPR);	2021	/* Serialise with the interrupt handler and NAPI, then
1974	/* Stop the chip's Tx and Rx processes. */	2022	* disable interrupts. We have to clear the
1975	sh_eth_write(ndev, 0, EDTRR);	2023	* irq_enabled flag first to ensure that interrupts
1976	sh_eth_write(ndev, 0, EDRRR);	2024	* won't be re-enabled.
		2025	*/
		2026	mdp->irq_enabled = false;
1977	synchronize_irq(ndev->irq);	2027	synchronize_irq(ndev->irq);
1978	}	2028	napi_synchronize(&mdp->napi);
		2029	sh_eth_write(ndev, 0x0000, EESIPR);
1979		2030
1980	/* Free all the skbuffs in the Rx queue. */	2031	sh_eth_dev_exit(ndev);
1981	sh_eth_ring_free(ndev);	2032
1982	/* Free DMA buffer */	2033	/* Free all the skbuffs in the Rx queue. */
1983	sh_eth_free_dma_buffer(mdp);	2034	sh_eth_ring_free(ndev);
		2035	/* Free DMA buffer */
		2036	sh_eth_free_dma_buffer(mdp);
		2037	}
1984		2038
1985	/* Set new parameters */	2039	/* Set new parameters */
1986	mdp->num_rx_ring = ring->rx_pending;	2040	mdp->num_rx_ring = ring->rx_pending;
1987	mdp->num_tx_ring = ring->tx_pending;	2041	mdp->num_tx_ring = ring->tx_pending;
1988		2042
1989	ret = sh_eth_ring_init(ndev);
1990	if (ret < 0) {
1991	netdev_err(ndev, "%s: sh_eth_ring_init failed.\n", __func__);
1992	return ret;
1993	}
1994	ret = sh_eth_dev_init(ndev, false);
1995	if (ret < 0) {
1996	netdev_err(ndev, "%s: sh_eth_dev_init failed.\n", __func__);
1997	return ret;
1998	}
1999
2000	if (netif_running(ndev)) {	2043	if (netif_running(ndev)) {
		2044	ret = sh_eth_ring_init(ndev);
		2045	if (ret < 0) {
		2046	netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
		2047	__func__);
		2048	return ret;
		2049	}
		2050	ret = sh_eth_dev_init(ndev, false);
		2051	if (ret < 0) {
		2052	netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
		2053	__func__);
		2054	return ret;
		2055	}
		2056
		2057	mdp->irq_enabled = true;
2001	sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);	2058	sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
2002	/* Setting the Rx mode will start the Rx process. */	2059	/* Setting the Rx mode will start the Rx process. */
2003	sh_eth_write(ndev, EDRRR_R, EDRRR);	2060	sh_eth_write(ndev, EDRRR_R, EDRRR);
2004	netif_wake_queue(ndev);	2061	netif_device_attach(ndev);
2005	}	2062	}
2006		2063
2007	return 0;	2064	return 0;
@@ -2117,6 +2174,9 @@ static int sh_eth_start_xmit(struct sk_buff skb, struct net_device ndev) · 109 unmodified lines
2117	}	2174	}
2118	spin_unlock_irqrestore(&mdp->lock, flags);	2175	spin_unlock_irqrestore(&mdp->lock, flags);
2119		2176
		2177	if (skb_padto(skb, ETH_ZLEN))
		2178	return NETDEV_TX_OK;
		2179
2120	entry = mdp->cur_tx % mdp->num_tx_ring;	2180	entry = mdp->cur_tx % mdp->num_tx_ring;
2121	mdp->tx_skbuff[entry] = skb;	2181	mdp->tx_skbuff[entry] = skb;
2122	txdesc = &mdp->tx_ring[entry];	2182	txdesc = &mdp->tx_ring[entry];
@@ -2126,10 +2186,11 @@ static int sh_eth_start_xmit(struct sk_buff skb, struct net_device ndev) · 3 unmodified lines
2126	skb->len + 2);	2186	skb->len + 2);
2127	txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,	2187	txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2128	DMA_TO_DEVICE);	2188	DMA_TO_DEVICE);
2129	if (skb->len < ETH_ZLEN)	2189	if (dma_mapping_error(&ndev->dev, txdesc->addr)) {
2130	txdesc->buffer_length = ETH_ZLEN;	2190	kfree_skb(skb);
2131	else	2191	return NETDEV_TX_OK;
2132	txdesc->buffer_length = skb->len;	2192	}
		2193	txdesc->buffer_length = skb->len;
2133		2194
2134	if (entry >= mdp->num_tx_ring - 1)	2195	if (entry >= mdp->num_tx_ring - 1)
2135	txdesc->status \|= cpu_to_edmac(mdp, TD_TACT \| TD_TDLE);	2196	txdesc->status \|= cpu_to_edmac(mdp, TD_TACT \| TD_TDLE);
@@ -2181,14 +2242,17 @@ static int sh_eth_close(struct net_device *ndev) · 45 unmodified lines
2181		2242
2182	netif_stop_queue(ndev);	2243	netif_stop_queue(ndev);
2183		2244
2184	/* Disable interrupts by clearing the interrupt mask. */	2245	/* Serialise with the interrupt handler and NAPI, then disable
		2246	* interrupts. We have to clear the irq_enabled flag first to
		2247	* ensure that interrupts won't be re-enabled.
		2248	*/
		2249	mdp->irq_enabled = false;
		2250	synchronize_irq(ndev->irq);
		2251	napi_disable(&mdp->napi);
2185	sh_eth_write(ndev, 0x0000, EESIPR);	2252	sh_eth_write(ndev, 0x0000, EESIPR);
2186		2253
2187	/* Stop the chip's Tx and Rx processes. */	2254	sh_eth_dev_exit(ndev);
2188	sh_eth_write(ndev, 0, EDTRR);
2189	sh_eth_write(ndev, 0, EDRRR);
2190		2255
2191	sh_eth_get_stats(ndev);
2192	/* PHY Disconnect */	2256	/* PHY Disconnect */
2193	if (mdp->phydev) {	2257	if (mdp->phydev) {
2194	phy_stop(mdp->phydev);	2258	phy_stop(mdp->phydev);
@@ -2198,8 +2262,6 @@ static int sh_eth_close(struct net_device *ndev) · 3 unmodified lines
2198		2262
2199	free_irq(ndev->irq, ndev);	2263	free_irq(ndev->irq, ndev);
2200		2264
2201	napi_disable(&mdp->napi);
2202
2203	/* Free all the skbuffs in the Rx queue. */	2265	/* Free all the skbuffs in the Rx queue. */
2204	sh_eth_ring_free(ndev);	2266	sh_eth_ring_free(ndev);
2205		2267

drivers/net/ethernet/renesas/sh_eth.h+1−0

@@ -513,6 +513,7 @@ struct sh_eth_private { · 512 unmodified lines
513	u32 rx_buf_sz; /* Based on MTU+slack. */	513	u32 rx_buf_sz; /* Based on MTU+slack. */
514	int edmac_endian;	514	int edmac_endian;
515	struct napi_struct napi;	515	struct napi_struct napi;
		516	bool irq_enabled;
516	/* MII transceiver section. */	517	/* MII transceiver section. */
517	u32 phy_id; /* PHY ID */	518	u32 phy_id; /* PHY ID */
518	struct mii_bus mii_bus; / MDIO bus control */	519	struct mii_bus mii_bus; / MDIO bus control */

drivers/net/ethernet/stmicro/stmmac/stmmac_main.c+4−1

  * @addr: iobase memory address
  * Description: this is the main probe function used to
  * call the alloc_etherdev, allocate the priv structure.
+ * Return:
+ * on success the new private structure is returned, otherwise the error
+ * pointer.
  */
 struct stmmac_priv *stmmac_dvr_probe(struct device *device,
 				     struct plat_stmmacenet_data *plat_dat,
 	ndev = alloc_etherdev(sizeof(struct stmmac_priv));
 	if (!ndev)
-		return NULL;
+		return ERR_PTR(-ENOMEM);
 	SET_NETDEV_DEV(ndev, device);

drivers/net/ethernet/ti/cpsw.c+22−0

@@ -1683,6 +1683,19 @@ static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev, · 1682 unmodified lines
1683	if (vid == priv->data.default_vlan)	1683	if (vid == priv->data.default_vlan)
1684	return 0;	1684	return 0;
1685		1685
		1686	if (priv->data.dual_emac) {
		1687	/* In dual EMAC, reserved VLAN id should not be used for
		1688	* creating VLAN interfaces as this can break the dual
		1689	* EMAC port separation
		1690	*/
		1691	int i;
		1692
		1693	for (i = 0; i < priv->data.slaves; i++) {
		1694	if (vid == priv->slaves[i].port_vlan)
		1695	return -EINVAL;
		1696	}
		1697	}
		1698
1686	dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);	1699	dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1687	return cpsw_add_vlan_ale_entry(priv, vid);	1700	return cpsw_add_vlan_ale_entry(priv, vid);
1688	}	1701	}
@@ -1696,6 +1709,15 @@ static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev, · 7 unmodified lines
1696	if (vid == priv->data.default_vlan)	1709	if (vid == priv->data.default_vlan)
1697	return 0;	1710	return 0;
1698		1711
		1712	if (priv->data.dual_emac) {
		1713	int i;
		1714
		1715	for (i = 0; i < priv->data.slaves; i++) {
		1716	if (vid == priv->slaves[i].port_vlan)
		1717	return -EINVAL;
		1718	}
		1719	}
		1720
1699	dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);	1721	dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1700	ret = cpsw_ale_del_vlan(priv->ale, vid, 0);	1722	ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1701	if (ret != 0)	1723	if (ret != 0)

drivers/net/ipvlan/ipvlan_core.c+4−2

@@ -377,9 +377,11 @@ static int ipvlan_process_v6_outbound(struct sk_buff *skb) · 376 unmodified lines
377	};	377	};
378		378
379	dst = ip6_route_output(dev_net(dev), NULL, &fl6);	379	dst = ip6_route_output(dev_net(dev), NULL, &fl6);
380	if (IS_ERR(dst))	380	if (dst->error) {
		381	ret = dst->error;
		382	dst_release(dst);
381	goto err;	383	goto err;
382		384	}
383	skb_dst_drop(skb);	385	skb_dst_drop(skb);
384	skb_dst_set(skb, dst);	386	skb_dst_set(skb, dst);
385	err = ip6_local_out(skb);	387	err = ip6_local_out(skb);

drivers/net/wireless/ath/ath9k/main.c+3−4

 	__ath_cancel_work(sc);
+	disable_irq(sc->irq);
 	tasklet_disable(&sc->intr_tq);
 	tasklet_disable(&sc->bcon_tasklet);
 	spin_lock_bh(&sc->sc_pcu_lock);
 		r = -EIO;
 out:
+	enable_irq(sc->irq);
 	spin_unlock_bh(&sc->sc_pcu_lock);
 	tasklet_enable(&sc->bcon_tasklet);
 	tasklet_enable(&sc->intr_tq);
 	if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags))
 		return IRQ_NONE;
-	if (!AR_SREV_9100(ah) && test_bit(ATH_OP_HW_RESET, &common->op_flags))
-		return IRQ_NONE;
 	/* shared irq, not for us */
 	if (!ath9k_hw_intrpend(ah))
 		return IRQ_NONE;
 	ath9k_debug_sync_cause(sc, sync_cause);
 	status &= ah->imask;	/* discard unasked-for bits */
-	if (AR_SREV_9100(ah) && test_bit(ATH_OP_HW_RESET, &common->op_flags))
+	if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
 		return IRQ_HANDLED;
 	/*

drivers/net/wireless/iwlwifi/iwl-fw-file.h+2−0

  * @IWL_UCODE_TLV_API_BASIC_DWELL: use only basic dwell time in scan command,
  *	regardless of the band or the number of the probes. FW will calculate
  *	the actual dwell time.
+ * @IWL_UCODE_TLV_API_SINGLE_SCAN_EBS: EBS is supported for single scans too.
  */
 enum iwl_ucode_tlv_api {
 	IWL_UCODE_TLV_API_WOWLAN_CONFIG_TID	= BIT(0),
 	IWL_UCODE_TLV_API_SF_NO_DUMMY_NOTIF	= BIT(7),
 	IWL_UCODE_TLV_API_FRAGMENTED_SCAN	= BIT(8),
 	IWL_UCODE_TLV_API_BASIC_DWELL		= BIT(13),
+	IWL_UCODE_TLV_API_SINGLE_SCAN_EBS	= BIT(16),
 };
 /**

drivers/net/wireless/iwlwifi/mvm/fw-api-scan.h+5−2

 };
 /* iwl_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S
- * @flags: enum iwl_scan_channel_flgs
+ * @flags: enum iwl_scan_channel_flags
- * @non_ebs_ratio: how many regular scan iteration before EBS
+ * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is
+ *	involved.
+ *	1 - EBS is disabled.
+ *	2 - every second scan will be full scan(and so on).
  */
 struct iwl_scan_channel_opt {
 	__le16 flags;

drivers/net/wireless/iwlwifi/mvm/mac80211.c+9−11

@@ -3343,18 +3343,16 @@ static void iwl_mvm_mac_flush(struct ieee80211_hw *hw, · 3342 unmodified lines
3343	msk \|= mvmsta->tfd_queue_msk;	3343	msk \|= mvmsta->tfd_queue_msk;
3344	}	3344	}
3345		3345
3346	if (drop) {	3346	msk &= ~BIT(vif->hw_queue[IEEE80211_AC_VO]);
3347	if (iwl_mvm_flush_tx_path(mvm, msk, true))
3348	IWL_ERR(mvm, "flush request fail\n");
3349	mutex_unlock(&mvm->mutex);
3350	} else {
3351	mutex_unlock(&mvm->mutex);
3352		3347
3353	/* this can take a while, and we may need/want other operations	3348	if (iwl_mvm_flush_tx_path(mvm, msk, true))
3354	* to succeed while doing this, so do it without the mutex held	3349	IWL_ERR(mvm, "flush request fail\n");
3355	*/	3350	mutex_unlock(&mvm->mutex);
3356	iwl_trans_wait_tx_queue_empty(mvm->trans, msk);	3351
3357	}	3352	/* this can take a while, and we may need/want other operations
		3353	* to succeed while doing this, so do it without the mutex held
		3354	*/
		3355	iwl_trans_wait_tx_queue_empty(mvm->trans, msk);
3358	}	3356	}
3359		3357
3360	const struct ieee80211_ops iwl_mvm_hw_ops = {	3358	const struct ieee80211_ops iwl_mvm_hw_ops = {

drivers/net/wireless/iwlwifi/mvm/scan.c+41−12

 #define IWL_PLCP_QUIET_THRESH 1
 #define IWL_ACTIVE_QUIET_TIME 10
+#define IWL_DENSE_EBS_SCAN_RATIO 5
+#define IWL_SPARSE_EBS_SCAN_RATIO 1
 struct iwl_mvm_scan_params {
 	u32 max_out_time;
 		return iwl_umac_scan_stop(mvm, IWL_UMAC_SCAN_UID_SCHED_SCAN,
 					  notify);
+	if (mvm->scan_status == IWL_MVM_SCAN_NONE)
+		return 0;
+	if (iwl_mvm_is_radio_killed(mvm))
+		goto out;
 	if (mvm->scan_status != IWL_MVM_SCAN_SCHED &&
 	    (!(mvm->fw->ucode_capa.api[0] & IWL_UCODE_TLV_API_LMAC_SCAN) ||
 	     mvm->scan_status != IWL_MVM_SCAN_OS)) {
 	if (mvm->scan_status == IWL_MVM_SCAN_OS)
 		iwl_mvm_unref(mvm, IWL_MVM_REF_SCAN);
+out:
 	mvm->scan_status = IWL_MVM_SCAN_NONE;
 	if (notify) {
 	cmd->scan_prio = cpu_to_le32(IWL_SCAN_PRIORITY_HIGH);
 	cmd->iter_num = cpu_to_le32(1);
-	if (mvm->fw->ucode_capa.flags & IWL_UCODE_TLV_FLAGS_EBS_SUPPORT &&
-	    mvm->last_ebs_successful) {
-		cmd->channel_opt[0].flags =
-			cpu_to_le16(IWL_SCAN_CHANNEL_FLAG_EBS |
-				    IWL_SCAN_CHANNEL_FLAG_EBS_ACCURATE |
-				    IWL_SCAN_CHANNEL_FLAG_CACHE_ADD);
-		cmd->channel_opt[1].flags =
-			cpu_to_le16(IWL_SCAN_CHANNEL_FLAG_EBS |
-				    IWL_SCAN_CHANNEL_FLAG_EBS_ACCURATE |
-				    IWL_SCAN_CHANNEL_FLAG_CACHE_ADD);
-	}
 	if (iwl_mvm_rrm_scan_needed(mvm))
 		cmd->scan_flags |=
 			cpu_to_le32(IWL_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED);
 	cmd->schedule[1].iterations = 0;
 	cmd->schedule[1].full_scan_mul = 0;
+	if (mvm->fw->ucode_capa.api[0] & IWL_UCODE_TLV_API_SINGLE_SCAN_EBS &&
+	    mvm->last_ebs_successful) {
+		cmd->channel_opt[0].flags =
+			cpu_to_le16(IWL_SCAN_CHANNEL_FLAG_EBS |
+				    IWL_SCAN_CHANNEL_FLAG_EBS_ACCURATE |
+				    IWL_SCAN_CHANNEL_FLAG_CACHE_ADD);
+		cmd->channel_opt[0].non_ebs_ratio =
+			cpu_to_le16(IWL_DENSE_EBS_SCAN_RATIO);
+		cmd->channel_opt[1].flags =
+			cpu_to_le16(IWL_SCAN_CHANNEL_FLAG_EBS |
+				    IWL_SCAN_CHANNEL_FLAG_EBS_ACCURATE |
+				    IWL_SCAN_CHANNEL_FLAG_CACHE_ADD);
+		cmd->channel_opt[1].non_ebs_ratio =
+			cpu_to_le16(IWL_SPARSE_EBS_SCAN_RATIO);
+	}
 	for (i = 1; i <= req->req.n_ssids; i++)
 		ssid_bitmap |= BIT(i);
 	cmd->schedule[1].iterations = 0xff;
 	cmd->schedule[1].full_scan_mul = IWL_FULL_SCAN_MULTIPLIER;
+	if (mvm->fw->ucode_capa.flags & IWL_UCODE_TLV_FLAGS_EBS_SUPPORT &&
+	    mvm->last_ebs_successful) {
+		cmd->channel_opt[0].flags =
+			cpu_to_le16(IWL_SCAN_CHANNEL_FLAG_EBS |
+				    IWL_SCAN_CHANNEL_FLAG_EBS_ACCURATE |
+				    IWL_SCAN_CHANNEL_FLAG_CACHE_ADD);
+		cmd->channel_opt[0].non_ebs_ratio =
+			cpu_to_le16(IWL_DENSE_EBS_SCAN_RATIO);
+		cmd->channel_opt[1].flags =
+			cpu_to_le16(IWL_SCAN_CHANNEL_FLAG_EBS |
+				    IWL_SCAN_CHANNEL_FLAG_EBS_ACCURATE |
+				    IWL_SCAN_CHANNEL_FLAG_CACHE_ADD);
+		cmd->channel_opt[1].non_ebs_ratio =
+			cpu_to_le16(IWL_SPARSE_EBS_SCAN_RATIO);
+	}
 	iwl_mvm_lmac_scan_cfg_channels(mvm, req->channels, req->n_channels,
 				       ssid_bitmap, cmd);

drivers/net/wireless/iwlwifi/mvm/tx.c+9−2

 	if (ieee80211_is_probe_resp(fc))
 		tx_flags |= TX_CMD_FLG_TSF;
-	else if (ieee80211_is_back_req(fc))
-		tx_flags |= TX_CMD_FLG_ACK | TX_CMD_FLG_BAR;
 	if (ieee80211_has_morefrags(fc))
 		tx_flags |= TX_CMD_FLG_MORE_FRAG;
 		u8 *qc = ieee80211_get_qos_ctl(hdr);
 		tx_cmd->tid_tspec = qc[0] & 0xf;
 		tx_flags &= ~TX_CMD_FLG_SEQ_CTL;
+	} else if (ieee80211_is_back_req(fc)) {
+		struct ieee80211_bar *bar = (void *)skb->data;
+		u16 control = le16_to_cpu(bar->control);
+		tx_flags |= TX_CMD_FLG_ACK | TX_CMD_FLG_BAR;
+		tx_cmd->tid_tspec = (control &
+				     IEEE80211_BAR_CTRL_TID_INFO_MASK) >>
+			IEEE80211_BAR_CTRL_TID_INFO_SHIFT;
+		WARN_ON_ONCE(tx_cmd->tid_tspec >= IWL_MAX_TID_COUNT);
 	} else {
 		tx_cmd->tid_tspec = IWL_TID_NON_QOS;
 		if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)

drivers/pinctrl/pinctrl-at91.c+55−53

@@ -177,7 +177,7 @@ struct at91_pinctrl { · 176 unmodified lines
177	struct device *dev;	177	struct device *dev;
178	struct pinctrl_dev *pctl;	178	struct pinctrl_dev *pctl;
179		179
180	int nbanks;	180	int nactive_banks;
181		181
182	uint32_t *mux_mask;	182	uint32_t *mux_mask;
183	int nmux;	183	int nmux;
@@ -653,12 +653,18 @@ static int pin_check_config(struct at91_pinctrl info, const char name, · 469 unmodified lines
653	int mux;	653	int mux;
654		654
655	/* check if it's a valid config */	655	/* check if it's a valid config */
656	if (pin->bank >= info->nbanks) {	656	if (pin->bank >= gpio_banks) {
657	dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",	657	dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
658	name, index, pin->bank, info->nbanks);	658	name, index, pin->bank, gpio_banks);
659	return -EINVAL;	659	return -EINVAL;
660	}	660	}
661		661
		662	if (!gpio_chips[pin->bank]) {
		663	dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n",
		664	name, index, pin->bank);
		665	return -ENXIO;
		666	}
		667
662	if (pin->pin >= MAX_NB_GPIO_PER_BANK) {	668	if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
663	dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",	669	dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
664	name, index, pin->pin, MAX_NB_GPIO_PER_BANK);	670	name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
@@ -981,7 +987,8 @@ static void at91_pinctrl_child_count(struct at91_pinctrl *info, · 316 unmodified lines
981		987
982	for_each_child_of_node(np, child) {	988	for_each_child_of_node(np, child) {
983	if (of_device_is_compatible(child, gpio_compat)) {	989	if (of_device_is_compatible(child, gpio_compat)) {
984	info->nbanks++;	990	if (of_device_is_available(child))
		991	info->nactive_banks++;
985	} else {	992	} else {
986	info->nfunctions++;	993	info->nfunctions++;
987	info->ngroups += of_get_child_count(child);	994	info->ngroups += of_get_child_count(child);
@@ -1003,11 +1010,11 @@ static int at91_pinctrl_mux_mask(struct at91_pinctrl *info, · 15 unmodified lines
1003	}	1010	}
1004		1011
1005	size /= sizeof(*list);	1012	size /= sizeof(*list);
1006	if (!size \|\| size % info->nbanks) {	1013	if (!size \|\| size % gpio_banks) {
1007	dev_err(info->dev, "wrong mux mask array should be by %d\n", info->nbanks);	1014	dev_err(info->dev, "wrong mux mask array should be by %d\n", gpio_banks);
1008	return -EINVAL;	1015	return -EINVAL;
1009	}	1016	}
1010	info->nmux = size / info->nbanks;	1017	info->nmux = size / gpio_banks;
1011		1018
1012	info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL);	1019	info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL);
1013	if (!info->mux_mask) {	1020	if (!info->mux_mask) {
@@ -1131,7 +1138,7 @@ static int at91_pinctrl_probe_dt(struct platform_device *pdev, · 117 unmodified lines
1131	of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;	1138	of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
1132	at91_pinctrl_child_count(info, np);	1139	at91_pinctrl_child_count(info, np);
1133		1140
1134	if (info->nbanks < 1) {	1141	if (gpio_banks < 1) {
1135	dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n");	1142	dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n");
1136	return -EINVAL;	1143	return -EINVAL;
1137	}	1144	}
@@ -1144,7 +1151,7 @@ static int at91_pinctrl_probe_dt(struct platform_device *pdev, · 6 unmodified lines
1144		1151
1145	dev_dbg(&pdev->dev, "mux-mask\n");	1152	dev_dbg(&pdev->dev, "mux-mask\n");
1146	tmp = info->mux_mask;	1153	tmp = info->mux_mask;
1147	for (i = 0; i < info->nbanks; i++) {	1154	for (i = 0; i < gpio_banks; i++) {
1148	for (j = 0; j < info->nmux; j++, tmp++) {	1155	for (j = 0; j < info->nmux; j++, tmp++) {
1149	dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);	1156	dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
1150	}	1157	}
@@ -1162,7 +1169,7 @@ static int at91_pinctrl_probe_dt(struct platform_device *pdev, · 11 unmodified lines
1162	if (!info->groups)	1169	if (!info->groups)
1163	return -ENOMEM;	1170	return -ENOMEM;
1164		1171
1165	dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks);	1172	dev_dbg(&pdev->dev, "nbanks = %d\n", gpio_banks);
1166	dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);	1173	dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1167	dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);	1174	dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1168		1175
@@ -1185,7 +1192,7 @@ static int at91_pinctrl_probe(struct platform_device *pdev) · 16 unmodified lines
1185	{	1192	{
1186	struct at91_pinctrl *info;	1193	struct at91_pinctrl *info;
1187	struct pinctrl_pin_desc *pdesc;	1194	struct pinctrl_pin_desc *pdesc;
1188	int ret, i, j, k;	1195	int ret, i, j, k, ngpio_chips_enabled = 0;
1189		1196
1190	info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);	1197	info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1191	if (!info)	1198	if (!info)
@@ -1200,23 +1207,27 @@ static int at91_pinctrl_probe(struct platform_device *pdev) · 8 unmodified lines
1200	* to obtain references to the struct gpio_chip * for them, and we	1207	* to obtain references to the struct gpio_chip * for them, and we
1201	* need this to proceed.	1208	* need this to proceed.
1202	*/	1209	*/
1203	for (i = 0; i < info->nbanks; i++) {	1210	for (i = 0; i < gpio_banks; i++)
1204	if (!gpio_chips[i]) {	1211	if (gpio_chips[i])
1205	dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);	1212	ngpio_chips_enabled++;
1206	devm_kfree(&pdev->dev, info);	1213
1207	return -EPROBE_DEFER;	1214	if (ngpio_chips_enabled < info->nactive_banks) {
1208	}	1215	dev_warn(&pdev->dev,
		1216	"All GPIO chips are not registered yet (%d/%d)\n",
		1217	ngpio_chips_enabled, info->nactive_banks);
		1218	devm_kfree(&pdev->dev, info);
		1219	return -EPROBE_DEFER;
1209	}	1220	}
1210		1221
1211	at91_pinctrl_desc.name = dev_name(&pdev->dev);	1222	at91_pinctrl_desc.name = dev_name(&pdev->dev);
1212	at91_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK;	1223	at91_pinctrl_desc.npins = gpio_banks * MAX_NB_GPIO_PER_BANK;
1213	at91_pinctrl_desc.pins = pdesc =	1224	at91_pinctrl_desc.pins = pdesc =
1214	devm_kzalloc(&pdev->dev, sizeof(pdesc) at91_pinctrl_desc.npins, GFP_KERNEL);	1225	devm_kzalloc(&pdev->dev, sizeof(pdesc) at91_pinctrl_desc.npins, GFP_KERNEL);
1215		1226
1216	if (!at91_pinctrl_desc.pins)	1227	if (!at91_pinctrl_desc.pins)
1217	return -ENOMEM;	1228	return -ENOMEM;
1218		1229
1219	for (i = 0 , k = 0; i < info->nbanks; i++) {	1230	for (i = 0, k = 0; i < gpio_banks; i++) {
1220	for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {	1231	for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
1221	pdesc->number = k;	1232	pdesc->number = k;
1222	pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);	1233	pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
@@ -1234,8 +1245,9 @@ static int at91_pinctrl_probe(struct platform_device *pdev) · 11 unmodified lines
1234	}	1245	}
1235		1246
1236	/* We will handle a range of GPIO pins */	1247	/* We will handle a range of GPIO pins */
1237	for (i = 0; i < info->nbanks; i++)	1248	for (i = 0; i < gpio_banks; i++)
1238	pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);	1249	if (gpio_chips[i])
		1250	pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
1239		1251
1240	dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");	1252	dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
1241		1253
@@ -1613,9 +1625,10 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) · 371 unmodified lines
1613	static int at91_gpio_of_irq_setup(struct platform_device *pdev,	1625	static int at91_gpio_of_irq_setup(struct platform_device *pdev,
1614	struct at91_gpio_chip *at91_gpio)	1626	struct at91_gpio_chip *at91_gpio)
1615	{	1627	{
		1628	struct gpio_chip *gpiochip_prev = NULL;
1616	struct at91_gpio_chip *prev = NULL;	1629	struct at91_gpio_chip *prev = NULL;
1617	struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq);	1630	struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq);
1618	int ret;	1631	int ret, i;
1619		1632
1620	at91_gpio->pioc_hwirq = irqd_to_hwirq(d);	1633	at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
1621		1634
@@ -1641,24 +1654,33 @@ static int at91_gpio_of_irq_setup(struct platform_device *pdev, · 19 unmodified lines
1641	return ret;	1654	return ret;
1642	}	1655	}
1643		1656
1644	/* Setup chained handler */
1645	if (at91_gpio->pioc_idx)
1646	prev = gpio_chips[at91_gpio->pioc_idx - 1];
1647
1648	/* The top level handler handles one bank of GPIOs, except	1657	/* The top level handler handles one bank of GPIOs, except
1649	* on some SoC it can handle up to three...	1658	* on some SoC it can handle up to three...
1650	* We only set up the handler for the first of the list.	1659	* We only set up the handler for the first of the list.
1651	*/	1660	*/
1652	if (prev && prev->next == at91_gpio)	1661	gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq);
		1662	if (!gpiochip_prev) {
		1663	/* Then register the chain on the parent IRQ */
		1664	gpiochip_set_chained_irqchip(&at91_gpio->chip,
		1665	&gpio_irqchip,
		1666	at91_gpio->pioc_virq,
		1667	gpio_irq_handler);
1653	return 0;	1668	return 0;
		1669	}
1654		1670
1655	/* Then register the chain on the parent IRQ */	1671	prev = container_of(gpiochip_prev, struct at91_gpio_chip, chip);
1656	gpiochip_set_chained_irqchip(&at91_gpio->chip,
1657	&gpio_irqchip,
1658	at91_gpio->pioc_virq,
1659	gpio_irq_handler);
1660		1672
1661	return 0;	1673	/* we can only have 2 banks before */
		1674	for (i = 0; i < 2; i++) {
		1675	if (prev->next) {
		1676	prev = prev->next;
		1677	} else {
		1678	prev->next = at91_gpio;
		1679	return 0;
		1680	}
		1681	}
		1682
		1683	return -EINVAL;
1662	}	1684	}
1663		1685
1664	/* This structure is replicated for each GPIO block allocated at probe time */	1686	/* This structure is replicated for each GPIO block allocated at probe time */
@@ -1675,24 +1697,6 @@ static struct gpio_chip at91_gpio_template = { · 10 unmodified lines
1675	.ngpio = MAX_NB_GPIO_PER_BANK,	1697	.ngpio = MAX_NB_GPIO_PER_BANK,
1676	};	1698	};
1677		1699
1678	static void at91_gpio_probe_fixup(void)
1679	{
1680	unsigned i;
1681	struct at91_gpio_chip at91_gpio, last = NULL;
1682
1683	for (i = 0; i < gpio_banks; i++) {
1684	at91_gpio = gpio_chips[i];
1685
1686	/*
1687	* GPIO controller are grouped on some SoC:
1688	* PIOC, PIOD and PIOE can share the same IRQ line
1689	*/
1690	if (last && last->pioc_virq == at91_gpio->pioc_virq)
1691	last->next = at91_gpio;
1692	last = at91_gpio;
1693	}
1694	}
1695
1696	static struct of_device_id at91_gpio_of_match[] = {	1700	static struct of_device_id at91_gpio_of_match[] = {
1697	{ .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },	1701	{ .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1698	{ .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },	1702	{ .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
@@ -1805,8 +1809,6 @@ static int at91_gpio_probe(struct platform_device *pdev) · 106 unmodified lines
1805	gpio_chips[alias_idx] = at91_chip;	1809	gpio_chips[alias_idx] = at91_chip;
1806	gpio_banks = max(gpio_banks, alias_idx + 1);	1810	gpio_banks = max(gpio_banks, alias_idx + 1);
1807		1811
1808	at91_gpio_probe_fixup();
1809
1810	ret = at91_gpio_of_irq_setup(pdev, at91_chip);	1812	ret = at91_gpio_of_irq_setup(pdev, at91_chip);
1811	if (ret)	1813	if (ret)
1812	goto irq_setup_err;	1814	goto irq_setup_err;

drivers/regulator/core.c+3−1

 }
 EXPORT_SYMBOL_GPL(regulator_get_optional);
-/* Locks held by regulator_put() */
+/* regulator_list_mutex lock held by regulator_put() */
 static void _regulator_put(struct regulator *regulator)
 {
 	struct regulator_dev *rdev;
 	/* remove any sysfs entries */
 	if (regulator->dev)
 		sysfs_remove_link(&rdev->dev.kobj, regulator->supply_name);
+	mutex_lock(&rdev->mutex);
 	kfree(regulator->supply_name);
 	list_del(&regulator->list);
 	kfree(regulator);
 	rdev->open_count--;
 	rdev->exclusive = 0;
+	mutex_unlock(&rdev->mutex);
 	module_put(rdev->owner);
 }

drivers/regulator/s2mps11.c+38−4

@@ -405,6 +405,40 @@ static struct regulator_ops s2mps14_reg_ops; · 404 unmodified lines
405	.enable_mask = S2MPS14_ENABLE_MASK \	405	.enable_mask = S2MPS14_ENABLE_MASK \
406	}	406	}
407		407
		408	#define regulator_desc_s2mps13_buck7(num, min, step, min_sel) { \
		409	.name = "BUCK"#num, \
		410	.id = S2MPS13_BUCK##num, \
		411	.ops = &s2mps14_reg_ops, \
		412	.type = REGULATOR_VOLTAGE, \
		413	.owner = THIS_MODULE, \
		414	.min_uV = min, \
		415	.uV_step = step, \
		416	.linear_min_sel = min_sel, \
		417	.n_voltages = S2MPS14_BUCK_N_VOLTAGES, \
		418	.ramp_delay = S2MPS13_BUCK_RAMP_DELAY, \
		419	.vsel_reg = S2MPS13_REG_B1OUT + (num) * 2 - 1, \
		420	.vsel_mask = S2MPS14_BUCK_VSEL_MASK, \
		421	.enable_reg = S2MPS13_REG_B1CTRL + (num - 1) * 2, \
		422	.enable_mask = S2MPS14_ENABLE_MASK \
		423	}
		424
		425	#define regulator_desc_s2mps13_buck8_10(num, min, step, min_sel) { \
		426	.name = "BUCK"#num, \
		427	.id = S2MPS13_BUCK##num, \
		428	.ops = &s2mps14_reg_ops, \
		429	.type = REGULATOR_VOLTAGE, \
		430	.owner = THIS_MODULE, \
		431	.min_uV = min, \
		432	.uV_step = step, \
		433	.linear_min_sel = min_sel, \
		434	.n_voltages = S2MPS14_BUCK_N_VOLTAGES, \
		435	.ramp_delay = S2MPS13_BUCK_RAMP_DELAY, \
		436	.vsel_reg = S2MPS13_REG_B1OUT + (num) * 2 - 1, \
		437	.vsel_mask = S2MPS14_BUCK_VSEL_MASK, \
		438	.enable_reg = S2MPS13_REG_B1CTRL + (num) * 2 - 1, \
		439	.enable_mask = S2MPS14_ENABLE_MASK \
		440	}
		441
408	static const struct regulator_desc s2mps13_regulators[] = {	442	static const struct regulator_desc s2mps13_regulators[] = {
409	regulator_desc_s2mps13_ldo(1, MIN_800_MV, STEP_12_5_MV, 0x00),	443	regulator_desc_s2mps13_ldo(1, MIN_800_MV, STEP_12_5_MV, 0x00),
410	regulator_desc_s2mps13_ldo(2, MIN_1400_MV, STEP_50_MV, 0x0C),	444	regulator_desc_s2mps13_ldo(2, MIN_1400_MV, STEP_50_MV, 0x0C),
@@ -452,10 +486,10 @@ static const struct regulator_desc s2mps13_regulators[] = { · 41 unmodified lines
452	regulator_desc_s2mps13_buck(4, MIN_500_MV, STEP_6_25_MV, 0x10),	486	regulator_desc_s2mps13_buck(4, MIN_500_MV, STEP_6_25_MV, 0x10),
453	regulator_desc_s2mps13_buck(5, MIN_500_MV, STEP_6_25_MV, 0x10),	487	regulator_desc_s2mps13_buck(5, MIN_500_MV, STEP_6_25_MV, 0x10),
454	regulator_desc_s2mps13_buck(6, MIN_500_MV, STEP_6_25_MV, 0x10),	488	regulator_desc_s2mps13_buck(6, MIN_500_MV, STEP_6_25_MV, 0x10),
455	regulator_desc_s2mps13_buck(7, MIN_500_MV, STEP_6_25_MV, 0x10),	489	regulator_desc_s2mps13_buck7(7, MIN_500_MV, STEP_6_25_MV, 0x10),
456	regulator_desc_s2mps13_buck(8, MIN_1000_MV, STEP_12_5_MV, 0x20),	490	regulator_desc_s2mps13_buck8_10(8, MIN_1000_MV, STEP_12_5_MV, 0x20),
457	regulator_desc_s2mps13_buck(9, MIN_1000_MV, STEP_12_5_MV, 0x20),	491	regulator_desc_s2mps13_buck8_10(9, MIN_1000_MV, STEP_12_5_MV, 0x20),
458	regulator_desc_s2mps13_buck(10, MIN_500_MV, STEP_6_25_MV, 0x10),	492	regulator_desc_s2mps13_buck8_10(10, MIN_500_MV, STEP_6_25_MV, 0x10),
459	};	493	};
460		494
461	static int s2mps14_regulator_enable(struct regulator_dev *rdev)	495	static int s2mps14_regulator_enable(struct regulator_dev *rdev)

drivers/rtc/rtc-s5m.c+1−0

@@ -832,6 +832,7 @@ static SIMPLE_DEV_PM_OPS(s5m_rtc_pm_ops, s5m_rtc_suspend, s5m_rtc_resume); · 831 unmodified lines
832	static const struct platform_device_id s5m_rtc_id[] = {	832	static const struct platform_device_id s5m_rtc_id[] = {
833	{ "s5m-rtc", S5M8767X },	833	{ "s5m-rtc", S5M8767X },
834	{ "s2mps14-rtc", S2MPS14X },	834	{ "s2mps14-rtc", S2MPS14X },
		835	{ },
835	};	836	};
836		837
837	static struct platform_driver s5m_rtc_driver = {	838	static struct platform_driver s5m_rtc_driver = {

drivers/s390/net/qeth_core_main.c+101−16

@@ -1784,6 +1784,8 @@ static int qeth_idx_activate_get_answer(struct qeth_channel *channel, · 1783 unmodified lines
1784	QETH_DBF_TEXT(SETUP, 2, "idxanswr");	1784	QETH_DBF_TEXT(SETUP, 2, "idxanswr");
1785	card = CARD_FROM_CDEV(channel->ccwdev);	1785	card = CARD_FROM_CDEV(channel->ccwdev);
1786	iob = qeth_get_buffer(channel);	1786	iob = qeth_get_buffer(channel);
		1787	if (!iob)
		1788	return -ENOMEM;
1787	iob->callback = idx_reply_cb;	1789	iob->callback = idx_reply_cb;
1788	memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));	1790	memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
1789	channel->ccw.count = QETH_BUFSIZE;	1791	channel->ccw.count = QETH_BUFSIZE;
@@ -1834,6 +1836,8 @@ static int qeth_idx_activate_channel(struct qeth_channel *channel, · 44 unmodified lines
1834	QETH_DBF_TEXT(SETUP, 2, "idxactch");	1836	QETH_DBF_TEXT(SETUP, 2, "idxactch");
1835		1837
1836	iob = qeth_get_buffer(channel);	1838	iob = qeth_get_buffer(channel);
		1839	if (!iob)
		1840	return -ENOMEM;
1837	iob->callback = idx_reply_cb;	1841	iob->callback = idx_reply_cb;
1838	memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));	1842	memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
1839	channel->ccw.count = IDX_ACTIVATE_SIZE;	1843	channel->ccw.count = IDX_ACTIVATE_SIZE;
@@ -2021,10 +2025,36 @@ void qeth_prepare_control_data(struct qeth_card *card, int len, · 181 unmodified lines
2021	}	2025	}
2022	EXPORT_SYMBOL_GPL(qeth_prepare_control_data);	2026	EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
2023		2027
		2028	/**
		2029	* qeth_send_control_data() - send control command to the card
		2030	* @card: qeth_card structure pointer
		2031	* @len: size of the command buffer
		2032	* @iob: qeth_cmd_buffer pointer
		2033	* @reply_cb: callback function pointer
		2034	* @cb_card: pointer to the qeth_card structure
		2035	* @cb_reply: pointer to the qeth_reply structure
		2036	* @cb_cmd: pointer to the original iob for non-IPA
		2037	* commands, or to the qeth_ipa_cmd structure
		2038	* for the IPA commands.
		2039	* @reply_param: private pointer passed to the callback
		2040	*
		2041	* Returns the value of the `return_code' field of the response
		2042	* block returned from the hardware, or other error indication.
		2043	* Value of zero indicates successful execution of the command.
		2044	*
		2045	* Callback function gets called one or more times, with cb_cmd
		2046	* pointing to the response returned by the hardware. Callback
		2047	* function must return non-zero if more reply blocks are expected,
		2048	* and zero if the last or only reply block is received. Callback
		2049	* function can get the value of the reply_param pointer from the
		2050	* field 'param' of the structure qeth_reply.
		2051	*/
		2052
2024	int qeth_send_control_data(struct qeth_card *card, int len,	2053	int qeth_send_control_data(struct qeth_card *card, int len,
2025	struct qeth_cmd_buffer *iob,	2054	struct qeth_cmd_buffer *iob,
2026	int (reply_cb)(struct qeth_card , struct qeth_reply *,	2055	int (reply_cb)(struct qeth_card cb_card,
2027	unsigned long),	2056	struct qeth_reply *cb_reply,
		2057	unsigned long cb_cmd),
2028	void *reply_param)	2058	void *reply_param)
2029	{	2059	{
2030	int rc;	2060	int rc;
@@ -2914,9 +2944,16 @@ struct qeth_cmd_buffer qeth_get_ipacmd_buffer(struct qeth_card card, · 883 unmodified lines
2914	struct qeth_cmd_buffer *iob;	2944	struct qeth_cmd_buffer *iob;
2915	struct qeth_ipa_cmd *cmd;	2945	struct qeth_ipa_cmd *cmd;
2916		2946
2917	iob = qeth_wait_for_buffer(&card->write);	2947	iob = qeth_get_buffer(&card->write);
2918	cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);	2948	if (iob) {
2919	qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);	2949	cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
		2950	qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
		2951	} else {
		2952	dev_warn(&card->gdev->dev,
		2953	"The qeth driver ran out of channel command buffers\n");
		2954	QETH_DBF_MESSAGE(1, "%s The qeth driver ran out of channel command buffers",
		2955	dev_name(&card->gdev->dev));
		2956	}
2920		2957
2921	return iob;	2958	return iob;
2922	}	2959	}
@@ -2932,6 +2969,12 @@ void qeth_prepare_ipa_cmd(struct qeth_card card, struct qeth_cmd_buffer iob, · 9 unmodified lines
2932	}	2969	}
2933	EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);	2970	EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
2934		2971
		2972	/**
		2973	* qeth_send_ipa_cmd() - send an IPA command
		2974	*
		2975	* See qeth_send_control_data() for explanation of the arguments.
		2976	*/
		2977
2935	int qeth_send_ipa_cmd(struct qeth_card card, struct qeth_cmd_buffer iob,	2978	int qeth_send_ipa_cmd(struct qeth_card card, struct qeth_cmd_buffer iob,
2936	int (reply_cb)(struct qeth_card , struct qeth_reply*,	2979	int (reply_cb)(struct qeth_card , struct qeth_reply*,
2937	unsigned long),	2980	unsigned long),
@@ -2968,6 +3011,8 @@ int qeth_send_startlan(struct qeth_card *card) · 30 unmodified lines
2968	QETH_DBF_TEXT(SETUP, 2, "strtlan");	3011	QETH_DBF_TEXT(SETUP, 2, "strtlan");
2969		3012
2970	iob = qeth_get_ipacmd_buffer(card, IPA_CMD_STARTLAN, 0);	3013	iob = qeth_get_ipacmd_buffer(card, IPA_CMD_STARTLAN, 0);
		3014	if (!iob)
		3015	return -ENOMEM;
2971	rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);	3016	rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
2972	return rc;	3017	return rc;
2973	}	3018	}
@@ -3013,11 +3058,13 @@ static struct qeth_cmd_buffer qeth_get_adapter_cmd(struct qeth_card card, · 39 unmodified lines
3013		3058
3014	iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,	3059	iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
3015	QETH_PROT_IPV4);	3060	QETH_PROT_IPV4);
3016	cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);	3061	if (iob) {
3017	cmd->data.setadapterparms.hdr.cmdlength = cmdlen;	3062	cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
3018	cmd->data.setadapterparms.hdr.command_code = command;	3063	cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
3019	cmd->data.setadapterparms.hdr.used_total = 1;	3064	cmd->data.setadapterparms.hdr.command_code = command;
3020	cmd->data.setadapterparms.hdr.seq_no = 1;	3065	cmd->data.setadapterparms.hdr.used_total = 1;
		3066	cmd->data.setadapterparms.hdr.seq_no = 1;
		3067	}
3021		3068
3022	return iob;	3069	return iob;
3023	}	3070	}
@@ -3030,6 +3077,8 @@ int qeth_query_setadapterparms(struct qeth_card *card) · 6 unmodified lines
3030	QETH_CARD_TEXT(card, 3, "queryadp");	3077	QETH_CARD_TEXT(card, 3, "queryadp");
3031	iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,	3078	iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
3032	sizeof(struct qeth_ipacmd_setadpparms));	3079	sizeof(struct qeth_ipacmd_setadpparms));
		3080	if (!iob)
		3081	return -ENOMEM;
3033	rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);	3082	rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
3034	return rc;	3083	return rc;
3035	}	3084	}
@@ -3080,6 +3129,8 @@ int qeth_query_ipassists(struct qeth_card *card, enum qeth_prot_versions prot) · 44 unmodified lines
3080		3129
3081	QETH_DBF_TEXT_(SETUP, 2, "qipassi%i", prot);	3130	QETH_DBF_TEXT_(SETUP, 2, "qipassi%i", prot);
3082	iob = qeth_get_ipacmd_buffer(card, IPA_CMD_QIPASSIST, prot);	3131	iob = qeth_get_ipacmd_buffer(card, IPA_CMD_QIPASSIST, prot);
		3132	if (!iob)
		3133	return -ENOMEM;
3083	rc = qeth_send_ipa_cmd(card, iob, qeth_query_ipassists_cb, NULL);	3134	rc = qeth_send_ipa_cmd(card, iob, qeth_query_ipassists_cb, NULL);
3084	return rc;	3135	return rc;
3085	}	3136	}
@@ -3119,6 +3170,8 @@ int qeth_query_switch_attributes(struct qeth_card *card, · 33 unmodified lines
3119	return -ENOMEDIUM;	3170	return -ENOMEDIUM;
3120	iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_SWITCH_ATTRIBUTES,	3171	iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_SWITCH_ATTRIBUTES,
3121	sizeof(struct qeth_ipacmd_setadpparms_hdr));	3172	sizeof(struct qeth_ipacmd_setadpparms_hdr));
		3173	if (!iob)
		3174	return -ENOMEM;
3122	return qeth_send_ipa_cmd(card, iob,	3175	return qeth_send_ipa_cmd(card, iob,
3123	qeth_query_switch_attributes_cb, sw_info);	3176	qeth_query_switch_attributes_cb, sw_info);
3124	}	3177	}
@@ -3146,6 +3199,8 @@ static int qeth_query_setdiagass(struct qeth_card *card) · 21 unmodified lines
3146		3199
3147	QETH_DBF_TEXT(SETUP, 2, "qdiagass");	3200	QETH_DBF_TEXT(SETUP, 2, "qdiagass");
3148	iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SET_DIAG_ASS, 0);	3201	iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SET_DIAG_ASS, 0);
		3202	if (!iob)
		3203	return -ENOMEM;
3149	cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);	3204	cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
3150	cmd->data.diagass.subcmd_len = 16;	3205	cmd->data.diagass.subcmd_len = 16;
3151	cmd->data.diagass.subcmd = QETH_DIAGS_CMD_QUERY;	3206	cmd->data.diagass.subcmd = QETH_DIAGS_CMD_QUERY;
@@ -3197,6 +3252,8 @@ int qeth_hw_trap(struct qeth_card *card, enum qeth_diags_trap_action action) · 45 unmodified lines
3197		3252
3198	QETH_DBF_TEXT(SETUP, 2, "diagtrap");	3253	QETH_DBF_TEXT(SETUP, 2, "diagtrap");
3199	iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SET_DIAG_ASS, 0);	3254	iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SET_DIAG_ASS, 0);
		3255	if (!iob)
		3256	return -ENOMEM;
3200	cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);	3257	cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
3201	cmd->data.diagass.subcmd_len = 80;	3258	cmd->data.diagass.subcmd_len = 80;
3202	cmd->data.diagass.subcmd = QETH_DIAGS_CMD_TRAP;	3259	cmd->data.diagass.subcmd = QETH_DIAGS_CMD_TRAP;
@@ -4162,6 +4219,8 @@ void qeth_setadp_promisc_mode(struct qeth_card *card) · 959 unmodified lines
4162		4219
4163	iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,	4220	iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
4164	sizeof(struct qeth_ipacmd_setadpparms));	4221	sizeof(struct qeth_ipacmd_setadpparms));
		4222	if (!iob)
		4223	return;
4165	cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);	4224	cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
4166	cmd->data.setadapterparms.data.mode = mode;	4225	cmd->data.setadapterparms.data.mode = mode;
4167	qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);	4226	qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
@@ -4232,6 +4291,8 @@ int qeth_setadpparms_change_macaddr(struct qeth_card *card) · 64 unmodified lines
4232		4291
4233	iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,	4292	iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
4234	sizeof(struct qeth_ipacmd_setadpparms));	4293	sizeof(struct qeth_ipacmd_setadpparms));
		4294	if (!iob)
		4295	return -ENOMEM;
4235	cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);	4296	cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
4236	cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;	4297	cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
4237	cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;	4298	cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
@@ -4345,6 +4406,8 @@ static int qeth_setadpparms_set_access_ctrl(struct qeth_card *card, · 107 unmodified lines
4345	iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_ACCESS_CONTROL,	4406	iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_ACCESS_CONTROL,
4346	sizeof(struct qeth_ipacmd_setadpparms_hdr) +	4407	sizeof(struct qeth_ipacmd_setadpparms_hdr) +
4347	sizeof(struct qeth_set_access_ctrl));	4408	sizeof(struct qeth_set_access_ctrl));
		4409	if (!iob)
		4410	return -ENOMEM;
4348	cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);	4411	cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
4349	access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;	4412	access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
4350	access_ctrl_req->subcmd_code = isolation;	4413	access_ctrl_req->subcmd_code = isolation;
@@ -4588,6 +4651,10 @@ int qeth_snmp_command(struct qeth_card card, char __user udata) · 237 unmodified lines
4588		4651
4589	iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,	4652	iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
4590	QETH_SNMP_SETADP_CMDLENGTH + req_len);	4653	QETH_SNMP_SETADP_CMDLENGTH + req_len);
		4654	if (!iob) {
		4655	rc = -ENOMEM;
		4656	goto out;
		4657	}
4591	cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);	4658	cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
4592	memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);	4659	memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
4593	rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,	4660	rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
@@ -4599,7 +4666,7 @@ int qeth_snmp_command(struct qeth_card card, char __user udata) · 5 unmodified lines
4599	if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))	4666	if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
4600	rc = -EFAULT;	4667	rc = -EFAULT;
4601	}	4668	}
4602		4669	out:
4603	kfree(ureq);	4670	kfree(ureq);
4604	kfree(qinfo.udata);	4671	kfree(qinfo.udata);
4605	return rc;	4672	return rc;
@@ -4670,6 +4737,10 @@ int qeth_query_oat_command(struct qeth_card card, char __user udata) · 64 unmodified lines
4670	iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_OAT,	4737	iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_OAT,
4671	sizeof(struct qeth_ipacmd_setadpparms_hdr) +	4738	sizeof(struct qeth_ipacmd_setadpparms_hdr) +
4672	sizeof(struct qeth_query_oat));	4739	sizeof(struct qeth_query_oat));
		4740	if (!iob) {
		4741	rc = -ENOMEM;
		4742	goto out_free;
		4743	}
4673	cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);	4744	cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
4674	oat_req = &cmd->data.setadapterparms.data.query_oat;	4745	oat_req = &cmd->data.setadapterparms.data.query_oat;
4675	oat_req->subcmd_code = oat_data.command;	4746	oat_req->subcmd_code = oat_data.command;
@@ -4735,6 +4806,8 @@ static int qeth_query_card_info(struct qeth_card *card, · 59 unmodified lines
4735	return -EOPNOTSUPP;	4806	return -EOPNOTSUPP;
4736	iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_CARD_INFO,	4807	iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_CARD_INFO,
4737	sizeof(struct qeth_ipacmd_setadpparms_hdr));	4808	sizeof(struct qeth_ipacmd_setadpparms_hdr));
		4809	if (!iob)
		4810	return -ENOMEM;
4738	return qeth_send_ipa_cmd(card, iob, qeth_query_card_info_cb,	4811	return qeth_send_ipa_cmd(card, iob, qeth_query_card_info_cb,
4739	(void *)carrier_info);	4812	(void *)carrier_info);
4740	}	4813	}
@@ -5060,11 +5133,23 @@ retriable: · 319 unmodified lines
5060	card->options.adp.supported_funcs = 0;	5133	card->options.adp.supported_funcs = 0;
5061	card->options.sbp.supported_funcs = 0;	5134	card->options.sbp.supported_funcs = 0;
5062	card->info.diagass_support = 0;	5135	card->info.diagass_support = 0;
5063	qeth_query_ipassists(card, QETH_PROT_IPV4);	5136	rc = qeth_query_ipassists(card, QETH_PROT_IPV4);
5064	if (qeth_is_supported(card, IPA_SETADAPTERPARMS))	5137	if (rc == -ENOMEM)
5065	qeth_query_setadapterparms(card);	5138	goto out;
5066	if (qeth_adp_supported(card, IPA_SETADP_SET_DIAG_ASSIST))	5139	if (qeth_is_supported(card, IPA_SETADAPTERPARMS)) {
5067	qeth_query_setdiagass(card);	5140	rc = qeth_query_setadapterparms(card);
		5141	if (rc < 0) {
		5142	QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
		5143	goto out;
		5144	}
		5145	}
		5146	if (qeth_adp_supported(card, IPA_SETADP_SET_DIAG_ASSIST)) {
		5147	rc = qeth_query_setdiagass(card);
		5148	if (rc < 0) {
		5149	QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
		5150	goto out;
		5151	}
		5152	}
5068	return 0;	5153	return 0;
5069	out:	5154	out:
5070	dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "	5155	dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "

drivers/s390/net/qeth_l2_main.c+108−112

 static int qeth_l2_stop(struct net_device *);
 static int qeth_l2_send_delmac(struct qeth_card *, __u8 *);
 static int qeth_l2_send_setdelmac(struct qeth_card *, __u8 *,
-			   enum qeth_ipa_cmds,
+			   enum qeth_ipa_cmds);
-			   int (*reply_cb) (struct qeth_card *,
-					    struct qeth_reply*,
-					    unsigned long));
 static void qeth_l2_set_multicast_list(struct net_device *);
 static int qeth_l2_recover(void *);
 static void qeth_bridgeport_query_support(struct qeth_card *card);
 	return ndev;
 }
-static int qeth_l2_send_setgroupmac_cb(struct qeth_card *card,
+static int qeth_setdel_makerc(struct qeth_card *card, int retcode)
-				struct qeth_reply *reply,
-				unsigned long data)
 {
-	struct qeth_ipa_cmd *cmd;
+	int rc;
-	__u8 *mac;
-	QETH_CARD_TEXT(card, 2, "L2Sgmacb");
+	if (retcode)
-	cmd = (struct qeth_ipa_cmd *) data;
+		QETH_CARD_TEXT_(card, 2, "err%04x", retcode);
-	mac = &cmd->data.setdelmac.mac[0];
+	switch (retcode) {
-	/* MAC already registered, needed in couple/uncouple case */
+	case IPA_RC_SUCCESS:
-	if (cmd->hdr.return_code ==  IPA_RC_L2_DUP_MAC) {
+		rc = 0;
-		QETH_DBF_MESSAGE(2, "Group MAC %pM already existing on %s \n",
+		break;
-			  mac, QETH_CARD_IFNAME(card));
+	case IPA_RC_L2_UNSUPPORTED_CMD:
-		cmd->hdr.return_code = 0;
+		rc = -ENOSYS;
+		break;
+	case IPA_RC_L2_ADDR_TABLE_FULL:
+		rc = -ENOSPC;
+		break;
+	case IPA_RC_L2_DUP_MAC:
+	case IPA_RC_L2_DUP_LAYER3_MAC:
+		rc = -EEXIST;
+		break;
+	case IPA_RC_L2_MAC_NOT_AUTH_BY_HYP:
+	case IPA_RC_L2_MAC_NOT_AUTH_BY_ADP:
+		rc = -EPERM;
+		break;
+	case IPA_RC_L2_MAC_NOT_FOUND:
+		rc = -ENOENT;
+		break;
+	case -ENOMEM:
+		rc = -ENOMEM;
+		break;
+	default:
+		rc = -EIO;
+		break;
 	}
-	if (cmd->hdr.return_code)
+	return rc;
-		QETH_DBF_MESSAGE(2, "Could not set group MAC %pM on %s: %x\n",
-			  mac, QETH_CARD_IFNAME(card), cmd->hdr.return_code);
-	return 0;
 }
 static int qeth_l2_send_setgroupmac(struct qeth_card *card, __u8 *mac)
 {
-	QETH_CARD_TEXT(card, 2, "L2Sgmac");
+	int rc;
-	return qeth_l2_send_setdelmac(card, mac, IPA_CMD_SETGMAC,
-					  qeth_l2_send_setgroupmac_cb);
-}
-static int qeth_l2_send_delgroupmac_cb(struct qeth_card *card,
-				struct qeth_reply *reply,
-				unsigned long data)
-{
-	struct qeth_ipa_cmd *cmd;
-	__u8 *mac;
-	QETH_CARD_TEXT(card, 2, "L2Dgmacb");
+	QETH_CARD_TEXT(card, 2, "L2Sgmac");
-	cmd = (struct qeth_ipa_cmd *) data;
+	rc = qeth_setdel_makerc(card, qeth_l2_send_setdelmac(card, mac,
-	mac = &cmd->data.setdelmac.mac[0];
+					IPA_CMD_SETGMAC));
-	if (cmd->hdr.return_code)
+	if (rc == -EEXIST)
-		QETH_DBF_MESSAGE(2, "Could not delete group MAC %pM on %s: %x\n",
+		QETH_DBF_MESSAGE(2, "Group MAC %pM already existing on %s\n",
-			  mac, QETH_CARD_IFNAME(card), cmd->hdr.return_code);
+			mac, QETH_CARD_IFNAME(card));
-	return 0;
+	else if (rc)
+		QETH_DBF_MESSAGE(2, "Could not set group MAC %pM on %s: %d\n",
+			mac, QETH_CARD_IFNAME(card), rc);
+	return rc;
 }
 static int qeth_l2_send_delgroupmac(struct qeth_card *card, __u8 *mac)
 {
+	int rc;
 	QETH_CARD_TEXT(card, 2, "L2Dgmac");
-	return qeth_l2_send_setdelmac(card, mac, IPA_CMD_DELGMAC,
+	rc = qeth_setdel_makerc(card, qeth_l2_send_setdelmac(card, mac,
-					  qeth_l2_send_delgroupmac_cb);
+					IPA_CMD_DELGMAC));
+	if (rc)
+		QETH_DBF_MESSAGE(2,
+			"Could not delete group MAC %pM on %s: %d\n",
+			mac, QETH_CARD_IFNAME(card), rc);
+	return rc;
 }
 static void qeth_l2_add_mc(struct qeth_card *card, __u8 *mac, int vmac)
 	mc->is_vmac = vmac;
 	if (vmac) {
-		rc = qeth_l2_send_setdelmac(card, mac, IPA_CMD_SETVMAC,
+		rc = qeth_setdel_makerc(card,
-					NULL);
+			qeth_l2_send_setdelmac(card, mac, IPA_CMD_SETVMAC));
 	} else {
-		rc = qeth_l2_send_setgroupmac(card, mac);
+		rc = qeth_setdel_makerc(card,
+			qeth_l2_send_setgroupmac(card, mac));
 	}
 	if (!rc)
 		if (del) {
 			if (mc->is_vmac)
 				qeth_l2_send_setdelmac(card, mc->mc_addr,
-					IPA_CMD_DELVMAC, NULL);
+					IPA_CMD_DELVMAC);
 			else
 				qeth_l2_send_delgroupmac(card, mc->mc_addr);
 		}
 	QETH_CARD_TEXT_(card, 4, "L2sdv%x", ipacmd);
 	iob = qeth_get_ipacmd_buffer(card, ipacmd, QETH_PROT_IPV4);
+	if (!iob)
+		return -ENOMEM;
 	cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
 	cmd->data.setdelvlan.vlan_id = i;
 	return qeth_send_ipa_cmd(card, iob,
 {
 	struct qeth_card *card = dev->ml_priv;
 	struct qeth_vlan_vid *id;
+	int rc;
 	QETH_CARD_TEXT_(card, 4, "aid:%d", vid);
 	if (!vid)
 	id = kmalloc(sizeof(struct qeth_vlan_vid), GFP_ATOMIC);
 	if (id) {
 		id->vid = vid;
-		qeth_l2_send_setdelvlan(card, vid, IPA_CMD_SETVLAN);
+		rc = qeth_l2_send_setdelvlan(card, vid, IPA_CMD_SETVLAN);
+		if (rc) {
+			kfree(id);
+			return rc;
+		}
 		spin_lock_bh(&card->vlanlock);
 		list_add_tail(&id->list, &card->vid_list);
 		spin_unlock_bh(&card->vlanlock);
 {
 	struct qeth_vlan_vid *id, *tmpid = NULL;
 	struct qeth_card *card = dev->ml_priv;
+	int rc = 0;
 	QETH_CARD_TEXT_(card, 4, "kid:%d", vid);
 	if (card->info.type == QETH_CARD_TYPE_OSM) {
 	}
 	spin_unlock_bh(&card->vlanlock);
 	if (tmpid) {
-		qeth_l2_send_setdelvlan(card, vid, IPA_CMD_DELVLAN);
+		rc = qeth_l2_send_setdelvlan(card, vid, IPA_CMD_DELVLAN);
 		kfree(tmpid);
 	}
 	qeth_l2_set_multicast_list(card->dev);
-	return 0;
+	return rc;
 }
 static int qeth_l2_stop_card(struct qeth_card *card, int recovery_mode)
 }
 static int qeth_l2_send_setdelmac(struct qeth_card *card, __u8 *mac,
-			   enum qeth_ipa_cmds ipacmd,
+			   enum qeth_ipa_cmds ipacmd)
-			   int (*reply_cb) (struct qeth_card *,
-					    struct qeth_reply*,
-					    unsigned long))
 {
 	struct qeth_ipa_cmd *cmd;
 	struct qeth_cmd_buffer *iob;
 	QETH_CARD_TEXT(card, 2, "L2sdmac");
 	iob = qeth_get_ipacmd_buffer(card, ipacmd, QETH_PROT_IPV4);
+	if (!iob)
+		return -ENOMEM;
 	cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
 	cmd->data.setdelmac.mac_length = OSA_ADDR_LEN;
 	memcpy(&cmd->data.setdelmac.mac, mac, OSA_ADDR_LEN);
-	return qeth_send_ipa_cmd(card, iob, reply_cb, NULL);
+	return qeth_send_ipa_cmd(card, iob, NULL, NULL);
 }
-static int qeth_l2_send_setmac_cb(struct qeth_card *card,
+static int qeth_l2_send_setmac(struct qeth_card *card, __u8 *mac)
-			   struct qeth_reply *reply,
-			   unsigned long data)
 {
-	struct qeth_ipa_cmd *cmd;
+	int rc;
-	QETH_CARD_TEXT(card, 2, "L2Smaccb");
+	QETH_CARD_TEXT(card, 2, "L2Setmac");
-	cmd = (struct qeth_ipa_cmd *) data;
+	rc = qeth_setdel_makerc(card, qeth_l2_send_setdelmac(card, mac,
-	if (cmd->hdr.return_code) {
+					IPA_CMD_SETVMAC));
-		QETH_CARD_TEXT_(card, 2, "L2er%x", cmd->hdr.return_code);
+	if (rc == 0) {
+		card->info.mac_bits |= QETH_LAYER2_MAC_REGISTERED;
+		memcpy(card->dev->dev_addr, mac, OSA_ADDR_LEN);
+		dev_info(&card->gdev->dev,
+			"MAC address %pM successfully registered on device %s\n",
+			card->dev->dev_addr, card->dev->name);
+	} else {
 		card->info.mac_bits &= ~QETH_LAYER2_MAC_REGISTERED;
-		switch (cmd->hdr.return_code) {
+		switch (rc) {
-		case IPA_RC_L2_DUP_MAC:
+		case -EEXIST:
-		case IPA_RC_L2_DUP_LAYER3_MAC:
 			dev_warn(&card->gdev->dev,
-				"MAC address %pM already exists\n",
+				"MAC address %pM already exists\n", mac);
-				cmd->data.setdelmac.mac);
 			break;
-		case IPA_RC_L2_MAC_NOT_AUTH_BY_HYP:
+		case -EPERM:
-		case IPA_RC_L2_MAC_NOT_AUTH_BY_ADP:
 			dev_warn(&card->gdev->dev,
-				"MAC address %pM is not authorized\n",
+				"MAC address %pM is not authorized\n", mac);
-				cmd->data.setdelmac.mac);
-			break;
-		default:
 			break;
 		}
-	} else {
-		card->info.mac_bits |= QETH_LAYER2_MAC_REGISTERED;
-		memcpy(card->dev->dev_addr, cmd->data.setdelmac.mac,
-		       OSA_ADDR_LEN);
-		dev_info(&card->gdev->dev,
-			"MAC address %pM successfully registered on device %s\n",
-			card->dev->dev_addr, card->dev->name);
-	}
-	return 0;
-}
-static int qeth_l2_send_setmac(struct qeth_card *card, __u8 *mac)
-{
-	QETH_CARD_TEXT(card, 2, "L2Setmac");
-	return qeth_l2_send_setdelmac(card, mac, IPA_CMD_SETVMAC,
-					  qeth_l2_send_setmac_cb);
-}
-static int qeth_l2_send_delmac_cb(struct qeth_card *card,
-			   struct qeth_reply *reply,
-			   unsigned long data)
-{
-	struct qeth_ipa_cmd *cmd;
-	QETH_CARD_TEXT(card, 2, "L2Dmaccb");
-	cmd = (struct qeth_ipa_cmd *) data;
-	if (cmd->hdr.return_code) {
-		QETH_CARD_TEXT_(card, 2, "err%d", cmd->hdr.return_code);
-		return 0;
 	}
-	card->info.mac_bits &= ~QETH_LAYER2_MAC_REGISTERED;
+	return rc;
-	return 0;
 }
 static int qeth_l2_send_delmac(struct qeth_card *card, __u8 *mac)
 {
+	int rc;
 	QETH_CARD_TEXT(card, 2, "L2Delmac");
 	if (!(card->info.mac_bits & QETH_LAYER2_MAC_REGISTERED))
 		return 0;
-	return qeth_l2_send_setdelmac(card, mac, IPA_CMD_DELVMAC,
+	rc = qeth_setdel_makerc(card, qeth_l2_send_setdelmac(card, mac,
-					  qeth_l2_send_delmac_cb);
+					IPA_CMD_DELVMAC));
+	if (rc == 0)
+		card->info.mac_bits &= ~QETH_LAYER2_MAC_REGISTERED;
+	return rc;
 }
 static int qeth_l2_request_initial_mac(struct qeth_card *card)
 		if (rc) {
 			QETH_DBF_MESSAGE(2, "couldn't get MAC address on "
 				"device %s: x%x\n", CARD_BUS_ID(card), rc);
-			QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
+			QETH_DBF_TEXT_(SETUP, 2, "1err%04x", rc);
 			return rc;
 		}
 		QETH_DBF_HEX(SETUP, 2, card->dev->dev_addr, OSA_ADDR_LEN);
 		return -ERESTARTSYS;
 	}
 	rc = qeth_l2_send_delmac(card, &card->dev->dev_addr[0]);
-	if (!rc || (rc == IPA_RC_L2_MAC_NOT_FOUND))
+	if (!rc || (rc == -ENOENT))
 		rc = qeth_l2_send_setmac(card, addr->sa_data);
 	return rc ? -EINVAL : 0;
 }
 	recover_flag = card->state;
 	rc = qeth_core_hardsetup_card(card);
 	if (rc) {
-		QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
+		QETH_DBF_TEXT_(SETUP, 2, "2err%04x", rc);
 		rc = -ENODEV;
 		goto out_remove;
 	}
 	QETH_CARD_TEXT(card, 2, "brqsuppo");
 	iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETBRIDGEPORT, 0);
+	if (!iob)
+		return;
 	cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
 	cmd->data.sbp.hdr.cmdlength =
 		sizeof(struct qeth_ipacmd_sbp_hdr) +
 	if (!(card->options.sbp.supported_funcs & IPA_SBP_QUERY_BRIDGE_PORTS))
 		return -EOPNOTSUPP;
 	iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETBRIDGEPORT, 0);
+	if (!iob)
+		return -ENOMEM;
 	cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
 	cmd->data.sbp.hdr.cmdlength =
 		sizeof(struct qeth_ipacmd_sbp_hdr);
 	if (rc)
 		return rc;
 	rc = qeth_bridgeport_makerc(card, &cbctl, IPA_SBP_QUERY_BRIDGE_PORTS);
-	if (rc)
+	return rc;
-		return rc;
-	return 0;
 }
 EXPORT_SYMBOL_GPL(qeth_bridgeport_query_ports);
 	if (!(card->options.sbp.supported_funcs & setcmd))
 		return -EOPNOTSUPP;
 	iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETBRIDGEPORT, 0);
+	if (!iob)
+		return -ENOMEM;
 	cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
 	cmd->data.sbp.hdr.cmdlength = cmdlength;
 	cmd->data.sbp.hdr.command_code = setcmd;

drivers/s390/net/qeth_l3_main.c+39−11

 	QETH_CARD_TEXT(card, 4, "setdelmc");
 	iob = qeth_get_ipacmd_buffer(card, ipacmd, addr->proto);
+	if (!iob)
+		return -ENOMEM;
 	cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
 	memcpy(&cmd->data.setdelipm.mac, addr->mac, OSA_ADDR_LEN);
 	if (addr->proto == QETH_PROT_IPV6)
 	QETH_CARD_TEXT_(card, 4, "flags%02X", flags);
 	iob = qeth_get_ipacmd_buffer(card, ipacmd, addr->proto);
+	if (!iob)
+		return -ENOMEM;
 	cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
 	if (addr->proto == QETH_PROT_IPV6) {
 		memcpy(cmd->data.setdelip6.ip_addr, &addr->u.a6.addr,
 	QETH_CARD_TEXT(card, 4, "setroutg");
 	iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETRTG, prot);
+	if (!iob)
+		return -ENOMEM;
 	cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
 	cmd->data.setrtg.type = (type);
 	rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
 	QETH_CARD_TEXT(card, 4, "getasscm");
 	iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETASSPARMS, prot);
-	cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
+	if (iob) {
-	cmd->data.setassparms.hdr.assist_no = ipa_func;
+		cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
-	cmd->data.setassparms.hdr.length = 8 + len;
+		cmd->data.setassparms.hdr.assist_no = ipa_func;
-	cmd->data.setassparms.hdr.command_code = cmd_code;
+		cmd->data.setassparms.hdr.length = 8 + len;
-	cmd->data.setassparms.hdr.return_code = 0;
+		cmd->data.setassparms.hdr.command_code = cmd_code;
-	cmd->data.setassparms.hdr.seq_no = 0;
+		cmd->data.setassparms.hdr.return_code = 0;
+		cmd->data.setassparms.hdr.seq_no = 0;
+	}
 	return iob;
 }
 	QETH_CARD_TEXT(card, 4, "simassp6");
 	iob = qeth_l3_get_setassparms_cmd(card, ipa_func, cmd_code,
 				       0, QETH_PROT_IPV6);
+	if (!iob)
+		return -ENOMEM;
 	rc = qeth_l3_send_setassparms(card, iob, 0, 0,
 				   qeth_l3_default_setassparms_cb, NULL);
 	return rc;
 		length = sizeof(__u32);
 	iob = qeth_l3_get_setassparms_cmd(card, ipa_func, cmd_code,
 				       length, QETH_PROT_IPV4);
+	if (!iob)
+		return -ENOMEM;
 	rc = qeth_l3_send_setassparms(card, iob, length, data,
 				   qeth_l3_default_setassparms_cb, NULL);
 	return rc;
 	iob = qeth_get_ipacmd_buffer(card, IPA_CMD_CREATE_ADDR,
 				     QETH_PROT_IPV6);
+	if (!iob)
+		return -ENOMEM;
 	cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
 	*((__u16 *) &cmd->data.create_destroy_addr.unique_id[6]) =
 			card->info.unique_id;
 	iob = qeth_get_ipacmd_buffer(card, IPA_CMD_CREATE_ADDR,
 				     QETH_PROT_IPV6);
+	if (!iob)
+		return -ENOMEM;
 	cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
 	*((__u16 *) &cmd->data.create_destroy_addr.unique_id[6]) =
 			card->info.unique_id;
 	QETH_DBF_TEXT(SETUP, 2, "diagtrac");
 	iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SET_DIAG_ASS, 0);
+	if (!iob)
+		return -ENOMEM;
 	cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
 	cmd->data.diagass.subcmd_len = 16;
 	cmd->data.diagass.subcmd = QETH_DIAGS_CMD_TRACE;
 			IPA_CMD_ASS_ARP_QUERY_INFO,
 			sizeof(struct qeth_arp_query_data) - sizeof(char),
 			prot);
+	if (!iob)
+		return -ENOMEM;
 	cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
 	cmd->data.setassparms.data.query_arp.request_bits = 0x000F;
 	cmd->data.setassparms.data.query_arp.reply_bits = 0;
 				       IPA_CMD_ASS_ARP_ADD_ENTRY,
 				       sizeof(struct qeth_arp_cache_entry),
 				       QETH_PROT_IPV4);
+	if (!iob)
+		return -ENOMEM;
 	rc = qeth_l3_send_setassparms(card, iob,
 				   sizeof(struct qeth_arp_cache_entry),
 				   (unsigned long) entry,
 				       IPA_CMD_ASS_ARP_REMOVE_ENTRY,
 				       12,
 				       QETH_PROT_IPV4);
+	if (!iob)
+		return -ENOMEM;
 	rc = qeth_l3_send_setassparms(card, iob,
 				   12, (unsigned long)buf,
 				   qeth_l3_default_setassparms_cb, NULL);
 static int qeth_l3_setup_netdev(struct qeth_card *card)
 {
+	int rc;
 	if (card->info.type == QETH_CARD_TYPE_OSD ||
 	    card->info.type == QETH_CARD_TYPE_OSX) {
 		if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
 			return -ENODEV;
 		card->dev->flags |= IFF_NOARP;
 		card->dev->netdev_ops = &qeth_l3_netdev_ops;
-		qeth_l3_iqd_read_initial_mac(card);
+		rc = qeth_l3_iqd_read_initial_mac(card);
+		if (rc)
+			return rc;
 		if (card->options.hsuid[0])
 			memcpy(card->dev->perm_addr, card->options.hsuid, 9);
 	} else
 	recover_flag = card->state;
 	rc = qeth_core_hardsetup_card(card);
 	if (rc) {
-		QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
+		QETH_DBF_TEXT_(SETUP, 2, "2err%04x", rc);
 		rc = -ENODEV;
 		goto out_remove;
 	}
 contin:
 	rc = qeth_l3_setadapter_parms(card);
 	if (rc)
-		QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
+		QETH_DBF_TEXT_(SETUP, 2, "2err%04x", rc);
 	if (!card->options.sniffer) {
 		rc = qeth_l3_start_ipassists(card);
 		if (rc) {
 		}
 		rc = qeth_l3_setrouting_v4(card);
 		if (rc)
-			QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
+			QETH_DBF_TEXT_(SETUP, 2, "4err%04x", rc);
 		rc = qeth_l3_setrouting_v6(card);
 		if (rc)
-			QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
+			QETH_DBF_TEXT_(SETUP, 2, "5err%04x", rc);
 	}
 	netif_tx_disable(card->dev);

drivers/scsi/scsi.c+3−10

 		return -ENXIO;
 	if (!get_device(&sdev->sdev_gendev))
 		return -ENXIO;
-	/* We can fail this if we're doing SCSI operations
+	/* We can fail try_module_get if we're doing SCSI operations
 	 * from module exit (like cache flush) */
-	try_module_get(sdev->host->hostt->module);
+	__module_get(sdev->host->hostt->module);
 	return 0;
 }
  */
 void scsi_device_put(struct scsi_device *sdev)
 {
-#ifdef CONFIG_MODULE_UNLOAD
+	module_put(sdev->host->hostt->module);
-	struct module *module = sdev->host->hostt->module;
-	/* The module refcount will be zero if scsi_device_get()
-	 * was called from a module removal routine */
-	if (module && module_refcount(module) != 0)
-		module_put(module);
-#endif
 	put_device(&sdev->sdev_gendev);
 }
 EXPORT_SYMBOL(scsi_device_put);

drivers/spi/spi-dw-mid.c+0−1

@@ -271,7 +271,6 @@ int dw_spi_mid_init(struct dw_spi *dws) · 270 unmodified lines
271	iounmap(clk_reg);	271	iounmap(clk_reg);
272		272
273	dws->num_cs = 16;	273	dws->num_cs = 16;
274	dws->fifo_len = 40; /* FIFO has 40 words buffer */
275		274
276	#ifdef CONFIG_SPI_DW_MID_DMA	275	#ifdef CONFIG_SPI_DW_MID_DMA
277	dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);	276	dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);

drivers/spi/spi-dw.c+3−3

@@ -621,13 +621,13 @@ static void spi_hw_init(struct dw_spi *dws) · 620 unmodified lines
621	if (!dws->fifo_len) {	621	if (!dws->fifo_len) {
622	u32 fifo;	622	u32 fifo;
623		623
624	for (fifo = 2; fifo <= 257; fifo++) {	624	for (fifo = 2; fifo <= 256; fifo++) {
625	dw_writew(dws, DW_SPI_TXFLTR, fifo);	625	dw_writew(dws, DW_SPI_TXFLTR, fifo);
626	if (fifo != dw_readw(dws, DW_SPI_TXFLTR))	626	if (fifo != dw_readw(dws, DW_SPI_TXFLTR))
627	break;	627	break;
628	}	628	}
629		629
630	dws->fifo_len = (fifo == 257) ? 0 : fifo;	630	dws->fifo_len = (fifo == 2) ? 0 : fifo - 1;
631	dw_writew(dws, DW_SPI_TXFLTR, 0);	631	dw_writew(dws, DW_SPI_TXFLTR, 0);
632	}	632	}
633	}	633	}
@@ -673,7 +673,7 @@ int dw_spi_add_host(struct device dev, struct dw_spi dws) · 39 unmodified lines
673	if (dws->dma_ops && dws->dma_ops->dma_init) {	673	if (dws->dma_ops && dws->dma_ops->dma_init) {
674	ret = dws->dma_ops->dma_init(dws);	674	ret = dws->dma_ops->dma_init(dws);
675	if (ret) {	675	if (ret) {
676	dev_warn(&master->dev, "DMA init failed\n");	676	dev_warn(dev, "DMA init failed\n");
677	dws->dma_inited = 0;	677	dws->dma_inited = 0;
678	}	678	}
679	}	679	}

drivers/spi/spi-pxa2xx.c+1−1

@@ -546,8 +546,8 @@ static void giveback(struct driver_data *drv_data) · 545 unmodified lines
546	cs_deassert(drv_data);	546	cs_deassert(drv_data);
547	}	547	}
548		548
549	spi_finalize_current_message(drv_data->master);
550	drv_data->cur_chip = NULL;	549	drv_data->cur_chip = NULL;
		550	spi_finalize_current_message(drv_data->master);
551	}	551	}
552		552
553	static void reset_sccr1(struct driver_data *drv_data)	553	static void reset_sccr1(struct driver_data *drv_data)

drivers/spi/spi-sh-msiof.c+1−1

@@ -82,7 +82,7 @@ struct sh_msiof_spi_priv { · 81 unmodified lines
82	#define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */	82	#define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */
83	#define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */	83	#define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
84	#define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */	84	#define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
85	#define MDR1_FLD_MASK 0x000000c0 /* Frame Sync Signal Interval (0-3) */	85	#define MDR1_FLD_MASK 0x0000000c /* Frame Sync Signal Interval (0-3) */
86	#define MDR1_FLD_SHIFT 2	86	#define MDR1_FLD_SHIFT 2
87	#define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */	87	#define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */
88	/* TMDR1 */	88	/* TMDR1 */

drivers/staging/lustre/lustre/llite/vvp_io.c+1−1

@@ -632,7 +632,7 @@ static int vvp_io_kernel_fault(struct vvp_fault_io *cfio) · 631 unmodified lines
632	return 0;	632	return 0;
633	}	633	}
634		634
635	if (cfio->fault.ft_flags & VM_FAULT_SIGBUS) {	635	if (cfio->fault.ft_flags & (VM_FAULT_SIGBUS \| VM_FAULT_SIGSEGV)) {
636	CDEBUG(D_PAGE, "got addr %p - SIGBUS\n", vmf->virtual_address);	636	CDEBUG(D_PAGE, "got addr %p - SIGBUS\n", vmf->virtual_address);
637	return -EFAULT;	637	return -EFAULT;
638	}	638	}

drivers/staging/nvec/nvec.c+3−6

 static const struct mfd_cell nvec_devices[] = {
 	{
 		.name = "nvec-kbd",
-		.id = 1,
 	},
 	{
 		.name = "nvec-mouse",
-		.id = 1,
 	},
 	{
 		.name = "nvec-power",
-		.id = 1,
+		.id = 0,
 	},
 	{
 		.name = "nvec-power",
-		.id = 2,
+		.id = 1,
 	},
 	{
 		.name = "nvec-paz00",
-		.id = 1,
 	},
 };
 		nvec_msg_free(nvec, msg);
 	}
-	ret = mfd_add_devices(nvec->dev, -1, nvec_devices,
+	ret = mfd_add_devices(nvec->dev, 0, nvec_devices,
 			      ARRAY_SIZE(nvec_devices), NULL, 0, NULL);
 	if (ret)
 		dev_err(nvec->dev, "error adding subdevices\n");

drivers/usb/core/otg_whitelist.h+5−0

 	     le16_to_cpu(dev->descriptor.idProduct) == 0xbadd))
 		return 0;
+	/* OTG PET device is always targeted (see OTG 2.0 ECN 6.4.2) */
+	if ((le16_to_cpu(dev->descriptor.idVendor) == 0x1a0a &&
+	     le16_to_cpu(dev->descriptor.idProduct) == 0x0200))
+		return 1;
 	/* NOTE: can't use usb_match_id() since interface caches
 	 * aren't set up yet. this is cut/paste from that code.
 	 */

drivers/usb/core/quirks.c+4−0

@@ -179,6 +179,10 @@ static const struct usb_device_id usb_quirk_list[] = { · 178 unmodified lines
179	{ USB_DEVICE(0x0b05, 0x17e0), .driver_info =	179	{ USB_DEVICE(0x0b05, 0x17e0), .driver_info =
180	USB_QUIRK_IGNORE_REMOTE_WAKEUP },	180	USB_QUIRK_IGNORE_REMOTE_WAKEUP },
181		181
		182	/* Protocol and OTG Electrical Test Device */
		183	{ USB_DEVICE(0x1a0a, 0x0200), .driver_info =
		184	USB_QUIRK_LINEAR_UFRAME_INTR_BINTERVAL },
		185
182	{ } /* terminating entry must be last */	186	{ } /* terminating entry must be last */
183	};	187	};
184		188

drivers/usb/dwc2/core_intr.c+3−3

 	u32 gintsts;
 	irqreturn_t retval = IRQ_NONE;
+	spin_lock(&hsotg->lock);
 	if (!dwc2_is_controller_alive(hsotg)) {
 		dev_warn(hsotg->dev, "Controller is dead\n");
 		goto out;
 	}
-	spin_lock(&hsotg->lock);
 	gintsts = dwc2_read_common_intr(hsotg);
 	if (gintsts & ~GINTSTS_PRTINT)
 		retval = IRQ_HANDLED;
 		}
 	}
-	spin_unlock(&hsotg->lock);
 out:
+	spin_unlock(&hsotg->lock);
 	return retval;
 }
 EXPORT_SYMBOL_GPL(dwc2_handle_common_intr);

drivers/usb/phy/phy.c+1−1

@@ -34,7 +34,7 @@ static struct usb_phy __usb_find_phy(struct list_head list, · 33 unmodified lines
34	return phy;	34	return phy;
35	}	35	}
36		36
37	return ERR_PTR(-EPROBE_DEFER);	37	return ERR_PTR(-ENODEV);
38	}	38	}
39		39
40	static struct usb_phy __usb_find_phy_dev(struct device dev,	40	static struct usb_phy __usb_find_phy_dev(struct device dev,

drivers/usb/storage/unusual_devs.h+8−1

 UNUSUAL_DEV(  0x04e6, 0x000f, 0x0000, 0x9999,
 		"SCM Microsystems",
 		"eUSB SCSI Adapter (Bus Powered)",
-		USB_SC_DEVICE, USB_PR_DEVICE, usb_stor_euscsi_init,
+		USB_SC_SCSI, USB_PR_BULK, usb_stor_euscsi_init,
 		US_FL_SCM_MULT_TARG ),
 UNUSUAL_DEV(  0x04e6, 0x0101, 0x0200, 0x0200,
 		USB_SC_DEVICE, USB_PR_DEVICE, NULL,
 		US_FL_IGNORE_RESIDUE | US_FL_SANE_SENSE ),
+/* Reported by Dmitry Nezhevenko <dion@dion.org.ua> */
+UNUSUAL_DEV(  0x152d, 0x2566, 0x0114, 0x0114,
+		"JMicron",
+		"USB to ATA/ATAPI Bridge",
+		USB_SC_DEVICE, USB_PR_DEVICE, NULL,
+		US_FL_BROKEN_FUA ),
 /* Entrega Technologies U1-SC25 (later Xircom PortGear PGSCSI)
  * and Mac USB Dock USB-SCSI */
 UNUSUAL_DEV(  0x1645, 0x0007, 0x0100, 0x0133,

drivers/usb/storage/unusual_uas.h+7−0

@@ -140,3 +140,10 @@ UNUSUAL_DEV(0x4971, 0x1012, 0x0000, 0x9999, · 139 unmodified lines
140	"External HDD",	140	"External HDD",
141	USB_SC_DEVICE, USB_PR_DEVICE, NULL,	141	USB_SC_DEVICE, USB_PR_DEVICE, NULL,
142	US_FL_IGNORE_UAS),	142	US_FL_IGNORE_UAS),
		143
		144	/* Reported-by: Richard Henderson <rth@redhat.com> */
		145	UNUSUAL_DEV(0x4971, 0x8017, 0x0000, 0x9999,
		146	"SimpleTech",
		147	"External HDD",
		148	USB_SC_DEVICE, USB_PR_DEVICE, NULL,
		149	US_FL_NO_REPORT_OPCODES),

fs/btrfs/scrub.c+2−0

@@ -3065,6 +3065,8 @@ static noinline_for_stack int scrub_stripe(struct scrub_ctx *sctx, · 3064 unmodified lines
3065	path->search_commit_root = 1;	3065	path->search_commit_root = 1;
3066	path->skip_locking = 1;	3066	path->skip_locking = 1;
3067		3067
		3068	ppath->search_commit_root = 1;
		3069	ppath->skip_locking = 1;
3068	/*	3070	/*
3069	* trigger the readahead for extent tree csum tree and wait for	3071	* trigger the readahead for extent tree csum tree and wait for
3070	* completion. During readahead, the scrub is officially paused	3072	* completion. During readahead, the scrub is officially paused

fs/gfs2/quota.c+23−26

 static int gfs2_adjust_quota(struct gfs2_inode *ip, loff_t loc,
 			     s64 change, struct gfs2_quota_data *qd,
-			     struct fs_disk_quota *fdq)
+			     struct qc_dqblk *fdq)
 {
 	struct inode *inode = &ip->i_inode;
 	struct gfs2_sbd *sdp = GFS2_SB(inode);
 	be64_add_cpu(&q.qu_value, change);
 	qd->qd_qb.qb_value = q.qu_value;
 	if (fdq) {
-		if (fdq->d_fieldmask & FS_DQ_BSOFT) {
+		if (fdq->d_fieldmask & QC_SPC_SOFT) {
-			q.qu_warn = cpu_to_be64(fdq->d_blk_softlimit >> sdp->sd_fsb2bb_shift);
+			q.qu_warn = cpu_to_be64(fdq->d_spc_softlimit >> sdp->sd_sb.sb_bsize_shift);
 			qd->qd_qb.qb_warn = q.qu_warn;
 		}
-		if (fdq->d_fieldmask & FS_DQ_BHARD) {
+		if (fdq->d_fieldmask & QC_SPC_HARD) {
-			q.qu_limit = cpu_to_be64(fdq->d_blk_hardlimit >> sdp->sd_fsb2bb_shift);
+			q.qu_limit = cpu_to_be64(fdq->d_spc_hardlimit >> sdp->sd_sb.sb_bsize_shift);
 			qd->qd_qb.qb_limit = q.qu_limit;
 		}
-		if (fdq->d_fieldmask & FS_DQ_BCOUNT) {
+		if (fdq->d_fieldmask & QC_SPACE) {
-			q.qu_value = cpu_to_be64(fdq->d_bcount >> sdp->sd_fsb2bb_shift);
+			q.qu_value = cpu_to_be64(fdq->d_space >> sdp->sd_sb.sb_bsize_shift);
 			qd->qd_qb.qb_value = q.qu_value;
 		}
 	}
 }
 static int gfs2_get_dqblk(struct super_block *sb, struct kqid qid,
-			  struct fs_disk_quota *fdq)
+			  struct qc_dqblk *fdq)
 {
 	struct gfs2_sbd *sdp = sb->s_fs_info;
 	struct gfs2_quota_lvb *qlvb;
 	struct gfs2_holder q_gh;
 	int error;
-	memset(fdq, 0, sizeof(struct fs_disk_quota));
+	memset(fdq, 0, sizeof(*fdq));
 	if (sdp->sd_args.ar_quota == GFS2_QUOTA_OFF)
 		return -ESRCH; /* Crazy XFS error code */
 		goto out;
 	qlvb = (struct gfs2_quota_lvb *)qd->qd_gl->gl_lksb.sb_lvbptr;
-	fdq->d_version = FS_DQUOT_VERSION;
+	fdq->d_spc_hardlimit = be64_to_cpu(qlvb->qb_limit) << sdp->sd_sb.sb_bsize_shift;
-	fdq->d_flags = (qid.type == USRQUOTA) ? FS_USER_QUOTA : FS_GROUP_QUOTA;
+	fdq->d_spc_softlimit = be64_to_cpu(qlvb->qb_warn) << sdp->sd_sb.sb_bsize_shift;
-	fdq->d_id = from_kqid_munged(current_user_ns(), qid);
+	fdq->d_space = be64_to_cpu(qlvb->qb_value) << sdp->sd_sb.sb_bsize_shift;
-	fdq->d_blk_hardlimit = be64_to_cpu(qlvb->qb_limit) << sdp->sd_fsb2bb_shift;
-	fdq->d_blk_softlimit = be64_to_cpu(qlvb->qb_warn) << sdp->sd_fsb2bb_shift;
-	fdq->d_bcount = be64_to_cpu(qlvb->qb_value) << sdp->sd_fsb2bb_shift;
 	gfs2_glock_dq_uninit(&q_gh);
 out:
 }
 /* GFS2 only supports a subset of the XFS fields */
-#define GFS2_FIELDMASK (FS_DQ_BSOFT|FS_DQ_BHARD|FS_DQ_BCOUNT)
+#define GFS2_FIELDMASK (QC_SPC_SOFT|QC_SPC_HARD|QC_SPACE)
 static int gfs2_set_dqblk(struct super_block *sb, struct kqid qid,
-			  struct fs_disk_quota *fdq)
+			  struct qc_dqblk *fdq)
 {
 	struct gfs2_sbd *sdp = sb->s_fs_info;
 	struct gfs2_inode *ip = GFS2_I(sdp->sd_quota_inode);
 		goto out_i;
 	/* If nothing has changed, this is a no-op */
-	if ((fdq->d_fieldmask & FS_DQ_BSOFT) &&
+	if ((fdq->d_fieldmask & QC_SPC_SOFT) &&
-	    ((fdq->d_blk_softlimit >> sdp->sd_fsb2bb_shift) == be64_to_cpu(qd->qd_qb.qb_warn)))
+	    ((fdq->d_spc_softlimit >> sdp->sd_sb.sb_bsize_shift) == be64_to_cpu(qd->qd_qb.qb_warn)))
-		fdq->d_fieldmask ^= FS_DQ_BSOFT;
+		fdq->d_fieldmask ^= QC_SPC_SOFT;
-	if ((fdq->d_fieldmask & FS_DQ_BHARD) &&
+	if ((fdq->d_fieldmask & QC_SPC_HARD) &&
-	    ((fdq->d_blk_hardlimit >> sdp->sd_fsb2bb_shift) == be64_to_cpu(qd->qd_qb.qb_limit)))
+	    ((fdq->d_spc_hardlimit >> sdp->sd_sb.sb_bsize_shift) == be64_to_cpu(qd->qd_qb.qb_limit)))
-		fdq->d_fieldmask ^= FS_DQ_BHARD;
+		fdq->d_fieldmask ^= QC_SPC_HARD;
-	if ((fdq->d_fieldmask & FS_DQ_BCOUNT) &&
+	if ((fdq->d_fieldmask & QC_SPACE) &&
-	    ((fdq->d_bcount >> sdp->sd_fsb2bb_shift) == be64_to_cpu(qd->qd_qb.qb_value)))
+	    ((fdq->d_space >> sdp->sd_sb.sb_bsize_shift) == be64_to_cpu(qd->qd_qb.qb_value)))
-		fdq->d_fieldmask ^= FS_DQ_BCOUNT;
+		fdq->d_fieldmask ^= QC_SPACE;
 	if (fdq->d_fieldmask == 0)
 		goto out_i;

fs/nfs/direct.c+6−0

  */
 ssize_t nfs_direct_IO(int rw, struct kiocb *iocb, struct iov_iter *iter, loff_t pos)
 {
+	struct inode *inode = iocb->ki_filp->f_mapping->host;
+	/* we only support swap file calling nfs_direct_IO */
+	if (!IS_SWAPFILE(inode))
+		return 0;
 #ifndef CONFIG_NFS_SWAP
 	dprintk("NFS: nfs_direct_IO (%pD) off/no(%Ld/%lu) EINVAL\n",
 			iocb->ki_filp, (long long) pos, iter->nr_segs);

fs/nfs/inode.c+3−2

@@ -352,8 +352,9 @@ nfs_fhget(struct super_block sb, struct nfs_fh fh, struct nfs_fattr *fattr, st · 351 unmodified lines
352		352
353	nfs_attr_check_mountpoint(sb, fattr);	353	nfs_attr_check_mountpoint(sb, fattr);
354		354
355	if (((fattr->valid & NFS_ATTR_FATTR_FILEID) == 0) &&	355	if (nfs_attr_use_mounted_on_fileid(fattr))
356	!nfs_attr_use_mounted_on_fileid(fattr))	356	fattr->fileid = fattr->mounted_on_fileid;
		357	else if ((fattr->valid & NFS_ATTR_FATTR_FILEID) == 0)
357	goto out_no_inode;	358	goto out_no_inode;
358	if ((fattr->valid & NFS_ATTR_FATTR_TYPE) == 0)	359	if ((fattr->valid & NFS_ATTR_FATTR_TYPE) == 0)
359	goto out_no_inode;	360	goto out_no_inode;

fs/nfs/internal.h+0−2

@@ -31,8 +31,6 @@ static inline int nfs_attr_use_mounted_on_fileid(struct nfs_fattr *fattr) · 30 unmodified lines
31	(((fattr->valid & NFS_ATTR_FATTR_MOUNTPOINT) == 0) &&	31	(((fattr->valid & NFS_ATTR_FATTR_MOUNTPOINT) == 0) &&
32	((fattr->valid & NFS_ATTR_FATTR_V4_REFERRAL) == 0)))	32	((fattr->valid & NFS_ATTR_FATTR_V4_REFERRAL) == 0)))
33	return 0;	33	return 0;
34
35	fattr->fileid = fattr->mounted_on_fileid;
36	return 1;	34	return 1;
37	}	35	}
38		36

fs/nfs/nfs4client.c+1−1

@@ -639,7 +639,7 @@ int nfs41_walk_client_list(struct nfs_client *new, · 638 unmodified lines
639	prev = pos;	639	prev = pos;
640		640
641	status = nfs_wait_client_init_complete(pos);	641	status = nfs_wait_client_init_complete(pos);
642	if (status == 0) {	642	if (pos->cl_cons_state == NFS_CS_SESSION_INITING) {
643	nfs4_schedule_lease_recovery(pos);	643	nfs4_schedule_lease_recovery(pos);
644	status = nfs4_wait_clnt_recover(pos);	644	status = nfs4_wait_clnt_recover(pos);
645	}	645	}

fs/quota/dquot.c+39−44

 }
 /* Generic routine for getting common part of quota structure */
-static void do_get_dqblk(struct dquot *dquot, struct fs_disk_quota *di)
+static void do_get_dqblk(struct dquot *dquot, struct qc_dqblk *di)
 {
 	struct mem_dqblk *dm = &dquot->dq_dqb;
 	memset(di, 0, sizeof(*di));
-	di->d_version = FS_DQUOT_VERSION;
-	di->d_flags = dquot->dq_id.type == USRQUOTA ?
-			FS_USER_QUOTA : FS_GROUP_QUOTA;
-	di->d_id = from_kqid_munged(current_user_ns(), dquot->dq_id);
 	spin_lock(&dq_data_lock);
-	di->d_blk_hardlimit = stoqb(dm->dqb_bhardlimit);
+	di->d_spc_hardlimit = dm->dqb_bhardlimit;
-	di->d_blk_softlimit = stoqb(dm->dqb_bsoftlimit);
+	di->d_spc_softlimit = dm->dqb_bsoftlimit;
 	di->d_ino_hardlimit = dm->dqb_ihardlimit;
 	di->d_ino_softlimit = dm->dqb_isoftlimit;
-	di->d_bcount = dm->dqb_curspace + dm->dqb_rsvspace;
+	di->d_space = dm->dqb_curspace + dm->dqb_rsvspace;
-	di->d_icount = dm->dqb_curinodes;
+	di->d_ino_count = dm->dqb_curinodes;
-	di->d_btimer = dm->dqb_btime;
+	di->d_spc_timer = dm->dqb_btime;
-	di->d_itimer = dm->dqb_itime;
+	di->d_ino_timer = dm->dqb_itime;
 	spin_unlock(&dq_data_lock);
 }
 int dquot_get_dqblk(struct super_block *sb, struct kqid qid,
-		    struct fs_disk_quota *di)
+		    struct qc_dqblk *di)
 {
 	struct dquot *dquot;
 }
 EXPORT_SYMBOL(dquot_get_dqblk);
-#define VFS_FS_DQ_MASK \
+#define VFS_QC_MASK \
-	(FS_DQ_BCOUNT | FS_DQ_BSOFT | FS_DQ_BHARD | \
+	(QC_SPACE | QC_SPC_SOFT | QC_SPC_HARD | \
-	 FS_DQ_ICOUNT | FS_DQ_ISOFT | FS_DQ_IHARD | \
+	 QC_INO_COUNT | QC_INO_SOFT | QC_INO_HARD | \
-	 FS_DQ_BTIMER | FS_DQ_ITIMER)
+	 QC_SPC_TIMER | QC_INO_TIMER)
 /* Generic routine for setting common part of quota structure */
-static int do_set_dqblk(struct dquot *dquot, struct fs_disk_quota *di)
+static int do_set_dqblk(struct dquot *dquot, struct qc_dqblk *di)
 {
 	struct mem_dqblk *dm = &dquot->dq_dqb;
 	int check_blim = 0, check_ilim = 0;
 	struct mem_dqinfo *dqi = &sb_dqopt(dquot->dq_sb)->info[dquot->dq_id.type];
-	if (di->d_fieldmask & ~VFS_FS_DQ_MASK)
+	if (di->d_fieldmask & ~VFS_QC_MASK)
 		return -EINVAL;
-	if (((di->d_fieldmask & FS_DQ_BSOFT) &&
+	if (((di->d_fieldmask & QC_SPC_SOFT) &&
-	     (di->d_blk_softlimit > dqi->dqi_maxblimit)) ||
+	     stoqb(di->d_spc_softlimit) > dqi->dqi_maxblimit) ||
-	    ((di->d_fieldmask & FS_DQ_BHARD) &&
+	    ((di->d_fieldmask & QC_SPC_HARD) &&
-	     (di->d_blk_hardlimit > dqi->dqi_maxblimit)) ||
+	     stoqb(di->d_spc_hardlimit) > dqi->dqi_maxblimit) ||
-	    ((di->d_fieldmask & FS_DQ_ISOFT) &&
+	    ((di->d_fieldmask & QC_INO_SOFT) &&
 	     (di->d_ino_softlimit > dqi->dqi_maxilimit)) ||
-	    ((di->d_fieldmask & FS_DQ_IHARD) &&
+	    ((di->d_fieldmask & QC_INO_HARD) &&
 	     (di->d_ino_hardlimit > dqi->dqi_maxilimit)))
 		return -ERANGE;
 	spin_lock(&dq_data_lock);
-	if (di->d_fieldmask & FS_DQ_BCOUNT) {
+	if (di->d_fieldmask & QC_SPACE) {
-		dm->dqb_curspace = di->d_bcount - dm->dqb_rsvspace;
+		dm->dqb_curspace = di->d_space - dm->dqb_rsvspace;
 		check_blim = 1;
 		set_bit(DQ_LASTSET_B + QIF_SPACE_B, &dquot->dq_flags);
 	}
-	if (di->d_fieldmask & FS_DQ_BSOFT)
+	if (di->d_fieldmask & QC_SPC_SOFT)
-		dm->dqb_bsoftlimit = qbtos(di->d_blk_softlimit);
+		dm->dqb_bsoftlimit = di->d_spc_softlimit;
-	if (di->d_fieldmask & FS_DQ_BHARD)
+	if (di->d_fieldmask & QC_SPC_HARD)
-		dm->dqb_bhardlimit = qbtos(di->d_blk_hardlimit);
+		dm->dqb_bhardlimit = di->d_spc_hardlimit;
-	if (di->d_fieldmask & (FS_DQ_BSOFT | FS_DQ_BHARD)) {
+	if (di->d_fieldmask & (QC_SPC_SOFT | QC_SPC_HARD)) {
 		check_blim = 1;
 		set_bit(DQ_LASTSET_B + QIF_BLIMITS_B, &dquot->dq_flags);
 	}
-	if (di->d_fieldmask & FS_DQ_ICOUNT) {
+	if (di->d_fieldmask & QC_INO_COUNT) {
-		dm->dqb_curinodes = di->d_icount;
+		dm->dqb_curinodes = di->d_ino_count;
 		check_ilim = 1;
 		set_bit(DQ_LASTSET_B + QIF_INODES_B, &dquot->dq_flags);
 	}
-	if (di->d_fieldmask & FS_DQ_ISOFT)
+	if (di->d_fieldmask & QC_INO_SOFT)
 		dm->dqb_isoftlimit = di->d_ino_softlimit;
-	if (di->d_fieldmask & FS_DQ_IHARD)
+	if (di->d_fieldmask & QC_INO_HARD)
 		dm->dqb_ihardlimit = di->d_ino_hardlimit;
-	if (di->d_fieldmask & (FS_DQ_ISOFT | FS_DQ_IHARD)) {
+	if (di->d_fieldmask & (QC_INO_SOFT | QC_INO_HARD)) {
 		check_ilim = 1;
 		set_bit(DQ_LASTSET_B + QIF_ILIMITS_B, &dquot->dq_flags);
 	}
-	if (di->d_fieldmask & FS_DQ_BTIMER) {
+	if (di->d_fieldmask & QC_SPC_TIMER) {
-		dm->dqb_btime = di->d_btimer;
+		dm->dqb_btime = di->d_spc_timer;
 		check_blim = 1;
 		set_bit(DQ_LASTSET_B + QIF_BTIME_B, &dquot->dq_flags);
 	}
-	if (di->d_fieldmask & FS_DQ_ITIMER) {
+	if (di->d_fieldmask & QC_INO_TIMER) {
-		dm->dqb_itime = di->d_itimer;
+		dm->dqb_itime = di->d_ino_timer;
 		check_ilim = 1;
 		set_bit(DQ_LASTSET_B + QIF_ITIME_B, &dquot->dq_flags);
 	}
 		    dm->dqb_curspace < dm->dqb_bsoftlimit) {
 			dm->dqb_btime = 0;
 			clear_bit(DQ_BLKS_B, &dquot->dq_flags);
-		} else if (!(di->d_fieldmask & FS_DQ_BTIMER))
+		} else if (!(di->d_fieldmask & QC_SPC_TIMER))
 			/* Set grace only if user hasn't provided his own... */
 			dm->dqb_btime = get_seconds() + dqi->dqi_bgrace;
 	}
 		    dm->dqb_curinodes < dm->dqb_isoftlimit) {
 			dm->dqb_itime = 0;
 			clear_bit(DQ_INODES_B, &dquot->dq_flags);
-		} else if (!(di->d_fieldmask & FS_DQ_ITIMER))
+		} else if (!(di->d_fieldmask & QC_INO_TIMER))
 			/* Set grace only if user hasn't provided his own... */
 			dm->dqb_itime = get_seconds() + dqi->dqi_igrace;
 	}
 }
 int dquot_set_dqblk(struct super_block *sb, struct kqid qid,
-		  struct fs_disk_quota *di)
+		  struct qc_dqblk *di)
 {
 	struct dquot *dquot;
 	int rc;

fs/quota/quota.c+137−25

@@ -118,17 +118,27 @@ static int quota_setinfo(struct super_block sb, int type, void __user addr) · 117 unmodified lines
118	return sb->s_qcop->set_info(sb, type, &info);	118	return sb->s_qcop->set_info(sb, type, &info);
119	}	119	}
120		120
121	static void copy_to_if_dqblk(struct if_dqblk dst, struct fs_disk_quota src)	121	static inline qsize_t qbtos(qsize_t blocks)
		122	{
		123	return blocks << QIF_DQBLKSIZE_BITS;
		124	}
		125
		126	static inline qsize_t stoqb(qsize_t space)
		127	{
		128	return (space + QIF_DQBLKSIZE - 1) >> QIF_DQBLKSIZE_BITS;
		129	}
		130
		131	static void copy_to_if_dqblk(struct if_dqblk dst, struct qc_dqblk src)
122	{	132	{
123	memset(dst, 0, sizeof(*dst));	133	memset(dst, 0, sizeof(*dst));
124	dst->dqb_bhardlimit = src->d_blk_hardlimit;	134	dst->dqb_bhardlimit = stoqb(src->d_spc_hardlimit);
125	dst->dqb_bsoftlimit = src->d_blk_softlimit;	135	dst->dqb_bsoftlimit = stoqb(src->d_spc_softlimit);
126	dst->dqb_curspace = src->d_bcount;	136	dst->dqb_curspace = src->d_space;
127	dst->dqb_ihardlimit = src->d_ino_hardlimit;	137	dst->dqb_ihardlimit = src->d_ino_hardlimit;
128	dst->dqb_isoftlimit = src->d_ino_softlimit;	138	dst->dqb_isoftlimit = src->d_ino_softlimit;
129	dst->dqb_curinodes = src->d_icount;	139	dst->dqb_curinodes = src->d_ino_count;
130	dst->dqb_btime = src->d_btimer;	140	dst->dqb_btime = src->d_spc_timer;
131	dst->dqb_itime = src->d_itimer;	141	dst->dqb_itime = src->d_ino_timer;
132	dst->dqb_valid = QIF_ALL;	142	dst->dqb_valid = QIF_ALL;
133	}	143	}
134		144
@@ -136,7 +146,7 @@ static int quota_getquota(struct super_block *sb, int type, qid_t id, · 1 unmodified line
136	void __user *addr)	146	void __user *addr)
137	{	147	{
138	struct kqid qid;	148	struct kqid qid;
139	struct fs_disk_quota fdq;	149	struct qc_dqblk fdq;
140	struct if_dqblk idq;	150	struct if_dqblk idq;
141	int ret;	151	int ret;
142		152
@@ -154,36 +164,36 @@ static int quota_getquota(struct super_block *sb, int type, qid_t id, · 11 unmodified lines
154	return 0;	164	return 0;
155	}	165	}
156		166
157	static void copy_from_if_dqblk(struct fs_disk_quota dst, struct if_dqblk src)	167	static void copy_from_if_dqblk(struct qc_dqblk dst, struct if_dqblk src)
158	{	168	{
159	dst->d_blk_hardlimit = src->dqb_bhardlimit;	169	dst->d_spc_hardlimit = qbtos(src->dqb_bhardlimit);
160	dst->d_blk_softlimit = src->dqb_bsoftlimit;	170	dst->d_spc_softlimit = qbtos(src->dqb_bsoftlimit);
161	dst->d_bcount = src->dqb_curspace;	171	dst->d_space = src->dqb_curspace;
162	dst->d_ino_hardlimit = src->dqb_ihardlimit;	172	dst->d_ino_hardlimit = src->dqb_ihardlimit;
163	dst->d_ino_softlimit = src->dqb_isoftlimit;	173	dst->d_ino_softlimit = src->dqb_isoftlimit;
164	dst->d_icount = src->dqb_curinodes;	174	dst->d_ino_count = src->dqb_curinodes;
165	dst->d_btimer = src->dqb_btime;	175	dst->d_spc_timer = src->dqb_btime;
166	dst->d_itimer = src->dqb_itime;	176	dst->d_ino_timer = src->dqb_itime;
167		177
168	dst->d_fieldmask = 0;	178	dst->d_fieldmask = 0;
169	if (src->dqb_valid & QIF_BLIMITS)	179	if (src->dqb_valid & QIF_BLIMITS)
170	dst->d_fieldmask \|= FS_DQ_BSOFT \| FS_DQ_BHARD;	180	dst->d_fieldmask \|= QC_SPC_SOFT \| QC_SPC_HARD;
171	if (src->dqb_valid & QIF_SPACE)	181	if (src->dqb_valid & QIF_SPACE)
172	dst->d_fieldmask \|= FS_DQ_BCOUNT;	182	dst->d_fieldmask \|= QC_SPACE;
173	if (src->dqb_valid & QIF_ILIMITS)	183	if (src->dqb_valid & QIF_ILIMITS)
174	dst->d_fieldmask \|= FS_DQ_ISOFT \| FS_DQ_IHARD;	184	dst->d_fieldmask \|= QC_INO_SOFT \| QC_INO_HARD;
175	if (src->dqb_valid & QIF_INODES)	185	if (src->dqb_valid & QIF_INODES)
176	dst->d_fieldmask \|= FS_DQ_ICOUNT;	186	dst->d_fieldmask \|= QC_INO_COUNT;
177	if (src->dqb_valid & QIF_BTIME)	187	if (src->dqb_valid & QIF_BTIME)
178	dst->d_fieldmask \|= FS_DQ_BTIMER;	188	dst->d_fieldmask \|= QC_SPC_TIMER;
179	if (src->dqb_valid & QIF_ITIME)	189	if (src->dqb_valid & QIF_ITIME)
180	dst->d_fieldmask \|= FS_DQ_ITIMER;	190	dst->d_fieldmask \|= QC_INO_TIMER;
181	}	191	}
182		192
183	static int quota_setquota(struct super_block *sb, int type, qid_t id,	193	static int quota_setquota(struct super_block *sb, int type, qid_t id,
184	void __user *addr)	194	void __user *addr)
185	{	195	{
186	struct fs_disk_quota fdq;	196	struct qc_dqblk fdq;
187	struct if_dqblk idq;	197	struct if_dqblk idq;
188	struct kqid qid;	198	struct kqid qid;
189		199
@@ -247,10 +257,78 @@ static int quota_getxstatev(struct super_block sb, void __user addr) · 57 unmodified lines
247	return ret;	257	return ret;
248	}	258	}
249		259
		260	/*
		261	* XFS defines BBTOB and BTOBB macros inside fs/xfs/ and we cannot move them
		262	* out of there as xfsprogs rely on definitions being in that header file. So
		263	* just define same functions here for quota purposes.
		264	*/
		265	#define XFS_BB_SHIFT 9
		266
		267	static inline u64 quota_bbtob(u64 blocks)
		268	{
		269	return blocks << XFS_BB_SHIFT;
		270	}
		271
		272	static inline u64 quota_btobb(u64 bytes)
		273	{
		274	return (bytes + (1 << XFS_BB_SHIFT) - 1) >> XFS_BB_SHIFT;
		275	}
		276
		277	static void copy_from_xfs_dqblk(struct qc_dqblk dst, struct fs_disk_quota src)
		278	{
		279	dst->d_spc_hardlimit = quota_bbtob(src->d_blk_hardlimit);
		280	dst->d_spc_softlimit = quota_bbtob(src->d_blk_softlimit);
		281	dst->d_ino_hardlimit = src->d_ino_hardlimit;
		282	dst->d_ino_softlimit = src->d_ino_softlimit;
		283	dst->d_space = quota_bbtob(src->d_bcount);
		284	dst->d_ino_count = src->d_icount;
		285	dst->d_ino_timer = src->d_itimer;
		286	dst->d_spc_timer = src->d_btimer;
		287	dst->d_ino_warns = src->d_iwarns;
		288	dst->d_spc_warns = src->d_bwarns;
		289	dst->d_rt_spc_hardlimit = quota_bbtob(src->d_rtb_hardlimit);
		290	dst->d_rt_spc_softlimit = quota_bbtob(src->d_rtb_softlimit);
		291	dst->d_rt_space = quota_bbtob(src->d_rtbcount);
		292	dst->d_rt_spc_timer = src->d_rtbtimer;
		293	dst->d_rt_spc_warns = src->d_rtbwarns;
		294	dst->d_fieldmask = 0;
		295	if (src->d_fieldmask & FS_DQ_ISOFT)
		296	dst->d_fieldmask \|= QC_INO_SOFT;
		297	if (src->d_fieldmask & FS_DQ_IHARD)
		298	dst->d_fieldmask \|= QC_INO_HARD;
		299	if (src->d_fieldmask & FS_DQ_BSOFT)
		300	dst->d_fieldmask \|= QC_SPC_SOFT;
		301	if (src->d_fieldmask & FS_DQ_BHARD)
		302	dst->d_fieldmask \|= QC_SPC_HARD;
		303	if (src->d_fieldmask & FS_DQ_RTBSOFT)
		304	dst->d_fieldmask \|= QC_RT_SPC_SOFT;
		305	if (src->d_fieldmask & FS_DQ_RTBHARD)
		306	dst->d_fieldmask \|= QC_RT_SPC_HARD;
		307	if (src->d_fieldmask & FS_DQ_BTIMER)
		308	dst->d_fieldmask \|= QC_SPC_TIMER;
		309	if (src->d_fieldmask & FS_DQ_ITIMER)
		310	dst->d_fieldmask \|= QC_INO_TIMER;
		311	if (src->d_fieldmask & FS_DQ_RTBTIMER)
		312	dst->d_fieldmask \|= QC_RT_SPC_TIMER;
		313	if (src->d_fieldmask & FS_DQ_BWARNS)
		314	dst->d_fieldmask \|= QC_SPC_WARNS;
		315	if (src->d_fieldmask & FS_DQ_IWARNS)
		316	dst->d_fieldmask \|= QC_INO_WARNS;
		317	if (src->d_fieldmask & FS_DQ_RTBWARNS)
		318	dst->d_fieldmask \|= QC_RT_SPC_WARNS;
		319	if (src->d_fieldmask & FS_DQ_BCOUNT)
		320	dst->d_fieldmask \|= QC_SPACE;
		321	if (src->d_fieldmask & FS_DQ_ICOUNT)
		322	dst->d_fieldmask \|= QC_INO_COUNT;
		323	if (src->d_fieldmask & FS_DQ_RTBCOUNT)
		324	dst->d_fieldmask \|= QC_RT_SPACE;
		325	}
		326
250	static int quota_setxquota(struct super_block *sb, int type, qid_t id,	327	static int quota_setxquota(struct super_block *sb, int type, qid_t id,
251	void __user *addr)	328	void __user *addr)
252	{	329	{
253	struct fs_disk_quota fdq;	330	struct fs_disk_quota fdq;
		331	struct qc_dqblk qdq;
254	struct kqid qid;	332	struct kqid qid;
255		333
256	if (copy_from_user(&fdq, addr, sizeof(fdq)))	334	if (copy_from_user(&fdq, addr, sizeof(fdq)))
@@ -260,13 +338,44 @@ static int quota_setxquota(struct super_block *sb, int type, qid_t id, · 3 unmodified lines
260	qid = make_kqid(current_user_ns(), type, id);	338	qid = make_kqid(current_user_ns(), type, id);
261	if (!qid_valid(qid))	339	if (!qid_valid(qid))
262	return -EINVAL;	340	return -EINVAL;
263	return sb->s_qcop->set_dqblk(sb, qid, &fdq);	341	copy_from_xfs_dqblk(&qdq, &fdq);
		342	return sb->s_qcop->set_dqblk(sb, qid, &qdq);
		343	}
		344
		345	static void copy_to_xfs_dqblk(struct fs_disk_quota dst, struct qc_dqblk src,
		346	int type, qid_t id)
		347	{
		348	memset(dst, 0, sizeof(*dst));
		349	dst->d_version = FS_DQUOT_VERSION;
		350	dst->d_id = id;
		351	if (type == USRQUOTA)
		352	dst->d_flags = FS_USER_QUOTA;
		353	else if (type == PRJQUOTA)
		354	dst->d_flags = FS_PROJ_QUOTA;
		355	else
		356	dst->d_flags = FS_GROUP_QUOTA;
		357	dst->d_blk_hardlimit = quota_btobb(src->d_spc_hardlimit);
		358	dst->d_blk_softlimit = quota_btobb(src->d_spc_softlimit);
		359	dst->d_ino_hardlimit = src->d_ino_hardlimit;
		360	dst->d_ino_softlimit = src->d_ino_softlimit;
		361	dst->d_bcount = quota_btobb(src->d_space);
		362	dst->d_icount = src->d_ino_count;
		363	dst->d_itimer = src->d_ino_timer;
		364	dst->d_btimer = src->d_spc_timer;
		365	dst->d_iwarns = src->d_ino_warns;
		366	dst->d_bwarns = src->d_spc_warns;
		367	dst->d_rtb_hardlimit = quota_btobb(src->d_rt_spc_hardlimit);
		368	dst->d_rtb_softlimit = quota_btobb(src->d_rt_spc_softlimit);
		369	dst->d_rtbcount = quota_btobb(src->d_rt_space);
		370	dst->d_rtbtimer = src->d_rt_spc_timer;
		371	dst->d_rtbwarns = src->d_rt_spc_warns;
264	}	372	}
265		373
266	static int quota_getxquota(struct super_block *sb, int type, qid_t id,	374	static int quota_getxquota(struct super_block *sb, int type, qid_t id,
267	void __user *addr)	375	void __user *addr)
268	{	376	{
269	struct fs_disk_quota fdq;	377	struct fs_disk_quota fdq;
		378	struct qc_dqblk qdq;
270	struct kqid qid;	379	struct kqid qid;
271	int ret;	380	int ret;
272		381
@@ -275,8 +384,11 @@ static int quota_getxquota(struct super_block *sb, int type, qid_t id, · 2 unmodified lines
275	qid = make_kqid(current_user_ns(), type, id);	384	qid = make_kqid(current_user_ns(), type, id);
276	if (!qid_valid(qid))	385	if (!qid_valid(qid))
277	return -EINVAL;	386	return -EINVAL;
278	ret = sb->s_qcop->get_dqblk(sb, qid, &fdq);	387	ret = sb->s_qcop->get_dqblk(sb, qid, &qdq);
279	if (!ret && copy_to_user(addr, &fdq, sizeof(fdq)))	388	if (ret)
		389	return ret;
		390	copy_to_xfs_dqblk(&fdq, &qdq, type, id);
		391	if (copy_to_user(addr, &fdq, sizeof(fdq)))
280	return -EFAULT;	392	return -EFAULT;
281	return ret;	393	return ret;
282	}	394	}

fs/udf/file.c+1−1

@@ -224,7 +224,7 @@ out: · 223 unmodified lines
224	static int udf_release_file(struct inode inode, struct file filp)	224	static int udf_release_file(struct inode inode, struct file filp)
225	{	225	{
226	if (filp->f_mode & FMODE_WRITE &&	226	if (filp->f_mode & FMODE_WRITE &&
227	atomic_read(&inode->i_writecount) > 1) {	227	atomic_read(&inode->i_writecount) == 1) {
228	/*	228	/*
229	* Grab i_mutex to avoid races with writes changing i_size	229	* Grab i_mutex to avoid races with writes changing i_size
230	* while we are running.	230	* while we are running.

fs/xfs/xfs_qm.h+2−2

@@ -166,9 +166,9 @@ extern void xfs_qm_dqrele_all_inodes(struct xfs_mount *, uint); · 165 unmodified lines
166	/* quota ops */	166	/* quota ops */
167	extern int xfs_qm_scall_trunc_qfiles(struct xfs_mount *, uint);	167	extern int xfs_qm_scall_trunc_qfiles(struct xfs_mount *, uint);
168	extern int xfs_qm_scall_getquota(struct xfs_mount *, xfs_dqid_t,	168	extern int xfs_qm_scall_getquota(struct xfs_mount *, xfs_dqid_t,
169	uint, struct fs_disk_quota *);	169	uint, struct qc_dqblk *);
170	extern int xfs_qm_scall_setqlim(struct xfs_mount *, xfs_dqid_t, uint,	170	extern int xfs_qm_scall_setqlim(struct xfs_mount *, xfs_dqid_t, uint,
171	struct fs_disk_quota *);	171	struct qc_dqblk *);
172	extern int xfs_qm_scall_getqstat(struct xfs_mount *,	172	extern int xfs_qm_scall_getqstat(struct xfs_mount *,
173	struct fs_quota_stat *);	173	struct fs_quota_stat *);
174	extern int xfs_qm_scall_getqstatv(struct xfs_mount *,	174	extern int xfs_qm_scall_getqstatv(struct xfs_mount *,

fs/xfs/xfs_qm_syscalls.c+66−90

 STATIC int	xfs_qm_log_quotaoff_end(xfs_mount_t *, xfs_qoff_logitem_t *,
 					uint);
 STATIC uint	xfs_qm_export_flags(uint);
-STATIC uint	xfs_qm_export_qtype_flags(uint);
 /*
  * Turn off quota accounting and/or enforcement for all udquots and/or
 	return 0;
 }
-#define XFS_DQ_MASK \
+#define XFS_QC_MASK \
-	(FS_DQ_LIMIT_MASK | FS_DQ_TIMER_MASK | FS_DQ_WARNS_MASK)
+	(QC_LIMIT_MASK | QC_TIMER_MASK | QC_WARNS_MASK)
 /*
  * Adjust quota limits, and start/stop timers accordingly.
 	struct xfs_mount	*mp,
 	xfs_dqid_t		id,
 	uint			type,
-	fs_disk_quota_t		*newlim)
+	struct qc_dqblk		*newlim)
 {
 	struct xfs_quotainfo	*q = mp->m_quotainfo;
 	struct xfs_disk_dquot	*ddq;
 	int			error;
 	xfs_qcnt_t		hard, soft;
-	if (newlim->d_fieldmask & ~XFS_DQ_MASK)
+	if (newlim->d_fieldmask & ~XFS_QC_MASK)
 		return -EINVAL;
-	if ((newlim->d_fieldmask & XFS_DQ_MASK) == 0)
+	if ((newlim->d_fieldmask & XFS_QC_MASK) == 0)
 		return 0;
 	/*
 	/*
 	 * Make sure that hardlimits are >= soft limits before changing.
 	 */
-	hard = (newlim->d_fieldmask & FS_DQ_BHARD) ?
+	hard = (newlim->d_fieldmask & QC_SPC_HARD) ?
-		(xfs_qcnt_t) XFS_BB_TO_FSB(mp, newlim->d_blk_hardlimit) :
+		(xfs_qcnt_t) XFS_B_TO_FSB(mp, newlim->d_spc_hardlimit) :
 			be64_to_cpu(ddq->d_blk_hardlimit);
-	soft = (newlim->d_fieldmask & FS_DQ_BSOFT) ?
+	soft = (newlim->d_fieldmask & QC_SPC_SOFT) ?
-		(xfs_qcnt_t) XFS_BB_TO_FSB(mp, newlim->d_blk_softlimit) :
+		(xfs_qcnt_t) XFS_B_TO_FSB(mp, newlim->d_spc_softlimit) :
 			be64_to_cpu(ddq->d_blk_softlimit);
 	if (hard == 0 || hard >= soft) {
 		ddq->d_blk_hardlimit = cpu_to_be64(hard);
 	} else {
 		xfs_debug(mp, "blkhard %Ld < blksoft %Ld", hard, soft);
 	}
-	hard = (newlim->d_fieldmask & FS_DQ_RTBHARD) ?
+	hard = (newlim->d_fieldmask & QC_RT_SPC_HARD) ?
-		(xfs_qcnt_t) XFS_BB_TO_FSB(mp, newlim->d_rtb_hardlimit) :
+		(xfs_qcnt_t) XFS_B_TO_FSB(mp, newlim->d_rt_spc_hardlimit) :
 			be64_to_cpu(ddq->d_rtb_hardlimit);
-	soft = (newlim->d_fieldmask & FS_DQ_RTBSOFT) ?
+	soft = (newlim->d_fieldmask & QC_RT_SPC_SOFT) ?
-		(xfs_qcnt_t) XFS_BB_TO_FSB(mp, newlim->d_rtb_softlimit) :
+		(xfs_qcnt_t) XFS_B_TO_FSB(mp, newlim->d_rt_spc_softlimit) :
 			be64_to_cpu(ddq->d_rtb_softlimit);
 	if (hard == 0 || hard >= soft) {
 		ddq->d_rtb_hardlimit = cpu_to_be64(hard);
 		xfs_debug(mp, "rtbhard %Ld < rtbsoft %Ld", hard, soft);
 	}
-	hard = (newlim->d_fieldmask & FS_DQ_IHARD) ?
+	hard = (newlim->d_fieldmask & QC_INO_HARD) ?
 		(xfs_qcnt_t) newlim->d_ino_hardlimit :
 			be64_to_cpu(ddq->d_ino_hardlimit);
-	soft = (newlim->d_fieldmask & FS_DQ_ISOFT) ?
+	soft = (newlim->d_fieldmask & QC_INO_SOFT) ?
 		(xfs_qcnt_t) newlim->d_ino_softlimit :
 			be64_to_cpu(ddq->d_ino_softlimit);
 	if (hard == 0 || hard >= soft) {
 	/*
 	 * Update warnings counter(s) if requested
 	 */
-	if (newlim->d_fieldmask & FS_DQ_BWARNS)
+	if (newlim->d_fieldmask & QC_SPC_WARNS)
-		ddq->d_bwarns = cpu_to_be16(newlim->d_bwarns);
+		ddq->d_bwarns = cpu_to_be16(newlim->d_spc_warns);
-	if (newlim->d_fieldmask & FS_DQ_IWARNS)
+	if (newlim->d_fieldmask & QC_INO_WARNS)
-		ddq->d_iwarns = cpu_to_be16(newlim->d_iwarns);
+		ddq->d_iwarns = cpu_to_be16(newlim->d_ino_warns);
-	if (newlim->d_fieldmask & FS_DQ_RTBWARNS)
+	if (newlim->d_fieldmask & QC_RT_SPC_WARNS)
-		ddq->d_rtbwarns = cpu_to_be16(newlim->d_rtbwarns);
+		ddq->d_rtbwarns = cpu_to_be16(newlim->d_rt_spc_warns);
 	if (id == 0) {
 		/*
 		 * soft and hard limit values (already done, above), and
 		 * for warnings.
 		 */
-		if (newlim->d_fieldmask & FS_DQ_BTIMER) {
+		if (newlim->d_fieldmask & QC_SPC_TIMER) {
-			q->qi_btimelimit = newlim->d_btimer;
+			q->qi_btimelimit = newlim->d_spc_timer;
-			ddq->d_btimer = cpu_to_be32(newlim->d_btimer);
+			ddq->d_btimer = cpu_to_be32(newlim->d_spc_timer);
 		}
-		if (newlim->d_fieldmask & FS_DQ_ITIMER) {
+		if (newlim->d_fieldmask & QC_INO_TIMER) {
-			q->qi_itimelimit = newlim->d_itimer;
+			q->qi_itimelimit = newlim->d_ino_timer;
-			ddq->d_itimer = cpu_to_be32(newlim->d_itimer);
+			ddq->d_itimer = cpu_to_be32(newlim->d_ino_timer);
 		}
-		if (newlim->d_fieldmask & FS_DQ_RTBTIMER) {
+		if (newlim->d_fieldmask & QC_RT_SPC_TIMER) {
-			q->qi_rtbtimelimit = newlim->d_rtbtimer;
+			q->qi_rtbtimelimit = newlim->d_rt_spc_timer;
-			ddq->d_rtbtimer = cpu_to_be32(newlim->d_rtbtimer);
+			ddq->d_rtbtimer = cpu_to_be32(newlim->d_rt_spc_timer);
 		}
-		if (newlim->d_fieldmask & FS_DQ_BWARNS)
+		if (newlim->d_fieldmask & QC_SPC_WARNS)
-			q->qi_bwarnlimit = newlim->d_bwarns;
+			q->qi_bwarnlimit = newlim->d_spc_warns;
-		if (newlim->d_fieldmask & FS_DQ_IWARNS)
+		if (newlim->d_fieldmask & QC_INO_WARNS)
-			q->qi_iwarnlimit = newlim->d_iwarns;
+			q->qi_iwarnlimit = newlim->d_ino_warns;
-		if (newlim->d_fieldmask & FS_DQ_RTBWARNS)
+		if (newlim->d_fieldmask & QC_RT_SPC_WARNS)
-			q->qi_rtbwarnlimit = newlim->d_rtbwarns;
+			q->qi_rtbwarnlimit = newlim->d_rt_spc_warns;
 	} else {
 		/*
 		 * If the user is now over quota, start the timelimit.
 	struct xfs_mount	*mp,
 	xfs_dqid_t		id,
 	uint			type,
-	struct fs_disk_quota	*dst)
+	struct qc_dqblk		*dst)
 {
 	struct xfs_dquot	*dqp;
 	int			error;
 	}
 	memset(dst, 0, sizeof(*dst));
-	dst->d_version = FS_DQUOT_VERSION;
+	dst->d_spc_hardlimit =
-	dst->d_flags = xfs_qm_export_qtype_flags(dqp->q_core.d_flags);
+		XFS_FSB_TO_B(mp, be64_to_cpu(dqp->q_core.d_blk_hardlimit));
-	dst->d_id = be32_to_cpu(dqp->q_core.d_id);
+	dst->d_spc_softlimit =
-	dst->d_blk_hardlimit =
+		XFS_FSB_TO_B(mp, be64_to_cpu(dqp->q_core.d_blk_softlimit));
-		XFS_FSB_TO_BB(mp, be64_to_cpu(dqp->q_core.d_blk_hardlimit));
-	dst->d_blk_softlimit =
-		XFS_FSB_TO_BB(mp, be64_to_cpu(dqp->q_core.d_blk_softlimit));
 	dst->d_ino_hardlimit = be64_to_cpu(dqp->q_core.d_ino_hardlimit);
 	dst->d_ino_softlimit = be64_to_cpu(dqp->q_core.d_ino_softlimit);
-	dst->d_bcount = XFS_FSB_TO_BB(mp, dqp->q_res_bcount);
+	dst->d_space = XFS_FSB_TO_B(mp, dqp->q_res_bcount);
-	dst->d_icount = dqp->q_res_icount;
+	dst->d_ino_count = dqp->q_res_icount;
-	dst->d_btimer = be32_to_cpu(dqp->q_core.d_btimer);
+	dst->d_spc_timer = be32_to_cpu(dqp->q_core.d_btimer);
-	dst->d_itimer = be32_to_cpu(dqp->q_core.d_itimer);
+	dst->d_ino_timer = be32_to_cpu(dqp->q_core.d_itimer);
-	dst->d_iwarns = be16_to_cpu(dqp->q_core.d_iwarns);
+	dst->d_ino_warns = be16_to_cpu(dqp->q_core.d_iwarns);
-	dst->d_bwarns = be16_to_cpu(dqp->q_core.d_bwarns);
+	dst->d_spc_warns = be16_to_cpu(dqp->q_core.d_bwarns);
-	dst->d_rtb_hardlimit =
+	dst->d_rt_spc_hardlimit =
-		XFS_FSB_TO_BB(mp, be64_to_cpu(dqp->q_core.d_rtb_hardlimit));
+		XFS_FSB_TO_B(mp, be64_to_cpu(dqp->q_core.d_rtb_hardlimit));
-	dst->d_rtb_softlimit =
+	dst->d_rt_spc_softlimit =
-		XFS_FSB_TO_BB(mp, be64_to_cpu(dqp->q_core.d_rtb_softlimit));
+		XFS_FSB_TO_B(mp, be64_to_cpu(dqp->q_core.d_rtb_softlimit));
-	dst->d_rtbcount = XFS_FSB_TO_BB(mp, dqp->q_res_rtbcount);
+	dst->d_rt_space = XFS_FSB_TO_B(mp, dqp->q_res_rtbcount);
-	dst->d_rtbtimer = be32_to_cpu(dqp->q_core.d_rtbtimer);
+	dst->d_rt_spc_timer = be32_to_cpu(dqp->q_core.d_rtbtimer);
-	dst->d_rtbwarns = be16_to_cpu(dqp->q_core.d_rtbwarns);
+	dst->d_rt_spc_warns = be16_to_cpu(dqp->q_core.d_rtbwarns);
 	/*
 	 * Internally, we don't reset all the timers when quota enforcement
 	     dqp->q_core.d_flags == XFS_DQ_GROUP) ||
 	    (!XFS_IS_PQUOTA_ENFORCED(mp) &&
 	     dqp->q_core.d_flags == XFS_DQ_PROJ)) {
-		dst->d_btimer = 0;
+		dst->d_spc_timer = 0;
-		dst->d_itimer = 0;
+		dst->d_ino_timer = 0;
-		dst->d_rtbtimer = 0;
+		dst->d_rt_spc_timer = 0;
 	}
 #ifdef DEBUG
-	if (((XFS_IS_UQUOTA_ENFORCED(mp) && dst->d_flags == FS_USER_QUOTA) ||
+	if (((XFS_IS_UQUOTA_ENFORCED(mp) && type == XFS_DQ_USER) ||
-	     (XFS_IS_GQUOTA_ENFORCED(mp) && dst->d_flags == FS_GROUP_QUOTA) ||
+	     (XFS_IS_GQUOTA_ENFORCED(mp) && type == XFS_DQ_GROUP) ||
-	     (XFS_IS_PQUOTA_ENFORCED(mp) && dst->d_flags == FS_PROJ_QUOTA)) &&
+	     (XFS_IS_PQUOTA_ENFORCED(mp) && type == XFS_DQ_PROJ)) &&
-	    dst->d_id != 0) {
+	    id != 0) {
-		if ((dst->d_bcount > dst->d_blk_softlimit) &&
+		if ((dst->d_space > dst->d_spc_softlimit) &&
-		    (dst->d_blk_softlimit > 0)) {
+		    (dst->d_spc_softlimit > 0)) {
-			ASSERT(dst->d_btimer != 0);
+			ASSERT(dst->d_spc_timer != 0);
 		}
-		if ((dst->d_icount > dst->d_ino_softlimit) &&
+		if ((dst->d_ino_count > dst->d_ino_softlimit) &&
 		    (dst->d_ino_softlimit > 0)) {
-			ASSERT(dst->d_itimer != 0);
+			ASSERT(dst->d_ino_timer != 0);
 		}
 	}
 #endif
 	return error;
 }
-STATIC uint
-xfs_qm_export_qtype_flags(
-	uint flags)
-{
-	/*
-	 * Can't be more than one, or none.
-	 */
-	ASSERT((flags & (FS_PROJ_QUOTA | FS_USER_QUOTA)) !=
-		(FS_PROJ_QUOTA | FS_USER_QUOTA));
-	ASSERT((flags & (FS_PROJ_QUOTA | FS_GROUP_QUOTA)) !=
-		(FS_PROJ_QUOTA | FS_GROUP_QUOTA));
-	ASSERT((flags & (FS_USER_QUOTA | FS_GROUP_QUOTA)) !=
-		(FS_USER_QUOTA | FS_GROUP_QUOTA));
-	ASSERT((flags & (FS_PROJ_QUOTA|FS_USER_QUOTA|FS_GROUP_QUOTA)) != 0);
-	return (flags & XFS_DQ_USER) ?
-		FS_USER_QUOTA : (flags & XFS_DQ_PROJ) ?
-			FS_PROJ_QUOTA : FS_GROUP_QUOTA;
-}
 STATIC uint
 xfs_qm_export_flags(
 	uint flags)

fs/xfs/xfs_quotaops.c+4−4

@@ -131,7 +131,7 @@ STATIC int · 130 unmodified lines
131	xfs_fs_get_dqblk(	131	xfs_fs_get_dqblk(
132	struct super_block *sb,	132	struct super_block *sb,
133	struct kqid qid,	133	struct kqid qid,
134	struct fs_disk_quota *fdq)	134	struct qc_dqblk *qdq)
135	{	135	{
136	struct xfs_mount *mp = XFS_M(sb);	136	struct xfs_mount *mp = XFS_M(sb);
137		137
@@ -141,14 +141,14 @@ xfs_fs_get_dqblk( · 3 unmodified lines
141	return -ESRCH;	141	return -ESRCH;
142		142
143	return xfs_qm_scall_getquota(mp, from_kqid(&init_user_ns, qid),	143	return xfs_qm_scall_getquota(mp, from_kqid(&init_user_ns, qid),
144	xfs_quota_type(qid.type), fdq);	144	xfs_quota_type(qid.type), qdq);
145	}	145	}
146		146
147	STATIC int	147	STATIC int
148	xfs_fs_set_dqblk(	148	xfs_fs_set_dqblk(
149	struct super_block *sb,	149	struct super_block *sb,
150	struct kqid qid,	150	struct kqid qid,
151	struct fs_disk_quota *fdq)	151	struct qc_dqblk *qdq)
152	{	152	{
153	struct xfs_mount *mp = XFS_M(sb);	153	struct xfs_mount *mp = XFS_M(sb);
154		154
@@ -160,7 +160,7 @@ xfs_fs_set_dqblk( · 5 unmodified lines
160	return -ESRCH;	160	return -ESRCH;
161		161
162	return xfs_qm_scall_setqlim(mp, from_kqid(&init_user_ns, qid),	162	return xfs_qm_scall_setqlim(mp, from_kqid(&init_user_ns, qid),
163	xfs_quota_type(qid.type), fdq);	163	xfs_quota_type(qid.type), qdq);
164	}	164	}
165		165
166	const struct quotactl_ops xfs_quotactl_operations = {	166	const struct quotactl_ops xfs_quotactl_operations = {

include/linux/i2c.h+6−0

 	struct device dev;		/* the device structure		*/
 	int irq;			/* irq issued by device		*/
 	struct list_head detected;
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
 	i2c_slave_cb_t slave_cb;	/* callback for slave mode	*/
+#endif
 };
 #define to_i2c_client(d) container_of(d, struct i2c_client, dev)
 /* I2C slave support */
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
 enum i2c_slave_event {
 	I2C_SLAVE_REQ_READ_START,
 	I2C_SLAVE_REQ_READ_END,
 {
 	return client->slave_cb(client, event, val);
 }
+#endif
 /**
  * struct i2c_board_info - template for device creation
 	/* To determine what the adapter supports */
 	u32 (*functionality) (struct i2c_adapter *);
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
 	int (*reg_slave)(struct i2c_client *client);
 	int (*unreg_slave)(struct i2c_client *client);
+#endif
 };
 /**

include/linux/kernel.h+1−1

@@ -176,7 +176,7 @@ extern int _cond_resched(void); · 175 unmodified lines
176	*/	176	*/
177	# define might_sleep() \	177	# define might_sleep() \
178	do { __might_sleep(__FILE__, __LINE__, 0); might_resched(); } while (0)	178	do { __might_sleep(__FILE__, __LINE__, 0); might_resched(); } while (0)
179	# define sched_annotate_sleep() __set_current_state(TASK_RUNNING)	179	# define sched_annotate_sleep() (current->task_state_change = 0)
180	#else	180	#else
181	static inline void ___might_sleep(const char *file, int line,	181	static inline void ___might_sleep(const char *file, int line,
182	int preempt_offset) { }	182	int preempt_offset) { }

include/linux/mfd/samsung/s2mps13.h+2−0

 	S2MPS13_REG_B6CTRL,
 	S2MPS13_REG_B6OUT,
 	S2MPS13_REG_B7CTRL,
+	S2MPS13_REG_B7SW,
 	S2MPS13_REG_B7OUT,
 	S2MPS13_REG_B8CTRL,
 	S2MPS13_REG_B8OUT,
 	S2MPS13_REG_L26CTRL,
 	S2MPS13_REG_L27CTRL,
 	S2MPS13_REG_L28CTRL,
+	S2MPS13_REG_L29CTRL,
 	S2MPS13_REG_L30CTRL,
 	S2MPS13_REG_L31CTRL,
 	S2MPS13_REG_L32CTRL,

include/linux/mm.h+4−2

 #define VM_FAULT_WRITE	0x0008	/* Special case for get_user_pages */
 #define VM_FAULT_HWPOISON 0x0010	/* Hit poisoned small page */
 #define VM_FAULT_HWPOISON_LARGE 0x0020  /* Hit poisoned large page. Index encoded in upper bits */
+#define VM_FAULT_SIGSEGV 0x0040
 #define VM_FAULT_NOPAGE	0x0100	/* ->fault installed the pte, not return page */
 #define VM_FAULT_LOCKED	0x0200	/* ->fault locked the returned page */
 #define VM_FAULT_HWPOISON_LARGE_MASK 0xf000 /* encodes hpage index for large hwpoison */
-#define VM_FAULT_ERROR	(VM_FAULT_OOM | VM_FAULT_SIGBUS | VM_FAULT_HWPOISON | \
+#define VM_FAULT_ERROR	(VM_FAULT_OOM | VM_FAULT_SIGBUS | VM_FAULT_SIGSEGV | \
-			 VM_FAULT_FALLBACK | VM_FAULT_HWPOISON_LARGE)
+			 VM_FAULT_HWPOISON | VM_FAULT_HWPOISON_LARGE | \
+			 VM_FAULT_FALLBACK)
 /* Encode hstate index for a hwpoisoned large page */
 #define VM_FAULT_SET_HINDEX(x) ((x) << 12)

include/linux/oom.h+0−5

 	oom_killer_disabled = false;
 }
-static inline bool oom_gfp_allowed(gfp_t gfp_mask)
-{
-	return (gfp_mask & __GFP_FS) && !(gfp_mask & __GFP_NORETRY);
-}
 extern struct task_struct *find_lock_task_mm(struct task_struct *p);
 static inline bool task_will_free_mem(struct task_struct *task)

include/linux/perf_event.h+0−6

 #endif /* CONFIG_PERF_EVENTS */
 };
-enum perf_event_context_type {
-	task_context,
-	cpu_context,
-};
 /**
  * struct perf_event_context - event context structure
  *
  */
 struct perf_event_context {
 	struct pmu			*pmu;
-	enum perf_event_context_type	type;
 	/*
 	 * Protect the states of the events in the list,
 	 * nr_active, and the list:

include/linux/printk.h+12−3

 extern const char linux_banner[];
 extern const char linux_proc_banner[];
-extern char *log_buf_addr_get(void);
-extern u32 log_buf_len_get(void);
 static inline int printk_get_level(const char *buffer)
 {
 	if (buffer[0] == KERN_SOH_ASCII && buffer[1]) {
 extern void wake_up_klogd(void);
+char *log_buf_addr_get(void);
+u32 log_buf_len_get(void);
 void log_buf_kexec_setup(void);
 void __init setup_log_buf(int early);
 void dump_stack_set_arch_desc(const char *fmt, ...);
 {
 }
+static inline char *log_buf_addr_get(void)
+{
+	return NULL;
+}
+static inline u32 log_buf_len_get(void)
+{
+	return 0;
+}
 static inline void log_buf_kexec_setup(void)
 {
 }

include/linux/quota.h+45−2

@@ -321,6 +321,49 @@ struct dquot_operations { · 320 unmodified lines
321		321
322	struct path;	322	struct path;
323		323
		324	/* Structure for communicating via ->get_dqblk() & ->set_dqblk() */
		325	struct qc_dqblk {
		326	int d_fieldmask; /* mask of fields to change in ->set_dqblk() */
		327	u64 d_spc_hardlimit; /* absolute limit on used space */
		328	u64 d_spc_softlimit; /* preferred limit on used space */
		329	u64 d_ino_hardlimit; /* maximum # allocated inodes */
		330	u64 d_ino_softlimit; /* preferred inode limit */
		331	u64 d_space; /* Space owned by the user */
		332	u64 d_ino_count; /* # inodes owned by the user */
		333	s64 d_ino_timer; /* zero if within inode limits */
		334	/* if not, we refuse service */
		335	s64 d_spc_timer; /* similar to above; for space */
		336	int d_ino_warns; /* # warnings issued wrt num inodes */
		337	int d_spc_warns; /* # warnings issued wrt used space */
		338	u64 d_rt_spc_hardlimit; /* absolute limit on realtime space */
		339	u64 d_rt_spc_softlimit; /* preferred limit on RT space */
		340	u64 d_rt_space; /* realtime space owned */
		341	s64 d_rt_spc_timer; /* similar to above; for RT space */
		342	int d_rt_spc_warns; /* # warnings issued wrt RT space */
		343	};
		344
		345	/* Field specifiers for ->set_dqblk() in struct qc_dqblk */
		346	#define QC_INO_SOFT (1<<0)
		347	#define QC_INO_HARD (1<<1)
		348	#define QC_SPC_SOFT (1<<2)
		349	#define QC_SPC_HARD (1<<3)
		350	#define QC_RT_SPC_SOFT (1<<4)
		351	#define QC_RT_SPC_HARD (1<<5)
		352	#define QC_LIMIT_MASK (QC_INO_SOFT \| QC_INO_HARD \| QC_SPC_SOFT \| QC_SPC_HARD \| \
		353	QC_RT_SPC_SOFT \| QC_RT_SPC_HARD)
		354	#define QC_SPC_TIMER (1<<6)
		355	#define QC_INO_TIMER (1<<7)
		356	#define QC_RT_SPC_TIMER (1<<8)
		357	#define QC_TIMER_MASK (QC_SPC_TIMER \| QC_INO_TIMER \| QC_RT_SPC_TIMER)
		358	#define QC_SPC_WARNS (1<<9)
		359	#define QC_INO_WARNS (1<<10)
		360	#define QC_RT_SPC_WARNS (1<<11)
		361	#define QC_WARNS_MASK (QC_SPC_WARNS \| QC_INO_WARNS \| QC_RT_SPC_WARNS)
		362	#define QC_SPACE (1<<12)
		363	#define QC_INO_COUNT (1<<13)
		364	#define QC_RT_SPACE (1<<14)
		365	#define QC_ACCT_MASK (QC_SPACE \| QC_INO_COUNT \| QC_RT_SPACE)
		366
324	/* Operations handling requests from userspace */	367	/* Operations handling requests from userspace */
325	struct quotactl_ops {	368	struct quotactl_ops {
326	int (quota_on)(struct super_block , int, int, struct path *);	369	int (quota_on)(struct super_block , int, int, struct path *);
@@ -329,8 +372,8 @@ struct quotactl_ops { · 2 unmodified lines
329	int (quota_sync)(struct super_block , int);	372	int (quota_sync)(struct super_block , int);
330	int (get_info)(struct super_block , int, struct if_dqinfo *);	373	int (get_info)(struct super_block , int, struct if_dqinfo *);
331	int (set_info)(struct super_block , int, struct if_dqinfo *);	374	int (set_info)(struct super_block , int, struct if_dqinfo *);
332	int (get_dqblk)(struct super_block , struct kqid, struct fs_disk_quota *);	375	int (get_dqblk)(struct super_block , struct kqid, struct qc_dqblk *);
333	int (set_dqblk)(struct super_block , struct kqid, struct fs_disk_quota *);	376	int (set_dqblk)(struct super_block , struct kqid, struct qc_dqblk *);
334	int (get_xstate)(struct super_block , struct fs_quota_stat *);	377	int (get_xstate)(struct super_block , struct fs_quota_stat *);
335	int (set_xstate)(struct super_block , unsigned int, int);	378	int (set_xstate)(struct super_block , unsigned int, int);
336	int (get_xstatev)(struct super_block , struct fs_quota_statv *);	379	int (get_xstatev)(struct super_block , struct fs_quota_statv *);

include/linux/quotaops.h+2−2

@@ -98,9 +98,9 @@ int dquot_quota_sync(struct super_block *sb, int type); · 97 unmodified lines
98	int dquot_get_dqinfo(struct super_block sb, int type, struct if_dqinfo ii);	98	int dquot_get_dqinfo(struct super_block sb, int type, struct if_dqinfo ii);
99	int dquot_set_dqinfo(struct super_block sb, int type, struct if_dqinfo ii);	99	int dquot_set_dqinfo(struct super_block sb, int type, struct if_dqinfo ii);
100	int dquot_get_dqblk(struct super_block *sb, struct kqid id,	100	int dquot_get_dqblk(struct super_block *sb, struct kqid id,
101	struct fs_disk_quota *di);	101	struct qc_dqblk *di);
102	int dquot_set_dqblk(struct super_block *sb, struct kqid id,	102	int dquot_set_dqblk(struct super_block *sb, struct kqid id,
103	struct fs_disk_quota *di);	103	struct qc_dqblk *di);
104		104
105	int __dquot_transfer(struct inode inode, struct dquot *transfer_to);	105	int __dquot_transfer(struct inode inode, struct dquot *transfer_to);
106	int dquot_transfer(struct inode inode, struct iattr iattr);	106	int dquot_transfer(struct inode inode, struct iattr iattr);

include/net/ip.h+6−5

@@ -39,11 +39,12 @@ struct inet_skb_parm { · 38 unmodified lines
39	struct ip_options opt; /* Compiled IP options */	39	struct ip_options opt; /* Compiled IP options */
40	unsigned char flags;	40	unsigned char flags;
41		41
42	#define IPSKB_FORWARDED 1	42	#define IPSKB_FORWARDED BIT(0)
43	#define IPSKB_XFRM_TUNNEL_SIZE 2	43	#define IPSKB_XFRM_TUNNEL_SIZE BIT(1)
44	#define IPSKB_XFRM_TRANSFORMED 4	44	#define IPSKB_XFRM_TRANSFORMED BIT(2)
45	#define IPSKB_FRAG_COMPLETE 8	45	#define IPSKB_FRAG_COMPLETE BIT(3)
46	#define IPSKB_REROUTED 16	46	#define IPSKB_REROUTED BIT(4)
		47	#define IPSKB_DOREDIRECT BIT(5)
47		48
48	u16 frag_max_size;	49	u16 frag_max_size;
49	};	50	};

kernel/bpf/syscall.c+17−8

 	int ufd = attr->map_fd;
 	struct fd f = fdget(ufd);
 	struct bpf_map *map;
-	void *key, *value;
+	void *key, *value, *ptr;
 	int err;
 	if (CHECK_ATTR(BPF_MAP_LOOKUP_ELEM))
 	if (copy_from_user(key, ukey, map->key_size) != 0)
 		goto free_key;
-	err = -ENOENT;
+	err = -ENOMEM;
-	rcu_read_lock();
+	value = kmalloc(map->value_size, GFP_USER);
-	value = map->ops->map_lookup_elem(map, key);
 	if (!value)
-		goto err_unlock;
+		goto free_key;
+	rcu_read_lock();
+	ptr = map->ops->map_lookup_elem(map, key);
+	if (ptr)
+		memcpy(value, ptr, map->value_size);
+	rcu_read_unlock();
+	err = -ENOENT;
+	if (!ptr)
+		goto free_value;
 	err = -EFAULT;
 	if (copy_to_user(uvalue, value, map->value_size) != 0)
-		goto err_unlock;
+		goto free_value;
 	err = 0;
-err_unlock:
+free_value:
-	rcu_read_unlock();
+	kfree(value);
 free_key:
 	kfree(key);
 err_put:

kernel/cgroup.c+1−1

@@ -1909,7 +1909,7 @@ static void cgroup_kill_sb(struct super_block *sb) · 1908 unmodified lines
1909	*	1909	*
1910	* And don't kill the default root.	1910	* And don't kill the default root.
1911	*/	1911	*/
1912	if (css_has_online_children(&root->cgrp.self) \|\|	1912	if (!list_empty(&root->cgrp.self.children) \|\|
1913	root == &cgrp_dfl_root)	1913	root == &cgrp_dfl_root)
1914	cgroup_put(&root->cgrp);	1914	cgroup_put(&root->cgrp);
1915	else	1915	else

kernel/events/core.c+13−2

 		__perf_event_init_context(&cpuctx->ctx);
 		lockdep_set_class(&cpuctx->ctx.mutex, &cpuctx_mutex);
 		lockdep_set_class(&cpuctx->ctx.lock, &cpuctx_lock);
-		cpuctx->ctx.type = cpu_context;
 		cpuctx->ctx.pmu = pmu;
 		__perf_cpu_hrtimer_init(cpuctx, cpu);
 		 * task or CPU context:
 		 */
 		if (move_group) {
-			if (group_leader->ctx->type != ctx->type)
+			/*
+			 * Make sure we're both on the same task, or both
+			 * per-cpu events.
+			 */
+			if (group_leader->ctx->task != ctx->task)
+				goto err_context;
+			/*
+			 * Make sure we're both events for the same CPU;
+			 * grouping events for different CPUs is broken; since
+			 * you can never concurrently schedule them anyhow.
+			 */
+			if (group_leader->cpu != event->cpu)
 				goto err_context;
 		} else {
 			if (group_leader->ctx != ctx)

kernel/sched/core.c+2−3

 	 * since we will exit with TASK_RUNNING make sure we enter with it,
 	 * otherwise we will destroy state.
 	 */
-	if (WARN_ONCE(current->state != TASK_RUNNING,
+	WARN_ONCE(current->state != TASK_RUNNING && current->task_state_change,
 			"do not call blocking ops when !TASK_RUNNING; "
 			"state=%lx set at [<%p>] %pS\n",
 			current->state,
 			(void *)current->task_state_change,
-			(void *)current->task_state_change))
+			(void *)current->task_state_change);
-		__set_current_state(TASK_RUNNING);
 	___might_sleep(file, line, preempt_offset);
 }

mm/gup.c+2−2

@@ -296,7 +296,7 @@ static int faultin_page(struct task_struct tsk, struct vm_area_struct vma, · 295 unmodified lines
296	return -ENOMEM;	296	return -ENOMEM;
297	if (ret & (VM_FAULT_HWPOISON \| VM_FAULT_HWPOISON_LARGE))	297	if (ret & (VM_FAULT_HWPOISON \| VM_FAULT_HWPOISON_LARGE))
298	return *flags & FOLL_HWPOISON ? -EHWPOISON : -EFAULT;	298	return *flags & FOLL_HWPOISON ? -EHWPOISON : -EFAULT;
299	if (ret & VM_FAULT_SIGBUS)	299	if (ret & (VM_FAULT_SIGBUS \| VM_FAULT_SIGSEGV))
300	return -EFAULT;	300	return -EFAULT;
301	BUG();	301	BUG();
302	}	302	}
@@ -571,7 +571,7 @@ int fixup_user_fault(struct task_struct tsk, struct mm_struct mm, · 268 unmodified lines
571	return -ENOMEM;	571	return -ENOMEM;
572	if (ret & (VM_FAULT_HWPOISON \| VM_FAULT_HWPOISON_LARGE))	572	if (ret & (VM_FAULT_HWPOISON \| VM_FAULT_HWPOISON_LARGE))
573	return -EHWPOISON;	573	return -EHWPOISON;
574	if (ret & VM_FAULT_SIGBUS)	574	if (ret & (VM_FAULT_SIGBUS \| VM_FAULT_SIGSEGV))
575	return -EFAULT;	575	return -EFAULT;
576	BUG();	576	BUG();
577	}	577	}

mm/ksm.c+1−1

@@ -376,7 +376,7 @@ static int break_ksm(struct vm_area_struct *vma, unsigned long addr) · 375 unmodified lines
376	else	376	else
377	ret = VM_FAULT_WRITE;	377	ret = VM_FAULT_WRITE;
378	put_page(page);	378	put_page(page);
379	} while (!(ret & (VM_FAULT_WRITE \| VM_FAULT_SIGBUS \| VM_FAULT_OOM)));	379	} while (!(ret & (VM_FAULT_WRITE \| VM_FAULT_SIGBUS \| VM_FAULT_SIGSEGV \| VM_FAULT_OOM)));
380	/*	380	/*
381	* We must loop because handle_mm_fault() may back out if there's	381	* We must loop because handle_mm_fault() may back out if there's
382	* any difficulty e.g. if pte accessed bit gets updated concurrently.	382	* any difficulty e.g. if pte accessed bit gets updated concurrently.

mm/memcontrol.c+2−2

@@ -1477,9 +1477,9 @@ void mem_cgroup_print_oom_info(struct mem_cgroup memcg, struct task_struct p) · 1476 unmodified lines
1477		1477
1478	pr_info("Task in ");	1478	pr_info("Task in ");
1479	pr_cont_cgroup_path(task_cgroup(p, memory_cgrp_id));	1479	pr_cont_cgroup_path(task_cgroup(p, memory_cgrp_id));
1480	pr_info(" killed as a result of limit of ");	1480	pr_cont(" killed as a result of limit of ");
1481	pr_cont_cgroup_path(memcg->css.cgroup);	1481	pr_cont_cgroup_path(memcg->css.cgroup);
1482	pr_info("\n");	1482	pr_cont("\n");
1483		1483
1484	rcu_read_unlock();	1484	rcu_read_unlock();
1485		1485

mm/memory.c+1−1

@@ -2632,7 +2632,7 @@ static int do_anonymous_page(struct mm_struct mm, struct vm_area_struct vma, · 2631 unmodified lines
2632		2632
2633	/* Check if we need to add a guard page to the stack */	2633	/* Check if we need to add a guard page to the stack */
2634	if (check_stack_guard_page(vma, address) < 0)	2634	if (check_stack_guard_page(vma, address) < 0)
2635	return VM_FAULT_SIGBUS;	2635	return VM_FAULT_SIGSEGV;
2636		2636
2637	/* Use the zero-page for reads */	2637	/* Use the zero-page for reads */
2638	if (!(flags & FAULT_FLAG_WRITE) && !mm_forbids_zeropage(mm)) {	2638	if (!(flags & FAULT_FLAG_WRITE) && !mm_forbids_zeropage(mm)) {

mm/page_alloc.c+35−47

@@ -2332,12 +2332,21 @@ static inline struct page * · 2331 unmodified lines
2332	__alloc_pages_may_oom(gfp_t gfp_mask, unsigned int order,	2332	__alloc_pages_may_oom(gfp_t gfp_mask, unsigned int order,
2333	struct zonelist *zonelist, enum zone_type high_zoneidx,	2333	struct zonelist *zonelist, enum zone_type high_zoneidx,
2334	nodemask_t nodemask, struct zone preferred_zone,	2334	nodemask_t nodemask, struct zone preferred_zone,
2335	int classzone_idx, int migratetype)	2335	int classzone_idx, int migratetype, unsigned long *did_some_progress)
2336	{	2336	{
2337	struct page *page;	2337	struct page *page;
2338		2338
2339	/* Acquire the per-zone oom lock for each zone */	2339	*did_some_progress = 0;
		2340
		2341	if (oom_killer_disabled)
		2342	return NULL;
		2343
		2344	/*
		2345	* Acquire the per-zone oom lock for each zone. If that
		2346	* fails, somebody else is making progress for us.
		2347	*/
2340	if (!oom_zonelist_trylock(zonelist, gfp_mask)) {	2348	if (!oom_zonelist_trylock(zonelist, gfp_mask)) {
		2349	*did_some_progress = 1;
2341	schedule_timeout_uninterruptible(1);	2350	schedule_timeout_uninterruptible(1);
2342	return NULL;	2351	return NULL;
2343	}	2352	}
@@ -2363,12 +2372,18 @@ __alloc_pages_may_oom(gfp_t gfp_mask, unsigned int order, · 19 unmodified lines
2363	goto out;	2372	goto out;
2364		2373
2365	if (!(gfp_mask & __GFP_NOFAIL)) {	2374	if (!(gfp_mask & __GFP_NOFAIL)) {
		2375	/* Coredumps can quickly deplete all memory reserves */
		2376	if (current->flags & PF_DUMPCORE)
		2377	goto out;
2366	/* The OOM killer will not help higher order allocs */	2378	/* The OOM killer will not help higher order allocs */
2367	if (order > PAGE_ALLOC_COSTLY_ORDER)	2379	if (order > PAGE_ALLOC_COSTLY_ORDER)
2368	goto out;	2380	goto out;
2369	/* The OOM killer does not needlessly kill tasks for lowmem */	2381	/* The OOM killer does not needlessly kill tasks for lowmem */
2370	if (high_zoneidx < ZONE_NORMAL)	2382	if (high_zoneidx < ZONE_NORMAL)
2371	goto out;	2383	goto out;
		2384	/* The OOM killer does not compensate for light reclaim */
		2385	if (!(gfp_mask & __GFP_FS))
		2386	goto out;
2372	/*	2387	/*
2373	* GFP_THISNODE contains __GFP_NORETRY and we never hit this.	2388	* GFP_THISNODE contains __GFP_NORETRY and we never hit this.
2374	* Sanity check for bare calls of __GFP_THISNODE, not real OOM.	2389	* Sanity check for bare calls of __GFP_THISNODE, not real OOM.
@@ -2381,7 +2396,7 @@ __alloc_pages_may_oom(gfp_t gfp_mask, unsigned int order, · 6 unmodified lines
2381	}	2396	}
2382	/* Exhausted what can be done so it's blamo time */	2397	/* Exhausted what can be done so it's blamo time */
2383	out_of_memory(zonelist, gfp_mask, order, nodemask, false);	2398	out_of_memory(zonelist, gfp_mask, order, nodemask, false);
2384		2399	*did_some_progress = 1;
2385	out:	2400	out:
2386	oom_zonelist_unlock(zonelist, gfp_mask);	2401	oom_zonelist_unlock(zonelist, gfp_mask);
2387	return page;	2402	return page;
@@ -2658,7 +2673,7 @@ __alloc_pages_slowpath(gfp_t gfp_mask, unsigned int order, · 270 unmodified lines
2658	(gfp_mask & GFP_THISNODE) == GFP_THISNODE)	2673	(gfp_mask & GFP_THISNODE) == GFP_THISNODE)
2659	goto nopage;	2674	goto nopage;
2660		2675
2661	restart:	2676	retry:
2662	if (!(gfp_mask & __GFP_NO_KSWAPD))	2677	if (!(gfp_mask & __GFP_NO_KSWAPD))
2663	wake_all_kswapds(order, zonelist, high_zoneidx,	2678	wake_all_kswapds(order, zonelist, high_zoneidx,
2664	preferred_zone, nodemask);	2679	preferred_zone, nodemask);
@@ -2681,7 +2696,6 @@ restart: · 16 unmodified lines
2681	classzone_idx = zonelist_zone_idx(preferred_zoneref);	2696	classzone_idx = zonelist_zone_idx(preferred_zoneref);
2682	}	2697	}
2683		2698
2684	rebalance:
2685	/* This is the last chance, in general, before the goto nopage. */	2699	/* This is the last chance, in general, before the goto nopage. */
2686	page = get_page_from_freelist(gfp_mask, nodemask, order, zonelist,	2700	page = get_page_from_freelist(gfp_mask, nodemask, order, zonelist,
2687	high_zoneidx, alloc_flags & ~ALLOC_NO_WATERMARKS,	2701	high_zoneidx, alloc_flags & ~ALLOC_NO_WATERMARKS,
@@ -2788,54 +2802,28 @@ rebalance: · 100 unmodified lines
2788	if (page)	2802	if (page)
2789	goto got_pg;	2803	goto got_pg;
2790		2804
2791	/*
2792	* If we failed to make any progress reclaiming, then we are
2793	* running out of options and have to consider going OOM
2794	*/
2795	if (!did_some_progress) {
2796	if (oom_gfp_allowed(gfp_mask)) {
2797	if (oom_killer_disabled)
2798	goto nopage;
2799	/* Coredumps can quickly deplete all memory reserves */
2800	if ((current->flags & PF_DUMPCORE) &&
2801	!(gfp_mask & __GFP_NOFAIL))
2802	goto nopage;
2803	page = __alloc_pages_may_oom(gfp_mask, order,
2804	zonelist, high_zoneidx,
2805	nodemask, preferred_zone,
2806	classzone_idx, migratetype);
2807	if (page)
2808	goto got_pg;
2809
2810	if (!(gfp_mask & __GFP_NOFAIL)) {
2811	/*
2812	* The oom killer is not called for high-order
2813	* allocations that may fail, so if no progress
2814	* is being made, there are no other options and
2815	* retrying is unlikely to help.
2816	*/
2817	if (order > PAGE_ALLOC_COSTLY_ORDER)
2818	goto nopage;
2819	/*
2820	* The oom killer is not called for lowmem
2821	* allocations to prevent needlessly killing
2822	* innocent tasks.
2823	*/
2824	if (high_zoneidx < ZONE_NORMAL)
2825	goto nopage;
2826	}
2827
2828	goto restart;
2829	}
2830	}
2831
2832	/* Check if we should retry the allocation */	2805	/* Check if we should retry the allocation */
2833	pages_reclaimed += did_some_progress;	2806	pages_reclaimed += did_some_progress;
2834	if (should_alloc_retry(gfp_mask, order, did_some_progress,	2807	if (should_alloc_retry(gfp_mask, order, did_some_progress,
2835	pages_reclaimed)) {	2808	pages_reclaimed)) {
		2809	/*
		2810	* If we fail to make progress by freeing individual
		2811	* pages, but the allocation wants us to keep going,
		2812	* start OOM killing tasks.
		2813	*/
		2814	if (!did_some_progress) {
		2815	page = __alloc_pages_may_oom(gfp_mask, order, zonelist,
		2816	high_zoneidx, nodemask,
		2817	preferred_zone, classzone_idx,
		2818	migratetype,&did_some_progress);
		2819	if (page)
		2820	goto got_pg;
		2821	if (!did_some_progress)
		2822	goto nopage;
		2823	}
2836	/* Wait for some write requests to complete then retry */	2824	/* Wait for some write requests to complete then retry */
2837	wait_iff_congested(preferred_zone, BLK_RW_ASYNC, HZ/50);	2825	wait_iff_congested(preferred_zone, BLK_RW_ASYNC, HZ/50);
2838	goto rebalance;	2826	goto retry;
2839	} else {	2827	} else {
2840	/*	2828	/*
2841	* High-order allocations do not necessarily loop after	2829	* High-order allocations do not necessarily loop after

mm/vmscan.c+1−1

@@ -2656,7 +2656,7 @@ static bool throttle_direct_reclaim(gfp_t gfp_mask, struct zonelist *zonelist, · 2655 unmodified lines
2656	* should make reasonable progress.	2656	* should make reasonable progress.
2657	*/	2657	*/
2658	for_each_zone_zonelist_nodemask(zone, z, zonelist,	2658	for_each_zone_zonelist_nodemask(zone, z, zonelist,
2659	gfp_mask, nodemask) {	2659	gfp_zone(gfp_mask), nodemask) {
2660	if (zone_idx(zone) > ZONE_NORMAL)	2660	if (zone_idx(zone) > ZONE_NORMAL)
2661	continue;	2661	continue;
2662		2662

net/dsa/slave.c+1−0

@@ -46,6 +46,7 @@ void dsa_slave_mii_bus_init(struct dsa_switch *ds) · 45 unmodified lines
46	snprintf(ds->slave_mii_bus->id, MII_BUS_ID_SIZE, "dsa-%d:%.2x",	46	snprintf(ds->slave_mii_bus->id, MII_BUS_ID_SIZE, "dsa-%d:%.2x",
47	ds->index, ds->pd->sw_addr);	47	ds->index, ds->pd->sw_addr);
48	ds->slave_mii_bus->parent = ds->master_dev;	48	ds->slave_mii_bus->parent = ds->master_dev;
		49	ds->slave_mii_bus->phy_mask = ~ds->phys_mii_mask;
49	}	50	}
50		51
51		52

net/ipv4/ip_forward.c+2−1

@@ -129,7 +129,8 @@ int ip_forward(struct sk_buff *skb) · 128 unmodified lines
129	* We now generate an ICMP HOST REDIRECT giving the route	129	* We now generate an ICMP HOST REDIRECT giving the route
130	* we calculated.	130	* we calculated.
131	*/	131	*/
132	if (rt->rt_flags&RTCF_DOREDIRECT && !opt->srr && !skb_sec_path(skb))	132	if (IPCB(skb)->flags & IPSKB_DOREDIRECT && !opt->srr &&
		133	!skb_sec_path(skb))
133	ip_rt_send_redirect(skb);	134	ip_rt_send_redirect(skb);
134		135
135	skb->priority = rt_tos2priority(iph->tos);	136	skb->priority = rt_tos2priority(iph->tos);

net/ipv4/ping.c+4−1

 	sk = ping_lookup(net, skb, ntohs(icmph->un.echo.id));
 	if (sk != NULL) {
+		struct sk_buff *skb2 = skb_clone(skb, GFP_ATOMIC);
 		pr_debug("rcv on socket %p\n", sk);
-		ping_queue_rcv_skb(sk, skb_get(skb));
+		if (skb2)
+			ping_queue_rcv_skb(sk, skb2);
 		sock_put(sk);
 		return true;
 	}

net/ipv4/route.c+5−4

 	do_cache = res->fi && !itag;
 	if (out_dev == in_dev && err && IN_DEV_TX_REDIRECTS(out_dev) &&
+	    skb->protocol == htons(ETH_P_IP) &&
 	    (IN_DEV_SHARED_MEDIA(out_dev) ||
-	     inet_addr_onlink(out_dev, saddr, FIB_RES_GW(*res)))) {
+	     inet_addr_onlink(out_dev, saddr, FIB_RES_GW(*res))))
-		flags |= RTCF_DOREDIRECT;
+		IPCB(skb)->flags |= IPSKB_DOREDIRECT;
-		do_cache = false;
-	}
 	if (skb->protocol != htons(ETH_P_IP)) {
 		/* Not IP (i.e. ARP). Do not create route, if it is
 	r->rtm_flags	= (rt->rt_flags & ~0xFFFF) | RTM_F_CLONED;
 	if (rt->rt_flags & RTCF_NOTIFY)
 		r->rtm_flags |= RTM_F_NOTIFY;
+	if (IPCB(skb)->flags & IPSKB_DOREDIRECT)
+		r->rtm_flags |= RTCF_DOREDIRECT;
 	if (nla_put_be32(skb, RTA_DST, dst))
 		goto nla_put_failure;

net/ipv4/udp_diag.c+3−1

 	s_slot = cb->args[0];
 	num = s_num = cb->args[1];
-	for (slot = s_slot; slot <= table->mask; num = s_num = 0, slot++) {
+	for (slot = s_slot; slot <= table->mask; s_num = 0, slot++) {
 		struct sock *sk;
 		struct hlist_nulls_node *node;
 		struct udp_hslot *hslot = &table->hash[slot];
+		num = 0;
 		if (hlist_nulls_empty(&hslot->head))
 			continue;

net/ipv6/ip6_fib.c+26−19

 	return 0;
 }
+static void fib6_purge_rt(struct rt6_info *rt, struct fib6_node *fn,
+			  struct net *net)
+{
+	if (atomic_read(&rt->rt6i_ref) != 1) {
+		/* This route is used as dummy address holder in some split
+		 * nodes. It is not leaked, but it still holds other resources,
+		 * which must be released in time. So, scan ascendant nodes
+		 * and replace dummy references to this route with references
+		 * to still alive ones.
+		 */
+		while (fn) {
+			if (!(fn->fn_flags & RTN_RTINFO) && fn->leaf == rt) {
+				fn->leaf = fib6_find_prefix(net, fn);
+				atomic_inc(&fn->leaf->rt6i_ref);
+				rt6_release(rt);
+			}
+			fn = fn->parent;
+		}
+		/* No more references are possible at this point. */
+		BUG_ON(atomic_read(&rt->rt6i_ref) != 1);
+	}
+}
 /*
  *	Insert routing information in a node.
  */
 		rt->dst.rt6_next = iter->dst.rt6_next;
 		atomic_inc(&rt->rt6i_ref);
 		inet6_rt_notify(RTM_NEWROUTE, rt, info);
-		rt6_release(iter);
 		if (!(fn->fn_flags & RTN_RTINFO)) {
 			info->nl_net->ipv6.rt6_stats->fib_route_nodes++;
 			fn->fn_flags |= RTN_RTINFO;
 		}
+		fib6_purge_rt(iter, fn, info->nl_net);
+		rt6_release(iter);
 	}
 	return 0;
 		fn = fib6_repair_tree(net, fn);
 	}
-	if (atomic_read(&rt->rt6i_ref) != 1) {
+	fib6_purge_rt(rt, fn, net);
-		/* This route is used as dummy address holder in some split
-		 * nodes. It is not leaked, but it still holds other resources,
-		 * which must be released in time. So, scan ascendant nodes
-		 * and replace dummy references to this route with references
-		 * to still alive ones.
-		 */
-		while (fn) {
-			if (!(fn->fn_flags & RTN_RTINFO) && fn->leaf == rt) {
-				fn->leaf = fib6_find_prefix(net, fn);
-				atomic_inc(&fn->leaf->rt6i_ref);
-				rt6_release(rt);
-			}
-			fn = fn->parent;
-		}
-		/* No more references are possible at this point. */
-		BUG_ON(atomic_read(&rt->rt6i_ref) != 1);
-	}
 	inet6_rt_notify(RTM_DELROUTE, rt, info);
 	rt6_release(rt);

net/ipv6/route.c+5−1

 		rt = net->ipv6.ip6_null_entry;
 	else if (rt->dst.error) {
 		rt = net->ipv6.ip6_null_entry;
-	} else if (rt == net->ipv6.ip6_null_entry) {
+		goto out;
+	}
+	if (rt == net->ipv6.ip6_null_entry) {
 		fn = fib6_backtrack(fn, &fl6->saddr);
 		if (fn)
 			goto restart;
 	}
+out:
 	dst_hold(&rt->dst);
 	read_unlock_bh(&table->tb6_lock);

net/ipv6/xfrm6_policy.c+8−2

 {
 	struct flowi6 *fl6 = &fl->u.ip6;
 	int onlyproto = 0;
-	u16 offset = skb_network_header_len(skb);
 	const struct ipv6hdr *hdr = ipv6_hdr(skb);
+	u16 offset = sizeof(*hdr);
 	struct ipv6_opt_hdr *exthdr;
 	const unsigned char *nh = skb_network_header(skb);
-	u8 nexthdr = nh[IP6CB(skb)->nhoff];
+	u16 nhoff = IP6CB(skb)->nhoff;
 	int oif = 0;
+	u8 nexthdr;
+	if (!nhoff)
+		nhoff = offsetof(struct ipv6hdr, nexthdr);
+	nexthdr = nh[nhoff];
 	if (skb_dst(skb))
 		oif = skb_dst(skb)->dev->ifindex;

net/llc/sysctl_net_llc.c+4−4

@@ -18,28 +18,28 @@ static struct ctl_table llc2_timeout_table[] = { · 17 unmodified lines
18	{	18	{
19	.procname = "ack",	19	.procname = "ack",
20	.data = &sysctl_llc2_ack_timeout,	20	.data = &sysctl_llc2_ack_timeout,
21	.maxlen = sizeof(long),	21	.maxlen = sizeof(sysctl_llc2_ack_timeout),
22	.mode = 0644,	22	.mode = 0644,
23	.proc_handler = proc_dointvec_jiffies,	23	.proc_handler = proc_dointvec_jiffies,
24	},	24	},
25	{	25	{
26	.procname = "busy",	26	.procname = "busy",
27	.data = &sysctl_llc2_busy_timeout,	27	.data = &sysctl_llc2_busy_timeout,
28	.maxlen = sizeof(long),	28	.maxlen = sizeof(sysctl_llc2_busy_timeout),
29	.mode = 0644,	29	.mode = 0644,
30	.proc_handler = proc_dointvec_jiffies,	30	.proc_handler = proc_dointvec_jiffies,
31	},	31	},
32	{	32	{
33	.procname = "p",	33	.procname = "p",
34	.data = &sysctl_llc2_p_timeout,	34	.data = &sysctl_llc2_p_timeout,
35	.maxlen = sizeof(long),	35	.maxlen = sizeof(sysctl_llc2_p_timeout),
36	.mode = 0644,	36	.mode = 0644,
37	.proc_handler = proc_dointvec_jiffies,	37	.proc_handler = proc_dointvec_jiffies,
38	},	38	},
39	{	39	{
40	.procname = "rej",	40	.procname = "rej",
41	.data = &sysctl_llc2_rej_timeout,	41	.data = &sysctl_llc2_rej_timeout,
42	.maxlen = sizeof(long),	42	.maxlen = sizeof(sysctl_llc2_rej_timeout),
43	.mode = 0644,	43	.mode = 0644,
44	.proc_handler = proc_dointvec_jiffies,	44	.proc_handler = proc_dointvec_jiffies,
45	},	45	},

net/mac80211/pm.c+15−14

 		}
 	}
-	/* tear down aggregation sessions and remove STAs */
-	mutex_lock(&local->sta_mtx);
-	list_for_each_entry(sta, &local->sta_list, list) {
-		if (sta->uploaded) {
-			enum ieee80211_sta_state state;
-			state = sta->sta_state;
-			for (; state > IEEE80211_STA_NOTEXIST; state--)
-				WARN_ON(drv_sta_state(local, sta->sdata, sta,
-						      state, state - 1));
-		}
-	}
-	mutex_unlock(&local->sta_mtx);
 	/* remove all interfaces that were created in the driver */
 	list_for_each_entry(sdata, &local->interfaces, list) {
 		if (!ieee80211_sdata_running(sdata))
 		case NL80211_IFTYPE_STATION:
 			ieee80211_mgd_quiesce(sdata);
 			break;
+		case NL80211_IFTYPE_WDS:
+			/* tear down aggregation sessions and remove STAs */
+			mutex_lock(&local->sta_mtx);
+			sta = sdata->u.wds.sta;
+			if (sta && sta->uploaded) {
+				enum ieee80211_sta_state state;
+				state = sta->sta_state;
+				for (; state > IEEE80211_STA_NOTEXIST; state--)
+					WARN_ON(drv_sta_state(local, sta->sdata,
+							      sta, state,
+							      state - 1));
+			}
+			mutex_unlock(&local->sta_mtx);
+			break;
 		default:
 			break;
 		}

net/mac80211/rx.c+1−1

@@ -272,7 +272,7 @@ ieee80211_add_rx_radiotap_header(struct ieee80211_local *local, · 271 unmodified lines
272	else if (rate && rate->flags & IEEE80211_RATE_ERP_G)	272	else if (rate && rate->flags & IEEE80211_RATE_ERP_G)
273	channel_flags \|= IEEE80211_CHAN_OFDM \| IEEE80211_CHAN_2GHZ;	273	channel_flags \|= IEEE80211_CHAN_OFDM \| IEEE80211_CHAN_2GHZ;
274	else if (rate)	274	else if (rate)
275	channel_flags \|= IEEE80211_CHAN_OFDM \| IEEE80211_CHAN_2GHZ;	275	channel_flags \|= IEEE80211_CHAN_CCK \| IEEE80211_CHAN_2GHZ;
276	else	276	else
277	channel_flags \|= IEEE80211_CHAN_2GHZ;	277	channel_flags \|= IEEE80211_CHAN_2GHZ;
278	put_unaligned_le16(channel_flags, pos);	278	put_unaligned_le16(channel_flags, pos);

net/sched/cls_bpf.c+13−2

@@ -180,6 +180,11 @@ static int cls_bpf_modify_existing(struct net net, struct tcf_proto tp, · 179 unmodified lines
180	}	180	}
181		181
182	bpf_size = bpf_len * sizeof(*bpf_ops);	182	bpf_size = bpf_len * sizeof(*bpf_ops);
		183	if (bpf_size != nla_len(tb[TCA_BPF_OPS])) {
		184	ret = -EINVAL;
		185	goto errout;
		186	}
		187
183	bpf_ops = kzalloc(bpf_size, GFP_KERNEL);	188	bpf_ops = kzalloc(bpf_size, GFP_KERNEL);
184	if (bpf_ops == NULL) {	189	if (bpf_ops == NULL) {
185	ret = -ENOMEM;	190	ret = -ENOMEM;
@@ -215,15 +220,21 @@ static u32 cls_bpf_grab_new_handle(struct tcf_proto *tp, · 29 unmodified lines
215	struct cls_bpf_head *head)	220	struct cls_bpf_head *head)
216	{	221	{
217	unsigned int i = 0x80000000;	222	unsigned int i = 0x80000000;
		223	u32 handle;
218		224
219	do {	225	do {
220	if (++head->hgen == 0x7FFFFFFF)	226	if (++head->hgen == 0x7FFFFFFF)
221	head->hgen = 1;	227	head->hgen = 1;
222	} while (--i > 0 && cls_bpf_get(tp, head->hgen));	228	} while (--i > 0 && cls_bpf_get(tp, head->hgen));
223	if (i == 0)	229
		230	if (unlikely(i == 0)) {
224	pr_err("Insufficient number of handles\n");	231	pr_err("Insufficient number of handles\n");
		232	handle = 0;
		233	} else {
		234	handle = head->hgen;
		235	}
225		236
226	return i;	237	return handle;
227	}	238	}
228		239
229	static int cls_bpf_change(struct net net, struct sk_buff in_skb,	240	static int cls_bpf_change(struct net net, struct sk_buff in_skb,

net/sctp/associola.c+0−1

@@ -1182,7 +1182,6 @@ void sctp_assoc_update(struct sctp_association *asoc, · 1181 unmodified lines
1182	asoc->peer.peer_hmacs = new->peer.peer_hmacs;	1182	asoc->peer.peer_hmacs = new->peer.peer_hmacs;
1183	new->peer.peer_hmacs = NULL;	1183	new->peer.peer_hmacs = NULL;
1184		1184
1185	sctp_auth_key_put(asoc->asoc_shared_key);
1186	sctp_auth_asoc_init_active_key(asoc, GFP_ATOMIC);	1185	sctp_auth_asoc_init_active_key(asoc, GFP_ATOMIC);
1187	}	1186	}
1188		1187

net/socket.c+0−3

 static struct sock_iocb *alloc_sock_iocb(struct kiocb *iocb,
 					 struct sock_iocb *siocb)
 {
-	if (!is_sync_kiocb(iocb))
-		BUG();
 	siocb->kiocb = iocb;
 	iocb->private = siocb;
 	return siocb;

net/wireless/nl80211.c+4−5

 	if (!rdev->ops->get_key)
 		return -EOPNOTSUPP;
+	if (!pairwise && mac_addr && !(rdev->wiphy.flags & WIPHY_FLAG_IBSS_RSN))
+		return -ENOENT;
 	msg = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL);
 	if (!msg)
 		return -ENOMEM;
 	    nla_put(msg, NL80211_ATTR_MAC, ETH_ALEN, mac_addr))
 		goto nla_put_failure;
-	if (pairwise && mac_addr &&
-	    !(rdev->wiphy.flags & WIPHY_FLAG_IBSS_RSN))
-		return -ENOENT;
 	err = rdev_get_key(rdev, dev, key_idx, pairwise, mac_addr, &cookie,
 			   get_key_callback);
 	wdev_lock(dev->ieee80211_ptr);
 	err = nl80211_key_allowed(dev->ieee80211_ptr);
-	if (key.type == NL80211_KEYTYPE_PAIRWISE && mac_addr &&
+	if (key.type == NL80211_KEYTYPE_GROUP && mac_addr &&
 	    !(rdev->wiphy.flags & WIPHY_FLAG_IBSS_RSN))
 		err = -ENOENT;

net/wireless/util.c+6−0

 		goto out;
 	}
+	if (ieee80211_is_mgmt(fc)) {
+		if (ieee80211_has_order(fc))
+			hdrlen += IEEE80211_HT_CTL_LEN;
+		goto out;
+	}
 	if (ieee80211_is_ctl(fc)) {
 		/*
 		 * ACK and CTS are 10 bytes, all others 16. To see how

samples/bpf/test_maps.c+2−2

@@ -69,9 +69,9 @@ static void test_hashmap_sanity(int i, void *data) · 68 unmodified lines
69		69
70	/* iterate over two elements */	70	/* iterate over two elements */
71	assert(bpf_get_next_key(map_fd, &key, &next_key) == 0 &&	71	assert(bpf_get_next_key(map_fd, &key, &next_key) == 0 &&
72	next_key == 2);	72	(next_key == 1 \|\| next_key == 2));
73	assert(bpf_get_next_key(map_fd, &next_key, &next_key) == 0 &&	73	assert(bpf_get_next_key(map_fd, &next_key, &next_key) == 0 &&
74	next_key == 1);	74	(next_key == 1 \|\| next_key == 2));
75	assert(bpf_get_next_key(map_fd, &next_key, &next_key) == -1 &&	75	assert(bpf_get_next_key(map_fd, &next_key, &next_key) == -1 &&
76	errno == ENOENT);	76	errno == ENOENT);
77		77

sound/soc/atmel/atmel_ssc_dai.c+7−17

 	struct atmel_pcm_dma_params *dma_params;
 	int dir, channels, bits;
 	u32 tfmr, rfmr, tcmr, rcmr;
-	int start_event;
 	int ret;
 	int fslen, fslen_ext;
 		 * The SSC transmit clock is obtained from the BCLK signal on
 		 * on the TK line, and the SSC receive clock is
 		 * generated from the transmit clock.
-		 *
-		 *  For single channel data, one sample is transferred
-		 * on the falling edge of the LRC clock.
-		 * For two channel data, one sample is
-		 * transferred on both edges of the LRC clock.
 		 */
-		start_event = ((channels == 1)
-				? SSC_START_FALLING_RF
-				: SSC_START_EDGE_RF);
 		rcmr =	  SSC_BF(RCMR_PERIOD, 0)
 			| SSC_BF(RCMR_STTDLY, START_DELAY)
-			| SSC_BF(RCMR_START, start_event)
+			| SSC_BF(RCMR_START, SSC_START_FALLING_RF)
 			| SSC_BF(RCMR_CKI, SSC_CKI_RISING)
 			| SSC_BF(RCMR_CKO, SSC_CKO_NONE)
 			| SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
 		rfmr =	  SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
 			| SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
 			| SSC_BF(RFMR_FSLEN, 0)
-			| SSC_BF(RFMR_DATNB, 0)
+			| SSC_BF(RFMR_DATNB, (channels - 1))
 			| SSC_BIT(RFMR_MSBF)
 			| SSC_BF(RFMR_LOOP, 0)
 			| SSC_BF(RFMR_DATLEN, (bits - 1));
 		tcmr =	  SSC_BF(TCMR_PERIOD, 0)
 			| SSC_BF(TCMR_STTDLY, START_DELAY)
-			| SSC_BF(TCMR_START, start_event)
+			| SSC_BF(TCMR_START, SSC_START_FALLING_RF)
 			| SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
 			| SSC_BF(TCMR_CKO, SSC_CKO_NONE)
 			| SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ?
 			| SSC_BF(TFMR_FSDEN, 0)
 			| SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
 			| SSC_BF(TFMR_FSLEN, 0)
-			| SSC_BF(TFMR_DATNB, 0)
+			| SSC_BF(TFMR_DATNB, (channels - 1))
 			| SSC_BIT(TFMR_MSBF)
 			| SSC_BF(TFMR_DATDEF, 0)
 			| SSC_BF(TFMR_DATLEN, (bits - 1));
 		rcmr =	  SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
 			| SSC_BF(RCMR_STTDLY, 1)
 			| SSC_BF(RCMR_START, SSC_START_RISING_RF)
-			| SSC_BF(RCMR_CKI, SSC_CKI_RISING)
+			| SSC_BF(RCMR_CKI, SSC_CKI_FALLING)
 			| SSC_BF(RCMR_CKO, SSC_CKO_NONE)
 			| SSC_BF(RCMR_CKS, SSC_CKS_DIV);
 		tcmr =	  SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
 			| SSC_BF(TCMR_STTDLY, 1)
 			| SSC_BF(TCMR_START, SSC_START_RISING_RF)
-			| SSC_BF(TCMR_CKI, SSC_CKI_RISING)
+			| SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
 			| SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
 			| SSC_BF(TCMR_CKS, SSC_CKS_DIV);
 		rcmr =	  SSC_BF(RCMR_PERIOD, 0)
 			| SSC_BF(RCMR_STTDLY, START_DELAY)
 			| SSC_BF(RCMR_START, SSC_START_RISING_RF)
-			| SSC_BF(RCMR_CKI, SSC_CKI_RISING)
+			| SSC_BF(RCMR_CKI, SSC_CKI_FALLING)
 			| SSC_BF(RCMR_CKO, SSC_CKO_NONE)
 			| SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
 					   SSC_CKS_PIN : SSC_CKS_CLOCK);

sound/soc/codecs/rt5640.c+1−0

@@ -2124,6 +2124,7 @@ MODULE_DEVICE_TABLE(of, rt5640_of_match); · 2123 unmodified lines
2124	static struct acpi_device_id rt5640_acpi_match[] = {	2124	static struct acpi_device_id rt5640_acpi_match[] = {
2125	{ "INT33CA", 0 },	2125	{ "INT33CA", 0 },
2126	{ "10EC5640", 0 },	2126	{ "10EC5640", 0 },
		2127	{ "10EC5642", 0 },
2127	{ },	2128	{ },
2128	};	2129	};
2129	MODULE_DEVICE_TABLE(acpi, rt5640_acpi_match);	2130	MODULE_DEVICE_TABLE(acpi, rt5640_acpi_match);

sound/soc/codecs/sgtl5000.c+8−5

 	/* setting i2s data format */
 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 	case SND_SOC_DAIFMT_DSP_A:
-		i2sctl |= SGTL5000_I2S_MODE_PCM;
+		i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
 		break;
 	case SND_SOC_DAIFMT_DSP_B:
-		i2sctl |= SGTL5000_I2S_MODE_PCM;
+		i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
 		i2sctl |= SGTL5000_I2S_LRALIGN;
 		break;
 	case SND_SOC_DAIFMT_I2S:
-		i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
+		i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
 		break;
 	case SND_SOC_DAIFMT_RIGHT_J:
-		i2sctl |= SGTL5000_I2S_MODE_RJ;
+		i2sctl |= SGTL5000_I2S_MODE_RJ << SGTL5000_I2S_MODE_SHIFT;
 		i2sctl |= SGTL5000_I2S_LRPOL;
 		break;
 	case SND_SOC_DAIFMT_LEFT_J:
-		i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
+		i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
 		i2sctl |= SGTL5000_I2S_LRALIGN;
 		break;
 	default:
 	if (ret)
 		return ret;
+	/* Need 8 clocks before I2C accesses */
+	udelay(1);
 	/* read chip information */
 	ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, &reg);
 	if (ret)

sound/soc/codecs/tlv320aic3x.c+1−1

@@ -1046,7 +1046,7 @@ static int aic3x_prepare(struct snd_pcm_substream *substream, · 1045 unmodified lines
1046	delay += aic3x->tdm_delay;	1046	delay += aic3x->tdm_delay;
1047		1047
1048	/* Configure data delay */	1048	/* Configure data delay */
1049	snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, aic3x->tdm_delay);	1049	snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
1050		1050
1051	return 0;	1051	return 0;
1052	}	1052	}

sound/soc/codecs/wm8731.c+2−0

@@ -717,6 +717,8 @@ static int wm8731_i2c_probe(struct i2c_client *i2c, · 716 unmodified lines
717	if (wm8731 == NULL)	717	if (wm8731 == NULL)
718	return -ENOMEM;	718	return -ENOMEM;
719		719
		720	mutex_init(&wm8731->lock);
		721
720	wm8731->regmap = devm_regmap_init_i2c(i2c, &wm8731_regmap);	722	wm8731->regmap = devm_regmap_init_i2c(i2c, &wm8731_regmap);
721	if (IS_ERR(wm8731->regmap)) {	723	if (IS_ERR(wm8731->regmap)) {
722	ret = PTR_ERR(wm8731->regmap);	724	ret = PTR_ERR(wm8731->regmap);

sound/soc/intel/sst-haswell-ipc.c+2−2

@@ -651,11 +651,11 @@ static void hsw_notification_work(struct work_struct *work) · 650 unmodified lines
651	}	651	}
652		652
653	/* tell DSP that notification has been handled */	653	/* tell DSP that notification has been handled */
654	sst_dsp_shim_update_bits_unlocked(hsw->dsp, SST_IPCD,	654	sst_dsp_shim_update_bits(hsw->dsp, SST_IPCD,
655	SST_IPCD_BUSY \| SST_IPCD_DONE, SST_IPCD_DONE);	655	SST_IPCD_BUSY \| SST_IPCD_DONE, SST_IPCD_DONE);
656		656
657	/* unmask busy interrupt */	657	/* unmask busy interrupt */
658	sst_dsp_shim_update_bits_unlocked(hsw->dsp, SST_IMRX, SST_IMRX_BUSY, 0);	658	sst_dsp_shim_update_bits(hsw->dsp, SST_IMRX, SST_IMRX_BUSY, 0);
659	}	659	}
660		660
661	static struct ipc_message reply_find_msg(struct sst_hsw hsw, u32 header)	661	static struct ipc_message reply_find_msg(struct sst_hsw hsw, u32 header)

tools/perf/scripts/perl/Perf-Trace-Util/Context.c+4−1

@@ -5,7 +5,10 @@ · 4 unmodified lines
5	* ANY CHANGES MADE HERE WILL BE LOST!	5	* ANY CHANGES MADE HERE WILL BE LOST!
6	*	6	*
7	*/	7	*/
8		8	#include <stdbool.h>
		9	#ifndef HAS_BOOL
		10	# define HAS_BOOL 1
		11	#endif
9	#line 1 "Context.xs"	12	#line 1 "Context.xs"
10	/*	13	/*
11	* Context.xs. XS interfaces for perf script.	14	* Context.xs. XS interfaces for perf script.

tools/perf/util/annotate.c+14−4

 		goto out_free_ops;
 	ops->locked.ins = ins__find(name);
+	free(name);
 	if (ops->locked.ins == NULL)
 		goto out_free_ops;
 	if (!ops->locked.ins->ops)
 		return 0;
-	if (ops->locked.ins->ops->parse)
+	if (ops->locked.ins->ops->parse &&
-		ops->locked.ins->ops->parse(ops->locked.ops);
+	    ops->locked.ins->ops->parse(ops->locked.ops) < 0)
+		goto out_free_ops;
 	return 0;
 static void lock__delete(struct ins_operands *ops)
 {
+	struct ins *ins = ops->locked.ins;
+	if (ins && ins->ops->free)
+		ins->ops->free(ops->locked.ops);
+	else
+		ins__delete(ops->locked.ops);
 	zfree(&ops->locked.ops);
 	zfree(&ops->target.raw);
 	zfree(&ops->target.name);
 	if (!dl->ins->ops)
 		return;
-	if (dl->ins->ops->parse)
+	if (dl->ins->ops->parse && dl->ins->ops->parse(&dl->ops) < 0)
-		dl->ins->ops->parse(&dl->ops);
+		dl->ins = NULL;
 }
 static int disasm_line__parse(char *line, char **namep, char **rawp)

tools/perf/util/evlist.c+1−1

@@ -1445,7 +1445,7 @@ int perf_evlist__strerror_tp(struct perf_evlist *evlist __maybe_unused, · 1444 unmodified lines
1445	case ENOENT:	1445	case ENOENT:
1446	scnprintf(buf, size, "%s",	1446	scnprintf(buf, size, "%s",
1447	"Error:\tUnable to find debugfs\n"	1447	"Error:\tUnable to find debugfs\n"
1448	"Hint:\tWas your kernel was compiled with debugfs support?\n"	1448	"Hint:\tWas your kernel compiled with debugfs support?\n"
1449	"Hint:\tIs the debugfs filesystem mounted?\n"	1449	"Hint:\tIs the debugfs filesystem mounted?\n"
1450	"Hint:\tTry 'sudo mount -t debugfs nodev /sys/kernel/debug'");	1450	"Hint:\tTry 'sudo mount -t debugfs nodev /sys/kernel/debug'");
1451	break;	1451	break;

tools/perf/util/map.h+16−0

@@ -116,6 +116,22 @@ struct thread; · 115 unmodified lines
116	#define map__for_each_symbol(map, pos, n) \	116	#define map__for_each_symbol(map, pos, n) \
117	dso__for_each_symbol(map->dso, pos, n, map->type)	117	dso__for_each_symbol(map->dso, pos, n, map->type)
118		118
		119	/* map__for_each_symbol_with_name - iterate over the symbols in the given map
		120	* that have the given name
		121	*
		122	* @map: the 'struct map *' in which symbols itereated
		123	* @sym_name: the symbol name
		124	* @pos: the 'struct symbol *' to use as a loop cursor
		125	* @filter: to use when loading the DSO
		126	*/
		127	#define __map__for_each_symbol_by_name(map, sym_name, pos, filter) \
		128	for (pos = map__find_symbol_by_name(map, sym_name, filter); \
		129	pos && strcmp(pos->name, sym_name) == 0; \
		130	pos = symbol__next_by_name(pos))
		131
		132	#define map__for_each_symbol_by_name(map, sym_name, pos) \
		133	__map__for_each_symbol_by_name(map, sym_name, (pos), NULL)
		134
119	typedef int (symbol_filter_t)(struct map map, struct symbol *sym);	135	typedef int (symbol_filter_t)(struct map map, struct symbol *sym);
120		136
121	void map__init(struct map *map, enum map_type type,	137	void map__init(struct map *map, enum map_type type,

tools/perf/util/probe-event.c+16−18

@@ -446,7 +446,7 @@ static int post_process_probe_trace_events(struct probe_trace_event *tevs, · 445 unmodified lines
446	}	446	}
447		447
448	for (i = 0; i < ntevs; i++) {	448	for (i = 0; i < ntevs; i++) {
449	if (tevs[i].point.address) {	449	if (tevs[i].point.address && !tevs[i].point.retprobe) {
450	tmp = strdup(reloc_sym->name);	450	tmp = strdup(reloc_sym->name);
451	if (!tmp)	451	if (!tmp)
452	return -ENOMEM;	452	return -ENOMEM;
@@ -2193,18 +2193,17 @@ static int __add_probe_trace_events(struct perf_probe_event *pev, · 1740 unmodified lines
2193	return ret;	2193	return ret;
2194	}	2194	}
2195		2195
2196	static char *looking_function_name;	2196	static int find_probe_functions(struct map map, char name)
2197	static int num_matched_functions;
2198
2199	static int probe_function_filter(struct map *map __maybe_unused,
2200	struct symbol *sym)
2201	{	2197	{
2202	if ((sym->binding == STB_GLOBAL \|\| sym->binding == STB_LOCAL) &&	2198	int found = 0;
2203	strcmp(looking_function_name, sym->name) == 0) {	2199	struct symbol *sym;
2204	num_matched_functions++;	2200
2205	return 0;	2201	map__for_each_symbol_by_name(map, name, sym) {
		2202	if (sym->binding == STB_GLOBAL \|\| sym->binding == STB_LOCAL)
		2203	found++;
2206	}	2204	}
2207	return 1;	2205
		2206	return found;
2208	}	2207	}
2209		2208
2210	#define strdup_or_goto(str, label) \	2209	#define strdup_or_goto(str, label) \
@@ -2222,10 +2221,10 @@ static int find_probe_trace_events_from_map(struct perf_probe_event *pev, · 11 unmodified lines
2222	struct kmap *kmap = NULL;	2221	struct kmap *kmap = NULL;
2223	struct ref_reloc_sym *reloc_sym = NULL;	2222	struct ref_reloc_sym *reloc_sym = NULL;
2224	struct symbol *sym;	2223	struct symbol *sym;
2225	struct rb_node *nd;
2226	struct probe_trace_event *tev;	2224	struct probe_trace_event *tev;
2227	struct perf_probe_point *pp = &pev->point;	2225	struct perf_probe_point *pp = &pev->point;
2228	struct probe_trace_point *tp;	2226	struct probe_trace_point *tp;
		2227	int num_matched_functions;
2229	int ret, i;	2228	int ret, i;
2230		2229
2231	/* Init maps of given executable or kernel */	2230	/* Init maps of given executable or kernel */
@@ -2242,10 +2241,8 @@ static int find_probe_trace_events_from_map(struct perf_probe_event *pev, · 10 unmodified lines
2242	* Load matched symbols: Since the different local symbols may have	2241	* Load matched symbols: Since the different local symbols may have
2243	* same name but different addresses, this lists all the symbols.	2242	* same name but different addresses, this lists all the symbols.
2244	*/	2243	*/
2245	num_matched_functions = 0;	2244	num_matched_functions = find_probe_functions(map, pp->function);
2246	looking_function_name = pp->function;	2245	if (num_matched_functions == 0) {
2247	ret = map__load(map, probe_function_filter);
2248	if (ret \|\| num_matched_functions == 0) {
2249	pr_err("Failed to find symbol %s in %s\n", pp->function,	2246	pr_err("Failed to find symbol %s in %s\n", pp->function,
2250	target ? : "kernel");	2247	target ? : "kernel");
2251	ret = -ENOENT;	2248	ret = -ENOENT;
@@ -2257,7 +2254,7 @@ static int find_probe_trace_events_from_map(struct perf_probe_event *pev, · 5 unmodified lines
2257	goto out;	2254	goto out;
2258	}	2255	}
2259		2256
2260	if (!pev->uprobes) {	2257	if (!pev->uprobes && !pp->retprobe) {
2261	kmap = map__kmap(map);	2258	kmap = map__kmap(map);
2262	reloc_sym = kmap->ref_reloc_sym;	2259	reloc_sym = kmap->ref_reloc_sym;
2263	if (!reloc_sym) {	2260	if (!reloc_sym) {
@@ -2275,7 +2272,8 @@ static int find_probe_trace_events_from_map(struct perf_probe_event *pev, · 11 unmodified lines
2275	}	2272	}
2276		2273
2277	ret = 0;	2274	ret = 0;
2278	map__for_each_symbol(map, sym, nd) {	2275
		2276	map__for_each_symbol_by_name(map, pp->function, sym) {
2279	tev = (*tevs) + ret;	2277	tev = (*tevs) + ret;
2280	tp = &tev->point;	2278	tp = &tev->point;
2281	if (ret == num_matched_functions) {	2279	if (ret == num_matched_functions) {

tools/perf/util/symbol.c+28−3

 					    const char *name)
 {
 	struct rb_node *n;
+	struct symbol_name_rb_node *s;
 	if (symbols == NULL)
 		return NULL;
 	n = symbols->rb_node;
 	while (n) {
-		struct symbol_name_rb_node *s;
 		int cmp;
 		s = rb_entry(n, struct symbol_name_rb_node, rb_node);
 		else if (cmp > 0)
 			n = n->rb_right;
 		else
-			return &s->sym;
+			break;
 	}
-	return NULL;
+	if (n == NULL)
+		return NULL;
+	/* return first symbol that has same name (if any) */
+	for (n = rb_prev(n); n; n = rb_prev(n)) {
+		struct symbol_name_rb_node *tmp;
+		tmp = rb_entry(n, struct symbol_name_rb_node, rb_node);
+		if (strcmp(tmp->sym.name, s->sym.name))
+			break;
+		s = tmp;
+	}
+	return &s->sym;
 }
 struct symbol *dso__find_symbol(struct dso *dso,
 	return symbols__next(sym);
 }
+struct symbol *symbol__next_by_name(struct symbol *sym)
+{
+	struct symbol_name_rb_node *s = container_of(sym, struct symbol_name_rb_node, sym);
+	struct rb_node *n = rb_next(&s->rb_node);
+	return n ? &rb_entry(n, struct symbol_name_rb_node, rb_node)->sym : NULL;
+}
+ /*
+  * Teturns first symbol that matched with @name.
+  */
 struct symbol *dso__find_symbol_by_name(struct dso *dso, enum map_type type,
 					const char *name)
 {

tools/perf/util/symbol.h+1−0

@@ -231,6 +231,7 @@ struct symbol dso__find_symbol(struct dso dso, enum map_type type, · 230 unmodified lines
231	u64 addr);	231	u64 addr);
232	struct symbol dso__find_symbol_by_name(struct dso dso, enum map_type type,	232	struct symbol dso__find_symbol_by_name(struct dso dso, enum map_type type,
233	const char *name);	233	const char *name);
		234	struct symbol symbol__next_by_name(struct symbol sym);
234		235
235	struct symbol dso__first_symbol(struct dso dso, enum map_type type);	236	struct symbol dso__first_symbol(struct dso dso, enum map_type type);
236	struct symbol dso__next_symbol(struct symbol sym);	237	struct symbol dso__next_symbol(struct symbol sym);

Merge tag 'asoc-fix-v3.19-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus

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