Merge tag 'linux-can-next-for-6.5-20230622' of git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next

Marc Kleine-Budde says: ==================== pull-request: can-next 2023-06-22 The first patch is by Carsten Schmidt, targets the kvaser_usb driver and adds len8_dlc support. Marcel Hellwig's patch for the xilinx_can driver adds support for CAN transceivers via the PHY framework. Frank Jungclaus contributes 6+2 patches for the esd_usb driver in preparation for the upcoming CAN-USB/3 support. The 2 patches by Miquel Raynal for the sja1000 driver work around overruns stalls on the Renesas SoCs. The next 3 patches are by me and fix the coding style in the rx-offload helper and in the m_can and ti_hecc driver. Vincent Mailhol contributes 3 patches to fix and update the calculation of the length of CAN frames on the wire. Oliver Hartkopp's patch moves the CAN_RAW_FILTER_MAX definition into the correct header. The remaining 14 patches are by Jimmy Assarsson, target the kvaser_pciefd driver and bring various updates and improvements. * tag 'linux-can-next-for-6.5-20230622' of git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next: (33 commits) can: kvaser_pciefd: Use TX FIFO size read from CAN controller can: kvaser_pciefd: Refactor code can: kvaser_pciefd: Add len8_dlc support can: kvaser_pciefd: Use FIELD_{GET,PREP} and GENMASK where appropriate can: kvaser_pciefd: Sort register definitions can: kvaser_pciefd: Change return type for kvaser_pciefd_{receive,transmit,set_tx}_irq() can: kvaser_pciefd: Rename device ID defines can: kvaser_pciefd: Sort includes in alphabetic order can: kvaser_pciefd: Remove SPI flash parameter read functionality can: uapi: move CAN_RAW_FILTER_MAX definition to raw.h can: kvaser_pciefd: Define unsigned constants with type suffix 'U' can: kvaser_pciefd: Set hardware timestamp on transmitted packets can: kvaser_pciefd: Add function to set skb hwtstamps can: kvaser_pciefd: Remove handler for unused KVASER_PCIEFD_PACK_TYPE_EFRAME_ACK can: kvaser_pciefd: Remove useless write to interrupt register can: length: refactor frame lengths definition to add size in bits can: length: fix bitstuffing count can: length: fix description of the RRS field can: m_can: fix coding style can: ti_hecc: fix coding style ... ====================

Jakub Kicinski committed 3 years ago

Commit 08eeccb2 parents 0ec92a8 790ef3917 files · +809 −912Browse files

Unified · Split

17 files

drivers/net/can/Kconfig +1 −2
drivers/net/can/dev/length.c +2 −13
drivers/net/can/dev/rx-offload.c +1 −1
drivers/net/can/kvaser_pciefd.c +341 −614
drivers/net/can/m_can/m_can.c +2 −2
drivers/net/can/sja1000/sja1000.c +34 −6
drivers/net/can/sja1000/sja1000.h +1 −0
drivers/net/can/sja1000/sja1000_platform.c +4 −1
drivers/net/can/ti_hecc.c +1 −1
drivers/net/can/usb/esd_usb.c +174 −178
drivers/net/can/usb/kvaser_usb/kvaser_usb_core.c +1 −1
drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c +9 −4
drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c +3 −3
drivers/net/can/xilinx_can.c +19 −0
include/linux/can/length.h +214 −85
include/uapi/linux/can.h +0 −1
include/uapi/linux/can/raw.h +2 −0

drivers/net/can/Kconfig+1−2

@@ -153,8 +153,7 @@ config CAN_JANZ_ICAN3 · 152 unmodified lines
153	153	config CAN_KVASER_PCIEFD
154	154	depends on PCI
155	155	tristate "Kvaser PCIe FD cards"
156		− select CRC32
157		− help
	156	+ help
158	157	This is a driver for the Kvaser PCI Express CAN FD family.
159	158
160	159	Supported devices:

drivers/net/can/dev/length.c+2−13

@@ -78,18 +78,7 @@ unsigned int can_skb_get_frame_len(const struct sk_buff *skb) · 77 unmodified lines
78	78	else
79	79	len = cf->len;
80	80
81		− if (can_is_canfd_skb(skb)) {
82		− if (cf->can_id & CAN_EFF_FLAG)
83		− len += CANFD_FRAME_OVERHEAD_EFF;
84		− else
85		− len += CANFD_FRAME_OVERHEAD_SFF;
86		− } else {
87		− if (cf->can_id & CAN_EFF_FLAG)
88		− len += CAN_FRAME_OVERHEAD_EFF;
89		− else
90		− len += CAN_FRAME_OVERHEAD_SFF;
91		− }
92		−
93		− return len;
	81	+ return can_frame_bytes(can_is_canfd_skb(skb), cf->can_id & CAN_EFF_FLAG,
	82	+ false, len);
94	83	}
95	84	EXPORT_SYMBOL_GPL(can_skb_get_frame_len);

drivers/net/can/dev/rx-offload.c+1−1

@@ -220,7 +220,7 @@ int can_rx_offload_irq_offload_fifo(struct can_rx_offload *offload) · 219 unmodified lines
220	220	EXPORT_SYMBOL_GPL(can_rx_offload_irq_offload_fifo);
221	221
222	222	int can_rx_offload_queue_timestamp(struct can_rx_offload *offload,
223		− struct sk_buff *skb, u32 timestamp)
	223	+ struct sk_buff *skb, u32 timestamp)
224	224	{
225	225	struct can_rx_offload_cb *cb;
226	226

drivers/net/can/kvaser_pciefd.c+341−614

@@ -3,19 +3,19 @@ · 2 unmodified lines
3	3	* Parts of this driver are based on the following:
4	4	* - Kvaser linux pciefd driver (version 5.25)
5	5	* - PEAK linux canfd driver
6		− * - Altera Avalon EPCS flash controller driver
7	6	*/
8	7
9		−#include <linux/kernel.h>
10		−#include <linux/module.h>
	8	+#include <linux/bitfield.h>
	9	+#include <linux/can/dev.h>
11	10	#include <linux/device.h>
12	11	#include <linux/ethtool.h>
	12	+#include <linux/iopoll.h>
	13	+#include <linux/kernel.h>
	14	+#include <linux/minmax.h>
	15	+#include <linux/module.h>
	16	+#include <linux/netdevice.h>
13	17	#include <linux/pci.h>
14		−#include <linux/can/dev.h>
15	18	#include <linux/timer.h>
16		−#include <linux/netdevice.h>
17		−#include <linux/crc32.h>
18		−#include <linux/iopoll.h>
19	19
20	20	MODULE_LICENSE("Dual BSD/GPL");
21	21	MODULE_AUTHOR("Kvaser AB <support@kvaser.com>");
@@ -25,42 +25,25 @@ MODULE_DESCRIPTION("CAN driver for Kvaser CAN/PCIe devices"); · 3 unmodified lines
25	25
26	26	#define KVASER_PCIEFD_WAIT_TIMEOUT msecs_to_jiffies(1000)
27	27	#define KVASER_PCIEFD_BEC_POLL_FREQ (jiffies + msecs_to_jiffies(200))
28		−#define KVASER_PCIEFD_MAX_ERR_REP 256
29		−#define KVASER_PCIEFD_CAN_TX_MAX_COUNT 17
30		−#define KVASER_PCIEFD_MAX_CAN_CHANNELS 4
31		−#define KVASER_PCIEFD_DMA_COUNT 2
	28	+#define KVASER_PCIEFD_MAX_ERR_REP 256U
	29	+#define KVASER_PCIEFD_CAN_TX_MAX_COUNT 17U
	30	+#define KVASER_PCIEFD_MAX_CAN_CHANNELS 4UL
	31	+#define KVASER_PCIEFD_DMA_COUNT 2U
32	32
33		−#define KVASER_PCIEFD_DMA_SIZE (4 * 1024)
34		−#define KVASER_PCIEFD_64BIT_DMA_BIT BIT(0)
	33	+#define KVASER_PCIEFD_DMA_SIZE (4U * 1024U)
35	34
36	35	#define KVASER_PCIEFD_VENDOR 0x1a07
37		−#define KVASER_PCIEFD_4HS_ID 0x0d
38		−#define KVASER_PCIEFD_2HS_ID 0x0e
39		−#define KVASER_PCIEFD_HS_ID 0x0f
40		−#define KVASER_PCIEFD_MINIPCIE_HS_ID 0x10
41		−#define KVASER_PCIEFD_MINIPCIE_2HS_ID 0x11
	36	+#define KVASER_PCIEFD_4HS_DEVICE_ID 0x000d
	37	+#define KVASER_PCIEFD_2HS_V2_DEVICE_ID 0x000e
	38	+#define KVASER_PCIEFD_HS_V2_DEVICE_ID 0x000f
	39	+#define KVASER_PCIEFD_MINIPCIE_HS_V2_DEVICE_ID 0x0010
	40	+#define KVASER_PCIEFD_MINIPCIE_2HS_V2_DEVICE_ID 0x0011
42	41
43	42	/* PCIe IRQ registers */
44	43	#define KVASER_PCIEFD_IRQ_REG 0x40
45	44	#define KVASER_PCIEFD_IEN_REG 0x50
46		−/* DMA map */
	45	+/* DMA address translation map register base */
47	46	#define KVASER_PCIEFD_DMA_MAP_BASE 0x1000
48		−/* Kvaser KCAN CAN controller registers */
49		−#define KVASER_PCIEFD_KCAN0_BASE 0x10000
50		−#define KVASER_PCIEFD_KCAN_BASE_OFFSET 0x1000
51		−#define KVASER_PCIEFD_KCAN_FIFO_REG 0x100
52		−#define KVASER_PCIEFD_KCAN_FIFO_LAST_REG 0x180
53		−#define KVASER_PCIEFD_KCAN_CTRL_REG 0x2c0
54		−#define KVASER_PCIEFD_KCAN_CMD_REG 0x400
55		−#define KVASER_PCIEFD_KCAN_IEN_REG 0x408
56		−#define KVASER_PCIEFD_KCAN_IRQ_REG 0x410
57		−#define KVASER_PCIEFD_KCAN_TX_NPACKETS_REG 0x414
58		−#define KVASER_PCIEFD_KCAN_STAT_REG 0x418
59		−#define KVASER_PCIEFD_KCAN_MODE_REG 0x41c
60		−#define KVASER_PCIEFD_KCAN_BTRN_REG 0x420
61		−#define KVASER_PCIEFD_KCAN_BUS_LOAD_REG 0x424
62		−#define KVASER_PCIEFD_KCAN_BTRD_REG 0x428
63		−#define KVASER_PCIEFD_KCAN_PWM_REG 0x430
64	47	/* Loopback control register */
65	48	#define KVASER_PCIEFD_LOOP_REG 0x1f000
66	49	/* System identification and information registers */
@@ -78,183 +61,196 @@ MODULE_DESCRIPTION("CAN driver for Kvaser CAN/PCIe devices"); · 11 unmodified lines
78	61	#define KVASER_PCIEFD_SRB_STAT_REG (KVASER_PCIEFD_SRB_BASE + 0x210)
79	62	#define KVASER_PCIEFD_SRB_RX_NR_PACKETS_REG (KVASER_PCIEFD_SRB_BASE + 0x214)
80	63	#define KVASER_PCIEFD_SRB_CTRL_REG (KVASER_PCIEFD_SRB_BASE + 0x218)
81		−/* EPCS flash controller registers */
82		−#define KVASER_PCIEFD_SPI_BASE 0x1fc00
83		−#define KVASER_PCIEFD_SPI_RX_REG KVASER_PCIEFD_SPI_BASE
84		−#define KVASER_PCIEFD_SPI_TX_REG (KVASER_PCIEFD_SPI_BASE + 0x4)
85		−#define KVASER_PCIEFD_SPI_STATUS_REG (KVASER_PCIEFD_SPI_BASE + 0x8)
86		−#define KVASER_PCIEFD_SPI_CTRL_REG (KVASER_PCIEFD_SPI_BASE + 0xc)
87		−#define KVASER_PCIEFD_SPI_SSEL_REG (KVASER_PCIEFD_SPI_BASE + 0x14)
88		−
89		−#define KVASER_PCIEFD_IRQ_ALL_MSK 0x1f
	64	+/* Kvaser KCAN CAN controller registers */
	65	+#define KVASER_PCIEFD_KCAN0_BASE 0x10000
	66	+#define KVASER_PCIEFD_KCAN_BASE_OFFSET 0x1000
	67	+#define KVASER_PCIEFD_KCAN_FIFO_REG 0x100
	68	+#define KVASER_PCIEFD_KCAN_FIFO_LAST_REG 0x180
	69	+#define KVASER_PCIEFD_KCAN_CTRL_REG 0x2c0
	70	+#define KVASER_PCIEFD_KCAN_CMD_REG 0x400
	71	+#define KVASER_PCIEFD_KCAN_IEN_REG 0x408
	72	+#define KVASER_PCIEFD_KCAN_IRQ_REG 0x410
	73	+#define KVASER_PCIEFD_KCAN_TX_NR_PACKETS_REG 0x414
	74	+#define KVASER_PCIEFD_KCAN_STAT_REG 0x418
	75	+#define KVASER_PCIEFD_KCAN_MODE_REG 0x41c
	76	+#define KVASER_PCIEFD_KCAN_BTRN_REG 0x420
	77	+#define KVASER_PCIEFD_KCAN_BUS_LOAD_REG 0x424
	78	+#define KVASER_PCIEFD_KCAN_BTRD_REG 0x428
	79	+#define KVASER_PCIEFD_KCAN_PWM_REG 0x430
	80	+
	81	+/* PCI interrupt fields */
90	82	#define KVASER_PCIEFD_IRQ_SRB BIT(4)
	83	+#define KVASER_PCIEFD_IRQ_ALL_MASK GENMASK(4, 0)
91	84
92		−#define KVASER_PCIEFD_SYSID_NRCHAN_SHIFT 24
93		−#define KVASER_PCIEFD_SYSID_MAJOR_VER_SHIFT 16
94		−#define KVASER_PCIEFD_SYSID_BUILD_VER_SHIFT 1
	85	+/* Enable 64-bit DMA address translation */
	86	+#define KVASER_PCIEFD_64BIT_DMA_BIT BIT(0)
	87	+
	88	+/* System build information fields */
	89	+#define KVASER_PCIEFD_SYSID_VERSION_NR_CHAN_MASK GENMASK(31, 24)
	90	+#define KVASER_PCIEFD_SYSID_VERSION_MAJOR_MASK GENMASK(23, 16)
	91	+#define KVASER_PCIEFD_SYSID_VERSION_MINOR_MASK GENMASK(7, 0)
	92	+#define KVASER_PCIEFD_SYSID_BUILD_SEQ_MASK GENMASK(15, 1)
95	93
96	94	/* Reset DMA buffer 0, 1 and FIFO offset */
97		−#define KVASER_PCIEFD_SRB_CMD_RDB0 BIT(4)
98	95	#define KVASER_PCIEFD_SRB_CMD_RDB1 BIT(5)
	96	+#define KVASER_PCIEFD_SRB_CMD_RDB0 BIT(4)
99	97	#define KVASER_PCIEFD_SRB_CMD_FOR BIT(0)
100	98
101		−/* DMA packet done, buffer 0 and 1 */
102		−#define KVASER_PCIEFD_SRB_IRQ_DPD0 BIT(8)
103		−#define KVASER_PCIEFD_SRB_IRQ_DPD1 BIT(9)
104		−/* DMA overflow, buffer 0 and 1 */
105		−#define KVASER_PCIEFD_SRB_IRQ_DOF0 BIT(10)
106		−#define KVASER_PCIEFD_SRB_IRQ_DOF1 BIT(11)
107	99	/* DMA underflow, buffer 0 and 1 */
108		−#define KVASER_PCIEFD_SRB_IRQ_DUF0 BIT(12)
109	100	#define KVASER_PCIEFD_SRB_IRQ_DUF1 BIT(13)
	101	+#define KVASER_PCIEFD_SRB_IRQ_DUF0 BIT(12)
	102	+/* DMA overflow, buffer 0 and 1 */
	103	+#define KVASER_PCIEFD_SRB_IRQ_DOF1 BIT(11)
	104	+#define KVASER_PCIEFD_SRB_IRQ_DOF0 BIT(10)
	105	+/* DMA packet done, buffer 0 and 1 */
	106	+#define KVASER_PCIEFD_SRB_IRQ_DPD1 BIT(9)
	107	+#define KVASER_PCIEFD_SRB_IRQ_DPD0 BIT(8)
110	108
	109	+/* Got DMA support */
	110	+#define KVASER_PCIEFD_SRB_STAT_DMA BIT(24)
111	111	/* DMA idle */
112	112	#define KVASER_PCIEFD_SRB_STAT_DI BIT(15)
113		−/* DMA support */
114		−#define KVASER_PCIEFD_SRB_STAT_DMA BIT(24)
115	113
116	114	/* SRB current packet level */
117		−#define KVASER_PCIEFD_SRB_RX_NR_PACKETS_MASK 0xff
	115	+#define KVASER_PCIEFD_SRB_RX_NR_PACKETS_MASK GENMASK(7, 0)
118	116
119	117	/* DMA Enable */
120	118	#define KVASER_PCIEFD_SRB_CTRL_DMA_ENABLE BIT(0)
121	119
122		−/* EPCS flash controller definitions */
123		−#define KVASER_PCIEFD_CFG_IMG_SZ (64 * 1024)
124		−#define KVASER_PCIEFD_CFG_IMG_OFFSET (31 * 65536L)
125		−#define KVASER_PCIEFD_CFG_MAX_PARAMS 256
126		−#define KVASER_PCIEFD_CFG_MAGIC 0xcafef00d
127		−#define KVASER_PCIEFD_CFG_PARAM_MAX_SZ 24
128		−#define KVASER_PCIEFD_CFG_SYS_VER 1
129		−#define KVASER_PCIEFD_CFG_PARAM_NR_CHAN 130
130		−#define KVASER_PCIEFD_SPI_TMT BIT(5)
131		−#define KVASER_PCIEFD_SPI_TRDY BIT(6)
132		−#define KVASER_PCIEFD_SPI_RRDY BIT(7)
133		−#define KVASER_PCIEFD_FLASH_ID_EPCS16 0x14
134		−/* Commands for controlling the onboard flash */
135		−#define KVASER_PCIEFD_FLASH_RES_CMD 0xab
136		−#define KVASER_PCIEFD_FLASH_READ_CMD 0x3
137		−#define KVASER_PCIEFD_FLASH_STATUS_CMD 0x5
138		−
139		−/* Kvaser KCAN definitions */
140		−#define KVASER_PCIEFD_KCAN_CTRL_EFLUSH (4 << 29)
141		−#define KVASER_PCIEFD_KCAN_CTRL_EFRAME (5 << 29)
142		−
143		−#define KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT 16
144		−/* Request status packet */
145		−#define KVASER_PCIEFD_KCAN_CMD_SRQ BIT(0)
	120	+/* KCAN CTRL packet types */
	121	+#define KVASER_PCIEFD_KCAN_CTRL_TYPE_MASK GENMASK(31, 29)
	122	+#define KVASER_PCIEFD_KCAN_CTRL_TYPE_EFLUSH 0x4
	123	+#define KVASER_PCIEFD_KCAN_CTRL_TYPE_EFRAME 0x5
	124	+
	125	+/* Command sequence number */
	126	+#define KVASER_PCIEFD_KCAN_CMD_SEQ_MASK GENMASK(23, 16)
	127	+/* Command bits */
	128	+#define KVASER_PCIEFD_KCAN_CMD_MASK GENMASK(5, 0)
146	129	/* Abort, flush and reset */
147	130	#define KVASER_PCIEFD_KCAN_CMD_AT BIT(1)
	131	+/* Request status packet */
	132	+#define KVASER_PCIEFD_KCAN_CMD_SRQ BIT(0)
148	133
149		−/* Tx FIFO unaligned read */
150		−#define KVASER_PCIEFD_KCAN_IRQ_TAR BIT(0)
151		−/* Tx FIFO unaligned end */
152		−#define KVASER_PCIEFD_KCAN_IRQ_TAE BIT(1)
153		−/* Bus parameter protection error */
154		−#define KVASER_PCIEFD_KCAN_IRQ_BPP BIT(2)
155		−/* FDF bit when controller is in classic mode */
156		−#define KVASER_PCIEFD_KCAN_IRQ_FDIC BIT(3)
157		−/* Rx FIFO overflow */
158		−#define KVASER_PCIEFD_KCAN_IRQ_ROF BIT(5)
159		−/* Abort done */
160		−#define KVASER_PCIEFD_KCAN_IRQ_ABD BIT(13)
161		−/* Tx buffer flush done */
162		−#define KVASER_PCIEFD_KCAN_IRQ_TFD BIT(14)
163		−/* Tx FIFO overflow */
164		−#define KVASER_PCIEFD_KCAN_IRQ_TOF BIT(15)
165		−/* Tx FIFO empty */
166		−#define KVASER_PCIEFD_KCAN_IRQ_TE BIT(16)
167	134	/* Transmitter unaligned */
168	135	#define KVASER_PCIEFD_KCAN_IRQ_TAL BIT(17)
	136	+/* Tx FIFO empty */
	137	+#define KVASER_PCIEFD_KCAN_IRQ_TE BIT(16)
	138	+/* Tx FIFO overflow */
	139	+#define KVASER_PCIEFD_KCAN_IRQ_TOF BIT(15)
	140	+/* Tx buffer flush done */
	141	+#define KVASER_PCIEFD_KCAN_IRQ_TFD BIT(14)
	142	+/* Abort done */
	143	+#define KVASER_PCIEFD_KCAN_IRQ_ABD BIT(13)
	144	+/* Rx FIFO overflow */
	145	+#define KVASER_PCIEFD_KCAN_IRQ_ROF BIT(5)
	146	+/* FDF bit when controller is in classic CAN mode */
	147	+#define KVASER_PCIEFD_KCAN_IRQ_FDIC BIT(3)
	148	+/* Bus parameter protection error */
	149	+#define KVASER_PCIEFD_KCAN_IRQ_BPP BIT(2)
	150	+/* Tx FIFO unaligned end */
	151	+#define KVASER_PCIEFD_KCAN_IRQ_TAE BIT(1)
	152	+/* Tx FIFO unaligned read */
	153	+#define KVASER_PCIEFD_KCAN_IRQ_TAR BIT(0)
169	154
170		−#define KVASER_PCIEFD_KCAN_TX_NPACKETS_MAX_SHIFT 16
	155	+/* Tx FIFO size */
	156	+#define KVASER_PCIEFD_KCAN_TX_NR_PACKETS_MAX_MASK GENMASK(23, 16)
	157	+/* Tx FIFO current packet level */
	158	+#define KVASER_PCIEFD_KCAN_TX_NR_PACKETS_CURRENT_MASK GENMASK(7, 0)
171	159
172		−#define KVASER_PCIEFD_KCAN_STAT_SEQNO_SHIFT 24
173		−/* Abort request */
174		−#define KVASER_PCIEFD_KCAN_STAT_AR BIT(7)
175		−/* Idle state. Controller in reset mode and no abort or flush pending */
176		−#define KVASER_PCIEFD_KCAN_STAT_IDLE BIT(10)
177		−/* Bus off */
178		−#define KVASER_PCIEFD_KCAN_STAT_BOFF BIT(11)
179		−/* Reset mode request */
180		−#define KVASER_PCIEFD_KCAN_STAT_RMR BIT(14)
181		−/* Controller in reset mode */
182		−#define KVASER_PCIEFD_KCAN_STAT_IRM BIT(15)
183		−/* Controller got one-shot capability */
184		−#define KVASER_PCIEFD_KCAN_STAT_CAP BIT(16)
	160	+/* Current status packet sequence number */
	161	+#define KVASER_PCIEFD_KCAN_STAT_SEQNO_MASK GENMASK(31, 24)
185	162	/* Controller got CAN FD capability */
186	163	#define KVASER_PCIEFD_KCAN_STAT_FD BIT(19)
187		−#define KVASER_PCIEFD_KCAN_STAT_BUS_OFF_MSK (KVASER_PCIEFD_KCAN_STAT_AR \| \
188		− KVASER_PCIEFD_KCAN_STAT_BOFF \| KVASER_PCIEFD_KCAN_STAT_RMR \| \
189		− KVASER_PCIEFD_KCAN_STAT_IRM)
	164	+/* Controller got one-shot capability */
	165	+#define KVASER_PCIEFD_KCAN_STAT_CAP BIT(16)
	166	+/* Controller in reset mode */
	167	+#define KVASER_PCIEFD_KCAN_STAT_IRM BIT(15)
	168	+/* Reset mode request */
	169	+#define KVASER_PCIEFD_KCAN_STAT_RMR BIT(14)
	170	+/* Bus off */
	171	+#define KVASER_PCIEFD_KCAN_STAT_BOFF BIT(11)
	172	+/* Idle state. Controller in reset mode and no abort or flush pending */
	173	+#define KVASER_PCIEFD_KCAN_STAT_IDLE BIT(10)
	174	+/* Abort request */
	175	+#define KVASER_PCIEFD_KCAN_STAT_AR BIT(7)
	176	+/* Controller is bus off */
	177	+#define KVASER_PCIEFD_KCAN_STAT_BUS_OFF_MASK \
	178	+ (KVASER_PCIEFD_KCAN_STAT_AR \| KVASER_PCIEFD_KCAN_STAT_BOFF \| \
	179	+ KVASER_PCIEFD_KCAN_STAT_RMR \| KVASER_PCIEFD_KCAN_STAT_IRM)
190	180
191		−/* Reset mode */
192		−#define KVASER_PCIEFD_KCAN_MODE_RM BIT(8)
193		−/* Listen only mode */
194		−#define KVASER_PCIEFD_KCAN_MODE_LOM BIT(9)
195		−/* Error packet enable */
196		−#define KVASER_PCIEFD_KCAN_MODE_EPEN BIT(12)
197		−/* CAN FD non-ISO */
198		−#define KVASER_PCIEFD_KCAN_MODE_NIFDEN BIT(15)
199		−/* Acknowledgment packet type */
200		−#define KVASER_PCIEFD_KCAN_MODE_APT BIT(20)
201		−/* Active error flag enable. Clear to force error passive */
202		−#define KVASER_PCIEFD_KCAN_MODE_EEN BIT(23)
203	181	/* Classic CAN mode */
204	182	#define KVASER_PCIEFD_KCAN_MODE_CCM BIT(31)
	183	+/* Active error flag enable. Clear to force error passive */
	184	+#define KVASER_PCIEFD_KCAN_MODE_EEN BIT(23)
	185	+/* Acknowledgment packet type */
	186	+#define KVASER_PCIEFD_KCAN_MODE_APT BIT(20)
	187	+/* CAN FD non-ISO */
	188	+#define KVASER_PCIEFD_KCAN_MODE_NIFDEN BIT(15)
	189	+/* Error packet enable */
	190	+#define KVASER_PCIEFD_KCAN_MODE_EPEN BIT(12)
	191	+/* Listen only mode */
	192	+#define KVASER_PCIEFD_KCAN_MODE_LOM BIT(9)
	193	+/* Reset mode */
	194	+#define KVASER_PCIEFD_KCAN_MODE_RM BIT(8)
205	195
206		−#define KVASER_PCIEFD_KCAN_BTRN_SJW_SHIFT 13
207		−#define KVASER_PCIEFD_KCAN_BTRN_TSEG1_SHIFT 17
208		−#define KVASER_PCIEFD_KCAN_BTRN_TSEG2_SHIFT 26
209		−
210		−#define KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT 16
211		−
212		−/* Kvaser KCAN packet types */
213		−#define KVASER_PCIEFD_PACK_TYPE_DATA 0
214		−#define KVASER_PCIEFD_PACK_TYPE_ACK 1
215		−#define KVASER_PCIEFD_PACK_TYPE_TXRQ 2
216		−#define KVASER_PCIEFD_PACK_TYPE_ERROR 3
217		−#define KVASER_PCIEFD_PACK_TYPE_EFLUSH_ACK 4
218		−#define KVASER_PCIEFD_PACK_TYPE_EFRAME_ACK 5
219		−#define KVASER_PCIEFD_PACK_TYPE_ACK_DATA 6
220		−#define KVASER_PCIEFD_PACK_TYPE_STATUS 8
221		−#define KVASER_PCIEFD_PACK_TYPE_BUS_LOAD 9
222		−
223		−/* Kvaser KCAN packet common definitions */
224		−#define KVASER_PCIEFD_PACKET_SEQ_MSK 0xff
225		−#define KVASER_PCIEFD_PACKET_CHID_SHIFT 25
226		−#define KVASER_PCIEFD_PACKET_TYPE_SHIFT 28
227		−
228		−/* Kvaser KCAN TDATA and RDATA first word */
	196	+/* BTRN and BTRD fields */
	197	+#define KVASER_PCIEFD_KCAN_BTRN_TSEG2_MASK GENMASK(30, 26)
	198	+#define KVASER_PCIEFD_KCAN_BTRN_TSEG1_MASK GENMASK(25, 17)
	199	+#define KVASER_PCIEFD_KCAN_BTRN_SJW_MASK GENMASK(16, 13)
	200	+#define KVASER_PCIEFD_KCAN_BTRN_BRP_MASK GENMASK(12, 0)
	201	+
	202	+/* PWM Control fields */
	203	+#define KVASER_PCIEFD_KCAN_PWM_TOP_MASK GENMASK(23, 16)
	204	+#define KVASER_PCIEFD_KCAN_PWM_TRIGGER_MASK GENMASK(7, 0)
	205	+
	206	+/* KCAN packet type IDs */
	207	+#define KVASER_PCIEFD_PACK_TYPE_DATA 0x0
	208	+#define KVASER_PCIEFD_PACK_TYPE_ACK 0x1
	209	+#define KVASER_PCIEFD_PACK_TYPE_TXRQ 0x2
	210	+#define KVASER_PCIEFD_PACK_TYPE_ERROR 0x3
	211	+#define KVASER_PCIEFD_PACK_TYPE_EFLUSH_ACK 0x4
	212	+#define KVASER_PCIEFD_PACK_TYPE_EFRAME_ACK 0x5
	213	+#define KVASER_PCIEFD_PACK_TYPE_ACK_DATA 0x6
	214	+#define KVASER_PCIEFD_PACK_TYPE_STATUS 0x8
	215	+#define KVASER_PCIEFD_PACK_TYPE_BUS_LOAD 0x9
	216	+
	217	+/* Common KCAN packet definitions, second word */
	218	+#define KVASER_PCIEFD_PACKET_TYPE_MASK GENMASK(31, 28)
	219	+#define KVASER_PCIEFD_PACKET_CHID_MASK GENMASK(27, 25)
	220	+#define KVASER_PCIEFD_PACKET_SEQ_MASK GENMASK(7, 0)
	221	+
	222	+/* KCAN Transmit/Receive data packet, first word */
229	223	#define KVASER_PCIEFD_RPACKET_IDE BIT(30)
230	224	#define KVASER_PCIEFD_RPACKET_RTR BIT(29)
231		−/* Kvaser KCAN TDATA and RDATA second word */
232		−#define KVASER_PCIEFD_RPACKET_ESI BIT(13)
233		−#define KVASER_PCIEFD_RPACKET_BRS BIT(14)
234		−#define KVASER_PCIEFD_RPACKET_FDF BIT(15)
235		−#define KVASER_PCIEFD_RPACKET_DLC_SHIFT 8
236		−/* Kvaser KCAN TDATA second word */
237		−#define KVASER_PCIEFD_TPACKET_SMS BIT(16)
	225	+#define KVASER_PCIEFD_RPACKET_ID_MASK GENMASK(28, 0)
	226	+/* KCAN Transmit data packet, second word */
238	227	#define KVASER_PCIEFD_TPACKET_AREQ BIT(31)
	228	+#define KVASER_PCIEFD_TPACKET_SMS BIT(16)
	229	+/* KCAN Transmit/Receive data packet, second word */
	230	+#define KVASER_PCIEFD_RPACKET_FDF BIT(15)
	231	+#define KVASER_PCIEFD_RPACKET_BRS BIT(14)
	232	+#define KVASER_PCIEFD_RPACKET_ESI BIT(13)
	233	+#define KVASER_PCIEFD_RPACKET_DLC_MASK GENMASK(11, 8)
239	234
240		−/* Kvaser KCAN APACKET */
241		−#define KVASER_PCIEFD_APACKET_FLU BIT(8)
242		−#define KVASER_PCIEFD_APACKET_CT BIT(9)
243		−#define KVASER_PCIEFD_APACKET_ABL BIT(10)
	235	+/* KCAN Transmit acknowledge packet, first word */
244	236	#define KVASER_PCIEFD_APACKET_NACK BIT(11)
	237	+#define KVASER_PCIEFD_APACKET_ABL BIT(10)
	238	+#define KVASER_PCIEFD_APACKET_CT BIT(9)
	239	+#define KVASER_PCIEFD_APACKET_FLU BIT(8)
245	240
246		−/* Kvaser KCAN SPACK first word */
247		−#define KVASER_PCIEFD_SPACK_RXERR_SHIFT 8
248		−#define KVASER_PCIEFD_SPACK_BOFF BIT(16)
249		−#define KVASER_PCIEFD_SPACK_IDET BIT(20)
250		−#define KVASER_PCIEFD_SPACK_IRM BIT(21)
	241	+/* KCAN Status packet, first word */
251	242	#define KVASER_PCIEFD_SPACK_RMCD BIT(22)
252		−/* Kvaser KCAN SPACK second word */
253		−#define KVASER_PCIEFD_SPACK_AUTO BIT(21)
254		−#define KVASER_PCIEFD_SPACK_EWLR BIT(23)
	243	+#define KVASER_PCIEFD_SPACK_IRM BIT(21)
	244	+#define KVASER_PCIEFD_SPACK_IDET BIT(20)
	245	+#define KVASER_PCIEFD_SPACK_BOFF BIT(16)
	246	+#define KVASER_PCIEFD_SPACK_RXERR_MASK GENMASK(15, 8)
	247	+#define KVASER_PCIEFD_SPACK_TXERR_MASK GENMASK(7, 0)
	248	+/* KCAN Status packet, second word */
255	249	#define KVASER_PCIEFD_SPACK_EPLR BIT(24)
	250	+#define KVASER_PCIEFD_SPACK_EWLR BIT(23)
	251	+#define KVASER_PCIEFD_SPACK_AUTO BIT(21)
256	252
257		−/* Kvaser KCAN_EPACK second word */
	253	+/* KCAN Error detected packet, second word */
258	254	#define KVASER_PCIEFD_EPACK_DIR_TX BIT(0)
259	255
260	256	struct kvaser_pciefd;
@@ -306,195 +302,43 @@ static const struct can_bittiming_const kvaser_pciefd_bittiming_const = { · 45 unmodified lines
306	302	.brp_inc = 1,
307	303	};
308	304
309		−struct kvaser_pciefd_cfg_param {
310		− __le32 magic;
311		− __le32 nr;
312		− __le32 len;
313		− u8 data[KVASER_PCIEFD_CFG_PARAM_MAX_SZ];
314		−};
315		−
316		−struct kvaser_pciefd_cfg_img {
317		− __le32 version;
318		− __le32 magic;
319		− __le32 crc;
320		− struct kvaser_pciefd_cfg_param params[KVASER_PCIEFD_CFG_MAX_PARAMS];
321		−};
322		−
323	305	static struct pci_device_id kvaser_pciefd_id_table[] = {
324		− { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_4HS_ID), },
325		− { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_2HS_ID), },
326		− { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_HS_ID), },
327		− { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_MINIPCIE_HS_ID), },
328		− { PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_MINIPCIE_2HS_ID), },
329		− { 0,},
	306	+ {
	307	+ PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_4HS_DEVICE_ID),
	308	+ },
	309	+ {
	310	+ PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_2HS_V2_DEVICE_ID),
	311	+ },
	312	+ {
	313	+ PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_HS_V2_DEVICE_ID),
	314	+ },
	315	+ {
	316	+ PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_MINIPCIE_HS_V2_DEVICE_ID),
	317	+ },
	318	+ {
	319	+ PCI_DEVICE(KVASER_PCIEFD_VENDOR, KVASER_PCIEFD_MINIPCIE_2HS_V2_DEVICE_ID),
	320	+ },
	321	+ {
	322	+ 0,
	323	+ },
330	324	};
331	325	MODULE_DEVICE_TABLE(pci, kvaser_pciefd_id_table);
332	326
333		−/* Onboard flash memory functions */
334		−static int kvaser_pciefd_spi_wait_loop(struct kvaser_pciefd *pcie, int msk)
335		−{
336		− u32 res;
337		−
338		− return readl_poll_timeout(pcie->reg_base + KVASER_PCIEFD_SPI_STATUS_REG,
339		− res, res & msk, 0, 10);
340		−}
341		−
342		−static int kvaser_pciefd_spi_cmd(struct kvaser_pciefd pcie, const u8 tx,
343		− u32 tx_len, u8 *rx, u32 rx_len)
344		−{
345		− int c;
346		−
347		− iowrite32(BIT(0), pcie->reg_base + KVASER_PCIEFD_SPI_SSEL_REG);
348		− iowrite32(BIT(10), pcie->reg_base + KVASER_PCIEFD_SPI_CTRL_REG);
349		− ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG);
350		−
351		− c = tx_len;
352		− while (c--) {
353		− if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_TRDY))
354		− return -EIO;
355		−
356		− iowrite32(*tx++, pcie->reg_base + KVASER_PCIEFD_SPI_TX_REG);
357		−
358		− if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_RRDY))
359		− return -EIO;
360		−
361		− ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG);
362		− }
363		−
364		− c = rx_len;
365		− while (c-- > 0) {
366		− if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_TRDY))
367		− return -EIO;
368		−
369		− iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SPI_TX_REG);
370		−
371		− if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_RRDY))
372		− return -EIO;
373		−
374		− *rx++ = ioread32(pcie->reg_base + KVASER_PCIEFD_SPI_RX_REG);
375		− }
376		−
377		− if (kvaser_pciefd_spi_wait_loop(pcie, KVASER_PCIEFD_SPI_TMT))
378		− return -EIO;
379		−
380		− iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SPI_CTRL_REG);
381		−
382		− if (c != -1) {
383		− dev_err(&pcie->pci->dev, "Flash SPI transfer failed\n");
384		− return -EIO;
385		− }
386		−
387		− return 0;
388		−}
389		−
390		−static int kvaser_pciefd_cfg_read_and_verify(struct kvaser_pciefd *pcie,
391		− struct kvaser_pciefd_cfg_img *img)
392		−{
393		− int offset = KVASER_PCIEFD_CFG_IMG_OFFSET;
394		− int res, crc;
395		− u8 *crc_buff;
396		−
397		− u8 cmd[] = {
398		− KVASER_PCIEFD_FLASH_READ_CMD,
399		− (u8)((offset >> 16) & 0xff),
400		− (u8)((offset >> 8) & 0xff),
401		− (u8)(offset & 0xff)
402		− };
403		−
404		− res = kvaser_pciefd_spi_cmd(pcie, cmd, ARRAY_SIZE(cmd), (u8 *)img,
405		− KVASER_PCIEFD_CFG_IMG_SZ);
406		− if (res)
407		− return res;
408		−
409		− crc_buff = (u8 *)img->params;
410		−
411		− if (le32_to_cpu(img->version) != KVASER_PCIEFD_CFG_SYS_VER) {
412		− dev_err(&pcie->pci->dev,
413		− "Config flash corrupted, version number is wrong\n");
414		− return -ENODEV;
415		− }
416		−
417		− if (le32_to_cpu(img->magic) != KVASER_PCIEFD_CFG_MAGIC) {
418		− dev_err(&pcie->pci->dev,
419		− "Config flash corrupted, magic number is wrong\n");
420		− return -ENODEV;
421		− }
422		−
423		− crc = ~crc32_be(0xffffffff, crc_buff, sizeof(img->params));
424		− if (le32_to_cpu(img->crc) != crc) {
425		− dev_err(&pcie->pci->dev,
426		− "Stored CRC does not match flash image contents\n");
427		− return -EIO;
428		− }
429		−
430		− return 0;
431		−}
432		−
433		−static void kvaser_pciefd_cfg_read_params(struct kvaser_pciefd *pcie,
434		− struct kvaser_pciefd_cfg_img *img)
	327	+static inline void kvaser_pciefd_send_kcan_cmd(struct kvaser_pciefd_can *can, u32 cmd)
435	328	{
436		− struct kvaser_pciefd_cfg_param *param;
437		−
438		− param = &img->params[KVASER_PCIEFD_CFG_PARAM_NR_CHAN];
439		− memcpy(&pcie->nr_channels, param->data, le32_to_cpu(param->len));
	329	+ iowrite32(FIELD_PREP(KVASER_PCIEFD_KCAN_CMD_MASK, cmd) \|
	330	+ FIELD_PREP(KVASER_PCIEFD_KCAN_CMD_SEQ_MASK, ++can->cmd_seq),
	331	+ can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG);
440	332	}
441	333
442		−static int kvaser_pciefd_read_cfg(struct kvaser_pciefd *pcie)
	334	+static inline void kvaser_pciefd_request_status(struct kvaser_pciefd_can *can)
443	335	{
444		− int res;
445		− struct kvaser_pciefd_cfg_img *img;
446		−
447		− /* Read electronic signature */
448		− u8 cmd[] = {KVASER_PCIEFD_FLASH_RES_CMD, 0, 0, 0};
449		−
450		− res = kvaser_pciefd_spi_cmd(pcie, cmd, ARRAY_SIZE(cmd), cmd, 1);
451		− if (res)
452		− return -EIO;
453		−
454		− img = kmalloc(KVASER_PCIEFD_CFG_IMG_SZ, GFP_KERNEL);
455		− if (!img)
456		− return -ENOMEM;
457		−
458		− if (cmd[0] != KVASER_PCIEFD_FLASH_ID_EPCS16) {
459		− dev_err(&pcie->pci->dev,
460		− "Flash id is 0x%x instead of expected EPCS16 (0x%x)\n",
461		− cmd[0], KVASER_PCIEFD_FLASH_ID_EPCS16);
462		−
463		− res = -ENODEV;
464		− goto image_free;
465		− }
466		−
467		− cmd[0] = KVASER_PCIEFD_FLASH_STATUS_CMD;
468		− res = kvaser_pciefd_spi_cmd(pcie, cmd, 1, cmd, 1);
469		− if (res) {
470		− goto image_free;
471		− } else if (cmd[0] & 1) {
472		− res = -EIO;
473		− /* No write is ever done, the WIP should never be set */
474		− dev_err(&pcie->pci->dev, "Unexpected WIP bit set in flash\n");
475		− goto image_free;
476		− }
477		−
478		− res = kvaser_pciefd_cfg_read_and_verify(pcie, img);
479		− if (res) {
480		− res = -EIO;
481		− goto image_free;
482		− }
483		−
484		− kvaser_pciefd_cfg_read_params(pcie, img);
485		−
486		−image_free:
487		− kfree(img);
488		− return res;
	336	+ kvaser_pciefd_send_kcan_cmd(can, KVASER_PCIEFD_KCAN_CMD_SRQ);
489	337	}
490	338
491		−static void kvaser_pciefd_request_status(struct kvaser_pciefd_can *can)
	339	+static inline void kvaser_pciefd_abort_flush_reset(struct kvaser_pciefd_can *can)
492	340	{
493		− u32 cmd;
494		−
495		− cmd = KVASER_PCIEFD_KCAN_CMD_SRQ;
496		− cmd \|= ++can->cmd_seq << KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT;
497		− iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG);
	341	+ kvaser_pciefd_send_kcan_cmd(can, KVASER_PCIEFD_KCAN_CMD_AT);
498	342	}
499	343
500	344	static void kvaser_pciefd_enable_err_gen(struct kvaser_pciefd_can *can)
@@ -523,7 +367,7 @@ static void kvaser_pciefd_disable_err_gen(struct kvaser_pciefd_can *can) · 22 unmodified lines
523	367	spin_unlock_irqrestore(&can->lock, irq);
524	368	}
525	369
526		−static int kvaser_pciefd_set_tx_irq(struct kvaser_pciefd_can *can)
	370	+static void kvaser_pciefd_set_tx_irq(struct kvaser_pciefd_can *can)
527	371	{
528	372	u32 msk;
529	373
@@ -534,8 +378,13 @@ static int kvaser_pciefd_set_tx_irq(struct kvaser_pciefd_can *can) · 4 unmodified lines
534	378	KVASER_PCIEFD_KCAN_IRQ_TAR;
535	379
536	380	iowrite32(msk, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
	381	+}
537	382
538		− return 0;
	383	+static inline void kvaser_pciefd_set_skb_timestamp(const struct kvaser_pciefd *pcie,
	384	+ struct sk_buff *skb, u64 timestamp)
	385	+{
	386	+ skb_hwtstamps(skb)->hwtstamp =
	387	+ ns_to_ktime(div_u64(timestamp * 1000, pcie->freq_to_ticks_div));
539	388	}
540	389
541	390	static void kvaser_pciefd_setup_controller(struct kvaser_pciefd_can *can)
@@ -544,7 +393,6 @@ static void kvaser_pciefd_setup_controller(struct kvaser_pciefd_can *can) · 2 unmodified lines
544	393	unsigned long irq;
545	394
546	395	spin_lock_irqsave(&can->lock, irq);
547		−
548	396	mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
549	397	if (can->can.ctrlmode & CAN_CTRLMODE_FD) {
550	398	mode &= ~KVASER_PCIEFD_KCAN_MODE_CCM;
@@ -561,7 +409,6 @@ static void kvaser_pciefd_setup_controller(struct kvaser_pciefd_can *can) · 10 unmodified lines
561	409	mode \|= KVASER_PCIEFD_KCAN_MODE_LOM;
562	410	else
563	411	mode &= ~KVASER_PCIEFD_KCAN_MODE_LOM;
564		−
565	412	mode \|= KVASER_PCIEFD_KCAN_MODE_EEN;
566	413	mode \|= KVASER_PCIEFD_KCAN_MODE_EPEN;
567	414	/* Use ACK packet type */
@@ -578,18 +425,13 @@ static void kvaser_pciefd_start_controller_flush(struct kvaser_pciefd_can *can) · 10 unmodified lines
578	425	unsigned long irq;
579	426
580	427	spin_lock_irqsave(&can->lock, irq);
581		− iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
	428	+ iowrite32(GENMASK(31, 0), can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
582	429	iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD,
583	430	can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
584		−
585	431	status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);
586	432	if (status & KVASER_PCIEFD_KCAN_STAT_IDLE) {
587		− u32 cmd;
588		−
589	433	/* If controller is already idle, run abort, flush and reset */
590		− cmd = KVASER_PCIEFD_KCAN_CMD_AT;
591		− cmd \|= ++can->cmd_seq << KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT;
592		− iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG);
	434	+ kvaser_pciefd_abort_flush_reset(can);
593	435	} else if (!(status & KVASER_PCIEFD_KCAN_STAT_RMR)) {
594	436	u32 mode;
595	437
@@ -598,7 +440,6 @@ static void kvaser_pciefd_start_controller_flush(struct kvaser_pciefd_can *can) · 2 unmodified lines
598	440	mode \|= KVASER_PCIEFD_KCAN_MODE_RM;
599	441	iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
600	442	}
601		−
602	443	spin_unlock_irqrestore(&can->lock, irq);
603	444	}
604	445
@@ -608,7 +449,6 @@ static int kvaser_pciefd_bus_on(struct kvaser_pciefd_can *can) · 3 unmodified lines
608	449	unsigned long irq;
609	450
610	451	del_timer(&can->bec_poll_timer);
611		−
612	452	if (!completion_done(&can->flush_comp))
613	453	kvaser_pciefd_start_controller_flush(can);
614	454
@@ -620,11 +460,9 @@ static int kvaser_pciefd_bus_on(struct kvaser_pciefd_can *can) · 5 unmodified lines
620	460
621	461	spin_lock_irqsave(&can->lock, irq);
622	462	iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
623		− iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
624		−
	463	+ iowrite32(GENMASK(31, 0), can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
625	464	iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD,
626	465	can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
627		−
628	466	mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
629	467	mode &= ~KVASER_PCIEFD_KCAN_MODE_RM;
630	468	iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
@@ -637,11 +475,10 @@ static int kvaser_pciefd_bus_on(struct kvaser_pciefd_can *can) · 6 unmodified lines
637	475	}
638	476	/* Reset interrupt handling */
639	477	iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
640		− iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
	478	+ iowrite32(GENMASK(31, 0), can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
641	479
642	480	kvaser_pciefd_set_tx_irq(can);
643	481	kvaser_pciefd_setup_controller(can);
644		−
645	482	can->can.state = CAN_STATE_ERROR_ACTIVE;
646	483	netif_wake_queue(can->can.dev);
647	484	can->bec.txerr = 0;
@@ -659,10 +496,9 @@ static void kvaser_pciefd_pwm_stop(struct kvaser_pciefd_can *can) · 11 unmodified lines
659	496
660	497	spin_lock_irqsave(&can->lock, irq);
661	498	pwm_ctrl = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
662		− top = (pwm_ctrl >> KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT) & 0xff;
663		−
	499	+ top = FIELD_GET(KVASER_PCIEFD_KCAN_PWM_TOP_MASK, pwm_ctrl);
664	500	/* Set duty cycle to zero */
665		− pwm_ctrl \|= top;
	501	+ pwm_ctrl \|= FIELD_PREP(KVASER_PCIEFD_KCAN_PWM_TRIGGER_MASK, top);
666	502	iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
667	503	spin_unlock_irqrestore(&can->lock, irq);
668	504	}
@@ -675,18 +511,17 @@ static void kvaser_pciefd_pwm_start(struct kvaser_pciefd_can *can) · 6 unmodified lines
675	511
676	512	kvaser_pciefd_pwm_stop(can);
677	513	spin_lock_irqsave(&can->lock, irq);
678		−
679		− /* Set frequency to 500 KHz*/
	514	+ /* Set frequency to 500 KHz */
680	515	top = can->kv_pcie->bus_freq / (2 * 500000) - 1;
681	516
682		− pwm_ctrl = top & 0xff;
683		− pwm_ctrl \|= (top & 0xff) << KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT;
	517	+ pwm_ctrl = FIELD_PREP(KVASER_PCIEFD_KCAN_PWM_TRIGGER_MASK, top);
	518	+ pwm_ctrl \|= FIELD_PREP(KVASER_PCIEFD_KCAN_PWM_TOP_MASK, top);
684	519	iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
685	520
686	521	/* Set duty cycle to 95 */
687	522	trigger = (100 * top - 95 * (top + 1) + 50) / 100;
688		− pwm_ctrl = trigger & 0xff;
689		− pwm_ctrl \|= (top & 0xff) << KVASER_PCIEFD_KCAN_PWM_TOP_SHIFT;
	523	+ pwm_ctrl = FIELD_PREP(KVASER_PCIEFD_KCAN_PWM_TRIGGER_MASK, trigger);
	524	+ pwm_ctrl \|= FIELD_PREP(KVASER_PCIEFD_KCAN_PWM_TOP_MASK, top);
690	525	iowrite32(pwm_ctrl, can->reg_base + KVASER_PCIEFD_KCAN_PWM_REG);
691	526	spin_unlock_irqrestore(&can->lock, irq);
692	527	}
@@ -741,7 +576,6 @@ static int kvaser_pciefd_prepare_tx_packet(struct kvaser_pciefd_tx_packet *p, · 48 unmodified lines
741	576	int seq = can->echo_idx;
742	577
743	578	memset(p, 0, sizeof(*p));
744		−
745	579	if (can->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)
746	580	p->header[1] \|= KVASER_PCIEFD_TPACKET_SMS;
747	581
@@ -751,19 +585,24 @@ static int kvaser_pciefd_prepare_tx_packet(struct kvaser_pciefd_tx_packet *p, · 3 unmodified lines
751	585	if (cf->can_id & CAN_EFF_FLAG)
752	586	p->header[0] \|= KVASER_PCIEFD_RPACKET_IDE;
753	587
754		− p->header[0] \|= cf->can_id & CAN_EFF_MASK;
755		− p->header[1] \|= can_fd_len2dlc(cf->len) << KVASER_PCIEFD_RPACKET_DLC_SHIFT;
	588	+ p->header[0] \|= FIELD_PREP(KVASER_PCIEFD_RPACKET_ID_MASK, cf->can_id);
756	589	p->header[1] \|= KVASER_PCIEFD_TPACKET_AREQ;
757	590
758	591	if (can_is_canfd_skb(skb)) {
	592	+ p->header[1] \|= FIELD_PREP(KVASER_PCIEFD_RPACKET_DLC_MASK,
	593	+ can_fd_len2dlc(cf->len));
759	594	p->header[1] \|= KVASER_PCIEFD_RPACKET_FDF;
760	595	if (cf->flags & CANFD_BRS)
761	596	p->header[1] \|= KVASER_PCIEFD_RPACKET_BRS;
762	597	if (cf->flags & CANFD_ESI)
763	598	p->header[1] \|= KVASER_PCIEFD_RPACKET_ESI;
	599	+ } else {
	600	+ p->header[1] \|=
	601	+ FIELD_PREP(KVASER_PCIEFD_RPACKET_DLC_MASK,
	602	+ can_get_cc_dlc((struct can_frame *)cf, can->can.ctrlmode));
764	603	}
765	604
766		− p->header[1] \|= seq & KVASER_PCIEFD_PACKET_SEQ_MSK;
	605	+ p->header[1] \|= FIELD_PREP(KVASER_PCIEFD_PACKET_SEQ_MASK, seq);
767	606
768	607	packet_size = cf->len;
769	608	memcpy(p->data, cf->data, packet_size);
@@ -777,16 +616,15 @@ static netdev_tx_t kvaser_pciefd_start_xmit(struct sk_buff *skb, · 7 unmodified lines
777	616	struct kvaser_pciefd_can *can = netdev_priv(netdev);
778	617	unsigned long irq_flags;
779	618	struct kvaser_pciefd_tx_packet packet;
780		− int nwords;
	619	+ int nr_words;
781	620	u8 count;
782	621
783	622	if (can_dev_dropped_skb(netdev, skb))
784	623	return NETDEV_TX_OK;
785	624
786		− nwords = kvaser_pciefd_prepare_tx_packet(&packet, can, skb);
	625	+ nr_words = kvaser_pciefd_prepare_tx_packet(&packet, can, skb);
787	626
788	627	spin_lock_irqsave(&can->echo_lock, irq_flags);
789		−
790	628	/* Prepare and save echo skb in internal slot */
791	629	can_put_echo_skb(skb, netdev, can->echo_idx, 0);
792	630
@@ -799,13 +637,13 @@ static netdev_tx_t kvaser_pciefd_start_xmit(struct sk_buff *skb, · 6 unmodified lines
799	637	iowrite32(packet.header[1],
800	638	can->reg_base + KVASER_PCIEFD_KCAN_FIFO_REG);
801	639
802		− if (nwords) {
803		− u32 data_last = ((u32 *)packet.data)[nwords - 1];
	640	+ if (nr_words) {
	641	+ u32 data_last = ((u32 *)packet.data)[nr_words - 1];
804	642
805	643	/* Write data to fifo, except last word */
806	644	iowrite32_rep(can->reg_base +
807	645	KVASER_PCIEFD_KCAN_FIFO_REG, packet.data,
808		− nwords - 1);
	646	+ nr_words - 1);
809	647	/* Write last word to end of fifo */
810	648	__raw_writel(data_last, can->reg_base +
811	649	KVASER_PCIEFD_KCAN_FIFO_LAST_REG);
@@ -815,14 +653,13 @@ static netdev_tx_t kvaser_pciefd_start_xmit(struct sk_buff *skb, · 3 unmodified lines
815	653	KVASER_PCIEFD_KCAN_FIFO_LAST_REG);
816	654	}
817	655
818		− count = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NPACKETS_REG);
	656	+ count = FIELD_GET(KVASER_PCIEFD_KCAN_TX_NR_PACKETS_CURRENT_MASK,
	657	+ ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NR_PACKETS_REG));
819	658	/* No room for a new message, stop the queue until at least one
820	659	* successful transmit
821	660	*/
822		− if (count >= KVASER_PCIEFD_CAN_TX_MAX_COUNT \|\|
823		− can->can.echo_skb[can->echo_idx])
	661	+ if (count >= can->can.echo_skb_max \|\| can->can.echo_skb[can->echo_idx])
824	662	netif_stop_queue(netdev);
825		−
826	663	spin_unlock_irqrestore(&can->echo_lock, irq_flags);
827	664
828	665	return NETDEV_TX_OK;
@@ -840,25 +677,20 @@ static int kvaser_pciefd_set_bittiming(struct kvaser_pciefd_can *can, bool data) · 11 unmodified lines
840	677	else
841	678	bt = &can->can.bittiming;
842	679
843		− btrn = ((bt->phase_seg2 - 1) & 0x1f) <<
844		− KVASER_PCIEFD_KCAN_BTRN_TSEG2_SHIFT \|
845		− (((bt->prop_seg + bt->phase_seg1) - 1) & 0x1ff) <<
846		− KVASER_PCIEFD_KCAN_BTRN_TSEG1_SHIFT \|
847		− ((bt->sjw - 1) & 0xf) << KVASER_PCIEFD_KCAN_BTRN_SJW_SHIFT \|
848		− ((bt->brp - 1) & 0x1fff);
	680	+ btrn = FIELD_PREP(KVASER_PCIEFD_KCAN_BTRN_TSEG2_MASK, bt->phase_seg2 - 1) \|
	681	+ FIELD_PREP(KVASER_PCIEFD_KCAN_BTRN_TSEG1_MASK, bt->prop_seg + bt->phase_seg1 - 1) \|
	682	+ FIELD_PREP(KVASER_PCIEFD_KCAN_BTRN_SJW_MASK, bt->sjw - 1) \|
	683	+ FIELD_PREP(KVASER_PCIEFD_KCAN_BTRN_BRP_MASK, bt->brp - 1);
849	684
850	685	spin_lock_irqsave(&can->lock, irq_flags);
851	686	mode = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
852		−
853	687	/* Put the circuit in reset mode */
854	688	iowrite32(mode \| KVASER_PCIEFD_KCAN_MODE_RM,
855	689	can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
856	690
857	691	/* Can only set bittiming if in reset mode */
858	692	ret = readl_poll_timeout(can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG,
859		− test, test & KVASER_PCIEFD_KCAN_MODE_RM,
860		− 0, 10);
861		−
	693	+ test, test & KVASER_PCIEFD_KCAN_MODE_RM, 0, 10);
862	694	if (ret) {
863	695	spin_unlock_irqrestore(&can->lock, irq_flags);
864	696	return -EBUSY;
@@ -868,11 +700,10 @@ static int kvaser_pciefd_set_bittiming(struct kvaser_pciefd_can *can, bool data) · 3 unmodified lines
868	700	iowrite32(btrn, can->reg_base + KVASER_PCIEFD_KCAN_BTRD_REG);
869	701	else
870	702	iowrite32(btrn, can->reg_base + KVASER_PCIEFD_KCAN_BTRN_REG);
871		−
872	703	/* Restore previous reset mode status */
873	704	iowrite32(mode, can->reg_base + KVASER_PCIEFD_KCAN_MODE_REG);
874		−
875	705	spin_unlock_irqrestore(&can->lock, irq_flags);
	706	+
876	707	return 0;
877	708	}
878	709
@@ -910,6 +741,7 @@ static int kvaser_pciefd_get_berr_counter(const struct net_device *ndev, · 31 unmodified lines
910	741
911	742	bec->rxerr = can->bec.rxerr;
912	743	bec->txerr = can->bec.txerr;
	744	+
913	745	return 0;
914	746	}
915	747
@@ -941,7 +773,7 @@ static int kvaser_pciefd_setup_can_ctrls(struct kvaser_pciefd *pcie) · 25 unmodified lines
941	773	for (i = 0; i < pcie->nr_channels; i++) {
942	774	struct net_device *netdev;
943	775	struct kvaser_pciefd_can *can;
944		− u32 status, tx_npackets;
	776	+ u32 status, tx_nr_packets_max;
945	777
946	778	netdev = alloc_candev(sizeof(struct kvaser_pciefd_can),
947	779	KVASER_PCIEFD_CAN_TX_MAX_COUNT);
@@ -953,7 +785,6 @@ static int kvaser_pciefd_setup_can_ctrls(struct kvaser_pciefd *pcie) · 5 unmodified lines
953	785	netdev->ethtool_ops = &kvaser_pciefd_ethtool_ops;
954	786	can->reg_base = pcie->reg_base + KVASER_PCIEFD_KCAN0_BASE +
955	787	i * KVASER_PCIEFD_KCAN_BASE_OFFSET;
956		−
957	788	can->kv_pcie = pcie;
958	789	can->cmd_seq = 0;
959	790	can->err_rep_cnt = 0;
@@ -962,41 +793,31 @@ static int kvaser_pciefd_setup_can_ctrls(struct kvaser_pciefd *pcie) · 2 unmodified lines
962	793
963	794	init_completion(&can->start_comp);
964	795	init_completion(&can->flush_comp);
965		− timer_setup(&can->bec_poll_timer, kvaser_pciefd_bec_poll_timer,
966		− 0);
	796	+ timer_setup(&can->bec_poll_timer, kvaser_pciefd_bec_poll_timer, 0);
967	797
968	798	/* Disable Bus load reporting */
969	799	iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_BUS_LOAD_REG);
970	800
971		− tx_npackets = ioread32(can->reg_base +
972		− KVASER_PCIEFD_KCAN_TX_NPACKETS_REG);
973		− if (((tx_npackets >> KVASER_PCIEFD_KCAN_TX_NPACKETS_MAX_SHIFT) &
974		− 0xff) < KVASER_PCIEFD_CAN_TX_MAX_COUNT) {
975		− dev_err(&pcie->pci->dev,
976		− "Max Tx count is smaller than expected\n");
977		−
978		− free_candev(netdev);
979		− return -ENODEV;
980		− }
	801	+ tx_nr_packets_max =
	802	+ FIELD_GET(KVASER_PCIEFD_KCAN_TX_NR_PACKETS_MAX_MASK,
	803	+ ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NR_PACKETS_REG));
981	804
982	805	can->can.clock.freq = pcie->freq;
983		− can->can.echo_skb_max = KVASER_PCIEFD_CAN_TX_MAX_COUNT;
	806	+ can->can.echo_skb_max = min(KVASER_PCIEFD_CAN_TX_MAX_COUNT, tx_nr_packets_max - 1);
984	807	can->echo_idx = 0;
985	808	spin_lock_init(&can->echo_lock);
986	809	spin_lock_init(&can->lock);
	810	+
987	811	can->can.bittiming_const = &kvaser_pciefd_bittiming_const;
988	812	can->can.data_bittiming_const = &kvaser_pciefd_bittiming_const;
989		−
990	813	can->can.do_set_bittiming = kvaser_pciefd_set_nominal_bittiming;
991		− can->can.do_set_data_bittiming =
992		− kvaser_pciefd_set_data_bittiming;
993		−
	814	+ can->can.do_set_data_bittiming = kvaser_pciefd_set_data_bittiming;
994	815	can->can.do_set_mode = kvaser_pciefd_set_mode;
995	816	can->can.do_get_berr_counter = kvaser_pciefd_get_berr_counter;
996		−
997	817	can->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY \|
998	818	CAN_CTRLMODE_FD \|
999		− CAN_CTRLMODE_FD_NON_ISO;
	819	+ CAN_CTRLMODE_FD_NON_ISO \|
	820	+ CAN_CTRLMODE_CC_LEN8_DLC;
1000	821
1001	822	status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);
1002	823	if (!(status & KVASER_PCIEFD_KCAN_STAT_FD)) {
@@ -1011,10 +832,9 @@ static int kvaser_pciefd_setup_can_ctrls(struct kvaser_pciefd *pcie) · 8 unmodified lines
1011	832	can->can.ctrlmode_supported \|= CAN_CTRLMODE_ONE_SHOT;
1012	833
1013	834	netdev->flags \|= IFF_ECHO;
1014		−
1015	835	SET_NETDEV_DEV(netdev, &pcie->pci->dev);
1016	836
1017		− iowrite32(-1, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
	837	+ iowrite32(GENMASK(31, 0), can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1018	838	iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD,
1019	839	can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
1020	840
@@ -1073,18 +893,16 @@ static int kvaser_pciefd_setup_dma(struct kvaser_pciefd *pcie) · 52 unmodified lines
1073	893	for (i = 0; i < KVASER_PCIEFD_DMA_COUNT; i++) {
1074	894	unsigned int offset = KVASER_PCIEFD_DMA_MAP_BASE + 8 * i;
1075	895
1076		− pcie->dma_data[i] =
1077		− dmam_alloc_coherent(&pcie->pci->dev,
1078		− KVASER_PCIEFD_DMA_SIZE,
1079		− &dma_addr[i],
1080		− GFP_KERNEL);
	896	+ pcie->dma_data[i] = dmam_alloc_coherent(&pcie->pci->dev,
	897	+ KVASER_PCIEFD_DMA_SIZE,
	898	+ &dma_addr[i],
	899	+ GFP_KERNEL);
1081	900
1082	901	if (!pcie->dma_data[i] \|\| !dma_addr[i]) {
1083	902	dev_err(&pcie->pci->dev, "Rx dma_alloc(%u) failure\n",
1084	903	KVASER_PCIEFD_DMA_SIZE);
1085	904	return -ENOMEM;
1086	905	}
1087		−
1088	906	kvaser_pciefd_write_dma_map(pcie, dma_addr[i], offset);
1089	907	}
1090	908
@@ -1092,10 +910,10 @@ static int kvaser_pciefd_setup_dma(struct kvaser_pciefd *pcie) · 1 unmodified line
1092	910	iowrite32(KVASER_PCIEFD_SRB_CMD_FOR \| KVASER_PCIEFD_SRB_CMD_RDB0 \|
1093	911	KVASER_PCIEFD_SRB_CMD_RDB1,
1094	912	pcie->reg_base + KVASER_PCIEFD_SRB_CMD_REG);
1095		−
1096	913	/* Empty Rx FIFO */
1097		− srb_packet_count = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_RX_NR_PACKETS_REG) &
1098		− KVASER_PCIEFD_SRB_RX_NR_PACKETS_MASK;
	914	+ srb_packet_count =
	915	+ FIELD_GET(KVASER_PCIEFD_SRB_RX_NR_PACKETS_MASK,
	916	+ ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_RX_NR_PACKETS_REG));
1099	917	while (srb_packet_count) {
1100	918	/* Drop current packet in FIFO */
1101	919	ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_FIFO_LAST_REG);
@@ -1117,37 +935,21 @@ static int kvaser_pciefd_setup_dma(struct kvaser_pciefd *pcie) · 15 unmodified lines
1117	935
1118	936	static int kvaser_pciefd_setup_board(struct kvaser_pciefd *pcie)
1119	937	{
1120		− u32 sysid, srb_status, build;
1121		− u8 sysid_nr_chan;
1122		− int ret;
1123		−
1124		− ret = kvaser_pciefd_read_cfg(pcie);
1125		− if (ret)
1126		− return ret;
1127		−
1128		− sysid = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_VERSION_REG);
1129		− sysid_nr_chan = (sysid >> KVASER_PCIEFD_SYSID_NRCHAN_SHIFT) & 0xff;
1130		− if (pcie->nr_channels != sysid_nr_chan) {
1131		− dev_err(&pcie->pci->dev,
1132		− "Number of channels does not match: %u vs %u\n",
1133		− pcie->nr_channels,
1134		− sysid_nr_chan);
1135		− return -ENODEV;
1136		− }
	938	+ u32 version, srb_status, build;
1137	939
1138		− if (pcie->nr_channels > KVASER_PCIEFD_MAX_CAN_CHANNELS)
1139		− pcie->nr_channels = KVASER_PCIEFD_MAX_CAN_CHANNELS;
	940	+ version = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_VERSION_REG);
	941	+ pcie->nr_channels = min(KVASER_PCIEFD_MAX_CAN_CHANNELS,
	942	+ FIELD_GET(KVASER_PCIEFD_SYSID_VERSION_NR_CHAN_MASK, version));
1140	943
1141	944	build = ioread32(pcie->reg_base + KVASER_PCIEFD_SYSID_BUILD_REG);
1142		− dev_dbg(&pcie->pci->dev, "Version %u.%u.%u\n",
1143		− (sysid >> KVASER_PCIEFD_SYSID_MAJOR_VER_SHIFT) & 0xff,
1144		− sysid & 0xff,
1145		− (build >> KVASER_PCIEFD_SYSID_BUILD_VER_SHIFT) & 0x7fff);
	945	+ dev_dbg(&pcie->pci->dev, "Version %lu.%lu.%lu\n",
	946	+ FIELD_GET(KVASER_PCIEFD_SYSID_VERSION_MAJOR_MASK, version),
	947	+ FIELD_GET(KVASER_PCIEFD_SYSID_VERSION_MINOR_MASK, version),
	948	+ FIELD_GET(KVASER_PCIEFD_SYSID_BUILD_SEQ_MASK, build));
1146	949
1147	950	srb_status = ioread32(pcie->reg_base + KVASER_PCIEFD_SRB_STAT_REG);
1148	951	if (!(srb_status & KVASER_PCIEFD_SRB_STAT_DMA)) {
1149		− dev_err(&pcie->pci->dev,
1150		− "Hardware without DMA is not supported\n");
	952	+ dev_err(&pcie->pci->dev, "Hardware without DMA is not supported\n");
1151	953	return -ENODEV;
1152	954	}
1153	955
@@ -1157,10 +959,10 @@ static int kvaser_pciefd_setup_board(struct kvaser_pciefd *pcie) · 3 unmodified lines
1157	959	pcie->freq_to_ticks_div = pcie->freq / 1000000;
1158	960	if (pcie->freq_to_ticks_div == 0)
1159	961	pcie->freq_to_ticks_div = 1;
1160		−
1161	962	/* Turn off all loopback functionality */
1162	963	iowrite32(0, pcie->reg_base + KVASER_PCIEFD_LOOP_REG);
1163		− return ret;
	964	+
	965	+ return 0;
1164	966	}
1165	967
1166	968	static int kvaser_pciefd_handle_data_packet(struct kvaser_pciefd *pcie,
@@ -1170,56 +972,48 @@ static int kvaser_pciefd_handle_data_packet(struct kvaser_pciefd *pcie, · 3 unmodified lines
1170	972	struct sk_buff *skb;
1171	973	struct canfd_frame *cf;
1172	974	struct can_priv *priv;
1173		− struct net_device_stats *stats;
1174		− struct skb_shared_hwtstamps *shhwtstamps;
1175		− u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
	975	+ u8 ch_id = FIELD_GET(KVASER_PCIEFD_PACKET_CHID_MASK, p->header[1]);
	976	+ u8 dlc;
1176	977
1177	978	if (ch_id >= pcie->nr_channels)
1178	979	return -EIO;
1179	980
1180	981	priv = &pcie->can[ch_id]->can;
1181		− stats = &priv->dev->stats;
	982	+ dlc = FIELD_GET(KVASER_PCIEFD_RPACKET_DLC_MASK, p->header[1]);
1182	983
1183	984	if (p->header[1] & KVASER_PCIEFD_RPACKET_FDF) {
1184	985	skb = alloc_canfd_skb(priv->dev, &cf);
1185	986	if (!skb) {
1186		− stats->rx_dropped++;
	987	+ priv->dev->stats.rx_dropped++;
1187	988	return -ENOMEM;
1188	989	}
1189	990
	991	+ cf->len = can_fd_dlc2len(dlc);
1190	992	if (p->header[1] & KVASER_PCIEFD_RPACKET_BRS)
1191	993	cf->flags \|= CANFD_BRS;
1192		−
1193	994	if (p->header[1] & KVASER_PCIEFD_RPACKET_ESI)
1194	995	cf->flags \|= CANFD_ESI;
1195	996	} else {
1196	997	skb = alloc_can_skb(priv->dev, (struct can_frame **)&cf);
1197	998	if (!skb) {
1198		− stats->rx_dropped++;
	999	+ priv->dev->stats.rx_dropped++;
1199	1000	return -ENOMEM;
1200	1001	}
	1002	+ can_frame_set_cc_len((struct can_frame *)cf, dlc, priv->ctrlmode);
1201	1003	}
1202	1004
1203		− cf->can_id = p->header[0] & CAN_EFF_MASK;
	1005	+ cf->can_id = FIELD_GET(KVASER_PCIEFD_RPACKET_ID_MASK, p->header[0]);
1204	1006	if (p->header[0] & KVASER_PCIEFD_RPACKET_IDE)
1205	1007	cf->can_id \|= CAN_EFF_FLAG;
1206	1008
1207		− cf->len = can_fd_dlc2len(p->header[1] >> KVASER_PCIEFD_RPACKET_DLC_SHIFT);
1208		−
1209	1009	if (p->header[0] & KVASER_PCIEFD_RPACKET_RTR) {
1210	1010	cf->can_id \|= CAN_RTR_FLAG;
1211	1011	} else {
1212	1012	memcpy(cf->data, data, cf->len);
1213		−
1214		− stats->rx_bytes += cf->len;
	1013	+ priv->dev->stats.rx_bytes += cf->len;
1215	1014	}
1216		− stats->rx_packets++;
1217		−
1218		− shhwtstamps = skb_hwtstamps(skb);
1219		−
1220		− shhwtstamps->hwtstamp =
1221		− ns_to_ktime(div_u64(p->timestamp * 1000,
1222		− pcie->freq_to_ticks_div));
	1015	+ priv->dev->stats.rx_packets++;
	1016	+ kvaser_pciefd_set_skb_timestamp(pcie, skb, p->timestamp);
1223	1017
1224	1018	return netif_rx(skb);
1225	1019	}
@@ -1239,7 +1033,6 @@ static void kvaser_pciefd_change_state(struct kvaser_pciefd_can *can, · 13 unmodified lines
1239	1033	spin_lock_irqsave(&can->lock, irq_flags);
1240	1034	netif_stop_queue(can->can.dev);
1241	1035	spin_unlock_irqrestore(&can->lock, irq_flags);
1242		−
1243	1036	/* Prevent CAN controller from auto recover from bus off */
1244	1037	if (!can->can.restart_ms) {
1245	1038	kvaser_pciefd_start_controller_flush(can);
@@ -1257,7 +1050,7 @@ static void kvaser_pciefd_packet_to_state(struct kvaser_pciefd_rx_packet *p, · 11 unmodified lines
1257	1050	if (p->header[0] & KVASER_PCIEFD_SPACK_BOFF \|\|
1258	1051	p->header[0] & KVASER_PCIEFD_SPACK_IRM)
1259	1052	*new_state = CAN_STATE_BUS_OFF;
1260		− else if (bec->txerr >= 255 \|\| bec->rxerr >= 255)
	1053	+ else if (bec->txerr >= 255 \|\| bec->rxerr >= 255)
1261	1054	*new_state = CAN_STATE_BUS_OFF;
1262	1055	else if (p->header[1] & KVASER_PCIEFD_SPACK_EPLR)
1263	1056	*new_state = CAN_STATE_ERROR_PASSIVE;
@@ -1282,23 +1075,16 @@ static int kvaser_pciefd_rx_error_frame(struct kvaser_pciefd_can *can, · 18 unmodified lines
1282	1075	struct net_device *ndev = can->can.dev;
1283	1076	struct sk_buff *skb;
1284	1077	struct can_frame *cf = NULL;
1285		− struct skb_shared_hwtstamps *shhwtstamps;
1286		− struct net_device_stats *stats = &ndev->stats;
1287	1078
1288	1079	old_state = can->can.state;
1289	1080
1290		− bec.txerr = p->header[0] & 0xff;
1291		− bec.rxerr = (p->header[0] >> KVASER_PCIEFD_SPACK_RXERR_SHIFT) & 0xff;
1292		−
1293		− kvaser_pciefd_packet_to_state(p, &bec, &new_state, &tx_state,
1294		− &rx_state);
	1081	+ bec.txerr = FIELD_GET(KVASER_PCIEFD_SPACK_TXERR_MASK, p->header[0]);
	1082	+ bec.rxerr = FIELD_GET(KVASER_PCIEFD_SPACK_RXERR_MASK, p->header[0]);
1295	1083
	1084	+ kvaser_pciefd_packet_to_state(p, &bec, &new_state, &tx_state, &rx_state);
1296	1085	skb = alloc_can_err_skb(ndev, &cf);
1297		−
1298	1086	if (new_state != old_state) {
1299		− kvaser_pciefd_change_state(can, cf, new_state, tx_state,
1300		− rx_state);
1301		−
	1087	+ kvaser_pciefd_change_state(can, cf, new_state, tx_state, rx_state);
1302	1088	if (old_state == CAN_STATE_BUS_OFF &&
1303	1089	new_state == CAN_STATE_ERROR_ACTIVE &&
1304	1090	can->can.restart_ms) {
@@ -1311,28 +1097,25 @@ static int kvaser_pciefd_rx_error_frame(struct kvaser_pciefd_can *can, · 6 unmodified lines
1311	1097	can->err_rep_cnt++;
1312	1098	can->can.can_stats.bus_error++;
1313	1099	if (p->header[1] & KVASER_PCIEFD_EPACK_DIR_TX)
1314		− stats->tx_errors++;
	1100	+ ndev->stats.tx_errors++;
1315	1101	else
1316		− stats->rx_errors++;
	1102	+ ndev->stats.rx_errors++;
1317	1103
1318	1104	can->bec.txerr = bec.txerr;
1319	1105	can->bec.rxerr = bec.rxerr;
1320	1106
1321	1107	if (!skb) {
1322		− stats->rx_dropped++;
	1108	+ ndev->stats.rx_dropped++;
1323	1109	return -ENOMEM;
1324	1110	}
1325	1111
1326		− shhwtstamps = skb_hwtstamps(skb);
1327		− shhwtstamps->hwtstamp =
1328		− ns_to_ktime(div_u64(p->timestamp * 1000,
1329		− can->kv_pcie->freq_to_ticks_div));
	1112	+ kvaser_pciefd_set_skb_timestamp(can->kv_pcie, skb, p->timestamp);
1330	1113	cf->can_id \|= CAN_ERR_BUSERROR \| CAN_ERR_CNT;
1331		−
1332	1114	cf->data[6] = bec.txerr;
1333	1115	cf->data[7] = bec.rxerr;
1334	1116
1335	1117	netif_rx(skb);
	1118	+
1336	1119	return 0;
1337	1120	}
1338	1121
@@ -1340,19 +1123,19 @@ static int kvaser_pciefd_handle_error_packet(struct kvaser_pciefd *pcie, · 1 unmodified line
1340	1123	struct kvaser_pciefd_rx_packet *p)
1341	1124	{
1342	1125	struct kvaser_pciefd_can *can;
1343		− u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
	1126	+ u8 ch_id = FIELD_GET(KVASER_PCIEFD_PACKET_CHID_MASK, p->header[1]);
1344	1127
1345	1128	if (ch_id >= pcie->nr_channels)
1346	1129	return -EIO;
1347	1130
1348	1131	can = pcie->can[ch_id];
1349		−
1350	1132	kvaser_pciefd_rx_error_frame(can, p);
1351	1133	if (can->err_rep_cnt >= KVASER_PCIEFD_MAX_ERR_REP)
1352	1134	/* Do not report more errors, until bec_poll_timer expires */
1353	1135	kvaser_pciefd_disable_err_gen(can);
1354	1136	/* Start polling the error counters */
1355	1137	mod_timer(&can->bec_poll_timer, KVASER_PCIEFD_BEC_POLL_FREQ);
	1138	+
1356	1139	return 0;
1357	1140	}
1358	1141
@@ -1364,29 +1147,22 @@ static int kvaser_pciefd_handle_status_resp(struct kvaser_pciefd_can *can, · 5 unmodified lines
1364	1147
1365	1148	old_state = can->can.state;
1366	1149
1367		− bec.txerr = p->header[0] & 0xff;
1368		− bec.rxerr = (p->header[0] >> KVASER_PCIEFD_SPACK_RXERR_SHIFT) & 0xff;
1369		−
1370		− kvaser_pciefd_packet_to_state(p, &bec, &new_state, &tx_state,
1371		− &rx_state);
	1150	+ bec.txerr = FIELD_GET(KVASER_PCIEFD_SPACK_TXERR_MASK, p->header[0]);
	1151	+ bec.rxerr = FIELD_GET(KVASER_PCIEFD_SPACK_RXERR_MASK, p->header[0]);
1372	1152
	1153	+ kvaser_pciefd_packet_to_state(p, &bec, &new_state, &tx_state, &rx_state);
1373	1154	if (new_state != old_state) {
1374	1155	struct net_device *ndev = can->can.dev;
1375	1156	struct sk_buff *skb;
1376	1157	struct can_frame *cf;
1377		− struct skb_shared_hwtstamps *shhwtstamps;
1378	1158
1379	1159	skb = alloc_can_err_skb(ndev, &cf);
1380	1160	if (!skb) {
1381		− struct net_device_stats *stats = &ndev->stats;
1382		−
1383		− stats->rx_dropped++;
	1161	+ ndev->stats.rx_dropped++;
1384	1162	return -ENOMEM;
1385	1163	}
1386	1164
1387		− kvaser_pciefd_change_state(can, cf, new_state, tx_state,
1388		− rx_state);
1389		−
	1165	+ kvaser_pciefd_change_state(can, cf, new_state, tx_state, rx_state);
1390	1166	if (old_state == CAN_STATE_BUS_OFF &&
1391	1167	new_state == CAN_STATE_ERROR_ACTIVE &&
1392	1168	can->can.restart_ms) {
@@ -1394,10 +1170,7 @@ static int kvaser_pciefd_handle_status_resp(struct kvaser_pciefd_can *can, · 1 unmodified line
1394	1170	cf->can_id \|= CAN_ERR_RESTARTED;
1395	1171	}
1396	1172
1397		− shhwtstamps = skb_hwtstamps(skb);
1398		− shhwtstamps->hwtstamp =
1399		− ns_to_ktime(div_u64(p->timestamp * 1000,
1400		− can->kv_pcie->freq_to_ticks_div));
	1173	+ kvaser_pciefd_set_skb_timestamp(can->kv_pcie, skb, p->timestamp);
1401	1174
1402	1175	cf->data[6] = bec.txerr;
1403	1176	cf->data[7] = bec.rxerr;
@@ -1419,7 +1192,7 @@ static int kvaser_pciefd_handle_status_packet(struct kvaser_pciefd *pcie, · 15 unmodified lines
1419	1192	struct kvaser_pciefd_can *can;
1420	1193	u8 cmdseq;
1421	1194	u32 status;
1422		− u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
	1195	+ u8 ch_id = FIELD_GET(KVASER_PCIEFD_PACKET_CHID_MASK, p->header[1]);
1423	1196
1424	1197	if (ch_id >= pcie->nr_channels)
1425	1198	return -EIO;
@@ -1427,43 +1200,40 @@ static int kvaser_pciefd_handle_status_packet(struct kvaser_pciefd *pcie, · 1 unmodified line
1427	1200	can = pcie->can[ch_id];
1428	1201
1429	1202	status = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_STAT_REG);
1430		− cmdseq = (status >> KVASER_PCIEFD_KCAN_STAT_SEQNO_SHIFT) & 0xff;
	1203	+ cmdseq = FIELD_GET(KVASER_PCIEFD_KCAN_STAT_SEQNO_MASK, status);
1431	1204
1432	1205	/* Reset done, start abort and flush */
1433	1206	if (p->header[0] & KVASER_PCIEFD_SPACK_IRM &&
1434	1207	p->header[0] & KVASER_PCIEFD_SPACK_RMCD &&
1435	1208	p->header[1] & KVASER_PCIEFD_SPACK_AUTO &&
1436		− cmdseq == (p->header[1] & KVASER_PCIEFD_PACKET_SEQ_MSK) &&
	1209	+ cmdseq == FIELD_GET(KVASER_PCIEFD_PACKET_SEQ_MASK, p->header[1]) &&
1437	1210	status & KVASER_PCIEFD_KCAN_STAT_IDLE) {
1438		− u32 cmd;
1439		−
1440	1211	iowrite32(KVASER_PCIEFD_KCAN_IRQ_ABD,
1441	1212	can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1442		− cmd = KVASER_PCIEFD_KCAN_CMD_AT;
1443		− cmd \|= ++can->cmd_seq << KVASER_PCIEFD_KCAN_CMD_SEQ_SHIFT;
1444		− iowrite32(cmd, can->reg_base + KVASER_PCIEFD_KCAN_CMD_REG);
	1213	+ kvaser_pciefd_abort_flush_reset(can);
1445	1214	} else if (p->header[0] & KVASER_PCIEFD_SPACK_IDET &&
1446	1215	p->header[0] & KVASER_PCIEFD_SPACK_IRM &&
1447		− cmdseq == (p->header[1] & KVASER_PCIEFD_PACKET_SEQ_MSK) &&
	1216	+ cmdseq == FIELD_GET(KVASER_PCIEFD_PACKET_SEQ_MASK, p->header[1]) &&
1448	1217	status & KVASER_PCIEFD_KCAN_STAT_IDLE) {
1449	1218	/* Reset detected, send end of flush if no packet are in FIFO */
1450		− u8 count = ioread32(can->reg_base +
1451		− KVASER_PCIEFD_KCAN_TX_NPACKETS_REG) & 0xff;
	1219	+ u8 count;
1452	1220
	1221	+ count = FIELD_GET(KVASER_PCIEFD_KCAN_TX_NR_PACKETS_CURRENT_MASK,
	1222	+ ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NR_PACKETS_REG));
1453	1223	if (!count)
1454		− iowrite32(KVASER_PCIEFD_KCAN_CTRL_EFLUSH,
	1224	+ iowrite32(FIELD_PREP(KVASER_PCIEFD_KCAN_CTRL_TYPE_MASK,
	1225	+ KVASER_PCIEFD_KCAN_CTRL_TYPE_EFLUSH),
1455	1226	can->reg_base + KVASER_PCIEFD_KCAN_CTRL_REG);
1456	1227	} else if (!(p->header[1] & KVASER_PCIEFD_SPACK_AUTO) &&
1457		− cmdseq == (p->header[1] & KVASER_PCIEFD_PACKET_SEQ_MSK)) {
	1228	+ cmdseq == FIELD_GET(KVASER_PCIEFD_PACKET_SEQ_MASK, p->header[1])) {
1458	1229	/* Response to status request received */
1459	1230	kvaser_pciefd_handle_status_resp(can, p);
1460	1231	if (can->can.state != CAN_STATE_BUS_OFF &&
1461	1232	can->can.state != CAN_STATE_ERROR_ACTIVE) {
1462		− mod_timer(&can->bec_poll_timer,
1463		− KVASER_PCIEFD_BEC_POLL_FREQ);
	1233	+ mod_timer(&can->bec_poll_timer, KVASER_PCIEFD_BEC_POLL_FREQ);
1464	1234	}
1465	1235	} else if (p->header[0] & KVASER_PCIEFD_SPACK_RMCD &&
1466		− !(status & KVASER_PCIEFD_KCAN_STAT_BUS_OFF_MSK)) {
	1236	+ !(status & KVASER_PCIEFD_KCAN_STAT_BUS_OFF_MASK)) {
1467	1237	/* Reset to bus on detected */
1468	1238	if (!completion_done(&can->start_comp))
1469	1239	complete(&can->start_comp);
@@ -1472,50 +1242,14 @@ static int kvaser_pciefd_handle_status_packet(struct kvaser_pciefd *pcie, · 2 unmodified lines
1472	1242	return 0;
1473	1243	}
1474	1244
1475		−static int kvaser_pciefd_handle_eack_packet(struct kvaser_pciefd *pcie,
1476		− struct kvaser_pciefd_rx_packet *p)
1477		−{
1478		− struct kvaser_pciefd_can *can;
1479		− u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
1480		−
1481		− if (ch_id >= pcie->nr_channels)
1482		− return -EIO;
1483		−
1484		− can = pcie->can[ch_id];
1485		−
1486		− /* If this is the last flushed packet, send end of flush */
1487		− if (p->header[0] & KVASER_PCIEFD_APACKET_FLU) {
1488		− u8 count = ioread32(can->reg_base +
1489		− KVASER_PCIEFD_KCAN_TX_NPACKETS_REG) & 0xff;
1490		−
1491		− if (count == 0)
1492		− iowrite32(KVASER_PCIEFD_KCAN_CTRL_EFLUSH,
1493		− can->reg_base + KVASER_PCIEFD_KCAN_CTRL_REG);
1494		− } else {
1495		− int echo_idx = p->header[0] & KVASER_PCIEFD_PACKET_SEQ_MSK;
1496		− int dlc = can_get_echo_skb(can->can.dev, echo_idx, NULL);
1497		− struct net_device_stats *stats = &can->can.dev->stats;
1498		−
1499		− stats->tx_bytes += dlc;
1500		− stats->tx_packets++;
1501		−
1502		− if (netif_queue_stopped(can->can.dev))
1503		− netif_wake_queue(can->can.dev);
1504		− }
1505		−
1506		− return 0;
1507		−}
1508		−
1509	1245	static void kvaser_pciefd_handle_nack_packet(struct kvaser_pciefd_can *can,
1510	1246	struct kvaser_pciefd_rx_packet *p)
1511	1247	{
1512	1248	struct sk_buff *skb;
1513		− struct net_device_stats *stats = &can->can.dev->stats;
1514	1249	struct can_frame *cf;
1515	1250
1516	1251	skb = alloc_can_err_skb(can->can.dev, &cf);
1517		−
1518		− stats->tx_errors++;
	1252	+ can->can.dev->stats.tx_errors++;
1519	1253	if (p->header[0] & KVASER_PCIEFD_APACKET_ABL) {
1520	1254	if (skb)
1521	1255	cf->can_id \|= CAN_ERR_LOSTARB;
@@ -1526,9 +1260,10 @@ static void kvaser_pciefd_handle_nack_packet(struct kvaser_pciefd_can *can, · 4 unmodified lines
1526	1260
1527	1261	if (skb) {
1528	1262	cf->can_id \|= CAN_ERR_BUSERROR;
	1263	+ kvaser_pciefd_set_skb_timestamp(can->kv_pcie, skb, p->timestamp);
1529	1264	netif_rx(skb);
1530	1265	} else {
1531		− stats->rx_dropped++;
	1266	+ can->can.dev->stats.rx_dropped++;
1532	1267	netdev_warn(can->can.dev, "No memory left for err_skb\n");
1533	1268	}
1534	1269	}
@@ -1538,7 +1273,7 @@ static int kvaser_pciefd_handle_ack_packet(struct kvaser_pciefd *pcie, · 3 unmodified lines
1538	1273	{
1539	1274	struct kvaser_pciefd_can *can;
1540	1275	bool one_shot_fail = false;
1541		− u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
	1276	+ u8 ch_id = FIELD_GET(KVASER_PCIEFD_PACKET_CHID_MASK, p->header[1]);
1542	1277
1543	1278	if (ch_id >= pcie->nr_channels)
1544	1279	return -EIO;
@@ -1556,20 +1291,24 @@ static int kvaser_pciefd_handle_ack_packet(struct kvaser_pciefd *pcie, · 11 unmodified lines
1556	1291	if (p->header[0] & KVASER_PCIEFD_APACKET_FLU) {
1557	1292	netdev_dbg(can->can.dev, "Packet was flushed\n");
1558	1293	} else {
1559		− int echo_idx = p->header[0] & KVASER_PCIEFD_PACKET_SEQ_MSK;
1560		− int dlc = can_get_echo_skb(can->can.dev, echo_idx, NULL);
1561		− u8 count = ioread32(can->reg_base +
1562		− KVASER_PCIEFD_KCAN_TX_NPACKETS_REG) & 0xff;
	1294	+ int echo_idx = FIELD_GET(KVASER_PCIEFD_PACKET_SEQ_MASK, p->header[0]);
	1295	+ int len;
	1296	+ u8 count;
	1297	+ struct sk_buff *skb;
1563	1298
1564		− if (count < KVASER_PCIEFD_CAN_TX_MAX_COUNT &&
1565		− netif_queue_stopped(can->can.dev))
	1299	+ skb = can->can.echo_skb[echo_idx];
	1300	+ if (skb)
	1301	+ kvaser_pciefd_set_skb_timestamp(pcie, skb, p->timestamp);
	1302	+ len = can_get_echo_skb(can->can.dev, echo_idx, NULL);
	1303	+ count = FIELD_GET(KVASER_PCIEFD_KCAN_TX_NR_PACKETS_CURRENT_MASK,
	1304	+ ioread32(can->reg_base + KVASER_PCIEFD_KCAN_TX_NR_PACKETS_REG));
	1305	+
	1306	+ if (count < can->can.echo_skb_max && netif_queue_stopped(can->can.dev))
1566	1307	netif_wake_queue(can->can.dev);
1567	1308
1568	1309	if (!one_shot_fail) {
1569		− struct net_device_stats *stats = &can->can.dev->stats;
1570		−
1571		− stats->tx_bytes += dlc;
1572		− stats->tx_packets++;
	1310	+ can->can.dev->stats.tx_bytes += len;
	1311	+ can->can.dev->stats.tx_packets++;
1573	1312	}
1574	1313	}
1575	1314
@@ -1580,7 +1319,7 @@ static int kvaser_pciefd_handle_eflush_packet(struct kvaser_pciefd *pcie, · 4 unmodified lines
1580	1319	struct kvaser_pciefd_rx_packet *p)
1581	1320	{
1582	1321	struct kvaser_pciefd_can *can;
1583		− u8 ch_id = (p->header[1] >> KVASER_PCIEFD_PACKET_CHID_SHIFT) & 0x7;
	1322	+ u8 ch_id = FIELD_GET(KVASER_PCIEFD_PACKET_CHID_MASK, p->header[1]);
1584	1323
1585	1324	if (ch_id >= pcie->nr_channels)
1586	1325	return -EIO;
@@ -1619,15 +1358,15 @@ static int kvaser_pciefd_read_packet(struct kvaser_pciefd pcie, int start_pos, · 32 unmodified lines
1619	1358	pos += 2;
1620	1359	p->timestamp = le64_to_cpu(timestamp);
1621	1360
1622		− type = (p->header[1] >> KVASER_PCIEFD_PACKET_TYPE_SHIFT) & 0xf;
	1361	+ type = FIELD_GET(KVASER_PCIEFD_PACKET_TYPE_MASK, p->header[1]);
1623	1362	switch (type) {
1624	1363	case KVASER_PCIEFD_PACK_TYPE_DATA:
1625	1364	ret = kvaser_pciefd_handle_data_packet(pcie, p, &buffer[pos]);
1626	1365	if (!(p->header[0] & KVASER_PCIEFD_RPACKET_RTR)) {
1627	1366	u8 data_len;
1628	1367
1629		− data_len = can_fd_dlc2len(p->header[1] >>
1630		− KVASER_PCIEFD_RPACKET_DLC_SHIFT);
	1368	+ data_len = can_fd_dlc2len(FIELD_GET(KVASER_PCIEFD_RPACKET_DLC_MASK,
	1369	+ p->header[1]));
1631	1370	pos += DIV_ROUND_UP(data_len, 4);
1632	1371	}
1633	1372	break;
@@ -1644,16 +1383,13 @@ static int kvaser_pciefd_read_packet(struct kvaser_pciefd pcie, int start_pos, · 10 unmodified lines
1644	1383	ret = kvaser_pciefd_handle_error_packet(pcie, p);
1645	1384	break;
1646	1385
1647		− case KVASER_PCIEFD_PACK_TYPE_EFRAME_ACK:
1648		− ret = kvaser_pciefd_handle_eack_packet(pcie, p);
1649		− break;
1650		−
1651	1386	case KVASER_PCIEFD_PACK_TYPE_EFLUSH_ACK:
1652	1387	ret = kvaser_pciefd_handle_eflush_packet(pcie, p);
1653	1388	break;
1654	1389
1655	1390	case KVASER_PCIEFD_PACK_TYPE_ACK_DATA:
1656	1391	case KVASER_PCIEFD_PACK_TYPE_BUS_LOAD:
	1392	+ case KVASER_PCIEFD_PACK_TYPE_EFRAME_ACK:
1657	1393	case KVASER_PCIEFD_PACK_TYPE_TXRQ:
1658	1394	dev_info(&pcie->pci->dev,
1659	1395	"Received unexpected packet type 0x%08X\n", type);
@@ -1692,7 +1428,7 @@ static int kvaser_pciefd_read_buffer(struct kvaser_pciefd *pcie, int dma_buf) · 32 unmodified lines
1692	1428	return res;
1693	1429	}
1694	1430
1695		−static int kvaser_pciefd_receive_irq(struct kvaser_pciefd *pcie)
	1431	+static void kvaser_pciefd_receive_irq(struct kvaser_pciefd *pcie)
1696	1432	{
1697	1433	u32 irq;
1698	1434
@@ -1718,10 +1454,9 @@ static int kvaser_pciefd_receive_irq(struct kvaser_pciefd *pcie) · 19 unmodified lines
1718	1454	dev_err(&pcie->pci->dev, "DMA IRQ error 0x%08X\n", irq);
1719	1455
1720	1456	iowrite32(irq, pcie->reg_base + KVASER_PCIEFD_SRB_IRQ_REG);
1721		− return 0;
1722	1457	}
1723	1458
1724		−static int kvaser_pciefd_transmit_irq(struct kvaser_pciefd_can *can)
	1459	+static void kvaser_pciefd_transmit_irq(struct kvaser_pciefd_can *can)
1725	1460	{
1726	1461	u32 irq = ioread32(can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1727	1462
@@ -1739,7 +1474,6 @@ static int kvaser_pciefd_transmit_irq(struct kvaser_pciefd_can *can) · 11 unmodified lines
1739	1474	netdev_err(can->can.dev, "Rx FIFO overflow\n");
1740	1475
1741	1476	iowrite32(irq, can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);
1742		− return 0;
1743	1477	}
1744	1478
1745	1479	static irqreturn_t kvaser_pciefd_irq_handler(int irq, void *dev)
@@ -1750,7 +1484,7 @@ static irqreturn_t kvaser_pciefd_irq_handler(int irq, void *dev) · 4 unmodified lines
1750	1484
1751	1485	board_irq = ioread32(pcie->reg_base + KVASER_PCIEFD_IRQ_REG);
1752	1486
1753		− if (!(board_irq & KVASER_PCIEFD_IRQ_ALL_MSK))
	1487	+ if (!(board_irq & KVASER_PCIEFD_IRQ_ALL_MASK))
1754	1488	return IRQ_NONE;
1755	1489
1756	1490	if (board_irq & KVASER_PCIEFD_IRQ_SRB)
@@ -1768,20 +1502,18 @@ static irqreturn_t kvaser_pciefd_irq_handler(int irq, void *dev) · 11 unmodified lines
1768	1502	kvaser_pciefd_transmit_irq(pcie->can[i]);
1769	1503	}
1770	1504
1771		− iowrite32(board_irq, pcie->reg_base + KVASER_PCIEFD_IRQ_REG);
1772	1505	return IRQ_HANDLED;
1773	1506	}
1774	1507
1775	1508	static void kvaser_pciefd_teardown_can_ctrls(struct kvaser_pciefd *pcie)
1776	1509	{
1777	1510	int i;
1778		− struct kvaser_pciefd_can *can;
1779	1511
1780	1512	for (i = 0; i < pcie->nr_channels; i++) {
1781		− can = pcie->can[i];
	1513	+ struct kvaser_pciefd_can *can = pcie->can[i];
	1514	+
1782	1515	if (can) {
1783		− iowrite32(0,
1784		− can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
	1516	+ iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
1785	1517	kvaser_pciefd_pwm_stop(can);
1786	1518	free_candev(can->can.dev);
1787	1519	}
@@ -1842,10 +1574,8 @@ static int kvaser_pciefd_probe(struct pci_dev *pdev, · 54 unmodified lines
1842	1574	KVASER_PCIEFD_SRB_IRQ_DUF0 \| KVASER_PCIEFD_SRB_IRQ_DUF1,
1843	1575	pcie->reg_base + KVASER_PCIEFD_SRB_IEN_REG);
1844	1576
1845		− /* Reset IRQ handling, expected to be off before */
1846		− iowrite32(KVASER_PCIEFD_IRQ_ALL_MSK,
1847		− pcie->reg_base + KVASER_PCIEFD_IRQ_REG);
1848		− iowrite32(KVASER_PCIEFD_IRQ_ALL_MSK,
	1577	+ /* Enable PCI interrupts */
	1578	+ iowrite32(KVASER_PCIEFD_IRQ_ALL_MASK,
1849	1579	pcie->reg_base + KVASER_PCIEFD_IEN_REG);
1850	1580
1851	1581	/* Ready the DMA buffers */
@@ -1884,14 +1614,13 @@ err_disable_pci: · 32 unmodified lines
1884	1614
1885	1615	static void kvaser_pciefd_remove_all_ctrls(struct kvaser_pciefd *pcie)
1886	1616	{
1887		− struct kvaser_pciefd_can *can;
1888	1617	int i;
1889	1618
1890	1619	for (i = 0; i < pcie->nr_channels; i++) {
1891		− can = pcie->can[i];
	1620	+ struct kvaser_pciefd_can *can = pcie->can[i];
	1621	+
1892	1622	if (can) {
1893		− iowrite32(0,
1894		− can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
	1623	+ iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);
1895	1624	unregister_candev(can->can.dev);
1896	1625	del_timer(&can->bec_poll_timer);
1897	1626	kvaser_pciefd_pwm_stop(can);
@@ -1906,10 +1635,8 @@ static void kvaser_pciefd_remove(struct pci_dev *pdev) · 8 unmodified lines
1906	1635
1907	1636	kvaser_pciefd_remove_all_ctrls(pcie);
1908	1637
1909		− /* Turn off IRQ generation */
	1638	+ /* Disable interrupts */
1910	1639	iowrite32(0, pcie->reg_base + KVASER_PCIEFD_SRB_CTRL_REG);
1911		− iowrite32(KVASER_PCIEFD_IRQ_ALL_MSK,
1912		− pcie->reg_base + KVASER_PCIEFD_IRQ_REG);
1913	1640	iowrite32(0, pcie->reg_base + KVASER_PCIEFD_IEN_REG);
1914	1641
1915	1642	free_irq(pcie->pci->irq, pcie);

drivers/net/can/m_can/m_can.c+2−2

@@ -469,7 +469,7 @@ static void m_can_receive_skb(struct m_can_classdev *cdev, · 468 unmodified lines
469	469	int err;
470	470
471	471	err = can_rx_offload_queue_timestamp(&cdev->offload, skb,
472		− timestamp);
	472	+ timestamp);
473	473	if (err)
474	474	stats->rx_fifo_errors++;
475	475	} else {
@@ -895,7 +895,7 @@ static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus, · 419 unmodified lines
895	895	netdev_dbg(dev, "Arbitration phase error detected\n");
896	896	work_done += m_can_handle_lec_err(dev, lec);
897	897	}
898		−
	898	+
899	899	if (is_lec_err(dlec)) {
900	900	netdev_dbg(dev, "Data phase error detected\n");
901	901	work_done += m_can_handle_lec_err(dev, dlec);

drivers/net/can/sja1000/sja1000.c+34−6

@@ -387,6 +387,16 @@ static void sja1000_rx(struct net_device *dev) · 386 unmodified lines
387	387	netif_rx(skb);
388	388	}
389	389
	390	+static irqreturn_t sja1000_reset_interrupt(int irq, void *dev_id)
	391	+{
	392	+ struct net_device dev = (struct net_device )dev_id;
	393	+
	394	+ netdev_dbg(dev, "performing a soft reset upon overrun\n");
	395	+ sja1000_start(dev);
	396	+
	397	+ return IRQ_HANDLED;
	398	+}
	399	+
390	400	static int sja1000_err(struct net_device *dev, uint8_t isrc, uint8_t status)
391	401	{
392	402	struct sja1000_priv *priv = netdev_priv(dev);
@@ -397,6 +407,7 @@ static int sja1000_err(struct net_device *dev, uint8_t isrc, uint8_t status) · 4 unmodified lines
397	407	enum can_state rx_state, tx_state;
398	408	unsigned int rxerr, txerr;
399	409	uint8_t ecc, alc;
	410	+ int ret = 0;
400	411
401	412	skb = alloc_can_err_skb(dev, &cf);
402	413	if (skb == NULL)
@@ -413,6 +424,15 @@ static int sja1000_err(struct net_device *dev, uint8_t isrc, uint8_t status) · 10 unmodified lines
413	424	stats->rx_over_errors++;
414	425	stats->rx_errors++;
415	426	sja1000_write_cmdreg(priv, CMD_CDO); /* clear bit */
	427	+
	428	+ /* Some controllers needs additional handling upon overrun
	429	+ * condition: the controller may sometimes be totally confused
	430	+ * and refuse any new frame while its buffer is empty. The only
	431	+ * way to re-sync the read vs. write buffer offsets is to
	432	+ * stop any current handling and perform a reset.
	433	+ */
	434	+ if (priv->flags & SJA1000_QUIRK_RESET_ON_OVERRUN)
	435	+ ret = IRQ_WAKE_THREAD;
416	436	}
417	437
418	438	if (isrc & IRQ_EI) {
@@ -492,7 +512,7 @@ static int sja1000_err(struct net_device *dev, uint8_t isrc, uint8_t status) · 73 unmodified lines
492	512
493	513	netif_rx(skb);
494	514
495		− return 0;
	515	+ return ret;
496	516	}
497	517
498	518	irqreturn_t sja1000_interrupt(int irq, void *dev_id)
@@ -501,7 +521,8 @@ irqreturn_t sja1000_interrupt(int irq, void *dev_id) · 2 unmodified lines
501	521	struct sja1000_priv *priv = netdev_priv(dev);
502	522	struct net_device_stats *stats = &dev->stats;
503	523	uint8_t isrc, status;
504		− int n = 0;
	524	+ irqreturn_t ret = 0;
	525	+ int n = 0, err;
505	526
506	527	if (priv->pre_irq)
507	528	priv->pre_irq(priv);
@@ -546,19 +567,25 @@ irqreturn_t sja1000_interrupt(int irq, void *dev_id) · 38 unmodified lines
546	567	}
547	568	if (isrc & (IRQ_DOI \| IRQ_EI \| IRQ_BEI \| IRQ_EPI \| IRQ_ALI)) {
548	569	/* error interrupt */
549		− if (sja1000_err(dev, isrc, status))
	570	+ err = sja1000_err(dev, isrc, status);
	571	+ if (err == IRQ_WAKE_THREAD)
	572	+ ret = err;
	573	+ if (err)
550	574	break;
551	575	}
552	576	n++;
553	577	}
554	578	out:
	579	+ if (!ret)
	580	+ ret = (n) ? IRQ_HANDLED : IRQ_NONE;
	581	+
555	582	if (priv->post_irq)
556	583	priv->post_irq(priv);
557	584
558	585	if (n >= SJA1000_MAX_IRQ)
559	586	netdev_dbg(dev, "%d messages handled in ISR", n);
560	587
561		− return (n) ? IRQ_HANDLED : IRQ_NONE;
	588	+ return ret;
562	589	}
563	590	EXPORT_SYMBOL_GPL(sja1000_interrupt);
564	591
@@ -577,8 +604,9 @@ static int sja1000_open(struct net_device *dev) · 12 unmodified lines
577	604
578	605	/* register interrupt handler, if not done by the device driver */
579	606	if (!(priv->flags & SJA1000_CUSTOM_IRQ_HANDLER)) {
580		− err = request_irq(dev->irq, sja1000_interrupt, priv->irq_flags,
581		− dev->name, (void *)dev);
	607	+ err = request_threaded_irq(dev->irq, sja1000_interrupt,
	608	+ sja1000_reset_interrupt,
	609	+ priv->irq_flags, dev->name, (void *)dev);
582	610	if (err) {
583	611	close_candev(dev);
584	612	return -EAGAIN;

drivers/net/can/sja1000/sja1000.h+1−0

@@ -147,6 +147,7 @@ · 146 unmodified lines
147	147	*/
148	148	#define SJA1000_CUSTOM_IRQ_HANDLER BIT(0)
149	149	#define SJA1000_QUIRK_NO_CDR_REG BIT(1)
	150	+#define SJA1000_QUIRK_RESET_ON_OVERRUN BIT(2)
150	151
151	152	/*
152	153	* SJA1000 private data structure

drivers/net/can/sja1000/sja1000_platform.c+4−1

@@ -106,7 +106,7 @@ static void sp_technologic_init(struct sja1000_priv priv, struct device_node o · 105 unmodified lines
106	106
107	107	static void sp_rzn1_init(struct sja1000_priv priv, struct device_node of)
108	108	{
109		− priv->flags = SJA1000_QUIRK_NO_CDR_REG;
	109	+ priv->flags = SJA1000_QUIRK_NO_CDR_REG \| SJA1000_QUIRK_RESET_ON_OVERRUN;
110	110	}
111	111
112	112	static void sp_populate(struct sja1000_priv *priv,
@@ -277,6 +277,9 @@ static int sp_probe(struct platform_device *pdev) · 164 unmodified lines
277	277	priv->irq_flags = IRQF_SHARED;
278	278	}
279	279
	280	+ if (priv->flags & SJA1000_QUIRK_RESET_ON_OVERRUN)
	281	+ priv->irq_flags \|= IRQF_ONESHOT;
	282	+
280	283	dev->irq = irq;
281	284	priv->reg_base = addr;
282	285

drivers/net/can/ti_hecc.c+1−1

@@ -625,7 +625,7 @@ static int ti_hecc_error(struct net_device *ndev, int int_status, · 624 unmodified lines
625	625
626	626	timestamp = hecc_read(priv, HECC_CANLNT);
627	627	err = can_rx_offload_queue_timestamp(&priv->offload, skb,
628		− timestamp);
	628	+ timestamp);
629	629	if (err)
630	630	ndev->stats.rx_fifo_errors++;
631	631	}

drivers/net/can/usb/esd_usb.c+174−178

@@ -3,18 +3,19 @@ · 2 unmodified lines
3	3	* CAN driver for esd electronics gmbh CAN-USB/2 and CAN-USB/Micro
4	4	*
5	5	* Copyright (C) 2010-2012 esd electronic system design gmbh, Matthias Fuchs <socketcan@esd.eu>
6		− * Copyright (C) 2022 esd electronics gmbh, Frank Jungclaus <frank.jungclaus@esd.eu>
	6	+ * Copyright (C) 2022-2023 esd electronics gmbh, Frank Jungclaus <frank.jungclaus@esd.eu>
7	7	*/
8		−#include <linux/ethtool.h>
9		−#include <linux/signal.h>
10		−#include <linux/slab.h>
11		−#include <linux/module.h>
12		−#include <linux/netdevice.h>
13		−#include <linux/usb.h>
14	8
15	9	#include <linux/can.h>
16	10	#include <linux/can/dev.h>
17	11	#include <linux/can/error.h>
	12	+#include <linux/ethtool.h>
	13	+#include <linux/module.h>
	14	+#include <linux/netdevice.h>
	15	+#include <linux/signal.h>
	16	+#include <linux/slab.h>
	17	+#include <linux/units.h>
	18	+#include <linux/usb.h>
18	19
19	20	MODULE_AUTHOR("Matthias Fuchs <socketcan@esd.eu>");
20	21	MODULE_AUTHOR("Frank Jungclaus <frank.jungclaus@esd.eu>");
@@ -22,95 +23,87 @@ MODULE_DESCRIPTION("CAN driver for esd electronics gmbh CAN-USB/2 and CAN-USB/Mi · 1 unmodified line
22	23	MODULE_LICENSE("GPL v2");
23	24
24	25	/* USB vendor and product ID */
25		−#define USB_ESDGMBH_VENDOR_ID 0x0ab4
26		−#define USB_CANUSB2_PRODUCT_ID 0x0010
27		−#define USB_CANUSBM_PRODUCT_ID 0x0011
	26	+#define ESD_USB_ESDGMBH_VENDOR_ID 0x0ab4
	27	+#define ESD_USB_CANUSB2_PRODUCT_ID 0x0010
	28	+#define ESD_USB_CANUSBM_PRODUCT_ID 0x0011
28	29
29	30	/* CAN controller clock frequencies */
30		−#define ESD_USB2_CAN_CLOCK 60000000
31		−#define ESD_USBM_CAN_CLOCK 36000000
	31	+#define ESD_USB_2_CAN_CLOCK (60 * MEGA) /* Hz */
	32	+#define ESD_USB_M_CAN_CLOCK (36 * MEGA) /* Hz */
32	33
33	34	/* Maximum number of CAN nets */
34	35	#define ESD_USB_MAX_NETS 2
35	36
36	37	/* USB commands */
37		−#define CMD_VERSION 1 /* also used for VERSION_REPLY */
38		−#define CMD_CAN_RX 2 /* device to host only */
39		−#define CMD_CAN_TX 3 /* also used for TX_DONE */
40		−#define CMD_SETBAUD 4 /* also used for SETBAUD_REPLY */
41		−#define CMD_TS 5 /* also used for TS_REPLY */
42		−#define CMD_IDADD 6 /* also used for IDADD_REPLY */
	38	+#define ESD_USB_CMD_VERSION 1 /* also used for VERSION_REPLY */
	39	+#define ESD_USB_CMD_CAN_RX 2 /* device to host only */
	40	+#define ESD_USB_CMD_CAN_TX 3 /* also used for TX_DONE */
	41	+#define ESD_USB_CMD_SETBAUD 4 /* also used for SETBAUD_REPLY */
	42	+#define ESD_USB_CMD_TS 5 /* also used for TS_REPLY */
	43	+#define ESD_USB_CMD_IDADD 6 /* also used for IDADD_REPLY */
43	44
44	45	/* esd CAN message flags - dlc field */
45		−#define ESD_RTR 0x10
	46	+#define ESD_USB_RTR BIT(4)
46	47
47	48	/* esd CAN message flags - id field */
48		−#define ESD_EXTID 0x20000000
49		−#define ESD_EVENT 0x40000000
50		−#define ESD_IDMASK 0x1fffffff
	49	+#define ESD_USB_EXTID BIT(29)
	50	+#define ESD_USB_EVENT BIT(30)
	51	+#define ESD_USB_IDMASK GENMASK(28, 0)
51	52
52	53	/* esd CAN event ids */
53		−#define ESD_EV_CAN_ERROR_EXT 2 /* CAN controller specific diagnostic data */
	54	+#define ESD_USB_EV_CAN_ERROR_EXT 2 /* CAN controller specific diagnostic data */
54	55
55	56	/* baudrate message flags */
56		−#define ESD_USB_UBR 0x80000000
57		−#define ESD_USB_LOM 0x40000000
58		−#define ESD_USB_NO_BAUDRATE 0x7fffffff
59		−
60		−/* bit timing CAN-USB/2 */
61		−#define ESD_USB2_TSEG1_MIN 1
62		−#define ESD_USB2_TSEG1_MAX 16
63		−#define ESD_USB2_TSEG1_SHIFT 16
64		−#define ESD_USB2_TSEG2_MIN 1
65		−#define ESD_USB2_TSEG2_MAX 8
66		−#define ESD_USB2_TSEG2_SHIFT 20
67		−#define ESD_USB2_SJW_MAX 4
68		−#define ESD_USB2_SJW_SHIFT 14
69		−#define ESD_USBM_SJW_SHIFT 24
70		−#define ESD_USB2_BRP_MIN 1
71		−#define ESD_USB2_BRP_MAX 1024
72		−#define ESD_USB2_BRP_INC 1
73		−#define ESD_USB2_3_SAMPLES 0x00800000
	57	+#define ESD_USB_LOM BIT(30) /* Listen Only Mode */
	58	+#define ESD_USB_UBR BIT(31) /* User Bit Rate (controller BTR) in bits 0..27 */
	59	+#define ESD_USB_NO_BAUDRATE GENMASK(30, 0) /* bit rate unconfigured */
	60	+
	61	+/* bit timing esd CAN-USB */
	62	+#define ESD_USB_2_TSEG1_SHIFT 16
	63	+#define ESD_USB_2_TSEG2_SHIFT 20
	64	+#define ESD_USB_2_SJW_SHIFT 14
	65	+#define ESD_USB_M_SJW_SHIFT 24
	66	+#define ESD_USB_TRIPLE_SAMPLES BIT(23)
74	67
75	68	/* esd IDADD message */
76		−#define ESD_ID_ENABLE 0x80
77		−#define ESD_MAX_ID_SEGMENT 64
	69	+#define ESD_USB_ID_ENABLE BIT(7)
	70	+#define ESD_USB_MAX_ID_SEGMENT 64
78	71
79	72	/* SJA1000 ECC register (emulated by usb firmware) */
80		−#define SJA1000_ECC_SEG 0x1F
81		−#define SJA1000_ECC_DIR 0x20
82		−#define SJA1000_ECC_ERR 0x06
83		−#define SJA1000_ECC_BIT 0x00
84		−#define SJA1000_ECC_FORM 0x40
85		−#define SJA1000_ECC_STUFF 0x80
86		−#define SJA1000_ECC_MASK 0xc0
	73	+#define ESD_USB_SJA1000_ECC_SEG GENMASK(4, 0)
	74	+#define ESD_USB_SJA1000_ECC_DIR BIT(5)
	75	+#define ESD_USB_SJA1000_ECC_ERR BIT(2, 1)
	76	+#define ESD_USB_SJA1000_ECC_BIT 0x00
	77	+#define ESD_USB_SJA1000_ECC_FORM BIT(6)
	78	+#define ESD_USB_SJA1000_ECC_STUFF BIT(7)
	79	+#define ESD_USB_SJA1000_ECC_MASK GENMASK(7, 6)
87	80
88	81	/* esd bus state event codes */
89		−#define ESD_BUSSTATE_MASK 0xc0
90		−#define ESD_BUSSTATE_WARN 0x40
91		−#define ESD_BUSSTATE_ERRPASSIVE 0x80
92		−#define ESD_BUSSTATE_BUSOFF 0xc0
	82	+#define ESD_USB_BUSSTATE_MASK GENMASK(7, 6)
	83	+#define ESD_USB_BUSSTATE_WARN BIT(6)
	84	+#define ESD_USB_BUSSTATE_ERRPASSIVE BIT(7)
	85	+#define ESD_USB_BUSSTATE_BUSOFF GENMASK(7, 6)
93	86
94		−#define RX_BUFFER_SIZE 1024
95		−#define MAX_RX_URBS 4
96		−#define MAX_TX_URBS 16 /* must be power of 2 */
	87	+#define ESD_USB_RX_BUFFER_SIZE 1024
	88	+#define ESD_USB_MAX_RX_URBS 4
	89	+#define ESD_USB_MAX_TX_URBS 16 /* must be power of 2 */
97	90
98		−struct header_msg {
99		− u8 len; /* len is always the total message length in 32bit words */
	91	+struct esd_usb_header_msg {
	92	+ u8 len; /* total message length in 32bit words */
100	93	u8 cmd;
101	94	u8 rsvd[2];
102	95	};
103	96
104		−struct version_msg {
105		− u8 len;
	97	+struct esd_usb_version_msg {
	98	+ u8 len; /* total message length in 32bit words */
106	99	u8 cmd;
107	100	u8 rsvd;
108	101	u8 flags;
109	102	__le32 drv_version;
110	103	};
111	104
112		−struct version_reply_msg {
113		− u8 len;
	105	+struct esd_usb_version_reply_msg {
	106	+ u8 len; /* total message length in 32bit words */
114	107	u8 cmd;
115	108	u8 nets;
116	109	u8 features;
@@ -120,15 +113,15 @@ struct version_reply_msg { · 3 unmodified lines
120	113	__le32 ts;
121	114	};
122	115
123		−struct rx_msg {
124		− u8 len;
	116	+struct esd_usb_rx_msg {
	117	+ u8 len; /* total message length in 32bit words */
125	118	u8 cmd;
126	119	u8 net;
127	120	u8 dlc;
128	121	__le32 ts;
129	122	__le32 id; /* upper 3 bits contain flags */
130	123	union {
131		− u8 data[8];
	124	+ u8 data[CAN_MAX_DLEN];
132	125	struct {
133	126	u8 status; /* CAN Controller Status */
134	127	u8 ecc; /* Error Capture Register */
@@ -138,18 +131,18 @@ struct rx_msg { · 3 unmodified lines
138	131	};
139	132	};
140	133
141		−struct tx_msg {
142		− u8 len;
	134	+struct esd_usb_tx_msg {
	135	+ u8 len; /* total message length in 32bit words */
143	136	u8 cmd;
144	137	u8 net;
145	138	u8 dlc;
146	139	u32 hnd; /* opaque handle, not used by device */
147	140	__le32 id; /* upper 3 bits contain flags */
148		− u8 data[8];
	141	+ u8 data[CAN_MAX_DLEN];
149	142	};
150	143
151		−struct tx_done_msg {
152		− u8 len;
	144	+struct esd_usb_tx_done_msg {
	145	+ u8 len; /* total message length in 32bit words */
153	146	u8 cmd;
154	147	u8 net;
155	148	u8 status;
@@ -157,16 +150,16 @@ struct tx_done_msg { · 1 unmodified line
157	150	__le32 ts;
158	151	};
159	152
160		−struct id_filter_msg {
161		− u8 len;
	153	+struct esd_usb_id_filter_msg {
	154	+ u8 len; /* total message length in 32bit words */
162	155	u8 cmd;
163	156	u8 net;
164	157	u8 option;
165		− __le32 mask[ESD_MAX_ID_SEGMENT + 1];
	158	+ __le32 mask[ESD_USB_MAX_ID_SEGMENT + 1]; /* +1 for 29bit extended IDs */
166	159	};
167	160
168		−struct set_baudrate_msg {
169		− u8 len;
	161	+struct esd_usb_set_baudrate_msg {
	162	+ u8 len; /* total message length in 32bit words */
170	163	u8 cmd;
171	164	u8 net;
172	165	u8 rsvd;
@@ -175,19 +168,19 @@ struct set_baudrate_msg { · 2 unmodified lines
175	168
176	169	/* Main message type used between library and application */
177	170	union __packed esd_usb_msg {
178		− struct header_msg hdr;
179		− struct version_msg version;
180		− struct version_reply_msg version_reply;
181		− struct rx_msg rx;
182		− struct tx_msg tx;
183		− struct tx_done_msg txdone;
184		− struct set_baudrate_msg setbaud;
185		− struct id_filter_msg filter;
	171	+ struct esd_usb_header_msg hdr;
	172	+ struct esd_usb_version_msg version;
	173	+ struct esd_usb_version_reply_msg version_reply;
	174	+ struct esd_usb_rx_msg rx;
	175	+ struct esd_usb_tx_msg tx;
	176	+ struct esd_usb_tx_done_msg txdone;
	177	+ struct esd_usb_set_baudrate_msg setbaud;
	178	+ struct esd_usb_id_filter_msg filter;
186	179	};
187	180
188	181	static struct usb_device_id esd_usb_table[] = {
189		− {USB_DEVICE(USB_ESDGMBH_VENDOR_ID, USB_CANUSB2_PRODUCT_ID)},
190		− {USB_DEVICE(USB_ESDGMBH_VENDOR_ID, USB_CANUSBM_PRODUCT_ID)},
	182	+ {USB_DEVICE(ESD_USB_ESDGMBH_VENDOR_ID, ESD_USB_CANUSB2_PRODUCT_ID)},
	183	+ {USB_DEVICE(ESD_USB_ESDGMBH_VENDOR_ID, ESD_USB_CANUSBM_PRODUCT_ID)},
191	184	{}
192	185	};
193	186	MODULE_DEVICE_TABLE(usb, esd_usb_table);
@@ -208,8 +201,8 @@ struct esd_usb { · 14 unmodified lines
208	201	int net_count;
209	202	u32 version;
210	203	int rxinitdone;
211		− void *rxbuf[MAX_RX_URBS];
212		− dma_addr_t rxbuf_dma[MAX_RX_URBS];
	204	+ void *rxbuf[ESD_USB_MAX_RX_URBS];
	205	+ dma_addr_t rxbuf_dma[ESD_USB_MAX_RX_URBS];
213	206	};
214	207
215	208	struct esd_usb_net_priv {
@@ -217,7 +210,7 @@ struct esd_usb_net_priv { · 1 unmodified line
217	210
218	211	atomic_t active_tx_jobs;
219	212	struct usb_anchor tx_submitted;
220		− struct esd_tx_urb_context tx_contexts[MAX_TX_URBS];
	213	+ struct esd_tx_urb_context tx_contexts[ESD_USB_MAX_TX_URBS];
221	214
222	215	struct esd_usb *usb;
223	216	struct net_device *netdev;
@@ -232,9 +225,9 @@ static void esd_usb_rx_event(struct esd_usb_net_priv *priv, · 8 unmodified lines
232	225	struct net_device_stats *stats = &priv->netdev->stats;
233	226	struct can_frame *cf;
234	227	struct sk_buff *skb;
235		− u32 id = le32_to_cpu(msg->rx.id) & ESD_IDMASK;
	228	+ u32 id = le32_to_cpu(msg->rx.id) & ESD_USB_IDMASK;
236	229
237		− if (id == ESD_EV_CAN_ERROR_EXT) {
	230	+ if (id == ESD_USB_EV_CAN_ERROR_EXT) {
238	231	u8 state = msg->rx.ev_can_err_ext.status;
239	232	u8 ecc = msg->rx.ev_can_err_ext.ecc;
240	233
@@ -261,15 +254,15 @@ static void esd_usb_rx_event(struct esd_usb_net_priv *priv, · 20 unmodified lines
261	254
262	255	priv->old_state = state;
263	256
264		− switch (state & ESD_BUSSTATE_MASK) {
265		− case ESD_BUSSTATE_BUSOFF:
	257	+ switch (state & ESD_USB_BUSSTATE_MASK) {
	258	+ case ESD_USB_BUSSTATE_BUSOFF:
266	259	new_state = CAN_STATE_BUS_OFF;
267	260	can_bus_off(priv->netdev);
268	261	break;
269		− case ESD_BUSSTATE_WARN:
	262	+ case ESD_USB_BUSSTATE_WARN:
270	263	new_state = CAN_STATE_ERROR_WARNING;
271	264	break;
272		− case ESD_BUSSTATE_ERRPASSIVE:
	265	+ case ESD_USB_BUSSTATE_ERRPASSIVE:
273	266	new_state = CAN_STATE_ERROR_PASSIVE;
274	267	break;
275	268	default:
@@ -291,14 +284,14 @@ static void esd_usb_rx_event(struct esd_usb_net_priv *priv, · 15 unmodified lines
291	284
292	285	cf->can_id \|= CAN_ERR_PROT \| CAN_ERR_BUSERROR;
293	286
294		− switch (ecc & SJA1000_ECC_MASK) {
295		− case SJA1000_ECC_BIT:
	287	+ switch (ecc & ESD_USB_SJA1000_ECC_MASK) {
	288	+ case ESD_USB_SJA1000_ECC_BIT:
296	289	cf->data[2] \|= CAN_ERR_PROT_BIT;
297	290	break;
298		− case SJA1000_ECC_FORM:
	291	+ case ESD_USB_SJA1000_ECC_FORM:
299	292	cf->data[2] \|= CAN_ERR_PROT_FORM;
300	293	break;
301		− case SJA1000_ECC_STUFF:
	294	+ case ESD_USB_SJA1000_ECC_STUFF:
302	295	cf->data[2] \|= CAN_ERR_PROT_STUFF;
303	296	break;
304	297	default:
@@ -306,11 +299,11 @@ static void esd_usb_rx_event(struct esd_usb_net_priv *priv, · 1 unmodified line
306	299	}
307	300
308	301	/* Error occurred during transmission? */
309		− if (!(ecc & SJA1000_ECC_DIR))
	302	+ if (!(ecc & ESD_USB_SJA1000_ECC_DIR))
310	303	cf->data[2] \|= CAN_ERR_PROT_TX;
311	304
312	305	/* Bit stream position in CAN frame as the error was detected */
313		− cf->data[3] = ecc & SJA1000_ECC_SEG;
	306	+ cf->data[3] = ecc & ESD_USB_SJA1000_ECC_SEG;
314	307	}
315	308
316	309	if (skb) {
@@ -337,7 +330,7 @@ static void esd_usb_rx_can_msg(struct esd_usb_net_priv *priv, · 20 unmodified lines
337	330
338	331	id = le32_to_cpu(msg->rx.id);
339	332
340		− if (id & ESD_EVENT) {
	333	+ if (id & ESD_USB_EVENT) {
341	334	esd_usb_rx_event(priv, msg);
342	335	} else {
343	336	skb = alloc_can_skb(priv->netdev, &cf);
@@ -346,14 +339,14 @@ static void esd_usb_rx_can_msg(struct esd_usb_net_priv *priv, · 2 unmodified lines
346	339	return;
347	340	}
348	341
349		− cf->can_id = id & ESD_IDMASK;
350		− can_frame_set_cc_len(cf, msg->rx.dlc & ~ESD_RTR,
	342	+ cf->can_id = id & ESD_USB_IDMASK;
	343	+ can_frame_set_cc_len(cf, msg->rx.dlc & ~ESD_USB_RTR,
351	344	priv->can.ctrlmode);
352	345
353		− if (id & ESD_EXTID)
	346	+ if (id & ESD_USB_EXTID)
354	347	cf->can_id \|= CAN_EFF_FLAG;
355	348
356		− if (msg->rx.dlc & ESD_RTR) {
	349	+ if (msg->rx.dlc & ESD_USB_RTR) {
357	350	cf->can_id \|= CAN_RTR_FLAG;
358	351	} else {
359	352	for (i = 0; i < cf->len; i++)
@@ -377,7 +370,7 @@ static void esd_usb_tx_done_msg(struct esd_usb_net_priv *priv, · 17 unmodified lines
377	370	if (!netif_device_present(netdev))
378	371	return;
379	372
380		− context = &priv->tx_contexts[msg->txdone.hnd & (MAX_TX_URBS - 1)];
	373	+ context = &priv->tx_contexts[msg->txdone.hnd & (ESD_USB_MAX_TX_URBS - 1)];
381	374
382	375	if (!msg->txdone.status) {
383	376	stats->tx_packets++;
@@ -389,7 +382,7 @@ static void esd_usb_tx_done_msg(struct esd_usb_net_priv *priv, · 5 unmodified lines
389	382	}
390	383
391	384	/* Release context */
392		− context->echo_index = MAX_TX_URBS;
	385	+ context->echo_index = ESD_USB_MAX_TX_URBS;
393	386	atomic_dec(&priv->active_tx_jobs);
394	387
395	388	netif_wake_queue(netdev);
@@ -424,7 +417,7 @@ static void esd_usb_read_bulk_callback(struct urb *urb) · 28 unmodified lines
424	417	msg = (union esd_usb_msg *)(urb->transfer_buffer + pos);
425	418
426	419	switch (msg->hdr.cmd) {
427		− case CMD_CAN_RX:
	420	+ case ESD_USB_CMD_CAN_RX:
428	421	if (msg->rx.net >= dev->net_count) {
429	422	dev_err(dev->udev->dev.parent, "format error\n");
430	423	break;
@@ -433,7 +426,7 @@ static void esd_usb_read_bulk_callback(struct urb *urb) · 2 unmodified lines
433	426	esd_usb_rx_can_msg(dev->nets[msg->rx.net], msg);
434	427	break;
435	428
436		− case CMD_CAN_TX:
	429	+ case ESD_USB_CMD_CAN_TX:
437	430	if (msg->txdone.net >= dev->net_count) {
438	431	dev_err(dev->udev->dev.parent, "format error\n");
439	432	break;
@@ -444,7 +437,7 @@ static void esd_usb_read_bulk_callback(struct urb *urb) · 4 unmodified lines
444	437	break;
445	438	}
446	439
447		− pos += msg->hdr.len << 2;
	440	+ pos += msg->hdr.len * sizeof(u32); /* convert to # of bytes */
448	441
449	442	if (pos > urb->actual_length) {
450	443	dev_err(dev->udev->dev.parent, "format error\n");
@@ -454,7 +447,7 @@ static void esd_usb_read_bulk_callback(struct urb *urb) · 3 unmodified lines
454	447
455	448	resubmit_urb:
456	449	usb_fill_bulk_urb(urb, dev->udev, usb_rcvbulkpipe(dev->udev, 1),
457		− urb->transfer_buffer, RX_BUFFER_SIZE,
	450	+ urb->transfer_buffer, ESD_USB_RX_BUFFER_SIZE,
458	451	esd_usb_read_bulk_callback, dev);
459	452
460	453	retval = usb_submit_urb(urb, GFP_ATOMIC);
@@ -538,7 +531,7 @@ static int esd_usb_send_msg(struct esd_usb dev, union esd_usb_msg msg) · 77 unmodified lines
538	531	return usb_bulk_msg(dev->udev,
539	532	usb_sndbulkpipe(dev->udev, 2),
540	533	msg,
541		− msg->hdr.len << 2,
	534	+ msg->hdr.len * sizeof(u32), /* convert to # of bytes */
542	535	&actual_length,
543	536	1000);
544	537	}
@@ -563,7 +556,7 @@ static int esd_usb_setup_rx_urbs(struct esd_usb *dev) · 18 unmodified lines
563	556	if (dev->rxinitdone)
564	557	return 0;
565	558
566		− for (i = 0; i < MAX_RX_URBS; i++) {
	559	+ for (i = 0; i < ESD_USB_MAX_RX_URBS; i++) {
567	560	struct urb *urb = NULL;
568	561	u8 *buf = NULL;
569	562	dma_addr_t buf_dma;
@@ -575,7 +568,7 @@ static int esd_usb_setup_rx_urbs(struct esd_usb *dev) · 5 unmodified lines
575	568	break;
576	569	}
577	570
578		− buf = usb_alloc_coherent(dev->udev, RX_BUFFER_SIZE, GFP_KERNEL,
	571	+ buf = usb_alloc_coherent(dev->udev, ESD_USB_RX_BUFFER_SIZE, GFP_KERNEL,
579	572	&buf_dma);
580	573	if (!buf) {
581	574	dev_warn(dev->udev->dev.parent,
@@ -588,7 +581,7 @@ static int esd_usb_setup_rx_urbs(struct esd_usb *dev) · 6 unmodified lines
588	581
589	582	usb_fill_bulk_urb(urb, dev->udev,
590	583	usb_rcvbulkpipe(dev->udev, 1),
591		− buf, RX_BUFFER_SIZE,
	584	+ buf, ESD_USB_RX_BUFFER_SIZE,
592	585	esd_usb_read_bulk_callback, dev);
593	586	urb->transfer_flags \|= URB_NO_TRANSFER_DMA_MAP;
594	587	usb_anchor_urb(urb, &dev->rx_submitted);
@@ -596,7 +589,7 @@ static int esd_usb_setup_rx_urbs(struct esd_usb *dev) · 1 unmodified line
596	589	err = usb_submit_urb(urb, GFP_KERNEL);
597	590	if (err) {
598	591	usb_unanchor_urb(urb);
599		− usb_free_coherent(dev->udev, RX_BUFFER_SIZE, buf,
	592	+ usb_free_coherent(dev->udev, ESD_USB_RX_BUFFER_SIZE, buf,
600	593	urb->transfer_dma);
601	594	goto freeurb;
602	595	}
@@ -618,7 +611,7 @@ freeurb: · 15 unmodified lines
618	611	}
619	612
620	613	/* Warn if we've couldn't transmit all the URBs */
621		− if (i < MAX_RX_URBS) {
	614	+ if (i < ESD_USB_MAX_RX_URBS) {
622	615	dev_warn(dev->udev->dev.parent,
623	616	"rx performance may be slow\n");
624	617	}
@@ -653,14 +646,14 @@ static int esd_usb_start(struct esd_usb_net_priv *priv) · 28 unmodified lines
653	646	* the number of the starting bitmask (0..64) to the filter.option
654	647	* field followed by only some bitmasks.
655	648	*/
656		− msg->hdr.cmd = CMD_IDADD;
657		− msg->hdr.len = 2 + ESD_MAX_ID_SEGMENT;
	649	+ msg->hdr.cmd = ESD_USB_CMD_IDADD;
	650	+ msg->hdr.len = sizeof(struct esd_usb_id_filter_msg) / sizeof(u32); /* # of 32bit words */
658	651	msg->filter.net = priv->index;
659		− msg->filter.option = ESD_ID_ENABLE; /* start with segment 0 */
660		− for (i = 0; i < ESD_MAX_ID_SEGMENT; i++)
661		− msg->filter.mask[i] = cpu_to_le32(0xffffffff);
	652	+ msg->filter.option = ESD_USB_ID_ENABLE; /* start with segment 0 */
	653	+ for (i = 0; i < ESD_USB_MAX_ID_SEGMENT; i++)
	654	+ msg->filter.mask[i] = cpu_to_le32(GENMASK(31, 0));
662	655	/* enable 29bit extended IDs */
663		− msg->filter.mask[ESD_MAX_ID_SEGMENT] = cpu_to_le32(0x00000001);
	656	+ msg->filter.mask[ESD_USB_MAX_ID_SEGMENT] = cpu_to_le32(BIT(0));
664	657
665	658	err = esd_usb_send_msg(dev, msg);
666	659	if (err)
@@ -689,8 +682,8 @@ static void unlink_all_urbs(struct esd_usb *dev) · 22 unmodified lines
689	682
690	683	usb_kill_anchored_urbs(&dev->rx_submitted);
691	684
692		− for (i = 0; i < MAX_RX_URBS; ++i)
693		− usb_free_coherent(dev->udev, RX_BUFFER_SIZE,
	685	+ for (i = 0; i < ESD_USB_MAX_RX_URBS; ++i)
	686	+ usb_free_coherent(dev->udev, ESD_USB_RX_BUFFER_SIZE,
694	687	dev->rxbuf[i], dev->rxbuf_dma[i]);
695	688
696	689	for (i = 0; i < dev->net_count; i++) {
@@ -699,8 +692,8 @@ static void unlink_all_urbs(struct esd_usb *dev) · 2 unmodified lines
699	692	usb_kill_anchored_urbs(&priv->tx_submitted);
700	693	atomic_set(&priv->active_tx_jobs, 0);
701	694
702		− for (j = 0; j < MAX_TX_URBS; j++)
703		− priv->tx_contexts[j].echo_index = MAX_TX_URBS;
	695	+ for (j = 0; j < ESD_USB_MAX_TX_URBS; j++)
	696	+ priv->tx_contexts[j].echo_index = ESD_USB_MAX_TX_URBS;
704	697	}
705	698	}
706	699	}
@@ -765,25 +758,27 @@ static netdev_tx_t esd_usb_start_xmit(struct sk_buff *skb, · 58 unmodified lines
765	758
766	759	msg = (union esd_usb_msg *)buf;
767	760
768		− msg->hdr.len = 3; /* minimal length */
769		− msg->hdr.cmd = CMD_CAN_TX;
	761	+ /* minimal length as # of 32bit words */
	762	+ msg->hdr.len = offsetof(struct esd_usb_tx_msg, data) / sizeof(u32);
	763	+ msg->hdr.cmd = ESD_USB_CMD_CAN_TX;
770	764	msg->tx.net = priv->index;
771	765	msg->tx.dlc = can_get_cc_dlc(cf, priv->can.ctrlmode);
772	766	msg->tx.id = cpu_to_le32(cf->can_id & CAN_ERR_MASK);
773	767
774	768	if (cf->can_id & CAN_RTR_FLAG)
775		− msg->tx.dlc \|= ESD_RTR;
	769	+ msg->tx.dlc \|= ESD_USB_RTR;
776	770
777	771	if (cf->can_id & CAN_EFF_FLAG)
778		− msg->tx.id \|= cpu_to_le32(ESD_EXTID);
	772	+ msg->tx.id \|= cpu_to_le32(ESD_USB_EXTID);
779	773
780	774	for (i = 0; i < cf->len; i++)
781	775	msg->tx.data[i] = cf->data[i];
782	776
783		− msg->hdr.len += (cf->len + 3) >> 2;
	777	+ /* round up, then divide by 4 to add the payload length as # of 32bit words */
	778	+ msg->hdr.len += DIV_ROUND_UP(cf->len, sizeof(u32));
784	779
785		− for (i = 0; i < MAX_TX_URBS; i++) {
786		− if (priv->tx_contexts[i].echo_index == MAX_TX_URBS) {
	780	+ for (i = 0; i < ESD_USB_MAX_TX_URBS; i++) {
	781	+ if (priv->tx_contexts[i].echo_index == ESD_USB_MAX_TX_URBS) {
787	782	context = &priv->tx_contexts[i];
788	783	break;
789	784	}
@@ -800,10 +795,10 @@ static netdev_tx_t esd_usb_start_xmit(struct sk_buff *skb, · 10 unmodified lines
800	795	context->echo_index = i;
801	796
802	797	/* hnd must not be 0 - MSB is stripped in txdone handling */
803		− msg->tx.hnd = 0x80000000 \| i; /* returned in TX done message */
	798	+ msg->tx.hnd = BIT(31) \| i; /* returned in TX done message */
804	799
805	800	usb_fill_bulk_urb(urb, dev->udev, usb_sndbulkpipe(dev->udev, 2), buf,
806		− msg->hdr.len << 2,
	801	+ msg->hdr.len * sizeof(u32), /* convert to # of bytes */
807	802	esd_usb_write_bulk_callback, context);
808	803
809	804	urb->transfer_flags \|= URB_NO_TRANSFER_DMA_MAP;
@@ -815,7 +810,7 @@ static netdev_tx_t esd_usb_start_xmit(struct sk_buff *skb, · 5 unmodified lines
815	810	atomic_inc(&priv->active_tx_jobs);
816	811
817	812	/* Slow down tx path */
818		− if (atomic_read(&priv->active_tx_jobs) >= MAX_TX_URBS)
	813	+ if (atomic_read(&priv->active_tx_jobs) >= ESD_USB_MAX_TX_URBS)
819	814	netif_stop_queue(netdev);
820	815
821	816	err = usb_submit_urb(urb, GFP_ATOMIC);
@@ -865,18 +860,18 @@ static int esd_usb_close(struct net_device *netdev) · 43 unmodified lines
865	860	return -ENOMEM;
866	861
867	862	/* Disable all IDs (see esd_usb_start()) */
868		− msg->hdr.cmd = CMD_IDADD;
869		− msg->hdr.len = 2 + ESD_MAX_ID_SEGMENT;
	863	+ msg->hdr.cmd = ESD_USB_CMD_IDADD;
	864	+ msg->hdr.len = sizeof(struct esd_usb_id_filter_msg) / sizeof(u32);/* # of 32bit words */
870	865	msg->filter.net = priv->index;
871		− msg->filter.option = ESD_ID_ENABLE; /* start with segment 0 */
872		− for (i = 0; i <= ESD_MAX_ID_SEGMENT; i++)
	866	+ msg->filter.option = ESD_USB_ID_ENABLE; /* start with segment 0 */
	867	+ for (i = 0; i <= ESD_USB_MAX_ID_SEGMENT; i++)
873	868	msg->filter.mask[i] = 0;
874	869	if (esd_usb_send_msg(priv->usb, msg) < 0)
875	870	netdev_err(netdev, "sending idadd message failed\n");
876	871
877	872	/* set CAN controller to reset mode */
878		− msg->hdr.len = 2;
879		− msg->hdr.cmd = CMD_SETBAUD;
	873	+ msg->hdr.len = sizeof(struct esd_usb_set_baudrate_msg) / sizeof(u32); /* # of 32bit words */
	874	+ msg->hdr.cmd = ESD_USB_CMD_SETBAUD;
880	875	msg->setbaud.net = priv->index;
881	876	msg->setbaud.rsvd = 0;
882	877	msg->setbaud.baud = cpu_to_le32(ESD_USB_NO_BAUDRATE);
@@ -905,20 +900,21 @@ static const struct ethtool_ops esd_usb_ethtool_ops = { · 22 unmodified lines
905	900	.get_ts_info = ethtool_op_get_ts_info,
906	901	};
907	902
908		−static const struct can_bittiming_const esd_usb2_bittiming_const = {
909		− .name = "esd_usb2",
910		− .tseg1_min = ESD_USB2_TSEG1_MIN,
911		− .tseg1_max = ESD_USB2_TSEG1_MAX,
912		− .tseg2_min = ESD_USB2_TSEG2_MIN,
913		− .tseg2_max = ESD_USB2_TSEG2_MAX,
914		− .sjw_max = ESD_USB2_SJW_MAX,
915		− .brp_min = ESD_USB2_BRP_MIN,
916		− .brp_max = ESD_USB2_BRP_MAX,
917		− .brp_inc = ESD_USB2_BRP_INC,
	903	+static const struct can_bittiming_const esd_usb_2_bittiming_const = {
	904	+ .name = "esd_usb_2",
	905	+ .tseg1_min = 1,
	906	+ .tseg1_max = 16,
	907	+ .tseg2_min = 1,
	908	+ .tseg2_max = 8,
	909	+ .sjw_max = 4,
	910	+ .brp_min = 1,
	911	+ .brp_max = 1024,
	912	+ .brp_inc = 1,
918	913	};
919	914
920		−static int esd_usb2_set_bittiming(struct net_device *netdev)
	915	+static int esd_usb_2_set_bittiming(struct net_device *netdev)
921	916	{
	917	+ const struct can_bittiming_const *btc = &esd_usb_2_bittiming_const;
922	918	struct esd_usb_net_priv *priv = netdev_priv(netdev);
923	919	struct can_bittiming *bt = &priv->can.bittiming;
924	920	union esd_usb_msg *msg;
@@ -930,35 +926,35 @@ static int esd_usb2_set_bittiming(struct net_device *netdev) · 5 unmodified lines
930	926	if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
931	927	canbtr \|= ESD_USB_LOM;
932	928
933		− canbtr \|= (bt->brp - 1) & (ESD_USB2_BRP_MAX - 1);
	929	+ canbtr \|= (bt->brp - 1) & (btc->brp_max - 1);
934	930
935	931	if (le16_to_cpu(priv->usb->udev->descriptor.idProduct) ==
936		− USB_CANUSBM_PRODUCT_ID)
937		− sjw_shift = ESD_USBM_SJW_SHIFT;
	932	+ ESD_USB_CANUSBM_PRODUCT_ID)
	933	+ sjw_shift = ESD_USB_M_SJW_SHIFT;
938	934	else
939		− sjw_shift = ESD_USB2_SJW_SHIFT;
	935	+ sjw_shift = ESD_USB_2_SJW_SHIFT;
940	936
941		− canbtr \|= ((bt->sjw - 1) & (ESD_USB2_SJW_MAX - 1))
	937	+ canbtr \|= ((bt->sjw - 1) & (btc->sjw_max - 1))
942	938	<< sjw_shift;
943	939	canbtr \|= ((bt->prop_seg + bt->phase_seg1 - 1)
944		− & (ESD_USB2_TSEG1_MAX - 1))
945		− << ESD_USB2_TSEG1_SHIFT;
946		− canbtr \|= ((bt->phase_seg2 - 1) & (ESD_USB2_TSEG2_MAX - 1))
947		− << ESD_USB2_TSEG2_SHIFT;
	940	+ & (btc->tseg1_max - 1))
	941	+ << ESD_USB_2_TSEG1_SHIFT;
	942	+ canbtr \|= ((bt->phase_seg2 - 1) & (btc->tseg2_max - 1))
	943	+ << ESD_USB_2_TSEG2_SHIFT;
948	944	if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
949		− canbtr \|= ESD_USB2_3_SAMPLES;
	945	+ canbtr \|= ESD_USB_TRIPLE_SAMPLES;
950	946
951	947	msg = kmalloc(sizeof(*msg), GFP_KERNEL);
952	948	if (!msg)
953	949	return -ENOMEM;
954	950
955		− msg->hdr.len = 2;
956		− msg->hdr.cmd = CMD_SETBAUD;
	951	+ msg->hdr.len = sizeof(struct esd_usb_set_baudrate_msg) / sizeof(u32); /* # of 32bit words */
	952	+ msg->hdr.cmd = ESD_USB_CMD_SETBAUD;
957	953	msg->setbaud.net = priv->index;
958	954	msg->setbaud.rsvd = 0;
959	955	msg->setbaud.baud = cpu_to_le32(canbtr);
960	956
961		− netdev_info(netdev, "setting BTR=%#x\n", canbtr);
	957	+ netdev_dbg(netdev, "setting BTR=%#x\n", canbtr);
962	958
963	959	err = esd_usb_send_msg(priv->usb, msg);
964	960
@@ -999,7 +995,7 @@ static int esd_usb_probe_one_net(struct usb_interface *intf, int index) · 34 unmodified lines
999	995	int err = 0;
1000	996	int i;
1001	997
1002		− netdev = alloc_candev(sizeof(*priv), MAX_TX_URBS);
	998	+ netdev = alloc_candev(sizeof(*priv), ESD_USB_MAX_TX_URBS);
1003	999	if (!netdev) {
1004	1000	dev_err(&intf->dev, "couldn't alloc candev\n");
1005	1001	err = -ENOMEM;
@@ -1011,8 +1007,8 @@ static int esd_usb_probe_one_net(struct usb_interface *intf, int index) · 5 unmodified lines
1011	1007	init_usb_anchor(&priv->tx_submitted);
1012	1008	atomic_set(&priv->active_tx_jobs, 0);
1013	1009
1014		− for (i = 0; i < MAX_TX_URBS; i++)
1015		− priv->tx_contexts[i].echo_index = MAX_TX_URBS;
	1010	+ for (i = 0; i < ESD_USB_MAX_TX_URBS; i++)
	1011	+ priv->tx_contexts[i].echo_index = ESD_USB_MAX_TX_URBS;
1016	1012
1017	1013	priv->usb = dev;
1018	1014	priv->netdev = netdev;
@@ -1024,15 +1020,15 @@ static int esd_usb_probe_one_net(struct usb_interface *intf, int index) · 5 unmodified lines
1024	1020	CAN_CTRLMODE_BERR_REPORTING;
1025	1021
1026	1022	if (le16_to_cpu(dev->udev->descriptor.idProduct) ==
1027		− USB_CANUSBM_PRODUCT_ID)
1028		− priv->can.clock.freq = ESD_USBM_CAN_CLOCK;
	1023	+ ESD_USB_CANUSBM_PRODUCT_ID)
	1024	+ priv->can.clock.freq = ESD_USB_M_CAN_CLOCK;
1029	1025	else {
1030		− priv->can.clock.freq = ESD_USB2_CAN_CLOCK;
	1026	+ priv->can.clock.freq = ESD_USB_2_CAN_CLOCK;
1031	1027	priv->can.ctrlmode_supported \|= CAN_CTRLMODE_3_SAMPLES;
1032	1028	}
1033	1029
1034		− priv->can.bittiming_const = &esd_usb2_bittiming_const;
1035		− priv->can.do_set_bittiming = esd_usb2_set_bittiming;
	1030	+ priv->can.bittiming_const = &esd_usb_2_bittiming_const;
	1031	+ priv->can.do_set_bittiming = esd_usb_2_set_bittiming;
1036	1032	priv->can.do_set_mode = esd_usb_set_mode;
1037	1033	priv->can.do_get_berr_counter = esd_usb_get_berr_counter;
1038	1034
@@ -1090,8 +1086,8 @@ static int esd_usb_probe(struct usb_interface *intf, · 51 unmodified lines
1090	1086	}
1091	1087
1092	1088	/* query number of CAN interfaces (nets) */
1093		− msg->hdr.cmd = CMD_VERSION;
1094		− msg->hdr.len = 2;
	1089	+ msg->hdr.cmd = ESD_USB_CMD_VERSION;
	1090	+ msg->hdr.len = sizeof(struct esd_usb_version_msg) / sizeof(u32); /* # of 32bit words */
1095	1091	msg->version.rsvd = 0;
1096	1092	msg->version.flags = 0;
1097	1093	msg->version.drv_version = 0;

drivers/net/can/usb/kvaser_usb/kvaser_usb_core.c+1−1

@@ -816,7 +816,7 @@ static int kvaser_usb_init_one(struct kvaser_usb *dev, int channel) · 815 unmodified lines
816	816	init_completion(&priv->stop_comp);
817	817	init_completion(&priv->flush_comp);
818	818	init_completion(&priv->get_busparams_comp);
819		− priv->can.ctrlmode_supported = 0;
	819	+ priv->can.ctrlmode_supported = CAN_CTRLMODE_CC_LEN8_DLC;
820	820
821	821	priv->dev = dev;
822	822	priv->netdev = netdev;

drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c+9−4

@@ -1263,7 +1263,7 @@ static void kvaser_usb_hydra_rx_msg_std(const struct kvaser_usb *dev, · 1262 unmodified lines
1263	1263	if (flags & KVASER_USB_HYDRA_CF_FLAG_OVERRUN)
1264	1264	kvaser_usb_can_rx_over_error(priv->netdev);
1265	1265
1266		− cf->len = can_cc_dlc2len(cmd->rx_can.dlc);
	1266	+ can_frame_set_cc_len((struct can_frame *)cf, cmd->rx_can.dlc, priv->can.ctrlmode);
1267	1267
1268	1268	if (flags & KVASER_USB_HYDRA_CF_FLAG_REMOTE_FRAME) {
1269	1269	cf->can_id \|= CAN_RTR_FLAG;
@@ -1342,7 +1342,7 @@ static void kvaser_usb_hydra_rx_msg_ext(const struct kvaser_usb *dev, · 72 unmodified lines
1342	1342	if (flags & KVASER_USB_HYDRA_CF_FLAG_ESI)
1343	1343	cf->flags \|= CANFD_ESI;
1344	1344	} else {
1345		− cf->len = can_cc_dlc2len(dlc);
	1345	+ can_frame_set_cc_len((struct can_frame *)cf, dlc, priv->can.ctrlmode);
1346	1346	}
1347	1347
1348	1348	if (flags & KVASER_USB_HYDRA_CF_FLAG_REMOTE_FRAME) {
@@ -1442,7 +1442,7 @@ kvaser_usb_hydra_frame_to_cmd_ext(const struct kvaser_usb_net_priv *priv, · 93 unmodified lines
1442	1442	struct kvaser_usb *dev = priv->dev;
1443	1443	struct kvaser_cmd_ext *cmd;
1444	1444	struct canfd_frame cf = (struct canfd_frame )skb->data;
1445		− u8 dlc = can_fd_len2dlc(cf->len);
	1445	+ u8 dlc;
1446	1446	u8 nbr_of_bytes = cf->len;
1447	1447	u32 flags;
1448	1448	u32 id;
@@ -1467,6 +1467,11 @@ kvaser_usb_hydra_frame_to_cmd_ext(const struct kvaser_usb_net_priv *priv, · 18 unmodified lines
1467	1467
1468	1468	cmd->len = cpu_to_le16(*cmd_len);
1469	1469
	1470	+ if (can_is_canfd_skb(skb))
	1471	+ dlc = can_fd_len2dlc(cf->len);
	1472	+ else
	1473	+ dlc = can_get_cc_dlc((struct can_frame *)cf, priv->can.ctrlmode);
	1474	+
1470	1475	cmd->tx_can.databytes = nbr_of_bytes;
1471	1476	cmd->tx_can.dlc = dlc;
1472	1477
@@ -1542,7 +1547,7 @@ kvaser_usb_hydra_frame_to_cmd_std(const struct kvaser_usb_net_priv *priv, · 69 unmodified lines
1542	1547	id = cf->can_id & CAN_SFF_MASK;
1543	1548	}
1544	1549
1545		− cmd->tx_can.dlc = cf->len;
	1550	+ cmd->tx_can.dlc = can_get_cc_dlc(cf, priv->can.ctrlmode);
1546	1551
1547	1552	flags = (cf->can_id & CAN_EFF_FLAG ?
1548	1553	KVASER_USB_HYDRA_CF_FLAG_EXTENDED_ID : 0);

drivers/net/can/usb/kvaser_usb/kvaser_usb_leaf.c+3−3

@@ -573,7 +573,7 @@ kvaser_usb_leaf_frame_to_cmd(const struct kvaser_usb_net_priv *priv, · 572 unmodified lines
573	573	cmd->u.tx_can.data[1] = cf->can_id & 0x3f;
574	574	}
575	575
576		− cmd->u.tx_can.data[5] = cf->len;
	576	+ cmd->u.tx_can.data[5] = can_get_cc_dlc(cf, priv->can.ctrlmode);
577	577	memcpy(&cmd->u.tx_can.data[6], cf->data, cf->len);
578	578
579	579	if (cf->can_id & CAN_RTR_FLAG)
@@ -1349,7 +1349,7 @@ static void kvaser_usb_leaf_rx_can_msg(const struct kvaser_usb *dev, · 769 unmodified lines
1349	1349	else
1350	1350	cf->can_id &= CAN_SFF_MASK;
1351	1351
1352		− cf->len = can_cc_dlc2len(cmd->u.leaf.log_message.dlc);
	1352	+ can_frame_set_cc_len(cf, cmd->u.leaf.log_message.dlc & 0xF, priv->can.ctrlmode);
1353	1353
1354	1354	if (cmd->u.leaf.log_message.flags & MSG_FLAG_REMOTE_FRAME)
1355	1355	cf->can_id \|= CAN_RTR_FLAG;
@@ -1367,7 +1367,7 @@ static void kvaser_usb_leaf_rx_can_msg(const struct kvaser_usb *dev, · 11 unmodified lines
1367	1367	cf->can_id \|= CAN_EFF_FLAG;
1368	1368	}
1369	1369
1370		− cf->len = can_cc_dlc2len(rx_data[5]);
	1370	+ can_frame_set_cc_len(cf, rx_data[5] & 0xF, priv->can.ctrlmode);
1371	1371
1372	1372	if (cmd->u.rx_can_header.flag & MSG_FLAG_REMOTE_FRAME)
1373	1373	cf->can_id \|= CAN_RTR_FLAG;

drivers/net/can/xilinx_can.c+19−0

@@ -28,6 +28,7 @@ · 27 unmodified lines
28	28	#include <linux/types.h>
29	29	#include <linux/can/dev.h>
30	30	#include <linux/can/error.h>
	31	+#include <linux/phy/phy.h>
31	32	#include <linux/pm_runtime.h>
32	33
33	34	#define DRIVER_NAME "xilinx_can"
@@ -198,6 +199,7 @@ struct xcan_devtype_data { · 164 unmodified lines
198	199	* @bus_clk: Pointer to struct clk
199	200	* @can_clk: Pointer to struct clk
200	201	* @devtype: Device type specific constants
	202	+ * @transceiver: Optional pointer to associated CAN transceiver
201	203	*/
202	204	struct xcan_priv {
203	205	struct can_priv can;
@@ -215,6 +217,7 @@ struct xcan_priv { · 11 unmodified lines
215	217	struct clk *bus_clk;
216	218	struct clk *can_clk;
217	219	struct xcan_devtype_data devtype;
	220	+ struct phy *transceiver;
218	221	};
219	222
220	223	/* CAN Bittiming constants as per Xilinx CAN specs */
@@ -1419,6 +1422,10 @@ static int xcan_open(struct net_device *ndev) · 1198 unmodified lines
1419	1422	struct xcan_priv *priv = netdev_priv(ndev);
1420	1423	int ret;
1421	1424
	1425	+ ret = phy_power_on(priv->transceiver);
	1426	+ if (ret)
	1427	+ return ret;
	1428	+
1422	1429	ret = pm_runtime_get_sync(priv->dev);
1423	1430	if (ret < 0) {
1424	1431	netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n",
@@ -1462,6 +1469,7 @@ err_irq: · 37 unmodified lines
1462	1469	free_irq(ndev->irq, ndev);
1463	1470	err:
1464	1471	pm_runtime_put(priv->dev);
	1472	+ phy_power_off(priv->transceiver);
1465	1473
1466	1474	return ret;
1467	1475	}
@@ -1483,6 +1491,7 @@ static int xcan_close(struct net_device *ndev) · 15 unmodified lines
1483	1491	close_candev(ndev);
1484	1492
1485	1493	pm_runtime_put(priv->dev);
	1494	+ phy_power_off(priv->transceiver);
1486	1495
1487	1496	return 0;
1488	1497	}
@@ -1713,6 +1722,7 @@ static int xcan_probe(struct platform_device *pdev) · 224 unmodified lines
1713	1722	{
1714	1723	struct net_device *ndev;
1715	1724	struct xcan_priv *priv;
	1725	+ struct phy *transceiver;
1716	1726	const struct of_device_id *of_id;
1717	1727	const struct xcan_devtype_data *devtype = &xcan_axi_data;
1718	1728	void __iomem *addr;
@@ -1843,6 +1853,14 @@ static int xcan_probe(struct platform_device *pdev) · 124 unmodified lines
1843	1853	goto err_free;
1844	1854	}
1845	1855
	1856	+ transceiver = devm_phy_optional_get(&pdev->dev, NULL);
	1857	+ if (IS_ERR(transceiver)) {
	1858	+ ret = PTR_ERR(transceiver);
	1859	+ dev_err_probe(&pdev->dev, ret, "failed to get phy\n");
	1860	+ goto err_free;
	1861	+ }
	1862	+ priv->transceiver = transceiver;
	1863	+
1846	1864	priv->write_reg = xcan_write_reg_le;
1847	1865	priv->read_reg = xcan_read_reg_le;
1848	1866
@@ -1869,6 +1887,7 @@ static int xcan_probe(struct platform_device *pdev) · 20 unmodified lines
1869	1887	goto err_disableclks;
1870	1888	}
1871	1889
	1890	+ of_can_transceiver(ndev);
1872	1891	pm_runtime_put(&pdev->dev);
1873	1892
1874	1893	if (priv->devtype.flags & XCAN_FLAG_CANFD_2) {

include/linux/can/length.h+214−85

@@ -1,129 +1,258 @@
1	1	/* SPDX-License-Identifier: GPL-2.0 */
2	2	/* Copyright (C) 2020 Oliver Hartkopp <socketcan@hartkopp.net>
3	3	* Copyright (C) 2020 Marc Kleine-Budde <kernel@pengutronix.de>
	4	+ * Copyright (C) 2020, 2023 Vincent Mailhol <mailhol.vincent@wanadoo.fr>
4	5	*/
5	6
6	7	#ifndef _CAN_LENGTH_H
7	8	#define _CAN_LENGTH_H
8	9
	10	+#include <linux/bits.h>
9	11	#include <linux/can.h>
10	12	#include <linux/can/netlink.h>
	13	+#include <linux/math.h>
11	14
12	15	/*
13		− * Size of a Classical CAN Standard Frame
	16	+ * Size of a Classical CAN Standard Frame header in bits
14	17	*
15		− * Name of Field Bits
	18	+ * Name of Field Bits
16	19	* ---------------------------------------------------------
17		− * Start-of-frame 1
18		− * Identifier 11
19		− * Remote transmission request (RTR) 1
20		− * Identifier extension bit (IDE) 1
21		− * Reserved bit (r0) 1
22		− * Data length code (DLC) 4
23		− * Data field 0...64
24		− * CRC 15
25		− * CRC delimiter 1
26		− * ACK slot 1
27		− * ACK delimiter 1
28		− * End-of-frame (EOF) 7
29		− * Inter frame spacing 3
	20	+ * Start Of Frame (SOF) 1
	21	+ * Arbitration field:
	22	+ * base ID 11
	23	+ * Remote Transmission Request (RTR) 1
	24	+ * Control field:
	25	+ * IDentifier Extension bit (IDE) 1
	26	+ * FD Format indicator (FDF) 1
	27	+ * Data Length Code (DLC) 4
	28	+ *
	29	+ * including all fields preceding the data field, ignoring bitstuffing
	30	+ */
	31	+#define CAN_FRAME_HEADER_SFF_BITS 19
	32	+
	33	+/*
	34	+ * Size of a Classical CAN Extended Frame header in bits
30	35	*
31		− * rounded up and ignoring bitstuffing
	36	+ * Name of Field Bits
	37	+ * ---------------------------------------------------------
	38	+ * Start Of Frame (SOF) 1
	39	+ * Arbitration field:
	40	+ * base ID 11
	41	+ * Substitute Remote Request (SRR) 1
	42	+ * IDentifier Extension bit (IDE) 1
	43	+ * ID extension 18
	44	+ * Remote Transmission Request (RTR) 1
	45	+ * Control field:
	46	+ * FD Format indicator (FDF) 1
	47	+ * Reserved bit (r0) 1
	48	+ * Data length code (DLC) 4
	49	+ *
	50	+ * including all fields preceding the data field, ignoring bitstuffing
32	51	*/
33		−#define CAN_FRAME_OVERHEAD_SFF DIV_ROUND_UP(47, 8)
	52	+#define CAN_FRAME_HEADER_EFF_BITS 39
34	53
35	54	/*
36		− * Size of a Classical CAN Extended Frame
	55	+ * Size of a CAN-FD Standard Frame in bits
	56	+ *
	57	+ * Name of Field Bits
	58	+ * ---------------------------------------------------------
	59	+ * Start Of Frame (SOF) 1
	60	+ * Arbitration field:
	61	+ * base ID 11
	62	+ * Remote Request Substitution (RRS) 1
	63	+ * Control field:
	64	+ * IDentifier Extension bit (IDE) 1
	65	+ * FD Format indicator (FDF) 1
	66	+ * Reserved bit (res) 1
	67	+ * Bit Rate Switch (BRS) 1
	68	+ * Error Status Indicator (ESI) 1
	69	+ * Data length code (DLC) 4
	70	+ *
	71	+ * including all fields preceding the data field, ignoring bitstuffing
	72	+ */
	73	+#define CANFD_FRAME_HEADER_SFF_BITS 22
	74	+
	75	+/*
	76	+ * Size of a CAN-FD Extended Frame in bits
	77	+ *
	78	+ * Name of Field Bits
	79	+ * ---------------------------------------------------------
	80	+ * Start Of Frame (SOF) 1
	81	+ * Arbitration field:
	82	+ * base ID 11
	83	+ * Substitute Remote Request (SRR) 1
	84	+ * IDentifier Extension bit (IDE) 1
	85	+ * ID extension 18
	86	+ * Remote Request Substitution (RRS) 1
	87	+ * Control field:
	88	+ * FD Format indicator (FDF) 1
	89	+ * Reserved bit (res) 1
	90	+ * Bit Rate Switch (BRS) 1
	91	+ * Error Status Indicator (ESI) 1
	92	+ * Data length code (DLC) 4
	93	+ *
	94	+ * including all fields preceding the data field, ignoring bitstuffing
	95	+ */
	96	+#define CANFD_FRAME_HEADER_EFF_BITS 41
	97	+
	98	+/*
	99	+ * Size of a CAN CRC Field in bits
37	100	*
38	101	* Name of Field Bits
39	102	* ---------------------------------------------------------
40		− * Start-of-frame 1
41		− * Identifier A 11
42		− * Substitute remote request (SRR) 1
43		− * Identifier extension bit (IDE) 1
44		− * Identifier B 18
45		− * Remote transmission request (RTR) 1
46		− * Reserved bits (r1, r0) 2
47		− * Data length code (DLC) 4
48		− * Data field 0...64
49		− * CRC 15
50		− * CRC delimiter 1
51		− * ACK slot 1
52		− * ACK delimiter 1
53		− * End-of-frame (EOF) 7
54		− * Inter frame spacing 3
	103	+ * CRC sequence (CRC15) 15
	104	+ * CRC Delimiter 1
	105	+ *
	106	+ * ignoring bitstuffing
	107	+ */
	108	+#define CAN_FRAME_CRC_FIELD_BITS 16
	109	+
	110	+/*
	111	+ * Size of a CAN-FD CRC17 Field in bits (length: 0..16)
55	112	*
56		− * rounded up and ignoring bitstuffing
	113	+ * Name of Field Bits
	114	+ * ---------------------------------------------------------
	115	+ * Stuff Count 4
	116	+ * CRC Sequence (CRC17) 17
	117	+ * CRC Delimiter 1
	118	+ * Fixed stuff bits 6
57	119	*/
58		−#define CAN_FRAME_OVERHEAD_EFF DIV_ROUND_UP(67, 8)
	120	+#define CANFD_FRAME_CRC17_FIELD_BITS 28
59	121
60	122	/*
61		− * Size of a CAN-FD Standard Frame
	123	+ * Size of a CAN-FD CRC21 Field in bits (length: 20..64)
62	124	*
63	125	* Name of Field Bits
64	126	* ---------------------------------------------------------
65		− * Start-of-frame 1
66		− * Identifier 11
67		− * Reserved bit (r1) 1
68		− * Identifier extension bit (IDE) 1
69		− * Flexible data rate format (FDF) 1
70		− * Reserved bit (r0) 1
71		− * Bit Rate Switch (BRS) 1
72		− * Error Status Indicator (ESI) 1
73		− * Data length code (DLC) 4
74		− * Data field 0...512
75		− * Stuff Bit Count (SBC) 0...16: 4 20...64:5
76		− * CRC 0...16: 17 20...64:21
77		− * CRC delimiter (CD) 1
78		− * ACK slot (AS) 1
79		− * ACK delimiter (AD) 1
80		− * End-of-frame (EOF) 7
81		− * Inter frame spacing 3
82		− *
83		− * assuming CRC21, rounded up and ignoring bitstuffing
84		− */
85		−#define CANFD_FRAME_OVERHEAD_SFF DIV_ROUND_UP(61, 8)
	127	+ * Stuff Count 4
	128	+ * CRC sequence (CRC21) 21
	129	+ * CRC Delimiter 1
	130	+ * Fixed stuff bits 7
	131	+ */
	132	+#define CANFD_FRAME_CRC21_FIELD_BITS 33
86	133
87	134	/*
88		− * Size of a CAN-FD Extended Frame
	135	+ * Size of a CAN(-FD) Frame footer in bits
89	136	*
90	137	* Name of Field Bits
91	138	* ---------------------------------------------------------
92		− * Start-of-frame 1
93		− * Identifier A 11
94		− * Substitute remote request (SRR) 1
95		− * Identifier extension bit (IDE) 1
96		− * Identifier B 18
97		− * Reserved bit (r1) 1
98		− * Flexible data rate format (FDF) 1
99		− * Reserved bit (r0) 1
100		− * Bit Rate Switch (BRS) 1
101		− * Error Status Indicator (ESI) 1
102		− * Data length code (DLC) 4
103		− * Data field 0...512
104		− * Stuff Bit Count (SBC) 0...16: 4 20...64:5
105		− * CRC 0...16: 17 20...64:21
106		− * CRC delimiter (CD) 1
107		− * ACK slot (AS) 1
108		− * ACK delimiter (AD) 1
109		− * End-of-frame (EOF) 7
110		− * Inter frame spacing 3
111		− *
112		− * assuming CRC21, rounded up and ignoring bitstuffing
113		− */
114		−#define CANFD_FRAME_OVERHEAD_EFF DIV_ROUND_UP(80, 8)
	139	+ * ACK slot 1
	140	+ * ACK delimiter 1
	141	+ * End Of Frame (EOF) 7
	142	+ *
	143	+ * including all fields following the CRC field
	144	+ */
	145	+#define CAN_FRAME_FOOTER_BITS 9
	146	+
	147	+/*
	148	+ * First part of the Inter Frame Space
	149	+ * (a.k.a. IMF - intermission field)
	150	+ */
	151	+#define CAN_INTERMISSION_BITS 3
	152	+
	153	+/**
	154	+ * can_bitstuffing_len() - Calculate the maximum length with bitstuffing
	155	+ * @destuffed_len: length of a destuffed bit stream
	156	+ *
	157	+ * The worst bit stuffing case is a sequence in which dominant and
	158	+ * recessive bits alternate every four bits:
	159	+ *
	160	+ * Destuffed: 1 1111 0000 1111 0000 1111
	161	+ * Stuffed: 1 1111o 0000i 1111o 0000i 1111o
	162	+ *
	163	+ * Nomenclature
	164	+ *
	165	+ * - "0": dominant bit
	166	+ * - "o": dominant stuff bit
	167	+ * - "1": recessive bit
	168	+ * - "i": recessive stuff bit
	169	+ *
	170	+ * Aside from the first bit, one stuff bit is added every four bits.
	171	+ *
	172	+ * Return: length of the stuffed bit stream in the worst case scenario.
	173	+ */
	174	+#define can_bitstuffing_len(destuffed_len) \
	175	+ (destuffed_len + (destuffed_len - 1) / 4)
	176	+
	177	+#define __can_bitstuffing_len(bitstuffing, destuffed_len) \
	178	+ (bitstuffing ? can_bitstuffing_len(destuffed_len) : \
	179	+ destuffed_len)
	180	+
	181	+#define __can_cc_frame_bits(is_eff, bitstuffing, \
	182	+ intermission, data_len) \
	183	+( \
	184	+ __can_bitstuffing_len(bitstuffing, \
	185	+ (is_eff ? CAN_FRAME_HEADER_EFF_BITS : \
	186	+ CAN_FRAME_HEADER_SFF_BITS) + \
	187	+ (data_len) * BITS_PER_BYTE + \
	188	+ CAN_FRAME_CRC_FIELD_BITS) + \
	189	+ CAN_FRAME_FOOTER_BITS + \
	190	+ (intermission ? CAN_INTERMISSION_BITS : 0) \
	191	+)
	192	+
	193	+#define __can_fd_frame_bits(is_eff, bitstuffing, \
	194	+ intermission, data_len) \
	195	+( \
	196	+ __can_bitstuffing_len(bitstuffing, \
	197	+ (is_eff ? CANFD_FRAME_HEADER_EFF_BITS : \
	198	+ CANFD_FRAME_HEADER_SFF_BITS) + \
	199	+ (data_len) * BITS_PER_BYTE) + \
	200	+ ((data_len) <= 16 ? \
	201	+ CANFD_FRAME_CRC17_FIELD_BITS : \
	202	+ CANFD_FRAME_CRC21_FIELD_BITS) + \
	203	+ CAN_FRAME_FOOTER_BITS + \
	204	+ (intermission ? CAN_INTERMISSION_BITS : 0) \
	205	+)
	206	+
	207	+/**
	208	+ * can_frame_bits() - Calculate the number of bits on the wire in a
	209	+ * CAN frame
	210	+ * @is_fd: true: CAN-FD frame; false: Classical CAN frame.
	211	+ * @is_eff: true: Extended frame; false: Standard frame.
	212	+ * @bitstuffing: true: calculate the bitstuffing worst case; false:
	213	+ * calculate the bitstuffing best case (no dynamic
	214	+ * bitstuffing). CAN-FD's fixed stuff bits are always included.
	215	+ * @intermission: if and only if true, include the inter frame space
	216	+ * assuming no bus idle (i.e. only the intermission). Strictly
	217	+ * speaking, the inter frame space is not part of the
	218	+ * frame. However, it is needed when calculating the delay
	219	+ * between the Start Of Frame of two consecutive frames.
	220	+ * @data_len: length of the data field in bytes. Correspond to
	221	+ * can(fd)_frame->len. Should be zero for remote frames. No
	222	+ * sanitization is done on @data_len and it shall have no side
	223	+ * effects.
	224	+ *
	225	+ * Return: the numbers of bits on the wire of a CAN frame.
	226	+ */
	227	+#define can_frame_bits(is_fd, is_eff, bitstuffing, \
	228	+ intermission, data_len) \
	229	+( \
	230	+ is_fd ? __can_fd_frame_bits(is_eff, bitstuffing, \
	231	+ intermission, data_len) : \
	232	+ __can_cc_frame_bits(is_eff, bitstuffing, \
	233	+ intermission, data_len) \
	234	+)
	235	+
	236	+/*
	237	+ * Number of bytes in a CAN frame
	238	+ * (rounded up, including intermission)
	239	+ */
	240	+#define can_frame_bytes(is_fd, is_eff, bitstuffing, data_len) \
	241	+ DIV_ROUND_UP(can_frame_bits(is_fd, is_eff, bitstuffing, \
	242	+ true, data_len), \
	243	+ BITS_PER_BYTE)
115	244
116	245	/*
117	246	* Maximum size of a Classical CAN frame
118		− * (rounded up and ignoring bitstuffing)
	247	+ * (rounded up, ignoring bitstuffing but including intermission)
119	248	*/
120		−#define CAN_FRAME_LEN_MAX (CAN_FRAME_OVERHEAD_EFF + CAN_MAX_DLEN)
	249	+#define CAN_FRAME_LEN_MAX can_frame_bytes(false, true, false, CAN_MAX_DLEN)
121	250
122	251	/*
123	252	* Maximum size of a CAN-FD frame
124		− * (rounded up and ignoring bitstuffing)
	253	+ * (rounded up, ignoring dynamic bitstuffing but including intermission)
125	254	*/
126		−#define CANFD_FRAME_LEN_MAX (CANFD_FRAME_OVERHEAD_EFF + CANFD_MAX_DLEN)
	255	+#define CANFD_FRAME_LEN_MAX can_frame_bytes(true, true, false, CANFD_MAX_DLEN)
127	256
128	257	/*
129	258	* can_cc_dlc2len(value) - convert a given data length code (dlc) of a

include/uapi/linux/can.h+0−1

@@ -285,6 +285,5 @@ struct can_filter { · 284 unmodified lines
285	285	};
286	286
287	287	#define CAN_INV_FILTER 0x20000000U /* to be set in can_filter.can_id */
288		−#define CAN_RAW_FILTER_MAX 512 /* maximum number of can_filter set via setsockopt() */
289	288
290	289	#endif /* !_UAPI_CAN_H */

include/uapi/linux/can/raw.h+2−0

@@ -49,6 +49,8 @@ · 48 unmodified lines
49	49	#include <linux/can.h>
50	50
51	51	#define SOL_CAN_RAW (SOL_CAN_BASE + CAN_RAW)
	52	+#define CAN_RAW_FILTER_MAX 512 /* maximum number of can_filter set via setsockopt() */
	53	+
52	54	enum {
53	55	SCM_CAN_RAW_ERRQUEUE = 1,
54	56	};

Merge tag 'linux-can-next-for-6.5-20230622' of git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next

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