History

Merge tag 'armsoc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson: "The latest and greatest fixes for ARM platform code. Worth pointing out are: - Lines-wise, largest is a PXA fix for dealing with interrupts on DT that was quite broken. It's still newish code so while we could have held this off, it seemed appropriate to include now - Some GPIO fixes for OMAP platforms added a few lines. This was also fixes for code recently added (this release). - Small OMAP timer fix to behave better with partially upstreamed platforms, which is quite welcome. - Allwinner fixes about operating point control, reducing overclocking in some cases for better stability. plus a handful of other smaller fixes across the map" * tag 'armsoc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: arm64: juno: Fix misleading name of UART reference clock ARM: dts: sunxi: Remove overclocked/overvoltaged OPP ARM: dts: sun4i: a10-lime: Override and remove 1008MHz OPP setting ARM: socfpga: dts: fix spi1 interrupt ARM: dts: Fix gpio interrupts for dm816x ARM: dts: dra7: remove ti,hwmod property from pcie phy ARM: OMAP: dmtimer: disable pm runtime on remove ARM: OMAP: dmtimer: check for pm_runtime_get_sync() failure ARM: OMAP2+: Fix socbus family info for AM33xx devices ARM: dts: omap3: Add missing dmas for crypto ARM: dts: rockchip: disable gmac by default in rk3288.dtsi MAINTAINERS: add rockchip regexp to the ARM/Rockchip entry ARM: pxa: fix pxa interrupts handling in DT ARM: pxa: Fix typo in zeus.c ARM: sunxi: Have ARCH_SUNXI select RESET_CONTROLLER for clock driver usage

Linus Torvalds committed 11 years ago

Commit 08f41f72 parents 7fc377e 4550bdb18 files · +128 −85Browse files

Unified · Split

18 files
  1. MAINTAINERS +1 −0
  2. arch/arm/Kconfig +1 −0
  3. arch/arm/boot/dts/dm8168-evm.dts +19 −0
  4. arch/arm/boot/dts/dm816x.dtsi +14 −4
  5. arch/arm/boot/dts/dra7.dtsi +0 −2
  6. arch/arm/boot/dts/omap3.dtsi +4 −0
  7. arch/arm/boot/dts/rk3288.dtsi +1 −0
  8. arch/arm/boot/dts/socfpga.dtsi +1 −1
  9. arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts +16 −0
  10. arch/arm/boot/dts/sun4i-a10.dtsi +1 −2
  11. arch/arm/boot/dts/sun5i-a13.dtsi +1 −2
  12. arch/arm/boot/dts/sun7i-a20.dtsi +1 −2
  13. arch/arm/mach-omap2/id.c +2 −0
  14. arch/arm/mach-pxa/irq.c +48 −63
  15. arch/arm/mach-pxa/zeus.c +1 −1
  16. arch/arm/mach-sunxi/Kconfig +2 −6
  17. arch/arm/plat-omap/dmtimer.c +14 −1
  18. arch/arm64/boot/dts/arm/juno-clocks.dtsi +1 −1
MAINTAINERS+1−0
@@ -1362,6 +1362,7 @@ F: drivers/i2c/busses/i2c-rk3x.c · 1361 unmodified lines
13621362 F: drivers/*/*rockchip*
13631363 F: drivers/*/*/*rockchip*
13641364 F: sound/soc/rockchip/
1365+N: rockchip
13651366
13661367 ARM/SAMSUNG EXYNOS ARM ARCHITECTURES
13671368 M: Kukjin Kim <kgene@kernel.org>
arch/arm/Kconfig+1−0
@@ -619,6 +619,7 @@ config ARCH_PXA · 618 unmodified lines
619619 select GENERIC_CLOCKEVENTS
620620 select GPIO_PXA
621621 select HAVE_IDE
622+ select IRQ_DOMAIN
622623 select MULTI_IRQ_HANDLER
623624 select PLAT_PXA
624625 select SPARSE_IRQ
arch/arm/boot/dts/dm8168-evm.dts+19−0
@@ -36,6 +36,20 @@ · 35 unmodified lines
3636 >;
3737 };
3838
39+ mmc_pins: pinmux_mmc_pins {
40+ pinctrl-single,pins = <
41+ DM816X_IOPAD(0x0a70, MUX_MODE0) /* SD_POW */
42+ DM816X_IOPAD(0x0a74, MUX_MODE0) /* SD_CLK */
43+ DM816X_IOPAD(0x0a78, MUX_MODE0) /* SD_CMD */
44+ DM816X_IOPAD(0x0a7C, MUX_MODE0) /* SD_DAT0 */
45+ DM816X_IOPAD(0x0a80, MUX_MODE0) /* SD_DAT1 */
46+ DM816X_IOPAD(0x0a84, MUX_MODE0) /* SD_DAT2 */
47+ DM816X_IOPAD(0x0a88, MUX_MODE0) /* SD_DAT2 */
48+ DM816X_IOPAD(0x0a8c, MUX_MODE2) /* GP1[7] */
49+ DM816X_IOPAD(0x0a90, MUX_MODE2) /* GP1[8] */
50+ >;
51+ };
52+
3953 usb0_pins: pinmux_usb0_pins {
4054 pinctrl-single,pins = <
4155 DM816X_IOPAD(0x0d00, MUX_MODE0) /* USB0_DRVVBUS */
@@ -137,7 +151,12 @@ · 95 unmodified lines
137151 };
138152
139153 &mmc1 {
154+ pinctrl-names = "default";
155+ pinctrl-0 = <&mmc_pins>;
140156 vmmc-supply = <&vmmcsd_fixed>;
157+ bus-width = <4>;
158+ cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
159+ wp-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
141160 };
142161
143162 /* At least dm8168-evm rev c won't support multipoint, later may */
arch/arm/boot/dts/dm816x.dtsi+14−4
@@ -150,17 +150,27 @@ · 149 unmodified lines
150150 };
151151
152152 gpio1: gpio@48032000 {
153− compatible = "ti,omap3-gpio";
153+ compatible = "ti,omap4-gpio";
154154 ti,hwmods = "gpio1";
155+ ti,gpio-always-on;
155156 reg = <0x48032000 0x1000>;
156− interrupts = <97>;
157+ interrupts = <96>;
158+ gpio-controller;
159+ #gpio-cells = <2>;
160+ interrupt-controller;
161+ #interrupt-cells = <2>;
157162 };
158163
159164 gpio2: gpio@4804c000 {
160− compatible = "ti,omap3-gpio";
165+ compatible = "ti,omap4-gpio";
161166 ti,hwmods = "gpio2";
167+ ti,gpio-always-on;
162168 reg = <0x4804c000 0x1000>;
163− interrupts = <99>;
169+ interrupts = <98>;
170+ gpio-controller;
171+ #gpio-cells = <2>;
172+ interrupt-controller;
173+ #interrupt-cells = <2>;
164174 };
165175
166176 gpmc: gpmc@50000000 {
arch/arm/boot/dts/dra7.dtsi+0−2
@@ -1111,7 +1111,6 @@ · 1110 unmodified lines
11111111 "wkupclk", "refclk",
11121112 "div-clk", "phy-div";
11131113 #phy-cells = <0>;
1114− ti,hwmods = "pcie1-phy";
11151114 };
11161115
11171116 pcie2_phy: pciephy@4a095000 {
@@ -1130,7 +1129,6 @@ · 12 unmodified lines
11301129 "wkupclk", "refclk",
11311130 "div-clk", "phy-div";
11321131 #phy-cells = <0>;
1133− ti,hwmods = "pcie2-phy";
11341132 status = "disabled";
11351133 };
11361134 };
arch/arm/boot/dts/omap3.dtsi+4−0
@@ -92,6 +92,8 @@ · 91 unmodified lines
9292 ti,hwmods = "aes";
9393 reg = <0x480c5000 0x50>;
9494 interrupts = <0>;
95+ dmas = <&sdma 65 &sdma 66>;
96+ dma-names = "tx", "rx";
9597 };
9698
9799 prm: prm@48306000 {
@@ -550,6 +552,8 @@ · 452 unmodified lines
550552 ti,hwmods = "sham";
551553 reg = <0x480c3000 0x64>;
552554 interrupts = <49>;
555+ dmas = <&sdma 69>;
556+ dma-names = "rx";
553557 };
554558
555559 smartreflex_core: smartreflex@480cb000 {
arch/arm/boot/dts/rk3288.dtsi+1−0
@@ -411,6 +411,7 @@ · 410 unmodified lines
411411 "mac_clk_rx", "mac_clk_tx",
412412 "clk_mac_ref", "clk_mac_refout",
413413 "aclk_mac", "pclk_mac";
414+ status = "disabled";
414415 };
415416
416417 usb_host0_ehci: usb@ff500000 {
arch/arm/boot/dts/socfpga.dtsi+1−1
@@ -660,7 +660,7 @@ · 659 unmodified lines
660660 #address-cells = <1>;
661661 #size-cells = <0>;
662662 reg = <0xfff01000 0x1000>;
663− interrupts = <0 156 4>;
663+ interrupts = <0 155 4>;
664664 num-cs = <4>;
665665 clocks = <&spi_m_clk>;
666666 status = "disabled";
arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts+16−0
@@ -56,6 +56,22 @@ · 55 unmodified lines
5656 model = "Olimex A10-OLinuXino-LIME";
5757 compatible = "olimex,a10-olinuxino-lime", "allwinner,sun4i-a10";
5858
59+ cpus {
60+ cpu0: cpu@0 {
61+ /*
62+ * The A10-Lime is known to be unstable
63+ * when running at 1008 MHz
64+ */
65+ operating-points = <
66+ /* kHz uV */
67+ 912000 1350000
68+ 864000 1300000
69+ 624000 1250000
70+ >;
71+ cooling-max-level = <2>;
72+ };
73+ };
74+
5975 soc@01c00000 {
6076 emac: ethernet@01c0b000 {
6177 pinctrl-names = "default";
arch/arm/boot/dts/sun4i-a10.dtsi+1−2
@@ -75,7 +75,6 @@ · 74 unmodified lines
7575 clock-latency = <244144>; /* 8 32k periods */
7676 operating-points = <
7777 /* kHz uV */
78− 1056000 1500000
7978 1008000 1400000
8079 912000 1350000
8180 864000 1300000
@@ -83,7 +82,7 @@ · 1 unmodified line
8382 >;
8483 #cooling-cells = <2>;
8584 cooling-min-level = <0>;
86− cooling-max-level = <4>;
85+ cooling-max-level = <3>;
8786 };
8887 };
8988
arch/arm/boot/dts/sun5i-a13.dtsi+1−2
@@ -47,7 +47,6 @@ · 46 unmodified lines
4747 clock-latency = <244144>; /* 8 32k periods */
4848 operating-points = <
4949 /* kHz uV */
50− 1104000 1500000
5150 1008000 1400000
5251 912000 1350000
5352 864000 1300000
@@ -57,7 +56,7 @@ · 3 unmodified lines
5756 >;
5857 #cooling-cells = <2>;
5958 cooling-min-level = <0>;
60− cooling-max-level = <6>;
59+ cooling-max-level = <5>;
6160 };
6261 };
6362
arch/arm/boot/dts/sun7i-a20.dtsi+1−2
@@ -105,7 +105,6 @@ · 104 unmodified lines
105105 clock-latency = <244144>; /* 8 32k periods */
106106 operating-points = <
107107 /* kHz uV */
108− 1008000 1450000
109108 960000 1400000
110109 912000 1400000
111110 864000 1300000
@@ -116,7 +115,7 @@ · 4 unmodified lines
116115 >;
117116 #cooling-cells = <2>;
118117 cooling-min-level = <0>;
119− cooling-max-level = <7>;
118+ cooling-max-level = <6>;
120119 };
121120
122121 cpu@1 {
arch/arm/mach-omap2/id.c+2−0
@@ -720,6 +720,8 @@ static const char * __init omap_get_family(void) · 719 unmodified lines
720720 return kasprintf(GFP_KERNEL, "OMAP4");
721721 else if (soc_is_omap54xx())
722722 return kasprintf(GFP_KERNEL, "OMAP5");
723+ else if (soc_is_am33xx() || soc_is_am335x())
724+ return kasprintf(GFP_KERNEL, "AM33xx");
723725 else if (soc_is_am43xx())
724726 return kasprintf(GFP_KERNEL, "AM43xx");
725727 else if (soc_is_dra7xx())
arch/arm/mach-pxa/irq.c+48−63
@@ -11,6 +11,7 @@ · 10 unmodified lines
1111 * it under the terms of the GNU General Public License version 2 as
1212 * published by the Free Software Foundation.
1313 */
14+#include <linux/bitops.h>
1415 #include <linux/init.h>
1516 #include <linux/module.h>
1617 #include <linux/interrupt.h>
@@ -40,7 +41,6 @@ · 23 unmodified lines
4041 #define ICHP_VAL_IRQ (1 << 31)
4142 #define ICHP_IRQ(i) (((i) >> 16) & 0x7fff)
4243 #define IPR_VALID (1 << 31)
43−#define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f)
4444
4545 #define MAX_INTERNAL_IRQS 128
4646
@@ -51,6 +51,7 @@ · 4 unmodified lines
5151 static void __iomem *pxa_irq_base;
5252 static int pxa_internal_irq_nr;
5353 static bool cpu_has_ipr;
54+static struct irq_domain *pxa_irq_domain;
5455
5556 static inline void __iomem *irq_base(int i)
5657 {
@@ -66,18 +67,20 @@ static inline void __iomem *irq_base(int i) · 9 unmodified lines
6667 void pxa_mask_irq(struct irq_data *d)
6768 {
6869 void __iomem *base = irq_data_get_irq_chip_data(d);
70+ irq_hw_number_t irq = irqd_to_hwirq(d);
6971 uint32_t icmr = __raw_readl(base + ICMR);
7072
71− icmr &= ~(1 << IRQ_BIT(d->irq));
73+ icmr &= ~BIT(irq & 0x1f);
7274 __raw_writel(icmr, base + ICMR);
7375 }
7476
7577 void pxa_unmask_irq(struct irq_data *d)
7678 {
7779 void __iomem *base = irq_data_get_irq_chip_data(d);
80+ irq_hw_number_t irq = irqd_to_hwirq(d);
7881 uint32_t icmr = __raw_readl(base + ICMR);
7982
80− icmr |= 1 << IRQ_BIT(d->irq);
83+ icmr |= BIT(irq & 0x1f);
8184 __raw_writel(icmr, base + ICMR);
8285 }
8386
@@ -118,40 +121,63 @@ asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs) · 34 unmodified lines
118121 } while (1);
119122 }
120123
121−void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))
124+static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
125+ irq_hw_number_t hw)
122126 {
123− int irq, i, n;
127+ void __iomem *base = irq_base(hw / 32);
124128
125− BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
129+ /* initialize interrupt priority */
130+ if (cpu_has_ipr)
131+ __raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw));
132+
133+ irq_set_chip_and_handler(virq, &pxa_internal_irq_chip,
134+ handle_level_irq);
135+ irq_set_chip_data(virq, base);
136+ set_irq_flags(virq, IRQF_VALID);
137+
138+ return 0;
139+}
140+
141+static struct irq_domain_ops pxa_irq_ops = {
142+ .map = pxa_irq_map,
143+ .xlate = irq_domain_xlate_onecell,
144+};
145+
146+static __init void
147+pxa_init_irq_common(struct device_node *node, int irq_nr,
148+ int (*fn)(struct irq_data *, unsigned int))
149+{
150+ int n;
126151
127152 pxa_internal_irq_nr = irq_nr;
128− cpu_has_ipr = !cpu_is_pxa25x();
129− pxa_irq_base = io_p2v(0x40d00000);
153+ pxa_irq_domain = irq_domain_add_legacy(node, irq_nr,
154+ PXA_IRQ(0), 0,
155+ &pxa_irq_ops, NULL);
156+ if (!pxa_irq_domain)
157+ panic("Unable to add PXA IRQ domain\n");
158+ irq_set_default_host(pxa_irq_domain);
130159
131160 for (n = 0; n < irq_nr; n += 32) {
132161 void __iomem *base = irq_base(n >> 5);
133162
134163 __raw_writel(0, base + ICMR); /* disable all IRQs */
135164 __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */
136− for (i = n; (i < (n + 32)) && (i < irq_nr); i++) {
137− /* initialize interrupt priority */
138− if (cpu_has_ipr)
139− __raw_writel(i | IPR_VALID, pxa_irq_base + IPR(i));
140−
141− irq = PXA_IRQ(i);
142− irq_set_chip_and_handler(irq, &pxa_internal_irq_chip,
143− handle_level_irq);
144− irq_set_chip_data(irq, base);
145− set_irq_flags(irq, IRQF_VALID);
146− }
147165 }
148−
149166 /* only unmasked interrupts kick us out of idle */
150167 __raw_writel(1, irq_base(0) + ICCR);
151168
152169 pxa_internal_irq_chip.irq_set_wake = fn;
153170 }
154171
172+void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))
173+{
174+ BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
175+
176+ pxa_irq_base = io_p2v(0x40d00000);
177+ cpu_has_ipr = !cpu_is_pxa25x();
178+ pxa_init_irq_common(NULL, irq_nr, fn);
179+}
180+
155181 #ifdef CONFIG_PM
156182 static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32];
157183 static unsigned long saved_ipr[MAX_INTERNAL_IRQS];
@@ -203,30 +229,6 @@ struct syscore_ops pxa_irq_syscore_ops = { · 45 unmodified lines
203229 };
204230
205231 #ifdef CONFIG_OF
206−static struct irq_domain *pxa_irq_domain;
207−
208−static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
209− irq_hw_number_t hw)
210−{
211− void __iomem *base = irq_base(hw / 32);
212−
213− /* initialize interrupt priority */
214− if (cpu_has_ipr)
215− __raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw));
216−
217− irq_set_chip_and_handler(hw, &pxa_internal_irq_chip,
218− handle_level_irq);
219− irq_set_chip_data(hw, base);
220− set_irq_flags(hw, IRQF_VALID);
221−
222− return 0;
223−}
224−
225−static struct irq_domain_ops pxa_irq_ops = {
226− .map = pxa_irq_map,
227− .xlate = irq_domain_xlate_onecell,
228−};
229−
230232 static const struct of_device_id intc_ids[] __initconst = {
231233 { .compatible = "marvell,pxa-intc", },
232234 {}
@@ -236,7 +238,7 @@ void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int)) · 3 unmodified lines
236238 {
237239 struct device_node *node;
238240 struct resource res;
239− int n, ret;
241+ int ret;
240242
241243 node = of_find_matching_node(NULL, intc_ids);
242244 if (!node) {
@@ -267,23 +269,6 @@ void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int)) · 24 unmodified lines
267269 return;
268270 }
269271
270− pxa_irq_domain = irq_domain_add_legacy(node, pxa_internal_irq_nr, 0, 0,
271− &pxa_irq_ops, NULL);
272− if (!pxa_irq_domain)
273− panic("Unable to add PXA IRQ domain\n");
274−
275− irq_set_default_host(pxa_irq_domain);
276−
277− for (n = 0; n < pxa_internal_irq_nr; n += 32) {
278− void __iomem *base = irq_base(n >> 5);
279−
280− __raw_writel(0, base + ICMR); /* disable all IRQs */
281− __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */
282− }
283−
284− /* only unmasked interrupts kick us out of idle */
285− __raw_writel(1, irq_base(0) + ICCR);
286−
287− pxa_internal_irq_chip.irq_set_wake = fn;
272+ pxa_init_irq_common(node, pxa_internal_irq_nr, fn);
288273 }
289274 #endif /* CONFIG_OF */
arch/arm/mach-pxa/zeus.c+1−1
@@ -412,7 +412,7 @@ static struct fixed_voltage_config can_regulator_pdata = { · 411 unmodified lines
412412 };
413413
414414 static struct platform_device can_regulator_device = {
415− .name = "reg-fixed-volage",
415+ .name = "reg-fixed-voltage",
416416 .id = 0,
417417 .dev = {
418418 .platform_data = &can_regulator_pdata,
arch/arm/mach-sunxi/Kconfig+2−6
@@ -1,10 +1,12 @@
11 menuconfig ARCH_SUNXI
22 bool "Allwinner SoCs" if ARCH_MULTI_V7
33 select ARCH_REQUIRE_GPIOLIB
4+ select ARCH_HAS_RESET_CONTROLLER
45 select CLKSRC_MMIO
56 select GENERIC_IRQ_CHIP
67 select PINCTRL
78 select SUN4I_TIMER
9+ select RESET_CONTROLLER
810
911 if ARCH_SUNXI
1012
@@ -20,10 +22,8 @@ config MACH_SUN5I · 9 unmodified lines
2022 config MACH_SUN6I
2123 bool "Allwinner A31 (sun6i) SoCs support"
2224 default ARCH_SUNXI
23− select ARCH_HAS_RESET_CONTROLLER
2425 select ARM_GIC
2526 select MFD_SUN6I_PRCM
26− select RESET_CONTROLLER
2727 select SUN5I_HSTIMER
2828
2929 config MACH_SUN7I
@@ -37,16 +37,12 @@ config MACH_SUN7I · 7 unmodified lines
3737 config MACH_SUN8I
3838 bool "Allwinner A23 (sun8i) SoCs support"
3939 default ARCH_SUNXI
40− select ARCH_HAS_RESET_CONTROLLER
4140 select ARM_GIC
4241 select MFD_SUN6I_PRCM
43− select RESET_CONTROLLER
4442
4543 config MACH_SUN9I
4644 bool "Allwinner (sun9i) SoCs support"
4745 default ARCH_SUNXI
48− select ARCH_HAS_RESET_CONTROLLER
4946 select ARM_GIC
50− select RESET_CONTROLLER
5147
5248 endif
arch/arm/plat-omap/dmtimer.c+14−1
@@ -799,6 +799,7 @@ static int omap_dm_timer_probe(struct platform_device *pdev) · 798 unmodified lines
799799 struct device *dev = &pdev->dev;
800800 const struct of_device_id *match;
801801 const struct dmtimer_platform_data *pdata;
802+ int ret;
802803
803804 match = of_match_device(of_match_ptr(omap_timer_match), dev);
804805 pdata = match ? match->data : dev->platform_data;
@@ -860,7 +861,12 @@ static int omap_dm_timer_probe(struct platform_device *pdev) · 55 unmodified lines
860861 }
861862
862863 if (!timer->reserved) {
863− pm_runtime_get_sync(dev);
864+ ret = pm_runtime_get_sync(dev);
865+ if (ret < 0) {
866+ dev_err(dev, "%s: pm_runtime_get_sync failed!\n",
867+ __func__);
868+ goto err_get_sync;
869+ }
864870 __omap_dm_timer_init_regs(timer);
865871 pm_runtime_put(dev);
866872 }
@@ -873,6 +879,11 @@ static int omap_dm_timer_probe(struct platform_device *pdev) · 6 unmodified lines
873879 dev_dbg(dev, "Device Probed.\n");
874880
875881 return 0;
882+
883+err_get_sync:
884+ pm_runtime_put_noidle(dev);
885+ pm_runtime_disable(dev);
886+ return ret;
876887 }
877888
878889 /**
@@ -899,6 +910,8 @@ static int omap_dm_timer_remove(struct platform_device *pdev) · 20 unmodified lines
899910 }
900911 spin_unlock_irqrestore(&dm_timer_lock, flags);
901912
913+ pm_runtime_disable(&pdev->dev);
914+
902915 return ret;
903916 }
904917
arch/arm64/boot/dts/arm/juno-clocks.dtsi+1−1
@@ -8,7 +8,7 @@ · 7 unmodified lines
88 */
99
1010 /* SoC fixed clocks */
11− soc_uartclk: refclk72738khz {
11+ soc_uartclk: refclk7273800hz {
1212 compatible = "fixed-clock";
1313 #clock-cells = <0>;
1414 clock-frequency = <7273800>;

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