Tiger Lake is the followon to Ice Lake. PPERF and SMI_COUNT MSRs are also supported. The External Design Specification (EDS) is not published yet. It comes from an authoritative internal source. The patch has been tested on real hardware.
Unified · Split
| @@ -95,6 +95,8 @@ static bool test_intel(int idx, void *data) · 94 unmodified lines | |||
| 95 | case INTEL_FAM6_ICELAKE: | 95 | case INTEL_FAM6_ICELAKE: |
| 96 | case INTEL_FAM6_ICELAKE_X: | 96 | case INTEL_FAM6_ICELAKE_X: |
| 97 | case INTEL_FAM6_ICELAKE_D: | 97 | case INTEL_FAM6_ICELAKE_D: |
| 98 | case INTEL_FAM6_TIGERLAKE_L: | ||
| 99 | case INTEL_FAM6_TIGERLAKE: | ||
| 98 | if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF) | 100 | if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF) |
| 99 | return true; | 101 | return true; |
| 100 | break; | 102 | break; |