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| | 1 | /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- |
| | 2 | * |
| | 3 | * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. |
| | 4 | * Copyright 2000 VA Linux Systems, Inc., Fremont, California. |
| | 5 | * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. |
| | 6 | * Copyright 2014 Advanced Micro Devices, Inc. |
| | 7 | * |
| | 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
| | 9 | * copy of this software and associated documentation files (the "Software"), |
| | 10 | * to deal in the Software without restriction, including without limitation |
| | 11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| | 12 | * and/or sell copies of the Software, and to permit persons to whom the |
| | 13 | * Software is furnished to do so, subject to the following conditions: |
| | 14 | * |
| | 15 | * The above copyright notice and this permission notice shall be included in |
| | 16 | * all copies or substantial portions of the Software. |
| | 17 | * |
| | 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| | 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| | 20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| | 21 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| | 22 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| | 23 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| | 24 | * OTHER DEALINGS IN THE SOFTWARE. |
| | 25 | * |
| | 26 | * Authors: |
| | 27 | * Kevin E. Martin <martin@valinux.com> |
| | 28 | * Gareth Hughes <gareth@valinux.com> |
| | 29 | * Keith Whitwell <keith@tungstengraphics.com> |
| | 30 | */ |
| | 31 | |
| | 32 | #ifndef __AMDGPU_DRM_H__ |
| | 33 | #define __AMDGPU_DRM_H__ |
| | 34 | |
| | 35 | #include <drm/drm.h> |
| | 36 | |
| | 37 | #define DRM_AMDGPU_GEM_CREATE 0x00 |
| | 38 | #define DRM_AMDGPU_GEM_MMAP 0x01 |
| | 39 | #define DRM_AMDGPU_CTX 0x02 |
| | 40 | #define DRM_AMDGPU_BO_LIST 0x03 |
| | 41 | #define DRM_AMDGPU_CS 0x04 |
| | 42 | #define DRM_AMDGPU_INFO 0x05 |
| | 43 | #define DRM_AMDGPU_GEM_METADATA 0x06 |
| | 44 | #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 |
| | 45 | #define DRM_AMDGPU_GEM_VA 0x08 |
| | 46 | #define DRM_AMDGPU_WAIT_CS 0x09 |
| | 47 | #define DRM_AMDGPU_GEM_OP 0x10 |
| | 48 | #define DRM_AMDGPU_GEM_USERPTR 0x11 |
| | 49 | |
| | 50 | #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) |
| | 51 | #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) |
| | 52 | #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) |
| | 53 | #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) |
| | 54 | #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) |
| | 55 | #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) |
| | 56 | #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) |
| | 57 | #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) |
| | 58 | #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) |
| | 59 | #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) |
| | 60 | #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) |
| | 61 | #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) |
| | 62 | |
| | 63 | #define AMDGPU_GEM_DOMAIN_CPU 0x1 |
| | 64 | #define AMDGPU_GEM_DOMAIN_GTT 0x2 |
| | 65 | #define AMDGPU_GEM_DOMAIN_VRAM 0x4 |
| | 66 | #define AMDGPU_GEM_DOMAIN_GDS 0x8 |
| | 67 | #define AMDGPU_GEM_DOMAIN_GWS 0x10 |
| | 68 | #define AMDGPU_GEM_DOMAIN_OA 0x20 |
| | 69 | |
| | 70 | /* Flag that CPU access will be required for the case of VRAM domain */ |
| | 71 | #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) |
| | 72 | /* Flag that CPU access will not work, this VRAM domain is invisible */ |
| | 73 | #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) |
| | 74 | /* Flag that USWC attributes should be used for GTT */ |
| | 75 | #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) |
| | 76 | |
| | 77 | struct drm_amdgpu_gem_create_in { |
| | 78 | /** the requested memory size */ |
| | 79 | uint64_t bo_size; |
| | 80 | /** physical start_addr alignment in bytes for some HW requirements */ |
| | 81 | uint64_t alignment; |
| | 82 | /** the requested memory domains */ |
| | 83 | uint64_t domains; |
| | 84 | /** allocation flags */ |
| | 85 | uint64_t domain_flags; |
| | 86 | }; |
| | 87 | |
| | 88 | struct drm_amdgpu_gem_create_out { |
| | 89 | /** returned GEM object handle */ |
| | 90 | uint32_t handle; |
| | 91 | uint32_t _pad; |
| | 92 | }; |
| | 93 | |
| | 94 | union drm_amdgpu_gem_create { |
| | 95 | struct drm_amdgpu_gem_create_in in; |
| | 96 | struct drm_amdgpu_gem_create_out out; |
| | 97 | }; |
| | 98 | |
| | 99 | /** Opcode to create new residency list. */ |
| | 100 | #define AMDGPU_BO_LIST_OP_CREATE 0 |
| | 101 | /** Opcode to destroy previously created residency list */ |
| | 102 | #define AMDGPU_BO_LIST_OP_DESTROY 1 |
| | 103 | /** Opcode to update resource information in the list */ |
| | 104 | #define AMDGPU_BO_LIST_OP_UPDATE 2 |
| | 105 | |
| | 106 | struct drm_amdgpu_bo_list_in { |
| | 107 | /** Type of operation */ |
| | 108 | uint32_t operation; |
| | 109 | /** Handle of list or 0 if we want to create one */ |
| | 110 | uint32_t list_handle; |
| | 111 | /** Number of BOs in list */ |
| | 112 | uint32_t bo_number; |
| | 113 | /** Size of each element describing BO */ |
| | 114 | uint32_t bo_info_size; |
| | 115 | /** Pointer to array describing BOs */ |
| | 116 | uint64_t bo_info_ptr; |
| | 117 | }; |
| | 118 | |
| | 119 | struct drm_amdgpu_bo_list_entry { |
| | 120 | /** Handle of BO */ |
| | 121 | uint32_t bo_handle; |
| | 122 | /** New (if specified) BO priority to be used during migration */ |
| | 123 | uint32_t bo_priority; |
| | 124 | }; |
| | 125 | |
| | 126 | struct drm_amdgpu_bo_list_out { |
| | 127 | /** Handle of resource list */ |
| | 128 | uint32_t list_handle; |
| | 129 | uint32_t _pad; |
| | 130 | }; |
| | 131 | |
| | 132 | union drm_amdgpu_bo_list { |
| | 133 | struct drm_amdgpu_bo_list_in in; |
| | 134 | struct drm_amdgpu_bo_list_out out; |
| | 135 | }; |
| | 136 | |
| | 137 | /* context related */ |
| | 138 | #define AMDGPU_CTX_OP_ALLOC_CTX 1 |
| | 139 | #define AMDGPU_CTX_OP_FREE_CTX 2 |
| | 140 | #define AMDGPU_CTX_OP_QUERY_STATE 3 |
| | 141 | |
| | 142 | /* GPU reset status */ |
| | 143 | #define AMDGPU_CTX_NO_RESET 0 |
| | 144 | /* this the context caused it */ |
| | 145 | #define AMDGPU_CTX_GUILTY_RESET 1 |
| | 146 | /* some other context caused it */ |
| | 147 | #define AMDGPU_CTX_INNOCENT_RESET 2 |
| | 148 | /* unknown cause */ |
| | 149 | #define AMDGPU_CTX_UNKNOWN_RESET 3 |
| | 150 | |
| | 151 | struct drm_amdgpu_ctx_in { |
| | 152 | /** AMDGPU_CTX_OP_* */ |
| | 153 | uint32_t op; |
| | 154 | /** For future use, no flags defined so far */ |
| | 155 | uint32_t flags; |
| | 156 | uint32_t ctx_id; |
| | 157 | uint32_t _pad; |
| | 158 | }; |
| | 159 | |
| | 160 | union drm_amdgpu_ctx_out { |
| | 161 | struct { |
| | 162 | uint32_t ctx_id; |
| | 163 | uint32_t _pad; |
| | 164 | } alloc; |
| | 165 | |
| | 166 | struct { |
| | 167 | /** For future use, no flags defined so far */ |
| | 168 | uint64_t flags; |
| | 169 | /** Number of resets caused by this context so far. */ |
| | 170 | uint32_t hangs; |
| | 171 | /** Reset status since the last call of the ioctl. */ |
| | 172 | uint32_t reset_status; |
| | 173 | } state; |
| | 174 | }; |
| | 175 | |
| | 176 | union drm_amdgpu_ctx { |
| | 177 | struct drm_amdgpu_ctx_in in; |
| | 178 | union drm_amdgpu_ctx_out out; |
| | 179 | }; |
| | 180 | |
| | 181 | /* |
| | 182 | * This is not a reliable API and you should expect it to fail for any |
| | 183 | * number of reasons and have fallback path that do not use userptr to |
| | 184 | * perform any operation. |
| | 185 | */ |
| | 186 | #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) |
| | 187 | #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) |
| | 188 | #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) |
| | 189 | #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) |
| | 190 | |
| | 191 | struct drm_amdgpu_gem_userptr { |
| | 192 | uint64_t addr; |
| | 193 | uint64_t size; |
| | 194 | /* AMDGPU_GEM_USERPTR_* */ |
| | 195 | uint32_t flags; |
| | 196 | /* Resulting GEM handle */ |
| | 197 | uint32_t handle; |
| | 198 | }; |
| | 199 | |
| | 200 | /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ |
| | 201 | #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 |
| | 202 | #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf |
| | 203 | #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 |
| | 204 | #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f |
| | 205 | #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 |
| | 206 | #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 |
| | 207 | #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 |
| | 208 | #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 |
| | 209 | #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 |
| | 210 | #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 |
| | 211 | #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 |
| | 212 | #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 |
| | 213 | #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 |
| | 214 | #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 |
| | 215 | #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 |
| | 216 | #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 |
| | 217 | |
| | 218 | #define AMDGPU_TILING_SET(field, value) \ |
| | 219 | (((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) |
| | 220 | #define AMDGPU_TILING_GET(value, field) \ |
| | 221 | (((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) |
| | 222 | |
| | 223 | #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 |
| | 224 | #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 |
| | 225 | |
| | 226 | /** The same structure is shared for input/output */ |
| | 227 | struct drm_amdgpu_gem_metadata { |
| | 228 | /** GEM Object handle */ |
| | 229 | uint32_t handle; |
| | 230 | /** Do we want get or set metadata */ |
| | 231 | uint32_t op; |
| | 232 | struct { |
| | 233 | /** For future use, no flags defined so far */ |
| | 234 | uint64_t flags; |
| | 235 | /** family specific tiling info */ |
| | 236 | uint64_t tiling_info; |
| | 237 | uint32_t data_size_bytes; |
| | 238 | uint32_t data[64]; |
| | 239 | } data; |
| | 240 | }; |
| | 241 | |
| | 242 | struct drm_amdgpu_gem_mmap_in { |
| | 243 | /** the GEM object handle */ |
| | 244 | uint32_t handle; |
| | 245 | uint32_t _pad; |
| | 246 | }; |
| | 247 | |
| | 248 | struct drm_amdgpu_gem_mmap_out { |
| | 249 | /** mmap offset from the vma offset manager */ |
| | 250 | uint64_t addr_ptr; |
| | 251 | }; |
| | 252 | |
| | 253 | union drm_amdgpu_gem_mmap { |
| | 254 | struct drm_amdgpu_gem_mmap_in in; |
| | 255 | struct drm_amdgpu_gem_mmap_out out; |
| | 256 | }; |
| | 257 | |
| | 258 | struct drm_amdgpu_gem_wait_idle_in { |
| | 259 | /** GEM object handle */ |
| | 260 | uint32_t handle; |
| | 261 | /** For future use, no flags defined so far */ |
| | 262 | uint32_t flags; |
| | 263 | /** Absolute timeout to wait */ |
| | 264 | uint64_t timeout; |
| | 265 | }; |
| | 266 | |
| | 267 | struct drm_amdgpu_gem_wait_idle_out { |
| | 268 | /** BO status: 0 - BO is idle, 1 - BO is busy */ |
| | 269 | uint32_t status; |
| | 270 | /** Returned current memory domain */ |
| | 271 | uint32_t domain; |
| | 272 | }; |
| | 273 | |
| | 274 | union drm_amdgpu_gem_wait_idle { |
| | 275 | struct drm_amdgpu_gem_wait_idle_in in; |
| | 276 | struct drm_amdgpu_gem_wait_idle_out out; |
| | 277 | }; |
| | 278 | |
| | 279 | struct drm_amdgpu_wait_cs_in { |
| | 280 | /** Command submission handle */ |
| | 281 | uint64_t handle; |
| | 282 | /** Absolute timeout to wait */ |
| | 283 | uint64_t timeout; |
| | 284 | uint32_t ip_type; |
| | 285 | uint32_t ip_instance; |
| | 286 | uint32_t ring; |
| | 287 | uint32_t ctx_id; |
| | 288 | }; |
| | 289 | |
| | 290 | struct drm_amdgpu_wait_cs_out { |
| | 291 | /** CS status: 0 - CS completed, 1 - CS still busy */ |
| | 292 | uint64_t status; |
| | 293 | }; |
| | 294 | |
| | 295 | union drm_amdgpu_wait_cs { |
| | 296 | struct drm_amdgpu_wait_cs_in in; |
| | 297 | struct drm_amdgpu_wait_cs_out out; |
| | 298 | }; |
| | 299 | |
| | 300 | #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 |
| | 301 | #define AMDGPU_GEM_OP_SET_PLACEMENT 1 |
| | 302 | |
| | 303 | /* Sets or returns a value associated with a buffer. */ |
| | 304 | struct drm_amdgpu_gem_op { |
| | 305 | /** GEM object handle */ |
| | 306 | uint32_t handle; |
| | 307 | /** AMDGPU_GEM_OP_* */ |
| | 308 | uint32_t op; |
| | 309 | /** Input or return value */ |
| | 310 | uint64_t value; |
| | 311 | }; |
| | 312 | |
| | 313 | #define AMDGPU_VA_OP_MAP 1 |
| | 314 | #define AMDGPU_VA_OP_UNMAP 2 |
| | 315 | |
| | 316 | /* Mapping flags */ |
| | 317 | /* readable mapping */ |
| | 318 | #define AMDGPU_VM_PAGE_READABLE (1 << 1) |
| | 319 | /* writable mapping */ |
| | 320 | #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) |
| | 321 | /* executable mapping, new for VI */ |
| | 322 | #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) |
| | 323 | |
| | 324 | struct drm_amdgpu_gem_va { |
| | 325 | /** GEM object handle */ |
| | 326 | uint32_t handle; |
| | 327 | uint32_t _pad; |
| | 328 | /** AMDGPU_VA_OP_* */ |
| | 329 | uint32_t operation; |
| | 330 | /** AMDGPU_VM_PAGE_* */ |
| | 331 | uint32_t flags; |
| | 332 | /** va address to assign . Must be correctly aligned.*/ |
| | 333 | uint64_t va_address; |
| | 334 | /** Specify offset inside of BO to assign. Must be correctly aligned.*/ |
| | 335 | uint64_t offset_in_bo; |
| | 336 | /** Specify mapping size. Must be correctly aligned. */ |
| | 337 | uint64_t map_size; |
| | 338 | }; |
| | 339 | |
| | 340 | #define AMDGPU_HW_IP_GFX 0 |
| | 341 | #define AMDGPU_HW_IP_COMPUTE 1 |
| | 342 | #define AMDGPU_HW_IP_DMA 2 |
| | 343 | #define AMDGPU_HW_IP_UVD 3 |
| | 344 | #define AMDGPU_HW_IP_VCE 4 |
| | 345 | #define AMDGPU_HW_IP_NUM 5 |
| | 346 | |
| | 347 | #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 |
| | 348 | |
| | 349 | #define AMDGPU_CHUNK_ID_IB 0x01 |
| | 350 | #define AMDGPU_CHUNK_ID_FENCE 0x02 |
| | 351 | |
| | 352 | struct drm_amdgpu_cs_chunk { |
| | 353 | uint32_t chunk_id; |
| | 354 | uint32_t length_dw; |
| | 355 | uint64_t chunk_data; |
| | 356 | }; |
| | 357 | |
| | 358 | struct drm_amdgpu_cs_in { |
| | 359 | /** Rendering context id */ |
| | 360 | uint32_t ctx_id; |
| | 361 | /** Handle of resource list associated with CS */ |
| | 362 | uint32_t bo_list_handle; |
| | 363 | uint32_t num_chunks; |
| | 364 | uint32_t _pad; |
| | 365 | /** this points to uint64_t * which point to cs chunks */ |
| | 366 | uint64_t chunks; |
| | 367 | }; |
| | 368 | |
| | 369 | struct drm_amdgpu_cs_out { |
| | 370 | uint64_t handle; |
| | 371 | }; |
| | 372 | |
| | 373 | union drm_amdgpu_cs { |
| | 374 | struct drm_amdgpu_cs_in in; |
| | 375 | struct drm_amdgpu_cs_out out; |
| | 376 | }; |
| | 377 | |
| | 378 | /* Specify flags to be used for IB */ |
| | 379 | |
| | 380 | /* This IB should be submitted to CE */ |
| | 381 | #define AMDGPU_IB_FLAG_CE (1<<0) |
| | 382 | |
| | 383 | /* CE Preamble */ |
| | 384 | #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) |
| | 385 | |
| | 386 | struct drm_amdgpu_cs_chunk_ib { |
| | 387 | uint32_t _pad; |
| | 388 | /** AMDGPU_IB_FLAG_* */ |
| | 389 | uint32_t flags; |
| | 390 | /** Virtual address to begin IB execution */ |
| | 391 | uint64_t va_start; |
| | 392 | /** Size of submission */ |
| | 393 | uint32_t ib_bytes; |
| | 394 | /** HW IP to submit to */ |
| | 395 | uint32_t ip_type; |
| | 396 | /** HW IP index of the same type to submit to */ |
| | 397 | uint32_t ip_instance; |
| | 398 | /** Ring index to submit to */ |
| | 399 | uint32_t ring; |
| | 400 | }; |
| | 401 | |
| | 402 | struct drm_amdgpu_cs_chunk_fence { |
| | 403 | uint32_t handle; |
| | 404 | uint32_t offset; |
| | 405 | }; |
| | 406 | |
| | 407 | struct drm_amdgpu_cs_chunk_data { |
| | 408 | union { |
| | 409 | struct drm_amdgpu_cs_chunk_ib ib_data; |
| | 410 | struct drm_amdgpu_cs_chunk_fence fence_data; |
| | 411 | }; |
| | 412 | }; |
| | 413 | |
| | 414 | /** |
| | 415 | * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU |
| | 416 | * |
| | 417 | */ |
| | 418 | #define AMDGPU_IDS_FLAGS_FUSION 0x1 |
| | 419 | |
| | 420 | /* indicate if acceleration can be working */ |
| | 421 | #define AMDGPU_INFO_ACCEL_WORKING 0x00 |
| | 422 | /* get the crtc_id from the mode object id? */ |
| | 423 | #define AMDGPU_INFO_CRTC_FROM_ID 0x01 |
| | 424 | /* query hw IP info */ |
| | 425 | #define AMDGPU_INFO_HW_IP_INFO 0x02 |
| | 426 | /* query hw IP instance count for the specified type */ |
| | 427 | #define AMDGPU_INFO_HW_IP_COUNT 0x03 |
| | 428 | /* timestamp for GL_ARB_timer_query */ |
| | 429 | #define AMDGPU_INFO_TIMESTAMP 0x05 |
| | 430 | /* Query the firmware version */ |
| | 431 | #define AMDGPU_INFO_FW_VERSION 0x0e |
| | 432 | /* Subquery id: Query VCE firmware version */ |
| | 433 | #define AMDGPU_INFO_FW_VCE 0x1 |
| | 434 | /* Subquery id: Query UVD firmware version */ |
| | 435 | #define AMDGPU_INFO_FW_UVD 0x2 |
| | 436 | /* Subquery id: Query GMC firmware version */ |
| | 437 | #define AMDGPU_INFO_FW_GMC 0x03 |
| | 438 | /* Subquery id: Query GFX ME firmware version */ |
| | 439 | #define AMDGPU_INFO_FW_GFX_ME 0x04 |
| | 440 | /* Subquery id: Query GFX PFP firmware version */ |
| | 441 | #define AMDGPU_INFO_FW_GFX_PFP 0x05 |
| | 442 | /* Subquery id: Query GFX CE firmware version */ |
| | 443 | #define AMDGPU_INFO_FW_GFX_CE 0x06 |
| | 444 | /* Subquery id: Query GFX RLC firmware version */ |
| | 445 | #define AMDGPU_INFO_FW_GFX_RLC 0x07 |
| | 446 | /* Subquery id: Query GFX MEC firmware version */ |
| | 447 | #define AMDGPU_INFO_FW_GFX_MEC 0x08 |
| | 448 | /* Subquery id: Query SMC firmware version */ |
| | 449 | #define AMDGPU_INFO_FW_SMC 0x0a |
| | 450 | /* Subquery id: Query SDMA firmware version */ |
| | 451 | #define AMDGPU_INFO_FW_SDMA 0x0b |
| | 452 | /* number of bytes moved for TTM migration */ |
| | 453 | #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f |
| | 454 | /* the used VRAM size */ |
| | 455 | #define AMDGPU_INFO_VRAM_USAGE 0x10 |
| | 456 | /* the used GTT size */ |
| | 457 | #define AMDGPU_INFO_GTT_USAGE 0x11 |
| | 458 | /* Information about GDS, etc. resource configuration */ |
| | 459 | #define AMDGPU_INFO_GDS_CONFIG 0x13 |
| | 460 | /* Query information about VRAM and GTT domains */ |
| | 461 | #define AMDGPU_INFO_VRAM_GTT 0x14 |
| | 462 | /* Query information about register in MMR address space*/ |
| | 463 | #define AMDGPU_INFO_READ_MMR_REG 0x15 |
| | 464 | /* Query information about device: rev id, family, etc. */ |
| | 465 | #define AMDGPU_INFO_DEV_INFO 0x16 |
| | 466 | /* visible vram usage */ |
| | 467 | #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 |
| | 468 | |
| | 469 | #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 |
| | 470 | #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff |
| | 471 | #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 |
| | 472 | #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff |
| | 473 | |
| | 474 | /* Input structure for the INFO ioctl */ |
| | 475 | struct drm_amdgpu_info { |
| | 476 | /* Where the return value will be stored */ |
| | 477 | uint64_t return_pointer; |
| | 478 | /* The size of the return value. Just like "size" in "snprintf", |
| | 479 | * it limits how many bytes the kernel can write. */ |
| | 480 | uint32_t return_size; |
| | 481 | /* The query request id. */ |
| | 482 | uint32_t query; |
| | 483 | |
| | 484 | union { |
| | 485 | struct { |
| | 486 | uint32_t id; |
| | 487 | uint32_t _pad; |
| | 488 | } mode_crtc; |
| | 489 | |
| | 490 | struct { |
| | 491 | /** AMDGPU_HW_IP_* */ |
| | 492 | uint32_t type; |
| | 493 | /** |
| | 494 | * Index of the IP if there are more IPs of the same |
| | 495 | * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. |
| | 496 | */ |
| | 497 | uint32_t ip_instance; |
| | 498 | } query_hw_ip; |
| | 499 | |
| | 500 | struct { |
| | 501 | uint32_t dword_offset; |
| | 502 | /** number of registers to read */ |
| | 503 | uint32_t count; |
| | 504 | uint32_t instance; |
| | 505 | /** For future use, no flags defined so far */ |
| | 506 | uint32_t flags; |
| | 507 | } read_mmr_reg; |
| | 508 | |
| | 509 | struct { |
| | 510 | /** AMDGPU_INFO_FW_* */ |
| | 511 | uint32_t fw_type; |
| | 512 | /** |
| | 513 | * Index of the IP if there are more IPs of |
| | 514 | * the same type. |
| | 515 | */ |
| | 516 | uint32_t ip_instance; |
| | 517 | /** |
| | 518 | * Index of the engine. Whether this is used depends |
| | 519 | * on the firmware type. (e.g. MEC, SDMA) |
| | 520 | */ |
| | 521 | uint32_t index; |
| | 522 | uint32_t _pad; |
| | 523 | } query_fw; |
| | 524 | }; |
| | 525 | }; |
| | 526 | |
| | 527 | struct drm_amdgpu_info_gds { |
| | 528 | /** GDS GFX partition size */ |
| | 529 | uint32_t gds_gfx_partition_size; |
| | 530 | /** GDS compute partition size */ |
| | 531 | uint32_t compute_partition_size; |
| | 532 | /** total GDS memory size */ |
| | 533 | uint32_t gds_total_size; |
| | 534 | /** GWS size per GFX partition */ |
| | 535 | uint32_t gws_per_gfx_partition; |
| | 536 | /** GSW size per compute partition */ |
| | 537 | uint32_t gws_per_compute_partition; |
| | 538 | /** OA size per GFX partition */ |
| | 539 | uint32_t oa_per_gfx_partition; |
| | 540 | /** OA size per compute partition */ |
| | 541 | uint32_t oa_per_compute_partition; |
| | 542 | uint32_t _pad; |
| | 543 | }; |
| | 544 | |
| | 545 | struct drm_amdgpu_info_vram_gtt { |
| | 546 | uint64_t vram_size; |
| | 547 | uint64_t vram_cpu_accessible_size; |
| | 548 | uint64_t gtt_size; |
| | 549 | }; |
| | 550 | |
| | 551 | struct drm_amdgpu_info_firmware { |
| | 552 | uint32_t ver; |
| | 553 | uint32_t feature; |
| | 554 | }; |
| | 555 | |
| | 556 | #define AMDGPU_VRAM_TYPE_UNKNOWN 0 |
| | 557 | #define AMDGPU_VRAM_TYPE_GDDR1 1 |
| | 558 | #define AMDGPU_VRAM_TYPE_DDR2 2 |
| | 559 | #define AMDGPU_VRAM_TYPE_GDDR3 3 |
| | 560 | #define AMDGPU_VRAM_TYPE_GDDR4 4 |
| | 561 | #define AMDGPU_VRAM_TYPE_GDDR5 5 |
| | 562 | #define AMDGPU_VRAM_TYPE_HBM 6 |
| | 563 | #define AMDGPU_VRAM_TYPE_DDR3 7 |
| | 564 | |
| | 565 | struct drm_amdgpu_info_device { |
| | 566 | /** PCI Device ID */ |
| | 567 | uint32_t device_id; |
| | 568 | /** Internal chip revision: A0, A1, etc.) */ |
| | 569 | uint32_t chip_rev; |
| | 570 | uint32_t external_rev; |
| | 571 | /** Revision id in PCI Config space */ |
| | 572 | uint32_t pci_rev; |
| | 573 | uint32_t family; |
| | 574 | uint32_t num_shader_engines; |
| | 575 | uint32_t num_shader_arrays_per_engine; |
| | 576 | /* in KHz */ |
| | 577 | uint32_t gpu_counter_freq; |
| | 578 | uint64_t max_engine_clock; |
| | 579 | uint64_t max_memory_clock; |
| | 580 | /* cu information */ |
| | 581 | uint32_t cu_active_number; |
| | 582 | uint32_t cu_ao_mask; |
| | 583 | uint32_t cu_bitmap[4][4]; |
| | 584 | /** Render backend pipe mask. One render backend is CB+DB. */ |
| | 585 | uint32_t enabled_rb_pipes_mask; |
| | 586 | uint32_t num_rb_pipes; |
| | 587 | uint32_t num_hw_gfx_contexts; |
| | 588 | uint32_t _pad; |
| | 589 | uint64_t ids_flags; |
| | 590 | /** Starting virtual address for UMDs. */ |
| | 591 | uint64_t virtual_address_offset; |
| | 592 | /** The maximum virtual address */ |
| | 593 | uint64_t virtual_address_max; |
| | 594 | /** Required alignment of virtual addresses. */ |
| | 595 | uint32_t virtual_address_alignment; |
| | 596 | /** Page table entry - fragment size */ |
| | 597 | uint32_t pte_fragment_size; |
| | 598 | uint32_t gart_page_size; |
| | 599 | /** constant engine ram size*/ |
| | 600 | uint32_t ce_ram_size; |
| | 601 | /** video memory type info*/ |
| | 602 | uint32_t vram_type; |
| | 603 | /** video memory bit width*/ |
| | 604 | uint32_t vram_bit_width; |
| | 605 | }; |
| | 606 | |
| | 607 | struct drm_amdgpu_info_hw_ip { |
| | 608 | /** Version of h/w IP */ |
| | 609 | uint32_t hw_ip_version_major; |
| | 610 | uint32_t hw_ip_version_minor; |
| | 611 | /** Capabilities */ |
| | 612 | uint64_t capabilities_flags; |
| | 613 | /** command buffer address start alignment*/ |
| | 614 | uint32_t ib_start_alignment; |
| | 615 | /** command buffer size alignment*/ |
| | 616 | uint32_t ib_size_alignment; |
| | 617 | /** Bitmask of available rings. Bit 0 means ring 0, etc. */ |
| | 618 | uint32_t available_rings; |
| | 619 | uint32_t _pad; |
| | 620 | }; |
| | 621 | |
| | 622 | /* |
| | 623 | * Supported GPU families |
| | 624 | */ |
| | 625 | #define AMDGPU_FAMILY_UNKNOWN 0 |
| | 626 | #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ |
| | 627 | #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ |
| | 628 | #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ |
| | 629 | #define AMDGPU_FAMILY_CZ 135 /* Carrizo */ |
| | 630 | |
| | 631 | #endif |