Pull x86 cache flush updates from Thomas Gleixner: "A reworked version of the opt-in L1D flush mechanism. This is a stop gap for potential future speculation related hardware vulnerabilities and a mechanism for truly security paranoid applications. It allows a task to request that the L1D cache is flushed when the kernel switches to a different mm. This can be requested via prctl(). Changes vs the previous versions: - Get rid of the software flush fallback - Make the handling consistent with other mitigations - Kill the task when it ends up on a SMT enabled core which defeats the purpose of L1D flushing obviously" * tag 'x86-cpu-2021-08-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: Documentation: Add L1D flushing Documentation x86, prctl: Hook L1D flushing in via prctl x86/mm: Prepare for opt-in based L1D flush in switch_mm() x86/process: Make room for TIF_SPEC_L1D_FLUSH sched: Add task_work callback for paranoid L1D flush x86/mm: Refactor cond_ibpb() to support other use cases x86/smp: Add a per-cpu view of SMT state
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| @@ -213,6 +213,7 @@ struct prctl_mm_map { · 212 unmodified lines | ||
| 213 | 213 | /* Speculation control variants */ |
| 214 | 214 | # define PR_SPEC_STORE_BYPASS 0 |
| 215 | 215 | # define PR_SPEC_INDIRECT_BRANCH 1 |
| 216 | +# define PR_SPEC_L1D_FLUSH 2 | |
| 216 | 217 | /* Return and control values for PR_SET/GET_SPECULATION_CTRL */ |
| 217 | 218 | # define PR_SPEC_NOT_AFFECTED 0 |
| 218 | 219 | # define PR_SPEC_PRCTL (1UL << 0) |