Merge tag 'perf-core-2026-06-14' of gitolite.kernel.org:pub/scm/linux/kernel/git/tip/tip

Pull performance events updates from Ingo Molnar: "Core perf code updates: - Reveal PMU type in fdinfo (Chun-Tse Shao) Intel CPU PMU driver updates: - Fix various inaccurate hard-coded event configurations (Dapeng Mi) Intel uncore PMU driver updates (Zide Chen): - Fix discovery unit lookup bug for multi-die systems - Guard against invalid box control address - Fix PCI device refcount leak in UPI discovery - Defer ADL global PMON enable to enable_box() to save power - Fix uncore_die_to_cpu() for offline dies - Implement global init callback for GNR uncore AMD CPU PMU driver updates: - Always use the NMI latency mitigation (Sandipan Das) AMD uncore PMU driver updates: - Use Node ID to identify DF and UMC domains (Sandipan Das)" * tag 'perf-core-2026-06-14' of gitolite.kernel.org:pub/scm/linux/kernel/git/tip/tip: (22 commits) perf/x86/amd/uncore: Use Node ID to identify DF and UMC domains perf: Reveal PMU type in fdinfo perf/x86/intel/uncore: Implement global init callback for GNR uncore perf/x86/intel/uncore: Fix uncore_die_to_cpu() for offline dies perf/x86/intel/uncore: Move die_to_cpu() to uncore.c perf/x86/intel/uncore: Defer ADL global PMON enable to enable_box() perf/x86/intel/uncore: Fix PCI device refcount leak in UPI discovery perf/x86/intel/uncore: Guard against invalid box control address perf/x86/intel/uncore: Fix discovery unit lookup for multi-die systems perf/x86/amd/core: Always use the NMI latency mitigation perf/x86/intel: Update event constraints and cache_extra_regsfor CWF perf/x86/intel: Update event constraints and cache_extra_regsfor SRF perf/x86/intel: Update event constraints and cache_extra_regsfor NVL perf/x86/intel: Update event constraints for PTL perf/x86/intel: Update event constraints and cache_extra_regsfor ARL perf/x86/intel: Update event constraints and cache_extra_regsfor LNL perf/x86/intel: Update event constraints and cache_extra_regsfor MTL perf/x86/intel: Update event constraints and cache_extra_regsfor ADL perf/x86/intel: Update event constraints for DMR perf/x86/intel: Update event constraints and cache_extra_regsfor SPR ...

Linus Torvalds committed 5 months ago

Commit 0bcc2dc2 parents d8d706a 67d277211 files · +540 −145Browse files

Unified · Split

11 files

arch/x86/events/amd/core.c +3 −3
arch/x86/events/amd/uncore.c +3 −3
arch/x86/events/intel/core.c +408 −81
arch/x86/events/intel/ds.c +17 −6
arch/x86/events/intel/uncore.c +31 −1
arch/x86/events/intel/uncore.h +2 −1
arch/x86/events/intel/uncore_discovery.c +31 −15
arch/x86/events/intel/uncore_snb.c +0 −7
arch/x86/events/intel/uncore_snbep.c +12 −24
arch/x86/events/perf_event.h +4 −4
kernel/events/core.c +29 −0

arch/x86/events/amd/core.c+3−3

 	u64 even_ctr_mask = 0ULL;
 	int i;
-	if (!boot_cpu_has(X86_FEATURE_PERFCTR_CORE))
-		return 0;
 	/* Avoid calculating the value each time in the NMI handler */
 	perf_nmi_window = msecs_to_jiffies(100);
+	if (!boot_cpu_has(X86_FEATURE_PERFCTR_CORE))
+		return 0;
 	/*
 	 * If core performance counter extensions exists, we must use
 	 * MSR_F15H_PERF_CTL/MSR_F15H_PERF_CTR msrs. See also

arch/x86/events/amd/uncore.c+3−3

@@ -700,7 +700,7 @@ void amd_uncore_df_ctx_scan(struct amd_uncore *uncore, unsigned int cpu) · 699 unmodified lines
700	info.split.aux_data = 0;	700	info.split.aux_data = 0;
701	info.split.num_pmcs = NUM_COUNTERS_NB;	701	info.split.num_pmcs = NUM_COUNTERS_NB;
702	info.split.gid = 0;	702	info.split.gid = 0;
703	info.split.cid = topology_logical_package_id(cpu);	703	info.split.cid = topology_amd_node_id(cpu);
704		704
705	if (pmu_version >= 2) {	705	if (pmu_version >= 2) {
706	ebx.full = cpuid_ebx(EXT_PERFMON_DEBUG_FEATURES);	706	ebx.full = cpuid_ebx(EXT_PERFMON_DEBUG_FEATURES);
@@ -999,8 +999,8 @@ void amd_uncore_umc_ctx_scan(struct amd_uncore *uncore, unsigned int cpu) · 292 unmodified lines
999	cpuid(EXT_PERFMON_DEBUG_FEATURES, &eax, &ebx.full, &ecx, &edx);	999	cpuid(EXT_PERFMON_DEBUG_FEATURES, &eax, &ebx.full, &ecx, &edx);
1000	info.split.aux_data = ecx; /* stash active mask */	1000	info.split.aux_data = ecx; /* stash active mask */
1001	info.split.num_pmcs = ebx.split.num_umc_pmc;	1001	info.split.num_pmcs = ebx.split.num_umc_pmc;
1002	info.split.gid = topology_logical_package_id(cpu);	1002	info.split.gid = topology_amd_node_id(cpu);
1003	info.split.cid = topology_logical_package_id(cpu);	1003	info.split.cid = topology_amd_node_id(cpu);
1004	*per_cpu_ptr(uncore->info, cpu) = info;	1004	*per_cpu_ptr(uncore->info, cpu) = info;
1005	}	1005	}
1006		1006

arch/x86/events/intel/core.c+408−81

@@ -215,39 +215,47 @@ static struct event_constraint intel_slm_event_constraints[] __read_mostly = · 214 unmodified lines
215		215
216	static struct event_constraint intel_grt_event_constraints[] __read_mostly = {	216	static struct event_constraint intel_grt_event_constraints[] __read_mostly = {
217	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */	217	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
		218	FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
218	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */	219	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
219	FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */	220	FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
		221	FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
220	FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */	222	FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
221	EVENT_CONSTRAINT_END	223	EVENT_CONSTRAINT_END
222	};	224	};
223		225
224	static struct event_constraint intel_skt_event_constraints[] __read_mostly = {	226	static struct event_constraint intel_skt_event_constraints[] __read_mostly = {
225	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */	227	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
		228	FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
226	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */	229	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
227	FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */	230	FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
		231	FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
228	FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */	232	FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
229	FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */	233	FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */
		234	FIXED_EVENT_CONSTRAINT(0x0500, 4), /* pseudo TOPDOWN_BAD_SPECULATION.ALL */
230	FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */	235	FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */
		236	FIXED_EVENT_CONSTRAINT(0x0600, 5), /* pseudo TOPDOWN_FE_BOUND.ALL */
231	FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */	237	FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */
		238	FIXED_EVENT_CONSTRAINT(0x0700, 6), /* pseudo TOPDOWN_RETIRING.ALL */
232	EVENT_CONSTRAINT_END	239	EVENT_CONSTRAINT_END
233	};	240	};
234		241
235	static struct event_constraint intel_arw_event_constraints[] __read_mostly = {	242	static struct event_constraint intel_arw_event_constraints[] __read_mostly = {
236	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */	243	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
		244	FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
237	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */	245	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
238	FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */	246	FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
		247	FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
239	FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */	248	FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
240	FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */	249	FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */
		250	FIXED_EVENT_CONSTRAINT(0x0500, 4), /* pseudo TOPDOWN_BAD_SPECULATION.ALL */
241	FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */	251	FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */
		252	FIXED_EVENT_CONSTRAINT(0x0600, 5), /* pseudo TOPDOWN_FE_BOUND.ALL */
242	FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */	253	FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */
		254	FIXED_EVENT_CONSTRAINT(0x0700, 6), /* pseudo TOPDOWN_RETIRING.ALL */
243	INTEL_UEVENT_CONSTRAINT(0x01b7, 0x1),	255	INTEL_UEVENT_CONSTRAINT(0x01b7, 0x1),
244	INTEL_UEVENT_CONSTRAINT(0x02b7, 0x2),	256	INTEL_UEVENT_CONSTRAINT(0x02b7, 0x2),
245	INTEL_UEVENT_CONSTRAINT(0x04b7, 0x4),	257	INTEL_UEVENT_CONSTRAINT(0x04b7, 0x4),
246	INTEL_UEVENT_CONSTRAINT(0x08b7, 0x8),	258	INTEL_UEVENT_CONSTRAINT(0x08b7, 0x8),
247	INTEL_UEVENT_CONSTRAINT(0x01d4, 0x1),
248	INTEL_UEVENT_CONSTRAINT(0x02d4, 0x2),
249	INTEL_UEVENT_CONSTRAINT(0x04d4, 0x4),
250	INTEL_UEVENT_CONSTRAINT(0x08d4, 0x8),
251	INTEL_UEVENT_CONSTRAINT(0x0175, 0x1),	259	INTEL_UEVENT_CONSTRAINT(0x0175, 0x1),
252	INTEL_UEVENT_CONSTRAINT(0x0275, 0x2),	260	INTEL_UEVENT_CONSTRAINT(0x0275, 0x2),
253	INTEL_UEVENT_CONSTRAINT(0x21d3, 0x1),	261	INTEL_UEVENT_CONSTRAINT(0x21d3, 0x1),
@@ -310,10 +318,11 @@ static struct extra_reg intel_skl_extra_regs[] __read_mostly = { · 56 unmodified lines
310	static struct event_constraint intel_icl_event_constraints[] = {	318	static struct event_constraint intel_icl_event_constraints[] = {
311	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */	319	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
312	FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */	320	FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */
313	FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */	321	FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
314	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */	322	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
315	FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */	323	FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
316	FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */	324	FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
		325	FIXED_EVENT_CONSTRAINT(0x0400, 3), /* pseudo TOPDOWN.SLOTS */
317	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),	326	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
318	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),	327	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
319	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),	328	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
@@ -355,11 +364,12 @@ static struct extra_reg intel_glc_extra_regs[] __read_mostly = { · 35 unmodified lines
355		364
356	static struct event_constraint intel_glc_event_constraints[] = {	365	static struct event_constraint intel_glc_event_constraints[] = {
357	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */	366	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
358	FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */	367	FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
359	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */	368	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
360	FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */	369	FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
		370	FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
361	FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */	371	FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
362	FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */	372	FIXED_EVENT_CONSTRAINT(0x0400, 3), /* pseudo TOPDOWN.SLOTS */
363	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),	373	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
364	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),	374	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
365	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),	375	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
@@ -379,9 +389,13 @@ static struct event_constraint intel_glc_event_constraints[] = { · 13 unmodified lines
379		389
380	INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf),	390	INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf),
381	INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf),	391	INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf),
		392	INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf),
		393	INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf),
382	INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf),	394	INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf),
		395	INTEL_UEVENT_CONSTRAINT(0x0ca3, 0xf),
383	INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),	396	INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
384	INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),	397	INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
		398	INTEL_UEVENT_CONSTRAINT(0x01cd, 0xfe),
385	INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1),	399	INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1),
386	INTEL_EVENT_CONSTRAINT(0xce, 0x1),	400	INTEL_EVENT_CONSTRAINT(0xce, 0x1),
387	INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),	401	INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
@@ -407,11 +421,12 @@ static struct extra_reg intel_rwc_extra_regs[] __read_mostly = { · 19 unmodified lines
407		421
408	static struct event_constraint intel_lnc_event_constraints[] = {	422	static struct event_constraint intel_lnc_event_constraints[] = {
409	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */	423	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
410	FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */	424	FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
411	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */	425	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
412	FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */	426	FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
		427	FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
413	FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */	428	FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
414	FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */	429	FIXED_EVENT_CONSTRAINT(0x0400, 3), /* pseudo TOPDOWN.SLOTS */
415	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),	430	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
416	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),	431	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
417	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),	432	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
@@ -423,8 +438,6 @@ static struct event_constraint intel_lnc_event_constraints[] = { · 5 unmodified lines
423		438
424	INTEL_EVENT_CONSTRAINT(0x20, 0xf),	439	INTEL_EVENT_CONSTRAINT(0x20, 0xf),
425		440
426	INTEL_UEVENT_CONSTRAINT(0x012a, 0xf),
427	INTEL_UEVENT_CONSTRAINT(0x012b, 0xf),
428	INTEL_UEVENT_CONSTRAINT(0x0148, 0x4),	441	INTEL_UEVENT_CONSTRAINT(0x0148, 0x4),
429	INTEL_UEVENT_CONSTRAINT(0x0175, 0x4),	442	INTEL_UEVENT_CONSTRAINT(0x0175, 0x4),
430		443
@@ -435,15 +448,14 @@ static struct event_constraint intel_lnc_event_constraints[] = { · 4 unmodified lines
435	INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),	448	INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
436	INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),	449	INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
437	INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),	450	INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
438	INTEL_UEVENT_CONSTRAINT(0x10a4, 0x1),	451	INTEL_UEVENT_CONSTRAINT(0x10a4, 0x8),
439	INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8),	452	INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8),
440	INTEL_UEVENT_CONSTRAINT(0x01cd, 0x3fc),	453	INTEL_UEVENT_CONSTRAINT(0x01cd, 0x3fc),
441	INTEL_UEVENT_CONSTRAINT(0x02cd, 0x3),	454	INTEL_UEVENT_CONSTRAINT(0x02cd, 0x3),
442		455
		456	INTEL_UEVENT_CONSTRAINT(0x87d0, 0x3ff),
443	INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),	457	INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
444		458
445	INTEL_UEVENT_CONSTRAINT(0x00e0, 0xf),
446
447	EVENT_CONSTRAINT_END	459	EVENT_CONSTRAINT_END
448	};	460	};
449		461
@@ -460,11 +472,12 @@ static struct extra_reg intel_lnc_extra_regs[] __read_mostly = { · 10 unmodified lines
460		472
461	static struct event_constraint intel_pnc_event_constraints[] = {	473	static struct event_constraint intel_pnc_event_constraints[] = {
462	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */	474	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
463	FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */	475	FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
464	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */	476	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
465	FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */	477	FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
		478	FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
466	FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */	479	FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
467	FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */	480	FIXED_EVENT_CONSTRAINT(0x0400, 3), /* pseudo TOPDOWN.SLOTS */
468	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),	481	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
469	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),	482	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
470	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),	483	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
@@ -706,6 +719,80 @@ static __initconst const u64 glc_hw_cache_event_ids · 235 unmodified lines
706	},	719	},
707	};	720	};
708		721
		722	/* ADL P-core (Golden cove) specific event code. */
		723	static __initconst const u64 adl_glc_hw_cache_event_ids
		724	[PERF_COUNT_HW_CACHE_MAX]
		725	[PERF_COUNT_HW_CACHE_OP_MAX]
		726	[PERF_COUNT_HW_CACHE_RESULT_MAX] =
		727	{
		728	[ C(L1D ) ] = {
		729	[ C(OP_READ) ] = {
		730	[ C(RESULT_ACCESS) ] = 0x81d0,
		731	[ C(RESULT_MISS) ] = 0xe124,
		732	},
		733	[ C(OP_WRITE) ] = {
		734	[ C(RESULT_ACCESS) ] = 0x82d0,
		735	},
		736	},
		737	[ C(L1I ) ] = {
		738	[ C(OP_READ) ] = {
		739	[ C(RESULT_MISS) ] = 0xe424,
		740	},
		741	[ C(OP_WRITE) ] = {
		742	[ C(RESULT_ACCESS) ] = -1,
		743	[ C(RESULT_MISS) ] = -1,
		744	},
		745	},
		746	[ C(LL ) ] = {
		747	[ C(OP_READ) ] = {
		748	[ C(RESULT_ACCESS) ] = 0x12a,
		749	[ C(RESULT_MISS) ] = 0x12a,
		750	},
		751	[ C(OP_WRITE) ] = {
		752	[ C(RESULT_ACCESS) ] = 0x12a,
		753	[ C(RESULT_MISS) ] = 0x12a,
		754	},
		755	},
		756	[ C(DTLB) ] = {
		757	[ C(OP_READ) ] = {
		758	[ C(RESULT_ACCESS) ] = 0x81d0,
		759	[ C(RESULT_MISS) ] = 0xe12,
		760	},
		761	[ C(OP_WRITE) ] = {
		762	[ C(RESULT_ACCESS) ] = 0x82d0,
		763	[ C(RESULT_MISS) ] = 0xe13,
		764	},
		765	},
		766	[ C(ITLB) ] = {
		767	[ C(OP_READ) ] = {
		768	[ C(RESULT_ACCESS) ] = -1,
		769	[ C(RESULT_MISS) ] = 0xe11,
		770	},
		771	[ C(OP_WRITE) ] = {
		772	[ C(RESULT_ACCESS) ] = -1,
		773	[ C(RESULT_MISS) ] = -1,
		774	},
		775	[ C(OP_PREFETCH) ] = {
		776	[ C(RESULT_ACCESS) ] = -1,
		777	[ C(RESULT_MISS) ] = -1,
		778	},
		779	},
		780	[ C(BPU ) ] = {
		781	[ C(OP_READ) ] = {
		782	[ C(RESULT_ACCESS) ] = 0x4c4,
		783	[ C(RESULT_MISS) ] = 0x4c5,
		784	},
		785	[ C(OP_WRITE) ] = {
		786	[ C(RESULT_ACCESS) ] = -1,
		787	[ C(RESULT_MISS) ] = -1,
		788	},
		789	[ C(OP_PREFETCH) ] = {
		790	[ C(RESULT_ACCESS) ] = -1,
		791	[ C(RESULT_MISS) ] = -1,
		792	},
		793	},
		794	};
		795
709	static __initconst const u64 glc_hw_cache_extra_regs	796	static __initconst const u64 glc_hw_cache_extra_regs
710	[PERF_COUNT_HW_CACHE_MAX]	797	[PERF_COUNT_HW_CACHE_MAX]
711	[PERF_COUNT_HW_CACHE_OP_MAX]	798	[PERF_COUNT_HW_CACHE_OP_MAX]
@@ -713,18 +800,71 @@ static __initconst const u64 glc_hw_cache_extra_regs · 1 unmodified line
713	{	800	{
714	[ C(LL ) ] = {	801	[ C(LL ) ] = {
715	[ C(OP_READ) ] = {	802	[ C(OP_READ) ] = {
716	[ C(RESULT_ACCESS) ] = 0x10001,	803	[ C(RESULT_ACCESS) ] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
717	[ C(RESULT_MISS) ] = 0x3fbfc00001,	804	[ C(RESULT_MISS) ] = 0x3fbfc00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
718	},	805	},
719	[ C(OP_WRITE) ] = {	806	[ C(OP_WRITE) ] = {
720	[ C(RESULT_ACCESS) ] = 0x3f3ffc0002,	807	[ C(RESULT_ACCESS) ] = 0x3f3ffc0002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
721	[ C(RESULT_MISS) ] = 0x3f3fc00002,	808	[ C(RESULT_MISS) ] = 0x3f3fc00002, /* OCR.DEMAND_RFO.L3_MISS */
722	},	809	},
723	},	810	},
724	[ C(NODE) ] = {	811	[ C(NODE) ] = {
725	[ C(OP_READ) ] = {	812	[ C(OP_READ) ] = {
726	[ C(RESULT_ACCESS) ] = 0x10c000001,	813	[ C(RESULT_ACCESS) ] = 0x104000001, /* OCR.DEMAND_DATA_RD.LOCAL_DRAM */
727	[ C(RESULT_MISS) ] = 0x3fb3000001,	814	[ C(RESULT_MISS) ] = 0x730000001, /* OCR.DEMAND_DATA_RD.REMOTE_DRAM */
		815	},
		816	},
		817	};
		818
		819	/* ADL P-core (Golden cove) specific extra regs value. */
		820	static __initconst const u64 adl_glc_hw_cache_extra_regs
		821	[PERF_COUNT_HW_CACHE_MAX]
		822	[PERF_COUNT_HW_CACHE_OP_MAX]
		823	[PERF_COUNT_HW_CACHE_RESULT_MAX] =
		824	{
		825	[ C(LL ) ] = {
		826	[ C(OP_READ) ] = {
		827	[ C(RESULT_ACCESS) ] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
		828	[ C(RESULT_MISS) ] = 0x3fbfc00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
		829	},
		830	[ C(OP_WRITE) ] = {
		831	[ C(RESULT_ACCESS) ] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
		832	[ C(RESULT_MISS) ] = 0x3fbfc00002, /* OCR.DEMAND_RFO.L3_MISS */
		833	},
		834	},
		835	};
		836
		837	static __initconst const u64 lnc_hw_cache_extra_regs
		838	[PERF_COUNT_HW_CACHE_MAX]
		839	[PERF_COUNT_HW_CACHE_OP_MAX]
		840	[PERF_COUNT_HW_CACHE_RESULT_MAX] =
		841	{
		842	[ C(LL ) ] = {
		843	[ C(OP_READ) ] = {
		844	[ C(RESULT_ACCESS) ] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
		845	[ C(RESULT_MISS) ] = 0x9E7FA000001, /* OCR.DEMAND_DATA_RD.L3_MISS */
		846	},
		847	[ C(OP_WRITE) ] = {
		848	[ C(RESULT_ACCESS) ] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
		849	[ C(RESULT_MISS) ] = 0x9E7FA000002, /* OCR.DEMAND_RFO.L3_MISS */
		850	},
		851	},
		852	};
		853
		854	/* ARL specific lioncove hw_cache_extra_regs[] variant. */
		855	static __initconst const u64 arl_lnc_hw_cache_extra_regs
		856	[PERF_COUNT_HW_CACHE_MAX]
		857	[PERF_COUNT_HW_CACHE_OP_MAX]
		858	[PERF_COUNT_HW_CACHE_RESULT_MAX] =
		859	{
		860	[ C(LL ) ] = {
		861	[ C(OP_READ) ] = {
		862	[ C(RESULT_ACCESS) ] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
		863	[ C(RESULT_MISS) ] = 0xFE7F8000001, /* OCR.DEMAND_DATA_RD.L3_MISS */
		864	},
		865	[ C(OP_WRITE) ] = {
		866	[ C(RESULT_ACCESS) ] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
		867	[ C(RESULT_MISS) ] = 0xFE7F8000002, /* OCR.DEMAND_RFO.L3_MISS */
728	},	868	},
729	},	869	},
730	};	870	};
@@ -815,12 +955,29 @@ static __initconst const u64 pnc_hw_cache_extra_regs · 84 unmodified lines
815	{	955	{
816	[ C(LL ) ] = {	956	[ C(LL ) ] = {
817	[ C(OP_READ) ] = {	957	[ C(OP_READ) ] = {
818	[ C(RESULT_ACCESS) ] = 0x4000000000000001,	958	[ C(RESULT_ACCESS) ] = 0x4000000000000001, /* OMR.DEMAND_DATA_RD.ANY_RESPONSE */
819	[ C(RESULT_MISS) ] = 0xFFFFF000000001,	959	[ C(RESULT_MISS) ] = 0xFFFFF000000001, /* OMR.DEMAND_DATA_RD.L3_MISS */
820	},	960	},
821	[ C(OP_WRITE) ] = {	961	[ C(OP_WRITE) ] = {
822	[ C(RESULT_ACCESS) ] = 0x4000000000000002,	962	[ C(RESULT_ACCESS) ] = 0x4000000000000002, /* OMR.DEMAND_RFO.ANY_RESPONSE */
823	[ C(RESULT_MISS) ] = 0xFFFFF000000002,	963	[ C(RESULT_MISS) ] = 0xFFFFF000000002, /* OMR.DEMAND_RFO.L3_MISS */
		964	},
		965	},
		966	};
		967
		968	static __initconst const u64 cyc_hw_cache_extra_regs
		969	[PERF_COUNT_HW_CACHE_MAX]
		970	[PERF_COUNT_HW_CACHE_OP_MAX]
		971	[PERF_COUNT_HW_CACHE_RESULT_MAX] =
		972	{
		973	[ C(LL ) ] = {
		974	[ C(OP_READ) ] = {
		975	[ C(RESULT_ACCESS) ] = 0x4000000000000001, /* OMR.DEMAND_DATA_RD.ANY_RESPONSE */
		976	[ C(RESULT_MISS) ] = 0xFF03F000000001, /* OMR.DEMAND_DATA_RD.L3_MISS */
		977	},
		978	[ C(OP_WRITE) ] = {
		979	[ C(RESULT_ACCESS) ] = 0x4000000000000002, /* OMR.DEMAND_RFO.ANY_RESPONSE */
		980	[ C(RESULT_MISS) ] = 0xFF03F000000002, /* OMR.DEMAND_RFO.L3_MISS */
824	},	981	},
825	},	982	},
826	};	983	};
@@ -1019,6 +1176,41 @@ static __initconst const u64 skl_hw_cache_extra_regs · 192 unmodified lines
1019	},	1176	},
1020	};	1177	};
1021		1178
		1179	static __initconst const u64 snc_hw_cache_extra_regs
		1180	[PERF_COUNT_HW_CACHE_MAX]
		1181	[PERF_COUNT_HW_CACHE_OP_MAX]
		1182	[PERF_COUNT_HW_CACHE_RESULT_MAX] =
		1183	{
		1184	[ C(LL ) ] = {
		1185	[ C(OP_READ) ] = {
		1186	[ C(RESULT_ACCESS) ] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
		1187	[ C(RESULT_MISS) ] = 0x3FBFC00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
		1188	},
		1189	[ C(OP_WRITE) ] = {
		1190	[ C(RESULT_ACCESS) ] = 0x3F3FFC0002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
		1191	[ C(RESULT_MISS) ] = 0x3F3FC00002, /* OCR.DEMAND_RFO.L3_MISS */
		1192	},
		1193	[ C(OP_PREFETCH) ] = {
		1194	[ C(RESULT_ACCESS) ] = 0x0,
		1195	[ C(RESULT_MISS) ] = 0x0,
		1196	},
		1197	},
		1198	[ C(NODE) ] = {
		1199	[ C(OP_READ) ] = {
		1200	[ C(RESULT_ACCESS) ] = 0x104000001, /* OCR.DEMAND_DATA_RD.LOCAL_DRAM */
		1201	[ C(RESULT_MISS) ] = 0x730000001, /* OCR.DEMAND_DATA_RD.REMOTE_DRAM */
		1202	},
		1203	[ C(OP_WRITE) ] = {
		1204	[ C(RESULT_ACCESS) ] = 0x104000002, /* OCR.DEMAND_RFO.LOCAL_DRAM */
		1205	[ C(RESULT_MISS) ] = 0x730000002, /* OCR.DEMAND_RFO.REMOTE_DRAM */
		1206	},
		1207	[ C(OP_PREFETCH) ] = {
		1208	[ C(RESULT_ACCESS) ] = 0x0,
		1209	[ C(RESULT_MISS) ] = 0x0,
		1210	},
		1211	},
		1212	};
		1213
1022	#define SNB_DMND_DATA_RD (1ULL << 0)	1214	#define SNB_DMND_DATA_RD (1ULL << 0)
1023	#define SNB_DMND_RFO (1ULL << 1)	1215	#define SNB_DMND_RFO (1ULL << 1)
1024	#define SNB_DMND_IFETCH (1ULL << 2)	1216	#define SNB_DMND_IFETCH (1ULL << 2)
@@ -2342,22 +2534,82 @@ static __initconst const u64 tnt_hw_cache_extra_regs · 1317 unmodified lines
2342	},	2534	},
2343	};	2535	};
2344		2536
2345	static __initconst const u64 arw_hw_cache_extra_regs	2537	static __initconst const u64 grt_hw_cache_extra_regs
2346	[PERF_COUNT_HW_CACHE_MAX]	2538	[PERF_COUNT_HW_CACHE_MAX]
2347	[PERF_COUNT_HW_CACHE_OP_MAX]	2539	[PERF_COUNT_HW_CACHE_OP_MAX]
2348	[PERF_COUNT_HW_CACHE_RESULT_MAX] = {	2540	[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2349	[C(LL)] = {	2541	[C(LL)] = {
2350	[C(OP_READ)] = {	2542	[C(OP_READ)] = {
2351	[C(RESULT_ACCESS)] = 0x4000000000000001,	2543	[C(RESULT_ACCESS)] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
2352	[C(RESULT_MISS)] = 0xFFFFF000000001,	2544	[C(RESULT_MISS)] = 0x3F84400001, /* OCR.DEMAND_DATA_RD.L3_MISS */
2353	},	2545	},
2354	[C(OP_WRITE)] = {	2546	[C(OP_WRITE)] = {
2355	[C(RESULT_ACCESS)] = 0x4000000000000002,	2547	[C(RESULT_ACCESS)] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
2356	[C(RESULT_MISS)] = 0xFFFFF000000002,	2548	[C(RESULT_MISS)] = 0x3F84400002, /* OCR.DEMAND_RFO.L3_MISS */
2357	},	2549	},
2358	[C(OP_PREFETCH)] = {	2550	},
2359	[C(RESULT_ACCESS)] = 0x0,	2551	};
2360	[C(RESULT_MISS)] = 0x0,	2552
		2553	static __initconst const u64 cmt_hw_cache_extra_regs
		2554	[PERF_COUNT_HW_CACHE_MAX]
		2555	[PERF_COUNT_HW_CACHE_OP_MAX]
		2556	[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
		2557	[C(LL)] = {
		2558	[C(OP_READ)] = {
		2559	[C(RESULT_ACCESS)] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
		2560	[C(RESULT_MISS)] = 0x3fbfc00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
		2561	},
		2562	[C(OP_WRITE)] = {
		2563	[C(RESULT_ACCESS)] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
		2564	[C(RESULT_MISS)] = 0x3fbfc00002, /* OCR.DEMAND_RFO.L3_MISS */
		2565	},
		2566	},
		2567	};
		2568
		2569	static __initconst const u64 skt_hw_cache_extra_regs
		2570	[PERF_COUNT_HW_CACHE_MAX]
		2571	[PERF_COUNT_HW_CACHE_OP_MAX]
		2572	[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
		2573	[C(LL)] = {
		2574	[C(OP_READ)] = {
		2575	[C(RESULT_ACCESS)] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
		2576	[C(RESULT_MISS)] = 0x13FBFC00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
		2577	},
		2578	[C(OP_WRITE)] = {
		2579	[C(RESULT_ACCESS)] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
		2580	[C(RESULT_MISS)] = 0x13FBFC00002, /* OCR.DEMAND_RFO.L3_MISS */
		2581	},
		2582	},
		2583	};
		2584
		2585	static __initconst const u64 dkt_hw_cache_extra_regs
		2586	[PERF_COUNT_HW_CACHE_MAX]
		2587	[PERF_COUNT_HW_CACHE_OP_MAX]
		2588	[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
		2589	[C(LL)] = {
		2590	[C(OP_READ)] = {
		2591	[C(RESULT_ACCESS)] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
		2592	[C(RESULT_MISS)] = 0x33FBFC00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
		2593	},
		2594	[C(OP_WRITE)] = {
		2595	[C(RESULT_ACCESS)] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
		2596	[C(RESULT_MISS)] = 0x33FBFC00002, /* OCR.DEMAND_RFO.L3_MISS */
		2597	},
		2598	},
		2599	};
		2600
		2601	static __initconst const u64 arw_hw_cache_extra_regs
		2602	[PERF_COUNT_HW_CACHE_MAX]
		2603	[PERF_COUNT_HW_CACHE_OP_MAX]
		2604	[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
		2605	[C(LL)] = {
		2606	[C(OP_READ)] = {
		2607	[C(RESULT_ACCESS)] = 0x4000000000000009, /* OMR.DEMAND_DATA_RD.ANY_RESPONSE */
		2608	[C(RESULT_MISS)] = 0xFF03F000000009, /* OMR.DEMAND_DATA_RD.L3_MISS */
		2609	},
		2610	[C(OP_WRITE)] = {
		2611	[C(RESULT_ACCESS)] = 0x400000000000000A, /* OMR.DEMAND_RFO.ANY_RESPONSE */
		2612	[C(RESULT_MISS)] = 0xFF03F00000000A, /* OMR.DEMAND_RFO.L3_MISS */
2361	},	2613	},
2362	},	2614	},
2363	};	2615	};
@@ -2392,9 +2644,12 @@ static struct attribute *grt_mem_attrs[] = { · 28 unmodified lines
2392	};	2644	};
2393		2645
2394	static struct extra_reg intel_grt_extra_regs[] __read_mostly = {	2646	static struct extra_reg intel_grt_extra_regs[] __read_mostly = {
2395	/* must define OFFCORE_RSP_X first, see intel_fixup_er() */	2647	/*
2396	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),	2648	* Must define OFFCORE_RSP_X first, see intel_fixup_er().
2397	INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),	2649	* Bit 63 only valid on OFFCORE_RSP_0 MSR.
		2650	*/
		2651	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x8003f03fffffffffull, RSP_0),
		2652	INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3f03fffffffffull, RSP_1),
2398	INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),	2653	INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
2399	EVENT_EXTRA_END	2654	EVENT_EXTRA_END
2400	};	2655	};
@@ -2426,10 +2681,6 @@ static struct extra_reg intel_arw_extra_regs[] __read_mostly = { · 25 unmodified lines
2426	INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OMR_1, 0xc0ffffffffffffffull, OMR_1),	2681	INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OMR_1, 0xc0ffffffffffffffull, OMR_1),
2427	INTEL_UEVENT_EXTRA_REG(0x04b7, MSR_OMR_2, 0xc0ffffffffffffffull, OMR_2),	2682	INTEL_UEVENT_EXTRA_REG(0x04b7, MSR_OMR_2, 0xc0ffffffffffffffull, OMR_2),
2428	INTEL_UEVENT_EXTRA_REG(0x08b7, MSR_OMR_3, 0xc0ffffffffffffffull, OMR_3),	2683	INTEL_UEVENT_EXTRA_REG(0x08b7, MSR_OMR_3, 0xc0ffffffffffffffull, OMR_3),
2429	INTEL_UEVENT_EXTRA_REG(0x01d4, MSR_OMR_0, 0xc0ffffffffffffffull, OMR_0),
2430	INTEL_UEVENT_EXTRA_REG(0x02d4, MSR_OMR_1, 0xc0ffffffffffffffull, OMR_1),
2431	INTEL_UEVENT_EXTRA_REG(0x04d4, MSR_OMR_2, 0xc0ffffffffffffffull, OMR_2),
2432	INTEL_UEVENT_EXTRA_REG(0x08d4, MSR_OMR_3, 0xc0ffffffffffffffull, OMR_3),
2433	INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),	2684	INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
2434	INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0),	2685	INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0),
2435	INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1),	2686	INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1),
@@ -3169,10 +3420,10 @@ static void intel_pmu_config_acr(int idx, u64 mask, u32 reload) · 733 unmodified lines
3169	wrmsrl(msr_b + msr_offset, mask);	3420	wrmsrl(msr_b + msr_offset, mask);
3170	cpuc->acr_cfg_b[idx] = mask;	3421	cpuc->acr_cfg_b[idx] = mask;
3171	}	3422	}
3172	/* Only need to update the reload value when there is a valid config value. */	3423	/* Only update CFG_C reload when ACR is actively enabled (mask != 0) */
3173	if (mask && cpuc->acr_cfg_c[idx] != reload) {	3424	if (mask && ((cpuc->cfg_c_val[idx] & ARCH_PEBS_RELOAD) != reload)) {
3174	wrmsrl(msr_c + msr_offset, reload);	3425	wrmsrl(msr_c + msr_offset, reload);
3175	cpuc->acr_cfg_c[idx] = reload;	3426	cpuc->cfg_c_val[idx] = reload;
3176	}	3427	}
3177	}	3428	}
3178		3429
@@ -3198,14 +3449,15 @@ static void intel_pmu_enable_event_ext(struct perf_event *event) · 19 unmodified lines
3198	{	3449	{
3199	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);	3450	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3200	struct hw_perf_event *hwc = &event->hw;	3451	struct hw_perf_event *hwc = &event->hw;
3201	union arch_pebs_index old, new;
3202	struct arch_pebs_cap cap;
3203	u64 ext = 0;	3452	u64 ext = 0;
3204		3453
3205	cap = hybrid(cpuc->pmu, arch_pebs_cap);	3454	if (is_acr_event_group(event))
		3455	ext \|= (-hwc->sample_period) & ARCH_PEBS_RELOAD;
3206		3456
3207	if (event->attr.precise_ip) {	3457	if (event->attr.precise_ip) {
3208	u64 pebs_data_cfg = intel_get_arch_pebs_data_config(event);	3458	u64 pebs_data_cfg = intel_get_arch_pebs_data_config(event);
		3459	struct arch_pebs_cap cap = hybrid(cpuc->pmu, arch_pebs_cap);
		3460	union arch_pebs_index old, new;
3209		3461
3210	ext \|= ARCH_PEBS_EN;	3462	ext \|= ARCH_PEBS_EN;
3211	if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD)	3463	if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD)
@@ -7490,6 +7742,15 @@ static __always_inline void intel_pmu_init_glc(struct pmu *pmu) · 4278 unmodified lines
7490	intel_pmu_ref_cycles_ext();	7742	intel_pmu_ref_cycles_ext();
7491	}	7743	}
7492		7744
		7745	static __always_inline void intel_pmu_init_glc_hybrid(struct pmu *pmu)
		7746	{
		7747	intel_pmu_init_glc(pmu);
		7748
		7749	/* ADL has different extra MSR values from Server for the L3 or node OCR/OMR events. */
		7750	memcpy(hybrid_var(pmu, hw_cache_event_ids), adl_glc_hw_cache_event_ids, sizeof(hw_cache_event_ids));
		7751	memcpy(hybrid_var(pmu, hw_cache_extra_regs), adl_glc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
		7752	}
		7753
7493	static __always_inline void intel_pmu_init_grt(struct pmu *pmu)	7754	static __always_inline void intel_pmu_init_grt(struct pmu *pmu)
7494	{	7755	{
7495	x86_pmu.mid_ack = true;	7756	x86_pmu.mid_ack = true;
@@ -7502,7 +7763,7 @@ static __always_inline void intel_pmu_init_grt(struct pmu *pmu) · 6 unmodified lines
7502	x86_pmu.flags \|= PMU_FL_INSTR_LATENCY;	7763	x86_pmu.flags \|= PMU_FL_INSTR_LATENCY;
7503		7764
7504	memcpy(hybrid_var(pmu, hw_cache_event_ids), glp_hw_cache_event_ids, sizeof(hw_cache_event_ids));	7765	memcpy(hybrid_var(pmu, hw_cache_event_ids), glp_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7505	memcpy(hybrid_var(pmu, hw_cache_extra_regs), tnt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));	7766	memcpy(hybrid_var(pmu, hw_cache_extra_regs), grt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7506	hybrid_var(pmu, hw_cache_event_ids)[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;	7767	hybrid_var(pmu, hw_cache_event_ids)[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
7507	hybrid(pmu, event_constraints) = intel_grt_event_constraints;	7768	hybrid(pmu, event_constraints) = intel_grt_event_constraints;
7508	hybrid(pmu, pebs_constraints) = intel_grt_pebs_event_constraints;	7769	hybrid(pmu, pebs_constraints) = intel_grt_pebs_event_constraints;
@@ -7511,12 +7772,24 @@ static __always_inline void intel_pmu_init_grt(struct pmu *pmu) · 2 unmodified lines
7511	intel_pmu_ref_cycles_ext();	7772	intel_pmu_ref_cycles_ext();
7512	}	7773	}
7513		7774
		7775	static __always_inline void intel_pmu_init_cmt(struct pmu *pmu)
		7776	{
		7777	intel_pmu_init_grt(pmu);
		7778	memcpy(hybrid_var(pmu, hw_cache_extra_regs),
		7779	cmt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
		7780	hybrid(pmu, pebs_constraints) = intel_cmt_pebs_event_constraints;
		7781	hybrid(pmu, extra_regs) = intel_cmt_extra_regs;
		7782	}
		7783
7514	static __always_inline void intel_pmu_init_lnc(struct pmu *pmu)	7784	static __always_inline void intel_pmu_init_lnc(struct pmu *pmu)
7515	{	7785	{
7516	intel_pmu_init_glc(pmu);	7786	intel_pmu_init_glc(pmu);
7517	hybrid(pmu, event_constraints) = intel_lnc_event_constraints;	7787	hybrid(pmu, event_constraints) = intel_lnc_event_constraints;
7518	hybrid(pmu, pebs_constraints) = intel_lnc_pebs_event_constraints;	7788	hybrid(pmu, pebs_constraints) = intel_lnc_pebs_event_constraints;
7519	hybrid(pmu, extra_regs) = intel_lnc_extra_regs;	7789	hybrid(pmu, extra_regs) = intel_lnc_extra_regs;
		7790
		7791	memcpy(hybrid_var(pmu, hw_cache_event_ids), adl_glc_hw_cache_event_ids, sizeof(hw_cache_event_ids));
		7792	memcpy(hybrid_var(pmu, hw_cache_extra_regs), lnc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7520	}	7793	}
7521		7794
7522	static __always_inline void intel_pmu_init_pnc(struct pmu *pmu)	7795	static __always_inline void intel_pmu_init_pnc(struct pmu *pmu)
@@ -7534,14 +7807,41 @@ static __always_inline void intel_pmu_init_pnc(struct pmu *pmu) · 11 unmodified lines
7534	static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr);	7807	static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
7535	}	7808	}
7536		7809
		7810	static __always_inline void intel_pmu_init_cyc(struct pmu *pmu)
		7811	{
		7812	intel_pmu_init_pnc(pmu);
		7813	memcpy(hybrid_var(pmu, hw_cache_extra_regs),
		7814	cyc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
		7815	}
		7816
7537	static __always_inline void intel_pmu_init_skt(struct pmu *pmu)	7817	static __always_inline void intel_pmu_init_skt(struct pmu *pmu)
7538	{	7818	{
7539	intel_pmu_init_grt(pmu);	7819	intel_pmu_init_cmt(pmu);
7540	hybrid(pmu, event_constraints) = intel_skt_event_constraints;	7820	hybrid(pmu, event_constraints) = intel_skt_event_constraints;
7541	hybrid(pmu, extra_regs) = intel_cmt_extra_regs;	7821	memcpy(hybrid_var(pmu, hw_cache_extra_regs),
		7822	skt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7542	static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr);	7823	static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
7543	}	7824	}
7544		7825
		7826	/* Hybrid client variant. */
		7827	static __always_inline void intel_pmu_init_dkt_hybrid(struct pmu *pmu)
		7828	{
		7829	intel_pmu_init_skt(pmu);
		7830	hybrid(pmu, pebs_constraints) = intel_dkt_pebs_event_constraints;
		7831	}
		7832
		7833	/*
		7834	* Darkmont is used by the CWF and PTL E-cores, but their L3 OCR
		7835	* events require different extra MSR values. Keep a separate init
		7836	* function for the non-hybrid server variant.
		7837	*/
		7838	static __always_inline void intel_pmu_init_dkt(struct pmu *pmu)
		7839	{
		7840	intel_pmu_init_dkt_hybrid(pmu);
		7841	memcpy(hybrid_var(pmu, hw_cache_extra_regs),
		7842	dkt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
		7843	}
		7844
7545	static __always_inline void intel_pmu_init_arw(struct pmu *pmu)	7845	static __always_inline void intel_pmu_init_arw(struct pmu *pmu)
7546	{	7846	{
7547	intel_pmu_init_grt(pmu);	7847	intel_pmu_init_grt(pmu);
@@ -7550,7 +7850,7 @@ static __always_inline void intel_pmu_init_arw(struct pmu *pmu) · 2 unmodified lines
7550	memcpy(hybrid_var(pmu, hw_cache_extra_regs),	7850	memcpy(hybrid_var(pmu, hw_cache_extra_regs),
7551	arw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));	7851	arw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7552	hybrid(pmu, event_constraints) = intel_arw_event_constraints;	7852	hybrid(pmu, event_constraints) = intel_arw_event_constraints;
7553	hybrid(pmu, pebs_constraints) = intel_arw_pebs_event_constraints;	7853	hybrid(pmu, pebs_constraints) = intel_dkt_pebs_event_constraints;
7554	hybrid(pmu, extra_regs) = intel_arw_extra_regs;	7854	hybrid(pmu, extra_regs) = intel_arw_extra_regs;
7555	static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr);	7855	static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
7556	}	7856	}
@@ -7864,8 +8164,7 @@ __init int intel_pmu_init(void) · 307 unmodified lines
7864		8164
7865	case INTEL_ATOM_CRESTMONT:	8165	case INTEL_ATOM_CRESTMONT:
7866	case INTEL_ATOM_CRESTMONT_X:	8166	case INTEL_ATOM_CRESTMONT_X:
7867	intel_pmu_init_grt(NULL);	8167	intel_pmu_init_cmt(NULL);
7868	x86_pmu.extra_regs = intel_cmt_extra_regs;
7869	intel_pmu_pebs_data_source_cmt();	8168	intel_pmu_pebs_data_source_cmt();
7870	x86_pmu.pebs_latency_data = cmt_latency_data;	8169	x86_pmu.pebs_latency_data = cmt_latency_data;
7871	x86_pmu.get_event_constraints = cmt_get_event_constraints;	8170	x86_pmu.get_event_constraints = cmt_get_event_constraints;
@@ -7877,7 +8176,7 @@ __init int intel_pmu_init(void) · 5 unmodified lines
7877	break;	8176	break;
7878		8177
7879	case INTEL_ATOM_DARKMONT_X:	8178	case INTEL_ATOM_DARKMONT_X:
7880	intel_pmu_init_skt(NULL);	8179	intel_pmu_init_dkt(NULL);
7881	intel_pmu_pebs_data_source_cmt();	8180	intel_pmu_pebs_data_source_cmt();
7882	x86_pmu.pebs_latency_data = cmt_latency_data;	8181	x86_pmu.pebs_latency_data = cmt_latency_data;
7883	x86_pmu.get_event_constraints = cmt_get_event_constraints;	8182	x86_pmu.get_event_constraints = cmt_get_event_constraints;
@@ -8153,17 +8452,19 @@ __init int intel_pmu_init(void) · 269 unmodified lines
8153		8452
8154	case INTEL_ICELAKE_X:	8453	case INTEL_ICELAKE_X:
8155	case INTEL_ICELAKE_D:	8454	case INTEL_ICELAKE_D:
		8455	memcpy(hw_cache_extra_regs, snc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8156	x86_pmu.pebs_ept = 1;	8456	x86_pmu.pebs_ept = 1;
8157	pmem = true;	8457	pmem = true;
8158	fallthrough;	8458	goto snc_common;
8159	case INTEL_ICELAKE_L:	8459	case INTEL_ICELAKE_L:
8160	case INTEL_ICELAKE:	8460	case INTEL_ICELAKE:
8161	case INTEL_TIGERLAKE_L:	8461	case INTEL_TIGERLAKE_L:
8162	case INTEL_TIGERLAKE:	8462	case INTEL_TIGERLAKE:
8163	case INTEL_ROCKETLAKE:	8463	case INTEL_ROCKETLAKE:
		8464	memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
		8465	snc_common:
8164	x86_pmu.late_ack = true;	8466	x86_pmu.late_ack = true;
8165	memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));	8467	memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
8166	memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8167	hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;	8468	hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
8168	intel_pmu_lbr_init_skl();	8469	intel_pmu_lbr_init_skl();
8169		8470
@@ -8259,7 +8560,7 @@ __init int intel_pmu_init(void) · 89 unmodified lines
8259		8560
8260	/* Initialize big core specific PerfMon capabilities.*/	8561	/* Initialize big core specific PerfMon capabilities.*/
8261	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];	8562	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8262	intel_pmu_init_glc(&pmu->pmu);	8563	intel_pmu_init_glc_hybrid(&pmu->pmu);
8263	if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) {	8564	if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) {
8264	pmu->cntr_mask64 <<= 2;	8565	pmu->cntr_mask64 <<= 2;
8265	pmu->cntr_mask64 \|= 0x3;	8566	pmu->cntr_mask64 \|= 0x3;
@@ -8316,13 +8617,12 @@ __init int intel_pmu_init(void) · 50 unmodified lines
8316		8617
8317	/* Initialize big core specific PerfMon capabilities.*/	8618	/* Initialize big core specific PerfMon capabilities.*/
8318	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];	8619	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8319	intel_pmu_init_glc(&pmu->pmu);	8620	intel_pmu_init_glc_hybrid(&pmu->pmu);
8320	pmu->extra_regs = intel_rwc_extra_regs;	8621	pmu->extra_regs = intel_rwc_extra_regs;
8321		8622
8322	/* Initialize Atom core specific PerfMon capabilities.*/	8623	/* Initialize Atom core specific PerfMon capabilities.*/
8323	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];	8624	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
8324	intel_pmu_init_grt(&pmu->pmu);	8625	intel_pmu_init_cmt(&pmu->pmu);
8325	pmu->extra_regs = intel_cmt_extra_regs;
8326		8626
8327	intel_pmu_pebs_data_source_mtl();	8627	intel_pmu_pebs_data_source_mtl();
8328	pr_cont("Meteorlake Hybrid events, ");	8628	pr_cont("Meteorlake Hybrid events, ");
@@ -8333,16 +8633,50 @@ __init int intel_pmu_init(void) · 4 unmodified lines
8333	case INTEL_WILDCATLAKE_L:	8633	case INTEL_WILDCATLAKE_L:
8334	pr_cont("Pantherlake Hybrid events, ");	8634	pr_cont("Pantherlake Hybrid events, ");
8335	name = "pantherlake_hybrid";	8635	name = "pantherlake_hybrid";
		8636
		8637	intel_pmu_init_hybrid(hybrid_big_small);
		8638
		8639	/* Initialize big core specific PerfMon capabilities.*/
		8640	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
		8641	intel_pmu_init_lnc(&pmu->pmu);
		8642	/* Initialize Atom core specific PerfMon capabilities.*/
		8643	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
		8644	intel_pmu_init_dkt_hybrid(&pmu->pmu);
		8645
8336	goto lnl_common;	8646	goto lnl_common;
8337		8647
8338	case INTEL_LUNARLAKE_M:
8339	case INTEL_ARROWLAKE:	8648	case INTEL_ARROWLAKE:
		8649	pr_cont("Arrowlake Hybrid events, ");
		8650	name = "arrowlake_hybrid";
		8651
		8652	intel_pmu_init_hybrid(hybrid_big_small);
		8653
		8654	/* Initialize big core specific PerfMon capabilities.*/
		8655	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
		8656	intel_pmu_init_lnc(&pmu->pmu);
		8657	memcpy(hybrid_var(&pmu->pmu, hw_cache_extra_regs),
		8658	arl_lnc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
		8659	/* Initialize Atom core specific PerfMon capabilities.*/
		8660	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
		8661	intel_pmu_init_skt(&pmu->pmu);
		8662
		8663	goto lnl_common;
		8664
		8665	case INTEL_LUNARLAKE_M:
8340	pr_cont("Lunarlake Hybrid events, ");	8666	pr_cont("Lunarlake Hybrid events, ");
8341	name = "lunarlake_hybrid";	8667	name = "lunarlake_hybrid";
8342		8668
8343	lnl_common:
8344	intel_pmu_init_hybrid(hybrid_big_small);	8669	intel_pmu_init_hybrid(hybrid_big_small);
8345		8670
		8671	/* Initialize big core specific PerfMon capabilities.*/
		8672	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
		8673	intel_pmu_init_lnc(&pmu->pmu);
		8674	/* Initialize Atom core specific PerfMon capabilities.*/
		8675	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
		8676	intel_pmu_init_skt(&pmu->pmu);
		8677
		8678	lnl_common:
		8679
8346	x86_pmu.pebs_latency_data = lnl_latency_data;	8680	x86_pmu.pebs_latency_data = lnl_latency_data;
8347	x86_pmu.get_event_constraints = mtl_get_event_constraints;	8681	x86_pmu.get_event_constraints = mtl_get_event_constraints;
8348	x86_pmu.hw_config = adl_hw_config;	8682	x86_pmu.hw_config = adl_hw_config;
@@ -8353,14 +8687,6 @@ __init int intel_pmu_init(void) · 4 unmodified lines
8353	extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?	8687	extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8354	mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;	8688	mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
8355		8689
8356	/* Initialize big core specific PerfMon capabilities.*/
8357	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8358	intel_pmu_init_lnc(&pmu->pmu);
8359
8360	/* Initialize Atom core specific PerfMon capabilities.*/
8361	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
8362	intel_pmu_init_skt(&pmu->pmu);
8363
8364	intel_pmu_pebs_data_source_lnl();	8690	intel_pmu_pebs_data_source_lnl();
8365	break;	8691	break;
8366		8692
@@ -8380,6 +8706,8 @@ __init int intel_pmu_init(void) · 13 unmodified lines
8380	/* Initialize big core specific PerfMon capabilities. */	8706	/* Initialize big core specific PerfMon capabilities. */
8381	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];	8707	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8382	intel_pmu_init_lnc(&pmu->pmu);	8708	intel_pmu_init_lnc(&pmu->pmu);
		8709	memcpy(hybrid_var(&pmu->pmu, hw_cache_extra_regs),
		8710	arl_lnc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8383		8711
8384	/* Initialize Atom core specific PerfMon capabilities. */	8712	/* Initialize Atom core specific PerfMon capabilities. */
8385	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];	8713	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
@@ -8387,8 +8715,7 @@ __init int intel_pmu_init(void) · 1 unmodified line
8387		8715
8388	/* Initialize Lower Power Atom specific PerfMon capabilities. */	8716	/* Initialize Lower Power Atom specific PerfMon capabilities. */
8389	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_TINY_IDX];	8717	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_TINY_IDX];
8390	intel_pmu_init_grt(&pmu->pmu);	8718	intel_pmu_init_cmt(&pmu->pmu);
8391	pmu->extra_regs = intel_cmt_extra_regs;
8392		8719
8393	intel_pmu_pebs_data_source_arl_h();	8720	intel_pmu_pebs_data_source_arl_h();
8394	pr_cont("ArrowLake-H Hybrid events, ");	8721	pr_cont("ArrowLake-H Hybrid events, ");
@@ -8413,7 +8740,7 @@ __init int intel_pmu_init(void) · 18 unmodified lines
8413		8740
8414	/* Initialize big core specific PerfMon capabilities.*/	8741	/* Initialize big core specific PerfMon capabilities.*/
8415	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];	8742	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8416	intel_pmu_init_pnc(&pmu->pmu);	8743	intel_pmu_init_cyc(&pmu->pmu);
8417		8744
8418	/* Initialize Atom core specific PerfMon capabilities.*/	8745	/* Initialize Atom core specific PerfMon capabilities.*/
8419	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];	8746	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];

arch/x86/events/intel/ds.c+17−6

 struct event_constraint intel_grt_pebs_event_constraints[] = {
 	/* Allow all events as PEBS with no flags */
 	INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0x3),
-	INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xf),
+	INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0x3f),
 	EVENT_CONSTRAINT_END
 };
-struct event_constraint intel_arw_pebs_event_constraints[] = {
+struct event_constraint intel_cmt_pebs_event_constraints[] = {
+	/* Allow all events as PEBS with no flags */
+	INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0x3),
+	INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xff),
+	EVENT_CONSTRAINT_END
+};
+struct event_constraint intel_dkt_pebs_event_constraints[] = {
 	/* Allow all events as PEBS with no flags */
 	INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0xff),
 	INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xff),
-	INTEL_FLAGS_UEVENT_CONSTRAINT(0x01d4, 0x1),
-	INTEL_FLAGS_UEVENT_CONSTRAINT(0x02d4, 0x2),
-	INTEL_FLAGS_UEVENT_CONSTRAINT(0x04d4, 0x4),
-	INTEL_FLAGS_UEVENT_CONSTRAINT(0x08d4, 0x8),
 	EVENT_CONSTRAINT_END
 };
 	INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL),	/* INST_RETIRED.PREC_DIST */
 	INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),
+	INTEL_FLAGS_UEVENT_CONSTRAINT(0x012a, 0x1),		/* OCR.* events */
+	INTEL_FLAGS_UEVENT_CONSTRAINT(0x012b, 0x1),		/* OCR.* events */
+	INTEL_FLAGS_UEVENT_CONSTRAINT(0x04a4, 0x1),		/* TOPDOWN.BAD_SPEC_SLOTS */
+	INTEL_FLAGS_UEVENT_CONSTRAINT(0x08a4, 0x1),		/* TOPDOWN.BR_MISPREDICT_SLOTS */
+	INTEL_FLAGS_UEVENT_CONSTRAINT(0x10a4, 0x8),		/* TOPDOWN.MEMORY_BOUND_SLOTS */
 	INTEL_HYBRID_LDLAT_CONSTRAINT(0x1cd, 0x3fc),
 	INTEL_HYBRID_STLAT_CONSTRAINT(0x2cd, 0x3),
 	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf),	/* MEM_INST_RETIRED.STLB_MISS_LOADS */
 	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf),	/* MEM_INST_RETIRED.SPLIT_STORES */
 	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf),	/* MEM_INST_RETIRED.ALL_LOADS */
 	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf),	/* MEM_INST_RETIRED.ALL_STORES */
+	INTEL_FLAGS_UEVENT_CONSTRAINT(0x87d0, 0x3ff),		/* MEM_INST_RETIRED.ANY */
 	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf),

arch/x86/events/intel/uncore.c+31−1

@@ -83,6 +83,25 @@ int uncore_device_to_die(struct pci_dev *dev) · 82 unmodified lines
83	return -1;	83	return -1;
84	}	84	}
85		85
		86	/*
		87	* Using cpus_read_lock() to ensure cpu is not going down between
		88	* looking at cpu_online_mask.
		89	*
		90	* The lock must be held by the caller.
		91	*/
		92	int uncore_die_to_cpu(int die)
		93	{
		94	int res = -1, cpu;
		95
		96	for_each_online_cpu(cpu) {
		97	if (topology_logical_die_id(cpu) == die) {
		98	res = cpu;
		99	break;
		100	}
		101	}
		102	return res;
		103	}
		104
86	static void uncore_free_pcibus_map(void)	105	static void uncore_free_pcibus_map(void)
87	{	106	{
88	struct pci2phy_map map, tmp;	107	struct pci2phy_map map, tmp;
@@ -1697,7 +1716,7 @@ err: · 1608 unmodified lines
1697	return ret;	1716	return ret;
1698	}	1717	}
1699		1718
1700	static int uncore_mmio_global_init(u64 ctl)	1719	static int uncore_mmio_global_init(int die, u64 ctl)
1701	{	1720	{
1702	void __iomem *io_addr;	1721	void __iomem *io_addr;
1703		1722
@@ -1712,6 +1731,16 @@ static int uncore_mmio_global_init(u64 ctl) · 8 unmodified lines
1712	return 0;	1731	return 0;
1713	}	1732	}
1714		1733
		1734	static int uncore_msr_global_init(int die, u64 msr)
		1735	{
		1736	int cpu = uncore_die_to_cpu(die);
		1737
		1738	if (cpu == -1)
		1739	return -ENODEV;
		1740
		1741	return wrmsrq_on_cpu(cpu, msr, 0);
		1742	}
		1743
1715	static const struct uncore_plat_init nhm_uncore_init __initconst = {	1744	static const struct uncore_plat_init nhm_uncore_init __initconst = {
1716	.cpu_init = nhm_uncore_cpu_init,	1745	.cpu_init = nhm_uncore_cpu_init,
1717	};	1746	};
@@ -1852,6 +1881,7 @@ static const struct uncore_plat_init gnr_uncore_init __initconst = { · 134 unmodified lines
1852	.domain[0].base_is_pci = true,	1881	.domain[0].base_is_pci = true,
1853	.domain[0].discovery_base = UNCORE_DISCOVERY_TABLE_DEVICE,	1882	.domain[0].discovery_base = UNCORE_DISCOVERY_TABLE_DEVICE,
1854	.domain[0].units_ignore = gnr_uncore_units_ignore,	1883	.domain[0].units_ignore = gnr_uncore_units_ignore,
		1884	.domain[0].global_init = uncore_msr_global_init,
1855	};	1885	};
1856		1886
1857	static const struct uncore_plat_init dmr_uncore_init __initconst = {	1887	static const struct uncore_plat_init dmr_uncore_init __initconst = {

arch/x86/events/intel/uncore.h+2−1

 	/* MSR address or PCI device used as the discovery base */
 	u32	discovery_base;
 	bool	base_is_pci;
-	int	(*global_init)(u64 ctl);
+	int	(*global_init)(int die, u64 ctl);
 	/* The units in the discovery table should be ignored. */
 	int	*units_ignore;
 int uncore_pcibus_to_dieid(struct pci_bus *bus);
 int uncore_die_to_segment(int die);
 int uncore_device_to_die(struct pci_dev *dev);
+int uncore_die_to_cpu(int die);
 ssize_t uncore_event_show(struct device *dev,
 			  struct device_attribute *attr, char *buf);

arch/x86/events/intel/uncore_discovery.c+31−15

 	if (!io_addr)
 		return -ENOMEM;
-	if (domain->global_init && domain->global_init(global.ctl)) {
+	if (domain->global_init && domain->global_init(die, global.ctl)) {
 		ret = -ENODEV;
 		goto out;
 	}
 	if (!die_mask)
 		return false;
-	cpus_read_lock();
 	for_each_online_cpu(cpu) {
 		die = topology_logical_die_id(cpu);
 		if (__test_and_set_bit(die, die_mask))
 		__parse_discovery_table(domain, base, die, &parsed);
 	}
-	cpus_read_unlock();
 	kfree(die_mask);
 	return parsed;
 }
 	for (i = 0; i < UNCORE_DISCOVERY_DOMAINS; i++) {
 		domain = &init->domain[i];
 		if (domain->discovery_base) {
+			cpus_read_lock();
 			if (!domain->base_is_pci)
 				ret |= uncore_discovery_msr(domain);
 			else
 				ret |= uncore_discovery_pci(domain);
+			cpus_read_unlock();
 		}
 	}
 	struct intel_uncore_discovery_unit *unit;
 	unit = intel_uncore_find_discovery_unit(box->pmu->type->boxes,
-						-1, box->pmu->pmu_idx);
+						box->dieid, box->pmu->pmu_idx);
-	if (WARN_ON_ONCE(!unit))
+	if (!unit)
 		return 0;
 	return unit->addr;
 void intel_generic_uncore_msr_init_box(struct intel_uncore_box *box)
 {
-	wrmsrq(intel_generic_uncore_box_ctl(box), GENERIC_PMON_BOX_CTL_INT);
+	u64 box_ctl = intel_generic_uncore_box_ctl(box);
+	if (!box_ctl)
+		return;
+	wrmsrq(box_ctl, GENERIC_PMON_BOX_CTL_INT);
 }
 void intel_generic_uncore_msr_disable_box(struct intel_uncore_box *box)
 {
-	wrmsrq(intel_generic_uncore_box_ctl(box), GENERIC_PMON_BOX_CTL_FRZ);
+	u64 box_ctl = intel_generic_uncore_box_ctl(box);
+	if (box_ctl)
+		wrmsrq(box_ctl, GENERIC_PMON_BOX_CTL_FRZ);
 }
 void intel_generic_uncore_msr_enable_box(struct intel_uncore_box *box)
 {
-	wrmsrq(intel_generic_uncore_box_ctl(box), 0);
+	u64 box_ctl = intel_generic_uncore_box_ctl(box);
+	if (box_ctl)
+		wrmsrq(box_ctl, 0);
 }
 static void intel_generic_uncore_msr_enable_event(struct intel_uncore_box *box,
 	if (box->pci_dev) {
 		box_ctl = UNCORE_DISCOVERY_PCI_BOX_CTRL(box_ctl);
 		hwc->config_base = box_ctl + uncore_pci_event_ctl(box, hwc->idx);
 		hwc->event_base  = box_ctl + uncore_pci_perf_ctr(box, hwc->idx);
 		return true;
 void intel_generic_uncore_pci_init_box(struct intel_uncore_box *box)
 {
-	struct pci_dev *pdev = box->pci_dev;
 	int box_ctl = intel_pci_uncore_box_ctl(box);
+	if (!box_ctl)
+		return;
 	__set_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags);
-	pci_write_config_dword(pdev, box_ctl, GENERIC_PMON_BOX_CTL_INT);
+	pci_write_config_dword(box->pci_dev, box_ctl, GENERIC_PMON_BOX_CTL_INT);
 }
 void intel_generic_uncore_pci_disable_box(struct intel_uncore_box *box)
 {
-	struct pci_dev *pdev = box->pci_dev;
 	int box_ctl = intel_pci_uncore_box_ctl(box);
-	pci_write_config_dword(pdev, box_ctl, GENERIC_PMON_BOX_CTL_FRZ);
+	if (box_ctl)
+		pci_write_config_dword(box->pci_dev, box_ctl,
+				       GENERIC_PMON_BOX_CTL_FRZ);
 }
 void intel_generic_uncore_pci_enable_box(struct intel_uncore_box *box)
 {
-	struct pci_dev *pdev = box->pci_dev;
 	int box_ctl = intel_pci_uncore_box_ctl(box);
-	pci_write_config_dword(pdev, box_ctl, 0);
+	if (box_ctl)
+		pci_write_config_dword(box->pci_dev, box_ctl, 0);
 }
 static void intel_generic_uncore_pci_enable_event(struct intel_uncore_box *box,

arch/x86/events/intel/uncore_snb.c+0−7

 	skl_uncore_msr_ops.init_box = rkl_uncore_msr_init_box;
 }
-static void adl_uncore_msr_init_box(struct intel_uncore_box *box)
-{
-	if (box->pmu->pmu_idx == 0)
-		wrmsrq(ADL_UNC_PERF_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN);
-}
 static void adl_uncore_msr_enable_box(struct intel_uncore_box *box)
 {
 	wrmsrq(ADL_UNC_PERF_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN);
 }
 static struct intel_uncore_ops adl_uncore_msr_ops = {
-	.init_box	= adl_uncore_msr_init_box,
 	.enable_box	= adl_uncore_msr_enable_box,
 	.disable_box	= adl_uncore_msr_disable_box,
 	.exit_box	= adl_uncore_msr_exit_box,

arch/x86/events/intel/uncore_snbep.c+12−24

 	return 0;
 }
-static int die_to_cpu(int die)
-{
-	int res = 0, cpu, current_die;
-	/*
-	 * Using cpus_read_lock() to ensure cpu is not going down between
-	 * looking at cpu_online_mask.
-	 */
-	cpus_read_lock();
-	for_each_online_cpu(cpu) {
-		current_die = topology_logical_die_id(cpu);
-		if (current_die == die) {
-			res = cpu;
-			break;
-		}
-	}
-	cpus_read_unlock();
-	return res;
-}
 enum {
 	IIO_TOPOLOGY_TYPE,
 	UPI_TOPOLOGY_TYPE,
 static int skx_pmu_get_topology(struct intel_uncore_type *type,
 				 int (*topology_cb)(struct intel_uncore_type*, int, int, u64))
 {
-	int die, ret = -EPERM;
+	int die, ret = -ENODEV;
 	u64 cpu_bus_msr;
+	int cpu;
+	cpus_read_lock();
 	for (die = 0; die < uncore_max_dies(); die++) {
-		ret = skx_msr_cpu_bus_read(die_to_cpu(die), &cpu_bus_msr);
+		cpu = uncore_die_to_cpu(die);
+		if (cpu == -1)
+			continue;
+		ret = skx_msr_cpu_bus_read(cpu, &cpu_bus_msr);
 		if (ret)
 			break;
 		if (ret)
 			break;
 	}
+	cpus_read_unlock();
 	return ret;
 }
 static int skx_upi_topology_cb(struct intel_uncore_type *type, int segment,
 				int die, u64 cpu_bus_msr)
 {
-	int idx, ret;
+	int idx, ret = 0;
 	struct intel_uncore_topology *upi;
 	unsigned int devfn;
 	struct pci_dev *dev = NULL;
 		dev = pci_get_domain_bus_and_slot(segment, bus, devfn);
 		if (dev) {
 			ret = upi_fill_topology(dev, upi, idx);
+			pci_dev_put(dev);
 			if (ret)
 				break;
 		}
 	}
-	pci_dev_put(dev);
 	return ret;
 }
 							  devfn);
 			if (dev) {
 				ret = upi_fill_topology(dev, upi, idx);
+				pci_dev_put(dev);
 				if (ret)
 					goto err;
 			}
 	}
 err:
 	pci_dev_put(ubox);
-	pci_dev_put(dev);
 	return ret;
 }

arch/x86/events/perf_event.h+4−4

 	u64			fixed_ctrl_val;
 	u64			active_fixed_ctrl_val;
-	/* Intel ACR configuration */
+	/* Intel ACR/arch-PEBS configuration */
 	u64			acr_cfg_b[X86_PMC_IDX_MAX];
-	u64			acr_cfg_c[X86_PMC_IDX_MAX];
-	/* Cached CFG_C values */
 	u64			cfg_c_val[X86_PMC_IDX_MAX];
 	/*
 extern struct event_constraint intel_grt_pebs_event_constraints[];
-extern struct event_constraint intel_arw_pebs_event_constraints[];
+extern struct event_constraint intel_cmt_pebs_event_constraints[];
+extern struct event_constraint intel_dkt_pebs_event_constraints[];
 extern struct event_constraint intel_nehalem_pebs_event_constraints[];

kernel/events/core.c+29−0

@@ -58,6 +58,7 @@ · 57 unmodified lines
58	#include <linux/percpu-rwsem.h>	58	#include <linux/percpu-rwsem.h>
59	#include <linux/unwind_deferred.h>	59	#include <linux/unwind_deferred.h>
60	#include <linux/kvm_types.h>	60	#include <linux/kvm_types.h>
		61	#include <linux/seq_file.h>
61		62
62	#include "internal.h"	63	#include "internal.h"
63		64
@@ -7546,6 +7547,33 @@ static int perf_fasync(int fd, struct file *filp, int on) · 7482 unmodified lines
7546	return 0;	7547	return 0;
7547	}	7548	}
7548		7549
		7550	static void perf_show_fdinfo(struct seq_file m, struct file f)
		7551	{
		7552	struct perf_event *event = f->private_data;
		7553	struct perf_event_context *ctx;
		7554	struct mutex *child_mutex;
		7555
		7556	ctx = perf_event_ctx_lock(event);
		7557	child_mutex = event->parent ? &event->parent->child_mutex : &event->child_mutex;
		7558	mutex_lock(child_mutex);
		7559
		7560	seq_printf(m, "perf_event_attr.type:\t%u\n", event->orig_type);
		7561	if (event->pmu)
		7562	seq_printf(m, "pmu_type:\t%u\n", event->pmu->type);
		7563	seq_printf(m, "perf_event_attr.config:\t0x%llx\n", (unsigned long long)event->attr.config);
		7564	seq_printf(m, "perf_event_attr.config1:\t0x%llx\n",
		7565	(unsigned long long)event->attr.config1);
		7566	seq_printf(m, "perf_event_attr.config2:\t0x%llx\n",
		7567	(unsigned long long)event->attr.config2);
		7568	seq_printf(m, "perf_event_attr.config3:\t0x%llx\n",
		7569	(unsigned long long)event->attr.config3);
		7570	seq_printf(m, "perf_event_attr.config4:\t0x%llx\n",
		7571	(unsigned long long)event->attr.config4);
		7572
		7573	mutex_unlock(child_mutex);
		7574	perf_event_ctx_unlock(event, ctx);
		7575	}
		7576
7549	static const struct file_operations perf_fops = {	7577	static const struct file_operations perf_fops = {
7550	.release = perf_release,	7578	.release = perf_release,
7551	.read = perf_read,	7579	.read = perf_read,
@@ -7554,6 +7582,7 @@ static const struct file_operations perf_fops = { · 2 unmodified lines
7554	.compat_ioctl = perf_compat_ioctl,	7582	.compat_ioctl = perf_compat_ioctl,
7555	.mmap = perf_mmap,	7583	.mmap = perf_mmap,
7556	.fasync = perf_fasync,	7584	.fasync = perf_fasync,
		7585	.show_fdinfo = perf_show_fdinfo,
7557	};	7586	};
7558		7587
7559	/*	7588	/*

Merge tag 'perf-core-2026-06-14' of gitolite.kernel.org:pub/scm/linux/kernel/git/tip/tip

Keyboard shortcuts

General

Issues and pull requests

Issues, pull requests and Inbox

Repository code