skl-tplg-interface.h describes firmware format details for Skylake topology files. It is part of the ABI and should reside in the uapi directory. While moving the file, also replace the license boilerplate with the SPDX License Identifier. No functional change.
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| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | ||
| 2 | /* | ||
| 3 | * skl-tplg-interface.h - Intel DSP FW private data interface | ||
| 4 | * | ||
| 5 | * Copyright (C) 2015 Intel Corp | ||
| 6 | * Author: Jeeja KP <jeeja.kp@intel.com> | ||
| 7 | * Nilofer, Samreen <samreen.nilofer@intel.com> | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __HDA_TPLG_INTERFACE_H__ | ||
| 11 | #define __HDA_TPLG_INTERFACE_H__ | ||
| 12 | |||
| 13 | /* | ||
| 14 | * Default types range from 0~12. type can range from 0 to 0xff | ||
| 15 | * SST types start at higher to avoid any overlapping in future | ||
| 16 | */ | ||
| 17 | #define SKL_CONTROL_TYPE_BYTE_TLV 0x100 | ||
| 18 | #define SKL_CONTROL_TYPE_MIC_SELECT 0x102 | ||
| 19 | |||
| 20 | #define HDA_SST_CFG_MAX 900 /* size of copier cfg*/ | ||
| 21 | #define MAX_IN_QUEUE 8 | ||
| 22 | #define MAX_OUT_QUEUE 8 | ||
| 23 | |||
| 24 | #define SKL_UUID_STR_SZ 40 | ||
| 25 | /* Event types goes here */ | ||
| 26 | /* Reserve event type 0 for no event handlers */ | ||
| 27 | enum skl_event_types { | ||
| 28 | SKL_EVENT_NONE = 0, | ||
| 29 | SKL_MIXER_EVENT, | ||
| 30 | SKL_MUX_EVENT, | ||
| 31 | SKL_VMIXER_EVENT, | ||
| 32 | SKL_PGA_EVENT | ||
| 33 | }; | ||
| 34 | |||
| 35 | /** | ||
| 36 | * enum skl_ch_cfg - channel configuration | ||
| 37 | * | ||
| 38 | * @SKL_CH_CFG_MONO: One channel only | ||
| 39 | * @SKL_CH_CFG_STEREO: L & R | ||
| 40 | * @SKL_CH_CFG_2_1: L, R & LFE | ||
| 41 | * @SKL_CH_CFG_3_0: L, C & R | ||
| 42 | * @SKL_CH_CFG_3_1: L, C, R & LFE | ||
| 43 | * @SKL_CH_CFG_QUATRO: L, R, Ls & Rs | ||
| 44 | * @SKL_CH_CFG_4_0: L, C, R & Cs | ||
| 45 | * @SKL_CH_CFG_5_0: L, C, R, Ls & Rs | ||
| 46 | * @SKL_CH_CFG_5_1: L, C, R, Ls, Rs & LFE | ||
| 47 | * @SKL_CH_CFG_DUAL_MONO: One channel replicated in two | ||
| 48 | * @SKL_CH_CFG_I2S_DUAL_STEREO_0: Stereo(L,R) in 4 slots, 1st stream:[ L, R, -, - ] | ||
| 49 | * @SKL_CH_CFG_I2S_DUAL_STEREO_1: Stereo(L,R) in 4 slots, 2nd stream:[ -, -, L, R ] | ||
| 50 | * @SKL_CH_CFG_INVALID: Invalid | ||
| 51 | */ | ||
| 52 | enum skl_ch_cfg { | ||
| 53 | SKL_CH_CFG_MONO = 0, | ||
| 54 | SKL_CH_CFG_STEREO = 1, | ||
| 55 | SKL_CH_CFG_2_1 = 2, | ||
| 56 | SKL_CH_CFG_3_0 = 3, | ||
| 57 | SKL_CH_CFG_3_1 = 4, | ||
| 58 | SKL_CH_CFG_QUATRO = 5, | ||
| 59 | SKL_CH_CFG_4_0 = 6, | ||
| 60 | SKL_CH_CFG_5_0 = 7, | ||
| 61 | SKL_CH_CFG_5_1 = 8, | ||
| 62 | SKL_CH_CFG_DUAL_MONO = 9, | ||
| 63 | SKL_CH_CFG_I2S_DUAL_STEREO_0 = 10, | ||
| 64 | SKL_CH_CFG_I2S_DUAL_STEREO_1 = 11, | ||
| 65 | SKL_CH_CFG_4_CHANNEL = 12, | ||
| 66 | SKL_CH_CFG_INVALID | ||
| 67 | }; | ||
| 68 | |||
| 69 | enum skl_module_type { | ||
| 70 | SKL_MODULE_TYPE_MIXER = 0, | ||
| 71 | SKL_MODULE_TYPE_COPIER, | ||
| 72 | SKL_MODULE_TYPE_UPDWMIX, | ||
| 73 | SKL_MODULE_TYPE_SRCINT, | ||
| 74 | SKL_MODULE_TYPE_ALGO, | ||
| 75 | SKL_MODULE_TYPE_BASE_OUTFMT, | ||
| 76 | SKL_MODULE_TYPE_KPB, | ||
| 77 | SKL_MODULE_TYPE_MIC_SELECT, | ||
| 78 | }; | ||
| 79 | |||
| 80 | enum skl_core_affinity { | ||
| 81 | SKL_AFFINITY_CORE_0 = 0, | ||
| 82 | SKL_AFFINITY_CORE_1, | ||
| 83 | SKL_AFFINITY_CORE_MAX | ||
| 84 | }; | ||
| 85 | |||
| 86 | enum skl_pipe_conn_type { | ||
| 87 | SKL_PIPE_CONN_TYPE_NONE = 0, | ||
| 88 | SKL_PIPE_CONN_TYPE_FE, | ||
| 89 | SKL_PIPE_CONN_TYPE_BE | ||
| 90 | }; | ||
| 91 | |||
| 92 | enum skl_hw_conn_type { | ||
| 93 | SKL_CONN_NONE = 0, | ||
| 94 | SKL_CONN_SOURCE = 1, | ||
| 95 | SKL_CONN_SINK = 2 | ||
| 96 | }; | ||
| 97 | |||
| 98 | enum skl_dev_type { | ||
| 99 | SKL_DEVICE_BT = 0x0, | ||
| 100 | SKL_DEVICE_DMIC = 0x1, | ||
| 101 | SKL_DEVICE_I2S = 0x2, | ||
| 102 | SKL_DEVICE_SLIMBUS = 0x3, | ||
| 103 | SKL_DEVICE_HDALINK = 0x4, | ||
| 104 | SKL_DEVICE_HDAHOST = 0x5, | ||
| 105 | SKL_DEVICE_NONE | ||
| 106 | }; | ||
| 107 | |||
| 108 | /** | ||
| 109 | * enum skl_interleaving - interleaving style | ||
| 110 | * | ||
| 111 | * @SKL_INTERLEAVING_PER_CHANNEL: [s1_ch1...s1_chN,...,sM_ch1...sM_chN] | ||
| 112 | * @SKL_INTERLEAVING_PER_SAMPLE: [s1_ch1...sM_ch1,...,s1_chN...sM_chN] | ||
| 113 | */ | ||
| 114 | enum skl_interleaving { | ||
| 115 | SKL_INTERLEAVING_PER_CHANNEL = 0, | ||
| 116 | SKL_INTERLEAVING_PER_SAMPLE = 1, | ||
| 117 | }; | ||
| 118 | |||
| 119 | enum skl_sample_type { | ||
| 120 | SKL_SAMPLE_TYPE_INT_MSB = 0, | ||
| 121 | SKL_SAMPLE_TYPE_INT_LSB = 1, | ||
| 122 | SKL_SAMPLE_TYPE_INT_SIGNED = 2, | ||
| 123 | SKL_SAMPLE_TYPE_INT_UNSIGNED = 3, | ||
| 124 | SKL_SAMPLE_TYPE_FLOAT = 4 | ||
| 125 | }; | ||
| 126 | |||
| 127 | enum module_pin_type { | ||
| 128 | /* All pins of the module takes same PCM inputs or outputs | ||
| 129 | * e.g. mixout | ||
| 130 | */ | ||
| 131 | SKL_PIN_TYPE_HOMOGENEOUS, | ||
| 132 | /* All pins of the module takes different PCM inputs or outputs | ||
| 133 | * e.g mux | ||
| 134 | */ | ||
| 135 | SKL_PIN_TYPE_HETEROGENEOUS, | ||
| 136 | }; | ||
| 137 | |||
| 138 | enum skl_module_param_type { | ||
| 139 | SKL_PARAM_DEFAULT = 0, | ||
| 140 | SKL_PARAM_INIT, | ||
| 141 | SKL_PARAM_SET, | ||
| 142 | SKL_PARAM_BIND | ||
| 143 | }; | ||
| 144 | |||
| 145 | struct skl_dfw_algo_data { | ||
| 146 | u32 set_params:2; | ||
| 147 | u32 rsvd:30; | ||
| 148 | u32 param_id; | ||
| 149 | u32 max; | ||
| 150 | char params[0]; | ||
| 151 | } __packed; | ||
| 152 | |||
| 153 | enum skl_tkn_dir { | ||
| 154 | SKL_DIR_IN, | ||
| 155 | SKL_DIR_OUT | ||
| 156 | }; | ||
| 157 | |||
| 158 | enum skl_tuple_type { | ||
| 159 | SKL_TYPE_TUPLE, | ||
| 160 | SKL_TYPE_DATA | ||
| 161 | }; | ||
| 162 | |||
| 163 | /* v4 configuration data */ | ||
| 164 | |||
| 165 | struct skl_dfw_v4_module_pin { | ||
| 166 | u16 module_id; | ||
| 167 | u16 instance_id; | ||
| 168 | } __packed; | ||
| 169 | |||
| 170 | struct skl_dfw_v4_module_fmt { | ||
| 171 | u32 channels; | ||
| 172 | u32 freq; | ||
| 173 | u32 bit_depth; | ||
| 174 | u32 valid_bit_depth; | ||
| 175 | u32 ch_cfg; | ||
| 176 | u32 interleaving_style; | ||
| 177 | u32 sample_type; | ||
| 178 | u32 ch_map; | ||
| 179 | } __packed; | ||
| 180 | |||
| 181 | struct skl_dfw_v4_module_caps { | ||
| 182 | u32 set_params:2; | ||
| 183 | u32 rsvd:30; | ||
| 184 | u32 param_id; | ||
| 185 | u32 caps_size; | ||
| 186 | u32 caps[HDA_SST_CFG_MAX]; | ||
| 187 | } __packed; | ||
| 188 | |||
| 189 | struct skl_dfw_v4_pipe { | ||
| 190 | u8 pipe_id; | ||
| 191 | u8 pipe_priority; | ||
| 192 | u16 conn_type:4; | ||
| 193 | u16 rsvd:4; | ||
| 194 | u16 memory_pages:8; | ||
| 195 | } __packed; | ||
| 196 | |||
| 197 | struct skl_dfw_v4_module { | ||
| 198 | char uuid[SKL_UUID_STR_SZ]; | ||
| 199 | |||
| 200 | u16 module_id; | ||
| 201 | u16 instance_id; | ||
| 202 | u32 max_mcps; | ||
| 203 | u32 mem_pages; | ||
| 204 | u32 obs; | ||
| 205 | u32 ibs; | ||
| 206 | u32 vbus_id; | ||
| 207 | |||
| 208 | u32 max_in_queue:8; | ||
| 209 | u32 max_out_queue:8; | ||
| 210 | u32 time_slot:8; | ||
| 211 | u32 core_id:4; | ||
| 212 | u32 rsvd1:4; | ||
| 213 | |||
| 214 | u32 module_type:8; | ||
| 215 | u32 conn_type:4; | ||
| 216 | u32 dev_type:4; | ||
| 217 | u32 hw_conn_type:4; | ||
| 218 | u32 rsvd2:12; | ||
| 219 | |||
| 220 | u32 params_fixup:8; | ||
| 221 | u32 converter:8; | ||
| 222 | u32 input_pin_type:1; | ||
| 223 | u32 output_pin_type:1; | ||
| 224 | u32 is_dynamic_in_pin:1; | ||
| 225 | u32 is_dynamic_out_pin:1; | ||
| 226 | u32 is_loadable:1; | ||
| 227 | u32 rsvd3:11; | ||
| 228 | |||
| 229 | struct skl_dfw_v4_pipe pipe; | ||
| 230 | struct skl_dfw_v4_module_fmt in_fmt[MAX_IN_QUEUE]; | ||
| 231 | struct skl_dfw_v4_module_fmt out_fmt[MAX_OUT_QUEUE]; | ||
| 232 | struct skl_dfw_v4_module_pin in_pin[MAX_IN_QUEUE]; | ||
| 233 | struct skl_dfw_v4_module_pin out_pin[MAX_OUT_QUEUE]; | ||
| 234 | struct skl_dfw_v4_module_caps caps; | ||
| 235 | } __packed; | ||
| 236 | |||
| 237 | #endif | ||