intel_rapl: support two power limits for every RAPL domain

RAPL MSR interface supports 2 power limits for package domain, and 1 power limit for other domains, while RAPL MMIO interface supports 2 power limits for both package and dram domains. And when 2 power limits are supported, the FW_LOCK bit is in bit 63 of the register, instead of bit 31. Remove the assumption that only pakcage domain supports 2 power limits. And allow the RAPL interface driver to specify the number of power limits supported, for every single RAPL domain it owns..

Zhang Rui committed 7 years ago

Commit 0c2dded1 parent d978e753 files · +28 −47Browse files

Unified · Split

3 files

drivers/powercap/intel_rapl_common.c +25 −47
drivers/powercap/intel_rapl_msr.c +1 −0
include/linux/intel_rapl.h +2 −0

drivers/powercap/intel_rapl_common.c+25−47

@@ -38,8 +38,8 @@ · 37 unmodified lines
38	38	#define POWER_LIMIT2_MASK (0x7FFFULL<<32)
39	39	#define POWER_LIMIT2_ENABLE BIT_ULL(47)
40	40	#define POWER_LIMIT2_CLAMP BIT_ULL(48)
41		−#define POWER_PACKAGE_LOCK BIT_ULL(63)
42		−#define POWER_PP_LOCK BIT(31)
	41	+#define POWER_HIGH_LOCK BIT_ULL(63)
	42	+#define POWER_LOW_LOCK BIT(31)
43	43
44	44	#define TIME_WINDOW1_MASK (0x7FULL<<17)
45	45	#define TIME_WINDOW2_MASK (0x7FULL<<49)
@@ -513,60 +513,38 @@ static const struct powercap_zone_constraint_ops constraint_ops = { · 467 unmodified lines
513	513	/* called after domain detection and package level data are set */
514	514	static void rapl_init_domains(struct rapl_package *rp)
515	515	{
516		− int i;
	516	+ enum rapl_domain_type i;
	517	+ enum rapl_domain_reg_id j;
517	518	struct rapl_domain *rd = rp->domains;
518	519
519	520	for (i = 0; i < RAPL_DOMAIN_MAX; i++) {
520	521	unsigned int mask = rp->domain_map & (1 << i);
521	522
522		− rd->regs[RAPL_DOMAIN_REG_LIMIT] =
523		− rp->priv->regs[i][RAPL_DOMAIN_REG_LIMIT];
524		− rd->regs[RAPL_DOMAIN_REG_STATUS] =
525		− rp->priv->regs[i][RAPL_DOMAIN_REG_STATUS];
526		− rd->regs[RAPL_DOMAIN_REG_PERF] =
527		− rp->priv->regs[i][RAPL_DOMAIN_REG_PERF];
528		− rd->regs[RAPL_DOMAIN_REG_POLICY] =
529		− rp->priv->regs[i][RAPL_DOMAIN_REG_POLICY];
530		− rd->regs[RAPL_DOMAIN_REG_INFO] =
531		− rp->priv->regs[i][RAPL_DOMAIN_REG_INFO];
532		−
533		− switch (mask) {
534		− case BIT(RAPL_DOMAIN_PACKAGE):
535		− rd->name = rapl_domain_names[RAPL_DOMAIN_PACKAGE];
536		− rd->id = RAPL_DOMAIN_PACKAGE;
537		− rd->rpl[0].prim_id = PL1_ENABLE;
538		− rd->rpl[0].name = pl1_name;
	523	+ if (!mask)
	524	+ continue;
	525	+
	526	+ rd->rp = rp;
	527	+ rd->name = rapl_domain_names[i];
	528	+ rd->id = i;
	529	+ rd->rpl[0].prim_id = PL1_ENABLE;
	530	+ rd->rpl[0].name = pl1_name;
	531	+ /* some domain may support two power limits */
	532	+ if (rp->priv->limits[i] == 2) {
539	533	rd->rpl[1].prim_id = PL2_ENABLE;
540	534	rd->rpl[1].name = pl2_name;
541		− break;
542		− case BIT(RAPL_DOMAIN_PP0):
543		− rd->name = rapl_domain_names[RAPL_DOMAIN_PP0];
544		− rd->id = RAPL_DOMAIN_PP0;
545		− rd->rpl[0].prim_id = PL1_ENABLE;
546		− rd->rpl[0].name = pl1_name;
547		− break;
548		− case BIT(RAPL_DOMAIN_PP1):
549		− rd->name = rapl_domain_names[RAPL_DOMAIN_PP1];
550		− rd->id = RAPL_DOMAIN_PP1;
551		− rd->rpl[0].prim_id = PL1_ENABLE;
552		− rd->rpl[0].name = pl1_name;
553		− break;
554		− case BIT(RAPL_DOMAIN_DRAM):
555		− rd->name = rapl_domain_names[RAPL_DOMAIN_DRAM];
556		− rd->id = RAPL_DOMAIN_DRAM;
557		− rd->rpl[0].prim_id = PL1_ENABLE;
558		− rd->rpl[0].name = pl1_name;
	535	+ }
	536	+
	537	+ for (j = 0; j < RAPL_DOMAIN_REG_MAX; j++)
	538	+ rd->regs[j] = rp->priv->regs[i][j];
	539	+
	540	+ if (i == RAPL_DOMAIN_DRAM) {
559	541	rd->domain_energy_unit =
560	542	rapl_defaults->dram_domain_energy_unit;
561	543	if (rd->domain_energy_unit)
562	544	pr_info("DRAM domain energy unit %dpj\n",
563	545	rd->domain_energy_unit);
564		− break;
565		− }
566		− if (mask) {
567		− rd->rp = rp;
568		− rd++;
569	546	}
	547	+ rd++;
570	548	}
571	549	}
572	550
@@ -613,7 +591,7 @@ static struct rapl_primitive_info rpi[] = { · 40 unmodified lines
613	591	RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
614	592	PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, 32,
615	593	RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
616		− PRIMITIVE_INFO_INIT(FW_LOCK, POWER_PP_LOCK, 31,
	594	+ PRIMITIVE_INFO_INIT(FW_LOCK, POWER_LOW_LOCK, 31,
617	595	RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
618	596	PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15,
619	597	RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
@@ -675,9 +653,9 @@ static int rapl_read_data_raw(struct rapl_domain *rd, · 55 unmodified lines
675	653
676	654	cpu = rd->rp->lead_cpu;
677	655
678		− /* special-case package domain, which uses a different bit */
679		− if (prim == FW_LOCK && rd->id == RAPL_DOMAIN_PACKAGE) {
680		− rp->mask = POWER_PACKAGE_LOCK;
	656	+ /* domain with 2 limits has different bit */
	657	+ if (prim == FW_LOCK && rd->rp->priv->limits[rd->id] == 2) {
	658	+ rp->mask = POWER_HIGH_LOCK;
681	659	rp->shift = 63;
682	660	}
683	661	/* non-hardware data are collected by the polling thread */

drivers/powercap/intel_rapl_msr.c+1−0

@@ -41,6 +41,7 @@ static struct rapl_if_priv rapl_msr_priv = { · 40 unmodified lines
41	41	MSR_DRAM_POWER_LIMIT, MSR_DRAM_ENERGY_STATUS, MSR_DRAM_PERF_STATUS, 0, MSR_DRAM_POWER_INFO },
42	42	.regs[RAPL_DOMAIN_PLATFORM] = {
43	43	MSR_PLATFORM_POWER_LIMIT, MSR_PLATFORM_ENERGY_STATUS, 0, 0, 0},
	44	+ .limits[RAPL_DOMAIN_PACKAGE] = 2,
44	45	};
45	46
46	47	/* Handles CPU hotplug on multi-socket systems.

include/linux/intel_rapl.h+2−0

@@ -104,6 +104,7 @@ struct reg_action { · 103 unmodified lines
104	104	* @pcap_rapl_online: CPU hotplug state for each RAPL interface.
105	105	* @reg_unit: Register for getting energy/power/time unit.
106	106	* @regs: Register sets for different RAPL Domains.
	107	+ * @limits: Number of power limits supported by each domain.
107	108	* @read_raw: Callback for reading RAPL interface specific
108	109	* registers.
109	110	* @write_raw: Callback for writing RAPL interface specific
@@ -115,6 +116,7 @@ struct rapl_if_priv { · 5 unmodified lines
115	116	enum cpuhp_state pcap_rapl_online;
116	117	u64 reg_unit;
117	118	u64 regs[RAPL_DOMAIN_MAX][RAPL_DOMAIN_REG_MAX];
	119	+ int limits[RAPL_DOMAIN_MAX];
118	120	int (read_raw)(int cpu, struct reg_action ra);
119	121	int (write_raw)(int cpu, struct reg_action ra);
120	122	};

intel_rapl: support two power limits for every RAPL domain

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