MT7629 is an ARM platform SoC which has the same PCIe IP as MT7622. The HW default value of its PCI host controller Device ID is invalid, fix it to match the hardware implementation.
Unified · Split
| @@ -73,6 +73,7 @@ · 72 unmodified lines | |||
| 73 | #define PCIE_MSI_VECTOR 0x0c0 | 73 | #define PCIE_MSI_VECTOR 0x0c0 |
| 74 | 74 | ||
| 75 | #define PCIE_CONF_VEND_ID 0x100 | 75 | #define PCIE_CONF_VEND_ID 0x100 |
| 76 | #define PCIE_CONF_DEVICE_ID 0x102 | ||
| 76 | #define PCIE_CONF_CLASS_ID 0x106 | 77 | #define PCIE_CONF_CLASS_ID 0x106 |
| 77 | 78 | ||
| 78 | #define PCIE_INT_MASK 0x420 | 79 | #define PCIE_INT_MASK 0x420 |
| @@ -141,12 +142,16 @@ struct mtk_pcie_port; · 62 unmodified lines | |||
| 141 | /** | 142 | /** |
| 142 | * struct mtk_pcie_soc - differentiate between host generations | 143 | * struct mtk_pcie_soc - differentiate between host generations |
| 143 | * @need_fix_class_id: whether this host's class ID needed to be fixed or not | 144 | * @need_fix_class_id: whether this host's class ID needed to be fixed or not |
| 145 | * @need_fix_device_id: whether this host's device ID needed to be fixed or not | ||
| 146 | * @device_id: device ID which this host need to be fixed | ||
| 144 | * @ops: pointer to configuration access functions | 147 | * @ops: pointer to configuration access functions |
| 145 | * @startup: pointer to controller setting functions | 148 | * @startup: pointer to controller setting functions |
| 146 | * @setup_irq: pointer to initialize IRQ functions | 149 | * @setup_irq: pointer to initialize IRQ functions |
| 147 | */ | 150 | */ |
| 148 | struct mtk_pcie_soc { | 151 | struct mtk_pcie_soc { |
| 149 | bool need_fix_class_id; | 152 | bool need_fix_class_id; |
| 153 | bool need_fix_device_id; | ||
| 154 | unsigned int device_id; | ||
| 150 | struct pci_ops *ops; | 155 | struct pci_ops *ops; |
| 151 | int (*startup)(struct mtk_pcie_port *port); | 156 | int (*startup)(struct mtk_pcie_port *port); |
| 152 | int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node); | 157 | int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node); |
| @@ -696,6 +701,9 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) · 543 unmodified lines | |||
| 696 | writew(val, port->base + PCIE_CONF_CLASS_ID); | 701 | writew(val, port->base + PCIE_CONF_CLASS_ID); |
| 697 | } | 702 | } |
| 698 | 703 | ||
| 704 | if (soc->need_fix_device_id) | ||
| 705 | writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID); | ||
| 706 | |||
| 699 | /* 100ms timeout value should be enough for Gen1/2 training */ | 707 | /* 100ms timeout value should be enough for Gen1/2 training */ |
| 700 | err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val, | 708 | err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val, |
| 701 | !!(val & PCIE_PORT_LINKUP_V2), 20, | 709 | !!(val & PCIE_PORT_LINKUP_V2), 20, |
| @@ -1216,11 +1224,21 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = { · 514 unmodified lines | |||
| 1216 | .setup_irq = mtk_pcie_setup_irq, | 1224 | .setup_irq = mtk_pcie_setup_irq, |
| 1217 | }; | 1225 | }; |
| 1218 | 1226 | ||
| 1227 | static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = { | ||
| 1228 | .need_fix_class_id = true, | ||
| 1229 | .need_fix_device_id = true, | ||
| 1230 | .device_id = PCI_DEVICE_ID_MEDIATEK_7629, | ||
| 1231 | .ops = &mtk_pcie_ops_v2, | ||
| 1232 | .startup = mtk_pcie_startup_port_v2, | ||
| 1233 | .setup_irq = mtk_pcie_setup_irq, | ||
| 1234 | }; | ||
| 1235 | |||
| 1219 | static const struct of_device_id mtk_pcie_ids[] = { | 1236 | static const struct of_device_id mtk_pcie_ids[] = { |
| 1220 | { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 }, | 1237 | { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 }, |
| 1221 | { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 }, | 1238 | { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 }, |
| 1222 | { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 }, | 1239 | { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 }, |
| 1223 | { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 }, | 1240 | { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 }, |
| 1241 | { .compatible = "mediatek,mt7629-pcie", .data = &mtk_pcie_soc_mt7629 }, | ||
| 1224 | {}, | 1242 | {}, |
| 1225 | }; | 1243 | }; |
| 1226 | 1244 | ||
| @@ -2132,6 +2132,7 @@ · 2131 unmodified lines | |||
| 2132 | #define PCI_VENDOR_ID_MYRICOM 0x14c1 | 2132 | #define PCI_VENDOR_ID_MYRICOM 0x14c1 |
| 2133 | 2133 | ||
| 2134 | #define PCI_VENDOR_ID_MEDIATEK 0x14c3 | 2134 | #define PCI_VENDOR_ID_MEDIATEK 0x14c3 |
| 2135 | #define PCI_DEVICE_ID_MEDIATEK_7629 0x7629 | ||
| 2135 | 2136 | ||
| 2136 | #define PCI_VENDOR_ID_TITAN 0x14D2 | 2137 | #define PCI_VENDOR_ID_TITAN 0x14D2 |
| 2137 | #define PCI_DEVICE_ID_TITAN_010L 0x8001 | 2138 | #define PCI_DEVICE_ID_TITAN_010L 0x8001 |