Gen-12 display can decompress surfaces compressed by the media engine, add a new modifier as the driver needs to know the surface was compressed by the media or render engine. v2: Update code comment describing the color plane order for YUV semiplanar formats.
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| @@ -421,6 +421,19 @@ extern "C" { · 420 unmodified lines | |||
| 421 | */ | 421 | */ |
| 422 | #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6) | 422 | #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6) |
| 423 | 423 | ||
| 424 | /* | ||
| 425 | * Intel color control surfaces (CCS) for Gen-12 media compression | ||
| 426 | * | ||
| 427 | * The main surface is Y-tiled and at plane index 0, the CCS is linear and | ||
| 428 | * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in | ||
| 429 | * main surface. In other words, 4 bits in CCS map to a main surface cache | ||
| 430 | * line pair. The main surface pitch is required to be a multiple of four | ||
| 431 | * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the | ||
| 432 | * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces, | ||
| 433 | * planes 2 and 3 for the respective CCS. | ||
| 434 | */ | ||
| 435 | #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7) | ||
| 436 | |||
| 424 | /* | 437 | /* |
| 425 | * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks | 438 | * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks |
| 426 | * | 439 | * |