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net: phy: mscc: fix initialization of the MACsec protocol mode

At the very end of the MACsec block initialization in the MSCC PHY driver, the MACsec "protocol mode" is set. This setting should be set based on the PHY id within the package, as the bank used to access the register used depends on this. This was not done correctly, and only the first bank was used leading to the two upper PHYs being unstable when using the VSC8584. This patch fixes it.

Antoine Tenart committed 6 years ago

Commit 0ddfee11 parent 31096c35 files · +21 −10Browse files

Unified · Split

5 files
  1. drivers/net/phy/mscc/mscc.h +2 −0
  2. drivers/net/phy/mscc/mscc_mac.h +3 −3
  3. drivers/net/phy/mscc/mscc_macsec.c +10 −6
  4. drivers/net/phy/mscc/mscc_macsec.h +2 −1
  5. drivers/net/phy/mscc/mscc_main.c +4 −0
drivers/net/phy/mscc/mscc.h+2−0
@@ -354,6 +354,8 @@ struct vsc8531_private { · 353 unmodified lines
354 u64 *stats;354 u64 *stats;
355 int nstats;355 int nstats;
356 bool pkg_init;356 bool pkg_init;
357 /* PHY address within the package. */
358 u8 addr;
357 /* For multiple port PHYs; the MDIO address of the base PHY in the359 /* For multiple port PHYs; the MDIO address of the base PHY in the
358 * package.360 * package.
359 */361 */
drivers/net/phy/mscc/mscc_mac.h+3−3
@@ -152,8 +152,8 @@ · 151 unmodified lines
152#define MSCC_MAC_PAUSE_CFG_STATE_PAUSE_STATE BIT(0)152#define MSCC_MAC_PAUSE_CFG_STATE_PAUSE_STATE BIT(0)
153#define MSCC_MAC_PAUSE_CFG_STATE_MAC_TX_PAUSE_GEN BIT(4)153#define MSCC_MAC_PAUSE_CFG_STATE_MAC_TX_PAUSE_GEN BIT(4)
154 154
155#define MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL 0x2155#define MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL 0x2
156#define MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE(x) (x)156#define MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE(x) (x)
157#define MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M GENMASK(2, 0)157#define MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M GENMASK(2, 0)
158 158
159#endif /* _MSCC_PHY_LINE_MAC_H_ */159#endif /* _MSCC_PHY_LINE_MAC_H_ */
drivers/net/phy/mscc/mscc_macsec.c+10−6
@@ -316,6 +316,8 @@ static void vsc8584_macsec_mac_init(struct phy_device *phydev, · 315 unmodified lines
316/* Must be called with mdio_lock taken */316/* Must be called with mdio_lock taken */
317static int __vsc8584_macsec_init(struct phy_device *phydev)317static int __vsc8584_macsec_init(struct phy_device *phydev)
318{318{
319 struct vsc8531_private *priv = phydev->priv;
320 enum macsec_bank proc_bank;
319 u32 val;321 u32 val;
320 322
321 vsc8584_macsec_block_init(phydev, MACSEC_INGR);323 vsc8584_macsec_block_init(phydev, MACSEC_INGR);
@@ -351,12 +353,14 @@ static int __vsc8584_macsec_init(struct phy_device *phydev) · 29 unmodified lines
351 val |= MSCC_FCBUF_ENA_CFG_TX_ENA | MSCC_FCBUF_ENA_CFG_RX_ENA;353 val |= MSCC_FCBUF_ENA_CFG_TX_ENA | MSCC_FCBUF_ENA_CFG_RX_ENA;
352 vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_ENA_CFG, val);354 vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_ENA_CFG, val);
353 355
354 val = vsc8584_macsec_phy_read(phydev, IP_1588,356 proc_bank = (priv->addr < 2) ? PROC_0 : PROC_2;
355 MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL);357
356 val &= ~MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M;358 val = vsc8584_macsec_phy_read(phydev, proc_bank,
357 val |= MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE(4);359 MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL);
358 vsc8584_macsec_phy_write(phydev, IP_1588,360 val &= ~MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M;
359 MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL, val);361 val |= MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE(4);
362 vsc8584_macsec_phy_write(phydev, proc_bank,
363 MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL, val);
360 364
361 return 0;365 return 0;
362}366}
drivers/net/phy/mscc/mscc_macsec.h+2−1
@@ -64,7 +64,8 @@ enum macsec_bank { · 63 unmodified lines
64 FC_BUFFER = 0x04,64 FC_BUFFER = 0x04,
65 HOST_MAC = 0x05,65 HOST_MAC = 0x05,
66 LINE_MAC = 0x06,66 LINE_MAC = 0x06,
67 IP_1588 = 0x0e,67 PROC_0 = 0x0e,
68 PROC_2 = 0x0f,
68 MACSEC_INGR = 0x38,69 MACSEC_INGR = 0x38,
69 MACSEC_EGR = 0x3c,70 MACSEC_EGR = 0x3c,
70};71};
drivers/net/phy/mscc/mscc_main.c+4−0
@@ -1347,6 +1347,8 @@ static int vsc8584_config_init(struct phy_device *phydev) · 1346 unmodified lines
1347 else1347 else
1348 vsc8531->base_addr = phydev->mdio.addr - addr;1348 vsc8531->base_addr = phydev->mdio.addr - addr;
1349 1349
1350 vsc8531->addr = addr;
1351
1350 /* Some parts of the init sequence are identical for every PHY in the1352 /* Some parts of the init sequence are identical for every PHY in the
1351 * package. Some parts are modifying the GPIO register bank which is a1353 * package. Some parts are modifying the GPIO register bank which is a
1352 * set of registers that are affecting all PHYs, a few resetting the1354 * set of registers that are affecting all PHYs, a few resetting the
@@ -1771,6 +1773,8 @@ static int vsc8514_config_init(struct phy_device *phydev) · 418 unmodified lines
1771 else1773 else
1772 vsc8531->base_addr = phydev->mdio.addr - addr;1774 vsc8531->base_addr = phydev->mdio.addr - addr;
1773 1775
1776 vsc8531->addr = addr;
1777
1774 /* Some parts of the init sequence are identical for every PHY in the1778 /* Some parts of the init sequence are identical for every PHY in the
1775 * package. Some parts are modifying the GPIO register bank which is a1779 * package. Some parts are modifying the GPIO register bank which is a
1776 * set of registers that are affecting all PHYs, a few resetting the1780 * set of registers that are affecting all PHYs, a few resetting the