lael-labs/linux

Documentation/devicetree/bindings/mmc/arasan,sdhci.txt+39−3

@@ -15,10 +15,15 @@ Required Properties: · 14 unmodified lines
15	- "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY	15	- "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
16	- "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY	16	- "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
17	For this device it is strongly suggested to include arasan,soc-ctl-syscon.	17	For this device it is strongly suggested to include arasan,soc-ctl-syscon.
		18	- "xlnx,zynqmp-8.9a": ZynqMP SDHCI 8.9a PHY
		19	For this device it is strongly suggested to include clock-output-names and
		20	#clock-cells.
18	- "ti,am654-sdhci-5.1", "arasan,sdhci-5.1": TI AM654 MMC PHY	21	- "ti,am654-sdhci-5.1", "arasan,sdhci-5.1": TI AM654 MMC PHY
19	Note: This binding has been deprecated and moved to [5].	22	Note: This binding has been deprecated and moved to [5].
20	- "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel LGM eMMC PHY	23	- "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel LGM eMMC PHY
21	For this device it is strongly suggested to include arasan,soc-ctl-syscon.	24	For this device it is strongly suggested to include arasan,soc-ctl-syscon.
		25	- "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1": Intel LGM SDXC PHY
		26	For this device it is strongly suggested to include arasan,soc-ctl-syscon.
22		27
23	[5] Documentation/devicetree/bindings/mmc/sdhci-am654.txt	28	[5] Documentation/devicetree/bindings/mmc/sdhci-am654.txt
24		29
@@ -38,15 +43,19 @@ Optional Properties: · 13 unmodified lines
38	- clock-output-names: If specified, this will be the name of the card clock	43	- clock-output-names: If specified, this will be the name of the card clock
39	which will be exposed by this device. Required if #clock-cells is	44	which will be exposed by this device. Required if #clock-cells is
40	specified.	45	specified.
41	- #clock-cells: If specified this should be the value <0>. With this property	46	- #clock-cells: If specified this should be the value <0> or <1>. With this
42	in place we will export a clock representing the Card Clock. This clock	47	property in place we will export one or two clocks representing the Card
43	is expected to be consumed by our PHY. You must also specify	48	Clock. These clocks are expected to be consumed by our PHY.
44	- xlnx,fails-without-test-cd: when present, the controller doesn't work when	49	- xlnx,fails-without-test-cd: when present, the controller doesn't work when
45	the CD line is not connected properly, and the line is not connected	50	the CD line is not connected properly, and the line is not connected
46	properly. Test mode can be used to force the controller to function.	51	properly. Test mode can be used to force the controller to function.
47	- xlnx,int-clock-stable-broken: when present, the controller always reports	52	- xlnx,int-clock-stable-broken: when present, the controller always reports
48	that the internal clock is stable even when it is not.	53	that the internal clock is stable even when it is not.
49		54
		55	- xlnx,mio-bank: When specified, this will indicate the MIO bank number in
		56	which the command and data lines are configured. If not specified, driver
		57	will assume this as 0.
		58
50	Example:	59	Example:
51	sdhci@e0100000 {	60	sdhci@e0100000 {
52	compatible = "arasan,sdhci-8.9a";	61	compatible = "arasan,sdhci-8.9a";
@@ -83,6 +92,18 @@ Example: · 30 unmodified lines
83	#clock-cells = <0>;	92	#clock-cells = <0>;
84	};	93	};
85		94
		95	sdhci: mmc@ff160000 {
		96	compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
		97	interrupt-parent = <&gic>;
		98	interrupts = <0 48 4>;
		99	reg = <0x0 0xff160000 0x0 0x1000>;
		100	clocks = <&clk200>, <&clk200>;
		101	clock-names = "clk_xin", "clk_ahb";
		102	clock-output-names = "clk_out_sd0", "clk_in_sd0";
		103	#clock-cells = <1>;
		104	clk-phase-sd-hs = <63>, <72>;
		105	};
		106
86	emmc: sdhci@ec700000 {	107	emmc: sdhci@ec700000 {
87	compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";	108	compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
88	reg = <0xec700000 0x300>;	109	reg = <0xec700000 0x300>;
@@ -97,3 +118,18 @@ Example: · 8 unmodified lines
97	phy-names = "phy_arasan";	118	phy-names = "phy_arasan";
98	arasan,soc-ctl-syscon = <&sysconf>;	119	arasan,soc-ctl-syscon = <&sysconf>;
99	};	120	};
		121
		122	sdxc: sdhci@ec600000 {
		123	compatible = "arasan,sdhci-5.1", "intel,lgm-sdhci-5.1-sdxc";
		124	reg = <0xec600000 0x300>;
		125	interrupt-parent = <&ioapic1>;
		126	interrupts = <43 1>;
		127	clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
		128	<&cgu0 LGM_GCLK_SDXC>;
		129	clock-names = "clk_xin", "clk_ahb", "gate";
		130	clock-output-names = "sdxc_cardclock";
		131	#clock-cells = <0>;
		132	phys = <&sdxc_phy>;
		133	phy-names = "phy_arasan";
		134	arasan,soc-ctl-syscon = <&sysconf>;
		135	};

Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt+3−0

 	       "fsl,imx6ull-usdhc"
 	       "fsl,imx7d-usdhc"
 	       "fsl,imx7ulp-usdhc"
+	       "fsl,imx8mq-usdhc"
+	       "fsl,imx8mm-usdhc"
+	       "fsl,imx8mn-usdhc"
 	       "fsl,imx8qxp-usdhc"
 Optional properties:

Documentation/devicetree/bindings/mmc/jz4740.txt+5−3

-* Ingenic JZ47xx MMC controllers
+* Ingenic XBurst MMC controllers
 This file documents the device tree properties used for the MMC controller in
-Ingenic JZ4740/JZ4780 SoCs. These are in addition to the core MMC properties
+Ingenic JZ4740/JZ4760/JZ4780/X1000 SoCs. These are in addition to the core MMC
-described in mmc.txt.
+properties described in mmc.txt.
 Required properties:
 - compatible: Should be one of the following:
   - "ingenic,jz4740-mmc" for the JZ4740
   - "ingenic,jz4725b-mmc" for the JZ4725B
+  - "ingenic,jz4760-mmc" for the JZ4760
   - "ingenic,jz4780-mmc" for the JZ4780
+  - "ingenic,x1000-mmc" for the X1000
 - reg: Should contain the MMC controller registers location and length.
 - interrupts: Should contain the interrupt specifier of the MMC controller.
 - clocks: Clock for the MMC controller.

Documentation/devicetree/bindings/mmc/mmc-controller.yaml+14−0

@@ -333,6 +333,19 @@ patternProperties: · 332 unmodified lines
333	required:	333	required:
334	- reg	334	- reg
335		335
		336	"^clk-phase-(legacy\|sd-hs\|mmc-(hs\|hs[24]00\|ddr52)\|uhs-(sdr(12\|25\|50\|104)\|ddr50))$":
		337	allOf:
		338	- $ref: /schemas/types.yaml#/definitions/uint32-array
		339	minItems: 2
		340	maxItems: 2
		341	items:
		342	minimum: 0
		343	maximum: 359
		344	description:
		345	Set the clock (phase) delays which are to be configured in the
		346	controller while switching to particular speed mode. These values
		347	are in pair of degrees.
		348
336	dependencies:	349	dependencies:
337	cd-debounce-delay-ms: [ cd-gpios ]	350	cd-debounce-delay-ms: [ cd-gpios ]
338	fixed-emmc-driver-type: [ non-removable ]	351	fixed-emmc-driver-type: [ non-removable ]
@@ -351,6 +364,7 @@ examples: · 12 unmodified lines
351	keep-power-in-suspend;	364	keep-power-in-suspend;
352	wakeup-source;	365	wakeup-source;
353	mmc-pwrseq = <&sdhci0_pwrseq>;	366	mmc-pwrseq = <&sdhci0_pwrseq>;
		367	clk-phase-sd-hs = <63>, <72>;
354	};	368	};
355		369
356	- \|	370	- \|

Documentation/devicetree/bindings/mmc/owl-mmc.yaml+59−0

@@ -0,0 +1,59 @@
	1	# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	%YAML 1.2
	3	---
	4	$id: http://devicetree.org/schemas/mmc/owl-mmc.yaml#
	5	$schema: http://devicetree.org/meta-schemas/core.yaml#
	6
	7	title: Actions Semi Owl SoCs SD/MMC/SDIO controller
	8
	9	allOf:
	10	- $ref: "mmc-controller.yaml"
	11
	12	maintainers:
	13	- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
	14
	15	properties:
	16	compatible:
	17	const: actions,owl-mmc
	18
	19	reg:
	20	maxItems: 1
	21
	22	interrupts:
	23	maxItems: 1
	24
	25	clocks:
	26	minItems: 1
	27
	28	resets:
	29	maxItems: 1
	30
	31	dmas:
	32	maxItems: 1
	33
	34	dma-names:
	35	const: mmc
	36
	37	required:
	38	- compatible
	39	- reg
	40	- interrupts
	41	- clocks
	42	- resets
	43	- dmas
	44	- dma-names
	45
	46	examples:
	47	- \|
	48	mmc0: mmc@e0330000 {
	49	compatible = "actions,owl-mmc";
	50	reg = <0x0 0xe0330000 0x0 0x4000>;
	51	interrupts = <0 42 4>;
	52	clocks = <&cmu 56>;
	53	resets = <&cmu 23>;
	54	dmas = <&dma 2>;
	55	dma-names = "mmc";
	56	bus-width = <4>;
	57	};
	58
	59	...

Documentation/devicetree/bindings/mmc/renesas,sdhi.txt+1−0

@@ -11,6 +11,7 @@ Required properties: · 10 unmodified lines
11	"renesas,sdhi-r8a7744" - SDHI IP on R8A7744 SoC	11	"renesas,sdhi-r8a7744" - SDHI IP on R8A7744 SoC
12	"renesas,sdhi-r8a7745" - SDHI IP on R8A7745 SoC	12	"renesas,sdhi-r8a7745" - SDHI IP on R8A7745 SoC
13	"renesas,sdhi-r8a774a1" - SDHI IP on R8A774A1 SoC	13	"renesas,sdhi-r8a774a1" - SDHI IP on R8A774A1 SoC
		14	"renesas,sdhi-r8a774b1" - SDHI IP on R8A774B1 SoC
14	"renesas,sdhi-r8a774c0" - SDHI IP on R8A774C0 SoC	15	"renesas,sdhi-r8a774c0" - SDHI IP on R8A774C0 SoC
15	"renesas,sdhi-r8a77470" - SDHI IP on R8A77470 SoC	16	"renesas,sdhi-r8a77470" - SDHI IP on R8A77470 SoC
16	"renesas,sdhi-mmc-r8a77470" - SDHI/MMC IP on R8A77470 SoC	17	"renesas,sdhi-mmc-r8a77470" - SDHI/MMC IP on R8A77470 SoC

Documentation/devicetree/bindings/mmc/sdhci-atmel.txt+5−0

 - clocks:		Phandlers to the clocks.
 - clock-names:		Must be "hclock", "multclk", "baseclk";
+Optional properties:
+- microchip,sdcal-inverted: when present, polarity on the SDCAL SoC pin is
+  inverted. The default polarity for this signal is described in the datasheet.
+  For instance on SAMA5D2, the pin is usually tied to the GND with a resistor
+  and a capacitor (see "SDMMC I/O Calibration" chapter).
 Example:

Documentation/devicetree/bindings/mmc/sdhci-milbeaut.txt+30−0

@@ -0,0 +1,30 @@
	1	* SOCIONEXT Milbeaut SDHCI controller
	2
	3	This file documents differences between the core properties in mmc.txt
	4	and the properties used by the sdhci_milbeaut driver.
	5
	6	Required properties:
	7	- compatible: "socionext,milbeaut-m10v-sdhci-3.0"
	8	- clocks: Must contain an entry for each entry in clock-names. It is a
	9	list of phandles and clock-specifier pairs.
	10	See ../clocks/clock-bindings.txt for details.
	11	- clock-names: Should contain the following two entries:
	12	"iface" - clock used for sdhci interface
	13	"core" - core clock for sdhci controller
	14
	15	Optional properties:
	16	- fujitsu,cmd-dat-delay-select: boolean property indicating that this host
	17	requires the CMD_DAT_DELAY control to be enabled.
	18
	19	Example:
	20	sdhci3: mmc@1b010000 {
	21	compatible = "socionext,milbeaut-m10v-sdhci-3.0";
	22	reg = <0x1b010000 0x10000>;
	23	interrupts = <0 265 0x4>;
	24	voltage-ranges = <3300 3300>;
	25	bus-width = <4>;
	26	clocks = <&clk 7>, <&ahb_clk>;
	27	clock-names = "core", "iface";
	28	cap-sdio-irq;
	29	fujitsu,cmd-dat-delay-select;
	30	};

Documentation/devicetree/bindings/net/wireless/ti,wl1251.txt+26−0

@@ -35,3 +35,29 @@ Examples: · 34 unmodified lines
35	ti,power-gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */	35	ti,power-gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */
36	};	36	};
37	};	37	};
		38
		39	&mmc3 {
		40	vmmc-supply = <&wlan_en>;
		41
		42	bus-width = <4>;
		43	non-removable;
		44	ti,non-removable;
		45	cap-power-off-card;
		46
		47	pinctrl-names = "default";
		48	pinctrl-0 = <&mmc3_pins>;
		49
		50	#address-cells = <1>;
		51	#size-cells = <0>;
		52
		53	wlan: wifi@1 {
		54	compatible = "ti,wl1251";
		55
		56	reg = <1>;
		57
		58	interrupt-parent = <&gpio1>;
		59	interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_21 */
		60
		61	ti,wl1251-has-eeprom;
		62	};
		63	};

MAINTAINERS+3−3

@@ -1399,6 +1399,7 @@ F: drivers/clk/actions/ · 1398 unmodified lines
1399	F: drivers/clocksource/timer-owl*	1399	F: drivers/clocksource/timer-owl*
1400	F: drivers/dma/owl-dma.c	1400	F: drivers/dma/owl-dma.c
1401	F: drivers/i2c/busses/i2c-owl.c	1401	F: drivers/i2c/busses/i2c-owl.c
		1402	F: drivers/mmc/host/owl-mmc.c
1402	F: drivers/pinctrl/actions/*	1403	F: drivers/pinctrl/actions/*
1403	F: drivers/soc/actions/	1404	F: drivers/soc/actions/
1404	F: include/dt-bindings/power/owl-*	1405	F: include/dt-bindings/power/owl-*
@@ -1407,6 +1408,7 @@ F: Documentation/devicetree/bindings/arm/actions.yaml · 2 unmodified lines
1407	F: Documentation/devicetree/bindings/clock/actions,owl-cmu.txt	1408	F: Documentation/devicetree/bindings/clock/actions,owl-cmu.txt
1408	F: Documentation/devicetree/bindings/dma/owl-dma.txt	1409	F: Documentation/devicetree/bindings/dma/owl-dma.txt
1409	F: Documentation/devicetree/bindings/i2c/i2c-owl.txt	1410	F: Documentation/devicetree/bindings/i2c/i2c-owl.txt
		1411	F: Documentation/devicetree/bindings/mmc/owl-mmc.yaml
1410	F: Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt	1412	F: Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt
1411	F: Documentation/devicetree/bindings/power/actions,owl-sps.txt	1413	F: Documentation/devicetree/bindings/power/actions,owl-sps.txt
1412	F: Documentation/devicetree/bindings/timer/actions,owl-timer.txt	1414	F: Documentation/devicetree/bindings/timer/actions,owl-timer.txt
@@ -17612,10 +17614,8 @@ S: Maintained · 16199 unmodified lines
17612	F: drivers/hwmon/vt8231.c	17614	F: drivers/hwmon/vt8231.c
17613		17615
17614	VUB300 USB to SDIO/SD/MMC bridge chip	17616	VUB300 USB to SDIO/SD/MMC bridge chip
17615	M: Tony Olech <tony.olech@elandigitalsystems.com>
17616	L: linux-mmc@vger.kernel.org	17617	L: linux-mmc@vger.kernel.org
17617	L: linux-usb@vger.kernel.org	17618	S: Orphan
17618	S: Supported
17619	F: drivers/mmc/host/vub300.c	17619	F: drivers/mmc/host/vub300.c
17620		17620
17621	W1 DALLAS'S 1-WIRE BUS	17621	W1 DALLAS'S 1-WIRE BUS

arch/arm/boot/dts/omap3-pandora-common.dtsi+34−2

@@ -226,6 +226,17 @@ · 225 unmodified lines
226	gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* GPIO_164 */	226	gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* GPIO_164 */
227	};	227	};
228		228
		229	/* wl1251 wifi+bt module */
		230	wlan_en: fixed-regulator-wg7210_en {
		231	compatible = "regulator-fixed";
		232	regulator-name = "vwlan";
		233	regulator-min-microvolt = <1800000>;
		234	regulator-max-microvolt = <1800000>;
		235	startup-delay-us = <50000>;
		236	enable-active-high;
		237	gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
		238	};
		239
229	/* wg7210 (wifi+bt module) 32k clock buffer */	240	/* wg7210 (wifi+bt module) 32k clock buffer */
230	wg7210_32k: fixed-regulator-wg7210_32k {	241	wg7210_32k: fixed-regulator-wg7210_32k {
231	compatible = "regulator-fixed";	242	compatible = "regulator-fixed";
@@ -522,9 +533,30 @@ · 290 unmodified lines
522	/wp-gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;/ /* GPIO_127 */	533	/wp-gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;/ /* GPIO_127 */
523	};	534	};
524		535
525	/* mmc3 is probed using pdata-quirks to pass wl1251 card data */
526	&mmc3 {	536	&mmc3 {
527	status = "disabled";	537	vmmc-supply = <&wlan_en>;
		538
		539	bus-width = <4>;
		540	non-removable;
		541	ti,non-removable;
		542	cap-power-off-card;
		543
		544	pinctrl-names = "default";
		545	pinctrl-0 = <&mmc3_pins>;
		546
		547	#address-cells = <1>;
		548	#size-cells = <0>;
		549
		550	wlan: wifi@1 {
		551	compatible = "ti,wl1251";
		552
		553	reg = <1>;
		554
		555	interrupt-parent = <&gpio1>;
		556	interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_21 */
		557
		558	ti,wl1251-has-eeprom;
		559	};
528	};	560	};
529		561
530	/* bluetooth*/	562	/* bluetooth*/

arch/arm/mach-omap2/Makefile+0−3

@@ -216,9 +216,6 @@ obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o · 215 unmodified lines
216		216
217	# Platform specific device init code	217	# Platform specific device init code
218		218
219	omap-hsmmc-$(CONFIG_MMC_OMAP_HS) := hsmmc.o
220	obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y)
221
222	obj-y += omap_phy_internal.o	219	obj-y += omap_phy_internal.o
223		220
224	obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o	221	obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o

arch/arm/mach-omap2/common.h+0−1

@@ -352,7 +352,6 @@ void omap_pcs_legacy_init(int irq, void (*rearm)(void)); · 351 unmodified lines
352	struct omap_sdrc_params;	352	struct omap_sdrc_params;
353	extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,	353	extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
354	struct omap_sdrc_params *sdrc_cs1);	354	struct omap_sdrc_params *sdrc_cs1);
355	struct omap2_hsmmc_info;
356	extern void omap_reserve(void);	355	extern void omap_reserve(void);
357		356
358	struct omap_hwmod;	357	struct omap_hwmod;

arch/arm/mach-omap2/hsmmc.c+0−171

@@ -1,171 +0,0 @@
1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* linux/arch/arm/mach-omap2/hsmmc.c
4	*
5	* Copyright (C) 2007-2008 Texas Instruments
6	* Copyright (C) 2008 Nokia Corporation
7	* Author: Texas Instruments
8	*/
9	#include <linux/kernel.h>
10	#include <linux/slab.h>
11	#include <linux/string.h>
12	#include <linux/delay.h>
13	#include <linux/mmc/host.h>
14	#include <linux/platform_data/hsmmc-omap.h>
15
16	#include "soc.h"
17	#include "omap_device.h"
18
19	#include "hsmmc.h"
20	#include "control.h"
21
22	#if IS_ENABLED(CONFIG_MMC_OMAP_HS)
23
24	static u16 control_pbias_offset;
25	static u16 control_devconf1_offset;
26
27	#define HSMMC_NAME_LEN 9
28
29	static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
30	struct omap_hsmmc_platform_data *mmc)
31	{
32	char *hc_name;
33
34	hc_name = kzalloc(HSMMC_NAME_LEN + 1, GFP_KERNEL);
35	if (!hc_name)
36	return -ENOMEM;
37
38	snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i", c->mmc, 1);
39	mmc->name = hc_name;
40	mmc->caps = c->caps;
41	mmc->reg_offset = 0;
42
43	return 0;
44	}
45
46	static int omap_hsmmc_done;
47
48	void omap_hsmmc_late_init(struct omap2_hsmmc_info *c)
49	{
50	struct platform_device *pdev;
51	int res;
52
53	if (omap_hsmmc_done)
54	return;
55
56	omap_hsmmc_done = 1;
57
58	for (; c->mmc; c++) {
59	pdev = c->pdev;
60	if (!pdev)
61	continue;
62	res = omap_device_register(pdev);
63	if (res)
64	pr_err("Could not late init MMC\n");
65	}
66	}
67
68	#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
69
70	static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
71	int ctrl_nr)
72	{
73	struct omap_hwmod *oh;
74	struct omap_hwmod *ohs[1];
75	struct omap_device *od;
76	struct platform_device *pdev;
77	char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
78	struct omap_hsmmc_platform_data *mmc_data;
79	struct omap_hsmmc_dev_attr *mmc_dev_attr;
80	char *name;
81	int res;
82
83	mmc_data = kzalloc(sizeof(*mmc_data), GFP_KERNEL);
84	if (!mmc_data)
85	return;
86
87	res = omap_hsmmc_pdata_init(hsmmcinfo, mmc_data);
88	if (res < 0)
89	goto free_mmc;
90
91	name = "omap_hsmmc";
92	res = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
93	"mmc%d", ctrl_nr);
94	WARN(res >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
95	"String buffer overflow in MMC%d device setup\n", ctrl_nr);
96
97	oh = omap_hwmod_lookup(oh_name);
98	if (!oh) {
99	pr_err("Could not look up %s\n", oh_name);
100	goto free_name;
101	}
102	ohs[0] = oh;
103	if (oh->dev_attr != NULL) {
104	mmc_dev_attr = oh->dev_attr;
105	mmc_data->controller_flags = mmc_dev_attr->flags;
106	}
107
108	pdev = platform_device_alloc(name, ctrl_nr - 1);
109	if (!pdev) {
110	pr_err("Could not allocate pdev for %s\n", name);
111	goto free_name;
112	}
113	dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
114
115	od = omap_device_alloc(pdev, ohs, 1);
116	if (IS_ERR(od)) {
117	pr_err("Could not allocate od for %s\n", name);
118	goto put_pdev;
119	}
120
121	res = platform_device_add_data(pdev, mmc_data,
122	sizeof(struct omap_hsmmc_platform_data));
123	if (res) {
124	pr_err("Could not add pdata for %s\n", name);
125	goto put_pdev;
126	}
127
128	hsmmcinfo->pdev = pdev;
129
130	res = omap_device_register(pdev);
131	if (res) {
132	pr_err("Could not register od for %s\n", name);
133	goto free_od;
134	}
135
136	goto free_mmc;
137
138	free_od:
139	omap_device_delete(od);
140
141	put_pdev:
142	platform_device_put(pdev);
143
144	free_name:
145	kfree(mmc_data->name);
146
147	free_mmc:
148	kfree(mmc_data);
149	}
150
151	void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers)
152	{
153	if (omap_hsmmc_done)
154	return;
155
156	omap_hsmmc_done = 1;
157
158	if (cpu_is_omap2430()) {
159	control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
160	control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
161	} else {
162	control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
163	control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
164	}
165
166	for (; controllers->mmc; controllers++)
167	omap_hsmmc_init_one(controllers, controllers->mmc);
168
169	}
170
171	#endif

arch/arm/mach-omap2/hsmmc.h+0−32

@@ -1,32 +0,0 @@
1	/* SPDX-License-Identifier: GPL-2.0-only */
2	/*
3	* MMC definitions for OMAP2
4	*/
5
6	struct mmc_card;
7
8	struct omap2_hsmmc_info {
9	u8 mmc; /* controller 1/2/3 */
10	u32 caps; /* 4/8 wires and any additional host
11	* capabilities OR'd (ref. linux/mmc/host.h) */
12	struct platform_device pdev; / mmc controller instance */
13	/* init some special card */
14	void (init_card)(struct mmc_card card);
15	};
16
17	#if IS_ENABLED(CONFIG_MMC_OMAP_HS)
18
19	void omap_hsmmc_init(struct omap2_hsmmc_info *);
20	void omap_hsmmc_late_init(struct omap2_hsmmc_info *);
21
22	#else
23
24	static inline void omap_hsmmc_init(struct omap2_hsmmc_info *info)
25	{
26	}
27
28	static inline void omap_hsmmc_late_init(struct omap2_hsmmc_info *info)
29	{
30	}
31
32	#endif

arch/arm/mach-omap2/pdata-quirks.c+0−105

@@ -7,7 +7,6 @@ · 6 unmodified lines
7	#include <linux/clk.h>	7	#include <linux/clk.h>
8	#include <linux/davinci_emac.h>	8	#include <linux/davinci_emac.h>
9	#include <linux/gpio.h>	9	#include <linux/gpio.h>
10	#include <linux/gpio/machine.h>
11	#include <linux/init.h>	10	#include <linux/init.h>
12	#include <linux/kernel.h>	11	#include <linux/kernel.h>
13	#include <linux/of_platform.h>	12	#include <linux/of_platform.h>
@@ -33,7 +32,6 @@ · 19 unmodified lines
33	#include "omap_device.h"	32	#include "omap_device.h"
34	#include "omap-secure.h"	33	#include "omap-secure.h"
35	#include "soc.h"	34	#include "soc.h"
36	#include "hsmmc.h"
37		35
38	static struct omap_hsmmc_platform_data __maybe_unused mmc_pdata[2];	36	static struct omap_hsmmc_platform_data __maybe_unused mmc_pdata[2];
39		37
@@ -300,118 +298,15 @@ static void __init omap3_logicpd_torpedo_init(void) · 260 unmodified lines
300	}	298	}
301		299
302	/* omap3pandora legacy devices */	300	/* omap3pandora legacy devices */
303	#define PANDORA_WIFI_IRQ_GPIO 21
304	#define PANDORA_WIFI_NRESET_GPIO 23
305		301
306	static struct platform_device pandora_backlight = {	302	static struct platform_device pandora_backlight = {
307	.name = "pandora-backlight",	303	.name = "pandora-backlight",
308	.id = -1,	304	.id = -1,
309	};	305	};
310		306
311	static struct regulator_consumer_supply pandora_vmmc3_supply[] = {
312	REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2"),
313	};
314
315	static struct regulator_init_data pandora_vmmc3 = {
316	.constraints = {
317	.valid_ops_mask = REGULATOR_CHANGE_STATUS,
318	},
319	.num_consumer_supplies = ARRAY_SIZE(pandora_vmmc3_supply),
320	.consumer_supplies = pandora_vmmc3_supply,
321	};
322
323	static struct fixed_voltage_config pandora_vwlan = {
324	.supply_name = "vwlan",
325	.microvolts = 1800000, /* 1.8V */
326	.startup_delay = 50000, /* 50ms */
327	.init_data = &pandora_vmmc3,
328	};
329
330	static struct platform_device pandora_vwlan_device = {
331	.name = "reg-fixed-voltage",
332	.id = 1,
333	.dev = {
334	.platform_data = &pandora_vwlan,
335	},
336	};
337
338	static struct gpiod_lookup_table pandora_vwlan_gpiod_table = {
339	.dev_id = "reg-fixed-voltage.1",
340	.table = {
341	/*
342	* As this is a low GPIO number it should be at the first
343	* GPIO bank.
344	*/
345	GPIO_LOOKUP("gpio-0-31", PANDORA_WIFI_NRESET_GPIO,
346	NULL, GPIO_ACTIVE_HIGH),
347	{ },
348	},
349	};
350
351	static void pandora_wl1251_init_card(struct mmc_card *card)
352	{
353	/*
354	* We have TI wl1251 attached to MMC3. Pass this information to
355	* SDIO core because it can't be probed by normal methods.
356	*/
357	if (card->type == MMC_TYPE_SDIO \|\| card->type == MMC_TYPE_SD_COMBO) {
358	card->quirks \|= MMC_QUIRK_NONSTD_SDIO;
359	card->cccr.wide_bus = 1;
360	card->cis.vendor = 0x104c;
361	card->cis.device = 0x9066;
362	card->cis.blksize = 512;
363	card->cis.max_dtr = 24000000;
364	card->ocr = 0x80;
365	}
366	}
367
368	static struct omap2_hsmmc_info pandora_mmc3[] = {
369	{
370	.mmc = 3,
371	.caps = MMC_CAP_4_BIT_DATA \| MMC_CAP_POWER_OFF_CARD,
372	.init_card = pandora_wl1251_init_card,
373	},
374	{} /* Terminator */
375	};
376
377	static void __init pandora_wl1251_init(void)
378	{
379	struct wl1251_platform_data pandora_wl1251_pdata;
380	int ret;
381
382	memset(&pandora_wl1251_pdata, 0, sizeof(pandora_wl1251_pdata));
383
384	pandora_wl1251_pdata.power_gpio = -1;
385
386	ret = gpio_request_one(PANDORA_WIFI_IRQ_GPIO, GPIOF_IN, "wl1251 irq");
387	if (ret < 0)
388	goto fail;
389
390	pandora_wl1251_pdata.irq = gpio_to_irq(PANDORA_WIFI_IRQ_GPIO);
391	if (pandora_wl1251_pdata.irq < 0)
392	goto fail_irq;
393
394	pandora_wl1251_pdata.use_eeprom = true;
395	ret = wl1251_set_platform_data(&pandora_wl1251_pdata);
396	if (ret < 0)
397	goto fail_irq;
398
399	return;
400
401	fail_irq:
402	gpio_free(PANDORA_WIFI_IRQ_GPIO);
403	fail:
404	pr_err("wl1251 board initialisation failed\n");
405	}
406
407	static void __init omap3_pandora_legacy_init(void)	307	static void __init omap3_pandora_legacy_init(void)
408	{	308	{
409	platform_device_register(&pandora_backlight);	309	platform_device_register(&pandora_backlight);
410	gpiod_add_lookup_table(&pandora_vwlan_gpiod_table);
411	platform_device_register(&pandora_vwlan_device);
412	omap_hsmmc_init(pandora_mmc3);
413	omap_hsmmc_late_init(pandora_mmc3);
414	pandora_wl1251_init();
415	}	310	}
416	#endif /* CONFIG_ARCH_OMAP3 */	311	#endif /* CONFIG_ARCH_OMAP3 */
417		312

drivers/memstick/core/Kconfig+9−9

@@ -6,16 +6,16 @@ · 5 unmodified lines
6	comment "MemoryStick drivers"	6	comment "MemoryStick drivers"
7		7
8	config MEMSTICK_UNSAFE_RESUME	8	config MEMSTICK_UNSAFE_RESUME
9	bool "Allow unsafe resume (DANGEROUS)"	9	bool "Allow unsafe resume (DANGEROUS)"
10	help	10	help
11	If you say Y here, the MemoryStick layer will assume that all	11	If you say Y here, the MemoryStick layer will assume that all
12	cards stayed in their respective slots during the suspend. The	12	cards stayed in their respective slots during the suspend. The
13	normal behaviour is to remove them at suspend and	13	normal behaviour is to remove them at suspend and
14	redetecting them at resume. Breaking this assumption will	14	redetecting them at resume. Breaking this assumption will
15	in most cases result in data corruption.	15	in most cases result in data corruption.
16		16
17	This option is usually just for embedded systems which use	17	This option is usually just for embedded systems which use
18	a MemoryStick card for rootfs. Most people should say N here.	18	a MemoryStick card for rootfs. Most people should say N here.
19		19
20	config MSPRO_BLOCK	20	config MSPRO_BLOCK
21	tristate "MemoryStick Pro block device driver"	21	tristate "MemoryStick Pro block device driver"

drivers/memstick/host/Kconfig+2−2

@@ -18,7 +18,7 @@ config MEMSTICK_TIFM_MS · 17 unmodified lines
18	'Misc devices: TI Flash Media PCI74xx/PCI76xx host adapter support	18	'Misc devices: TI Flash Media PCI74xx/PCI76xx host adapter support
19	(TIFM_7XX1)'.	19	(TIFM_7XX1)'.
20		20
21	To compile this driver as a module, choose M here: the	21	To compile this driver as a module, choose M here: the
22	module will be called tifm_ms.	22	module will be called tifm_ms.
23		23
24	config MEMSTICK_JMICRON_38X	24	config MEMSTICK_JMICRON_38X
@@ -29,7 +29,7 @@ config MEMSTICK_JMICRON_38X · 4 unmodified lines
29	Say Y here if you want to be able to access MemoryStick cards with	29	Say Y here if you want to be able to access MemoryStick cards with
30	the JMicron(R) JMB38X MemoryStick card reader.	30	the JMicron(R) JMB38X MemoryStick card reader.
31		31
32	To compile this driver as a module, choose M here: the	32	To compile this driver as a module, choose M here: the
33	module will be called jmb38x_ms.	33	module will be called jmb38x_ms.
34		34
35	config MEMSTICK_R592	35	config MEMSTICK_R592

drivers/memstick/host/jmb38x_ms.c+6−6

@@ -433,13 +433,13 @@ static int jmb38x_ms_issue_cmd(struct memstick_host *msh) · 432 unmodified lines
433	writel(((1 << 16) & BLOCK_COUNT_MASK)	433	writel(((1 << 16) & BLOCK_COUNT_MASK)
434	\| (data_len & BLOCK_SIZE_MASK),	434	\| (data_len & BLOCK_SIZE_MASK),
435	host->addr + BLOCK);	435	host->addr + BLOCK);
436	t_val = readl(host->addr + INT_STATUS_ENABLE);	436	t_val = readl(host->addr + INT_STATUS_ENABLE);
437	t_val \|= host->req->data_dir == READ	437	t_val \|= host->req->data_dir == READ
438	? INT_STATUS_FIFO_RRDY	438	? INT_STATUS_FIFO_RRDY
439	: INT_STATUS_FIFO_WRDY;	439	: INT_STATUS_FIFO_WRDY;
440		440
441	writel(t_val, host->addr + INT_STATUS_ENABLE);	441	writel(t_val, host->addr + INT_STATUS_ENABLE);
442	writel(t_val, host->addr + INT_SIGNAL_ENABLE);	442	writel(t_val, host->addr + INT_SIGNAL_ENABLE);
443	} else {	443	} else {
444	cmd &= ~(TPC_DATA_SEL \| 0xf);	444	cmd &= ~(TPC_DATA_SEL \| 0xf);
445	host->cmd_flags \|= REG_DATA;	445	host->cmd_flags \|= REG_DATA;

drivers/mmc/core/block.c+57−94

 	return 0;
 }
-static int ioctl_rpmb_card_status_poll(struct mmc_card *card, u32 *status,
-				       u32 retries_max)
-{
-	int err;
-	u32 retry_count = 0;
-	if (!status || !retries_max)
-		return -EINVAL;
-	do {
-		err = __mmc_send_status(card, status, 5);
-		if (err)
-			break;
-		if (!R1_STATUS(*status) &&
-				(R1_CURRENT_STATE(*status) != R1_STATE_PRG))
-			break; /* RPMB programming operation complete */
-		/*
-		 * Rechedule to give the MMC device a chance to continue
-		 * processing the previous command without being polled too
-		 * frequently.
-		 */
-		usleep_range(1000, 5000);
-	} while (++retry_count < retries_max);
-	if (retry_count == retries_max)
-		err = -EPERM;
-	return err;
-}
 static int ioctl_do_sanitize(struct mmc_card *card)
 {
 	int err;
 	return err;
 }
+static inline bool mmc_blk_in_tran_state(u32 status)
+{
+	/*
+	 * Some cards mishandle the status bits, so make sure to check both the
+	 * busy indication and the card state.
+	 */
+	return status & R1_READY_FOR_DATA &&
+	       (R1_CURRENT_STATE(status) == R1_STATE_TRAN);
+}
+static int card_busy_detect(struct mmc_card *card, unsigned int timeout_ms,
+			    u32 *resp_errs)
+{
+	unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
+	int err = 0;
+	u32 status;
+	do {
+		bool done = time_after(jiffies, timeout);
+		err = __mmc_send_status(card, &status, 5);
+		if (err) {
+			dev_err(mmc_dev(card->host),
+				"error %d requesting status\n", err);
+			return err;
+		}
+		/* Accumulate any response error bits seen */
+		if (resp_errs)
+			*resp_errs |= status;
+		/*
+		 * Timeout if the device never becomes ready for data and never
+		 * leaves the program state.
+		 */
+		if (done) {
+			dev_err(mmc_dev(card->host),
+				"Card stuck in wrong state! %s status: %#x\n",
+				 __func__, status);
+			return -ETIMEDOUT;
+		}
+		/*
+		 * Some cards mishandle the status bits,
+		 * so make sure to check both the busy
+		 * indication and the card state.
+		 */
+	} while (!mmc_blk_in_tran_state(status));
+	return err;
+}
 static int __mmc_blk_ioctl_cmd(struct mmc_card *card, struct mmc_blk_data *md,
 			       struct mmc_blk_ioc_data *idata)
 {
 	struct scatterlist sg;
 	int err;
 	unsigned int target_part;
-	u32 status = 0;
 	if (!card || !md || !idata)
 		return -EINVAL;
 	memcpy(&(idata->ic.response), cmd.resp, sizeof(cmd.resp));
-	if (idata->rpmb) {
+	if (idata->rpmb || (cmd.flags & MMC_RSP_R1B)) {
 		/*
-		 * Ensure RPMB command has completed by polling CMD13
+		 * Ensure RPMB/R1B command has completed by polling CMD13
 		 * "Send Status".
 		 */
-		err = ioctl_rpmb_card_status_poll(card, &status, 5);
+		err = card_busy_detect(card, MMC_BLK_TIMEOUT_MS, NULL);
-		if (err)
-			dev_err(mmc_dev(card->host),
-					"%s: Card Status=0x%08X, error %d\n",
-					__func__, status, err);
 	}
 	return err;
 	return ms;
 }
-static inline bool mmc_blk_in_tran_state(u32 status)
-{
-	/*
-	 * Some cards mishandle the status bits, so make sure to check both the
-	 * busy indication and the card state.
-	 */
-	return status & R1_READY_FOR_DATA &&
-	       (R1_CURRENT_STATE(status) == R1_STATE_TRAN);
-}
-static int card_busy_detect(struct mmc_card *card, unsigned int timeout_ms,
-			    struct request *req, u32 *resp_errs)
-{
-	unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
-	int err = 0;
-	u32 status;
-	do {
-		bool done = time_after(jiffies, timeout);
-		err = __mmc_send_status(card, &status, 5);
-		if (err) {
-			pr_err("%s: error %d requesting status\n",
-			       req->rq_disk->disk_name, err);
-			return err;
-		}
-		/* Accumulate any response error bits seen */
-		if (resp_errs)
-			*resp_errs |= status;
-		/*
-		 * Timeout if the device never becomes ready for data and never
-		 * leaves the program state.
-		 */
-		if (done) {
-			pr_err("%s: Card stuck in wrong state! %s %s status: %#x\n",
-				mmc_hostname(card->host),
-				req->rq_disk->disk_name, __func__, status);
-			return -ETIMEDOUT;
-		}
-		/*
-		 * Some cards mishandle the status bits,
-		 * so make sure to check both the busy
-		 * indication and the card state.
-		 */
-	} while (!mmc_blk_in_tran_state(status));
-	return err;
-}
 static int mmc_blk_reset(struct mmc_blk_data *md, struct mmc_host *host,
 			 int type)
 {
 	mmc_blk_send_stop(card, timeout);
-	err = card_busy_detect(card, timeout, req, NULL);
+	err = card_busy_detect(card, timeout, NULL);
 	mmc_retune_release(card->host);
 	if (mmc_host_is_spi(card->host) || rq_data_dir(req) == READ)
 		return 0;
-	err = card_busy_detect(card, MMC_BLK_TIMEOUT_MS, req, &status);
+	err = card_busy_detect(card, MMC_BLK_TIMEOUT_MS, &status);
 	/*
 	 * Do not assume data transferred correctly if there are any error bits

drivers/mmc/core/core.c+4−8

 	mmc_bus_put(host);
 }
-static void _mmc_detect_change(struct mmc_host *host, unsigned long delay,
+void _mmc_detect_change(struct mmc_host *host, unsigned long delay, bool cd_irq)
-				bool cd_irq)
 {
 	/*
 	 * If the device is configured as wakeup, we prevent a new sleep for
 	ret = host->bus_ops->hw_reset(host);
 	mmc_bus_put(host);
-	if (ret)
+	if (ret < 0)
 		pr_warn("%s: tried to HW reset card, got error %d\n",
 			mmc_hostname(host), ret);
 	mmc_bus_get(host);
-	/*
+	/* Verify a registered card to be functional, else remove it. */
-	 * if there is a _removable_ card registered, check whether it is
+	if (host->bus_ops && !host->bus_dead)
-	 * still present
-	 */
-	if (host->bus_ops && !host->bus_dead && mmc_card_is_removable(host))
 		host->bus_ops->detect(host);
 	host->detect_change = 0;

drivers/mmc/core/core.h+2−0

@@ -70,6 +70,8 @@ void mmc_rescan(struct work_struct *work); · 69 unmodified lines
70	void mmc_start_host(struct mmc_host *host);	70	void mmc_start_host(struct mmc_host *host);
71	void mmc_stop_host(struct mmc_host *host);	71	void mmc_stop_host(struct mmc_host *host);
72		72
		73	void _mmc_detect_change(struct mmc_host *host, unsigned long delay,
		74	bool cd_irq);
73	int _mmc_detect_card_removed(struct mmc_host *host);	75	int _mmc_detect_card_removed(struct mmc_host *host);
74	int mmc_detect_card_removed(struct mmc_host *host);	76	int mmc_detect_card_removed(struct mmc_host *host);
75		77

drivers/mmc/core/mmc.c+4−5

 	}
 }
-static void mmc_part_add(struct mmc_card *card, unsigned int size,
+static void mmc_part_add(struct mmc_card *card, u64 size,
 			 unsigned int part_cfg, char *name, int idx, bool ro,
 			 int area_type)
 {
 {
 	int idx;
 	u8 hc_erase_grp_sz, hc_wp_grp_sz;
-	unsigned int part_size;
+	u64 part_size;
 	/*
 	 * General purpose partition feature support --
 				(ext_csd[EXT_CSD_GP_SIZE_MULT + idx * 3 + 1]
 				<< 8) +
 				ext_csd[EXT_CSD_GP_SIZE_MULT + idx * 3];
-			part_size *= (size_t)(hc_erase_grp_sz *
+			part_size *= (hc_erase_grp_sz * hc_wp_grp_sz);
-				hc_wp_grp_sz);
 			mmc_part_add(card, part_size << 19,
 				EXT_CSD_PART_CONFIG_ACC_GP0 + idx,
 				"gp%d", idx, false,
 static int mmc_decode_ext_csd(struct mmc_card *card, u8 *ext_csd)
 {
 	int err = 0, idx;
-	unsigned int part_size;
+	u64 part_size;
 	struct device_node *np;
 	bool broken_hpi = false;

drivers/mmc/core/quirks.h+7−0

 	END_FIXUP
 };
 static const struct mmc_fixup sdio_fixup_methods[] = {
+	SDIO_FIXUP(SDIO_VENDOR_ID_TI_WL1251, SDIO_DEVICE_ID_TI_WL1251,
+		   add_quirk, MMC_QUIRK_NONSTD_FUNC_IF),
+	SDIO_FIXUP(SDIO_VENDOR_ID_TI_WL1251, SDIO_DEVICE_ID_TI_WL1251,
+		   add_quirk, MMC_QUIRK_DISABLE_CD),
 	SDIO_FIXUP(SDIO_VENDOR_ID_TI, SDIO_DEVICE_ID_TI_WL1271,
 		   add_quirk, MMC_QUIRK_NONSTD_FUNC_IF),

drivers/mmc/core/sdio.c+27−1

@@ -1048,9 +1048,35 @@ static int mmc_sdio_runtime_resume(struct mmc_host *host) · 1047 unmodified lines
1048	return ret;	1048	return ret;
1049	}	1049	}
1050		1050
		1051	/*
		1052	* SDIO HW reset
		1053	*
		1054	* Returns 0 if the HW reset was executed synchronously, returns 1 if the HW
		1055	* reset was asynchronously scheduled, else a negative error code.
		1056	*/
1051	static int mmc_sdio_hw_reset(struct mmc_host *host)	1057	static int mmc_sdio_hw_reset(struct mmc_host *host)
1052	{	1058	{
1053	mmc_power_cycle(host, host->card->ocr);	1059	struct mmc_card *card = host->card;
		1060
		1061	/*
		1062	* In case the card is shared among multiple func drivers, reset the
		1063	* card through a rescan work. In this way it will be removed and
		1064	* re-detected, thus all func drivers becomes informed about it.
		1065	*/
		1066	if (atomic_read(&card->sdio_funcs_probed) > 1) {
		1067	if (mmc_card_removed(card))
		1068	return 1;
		1069	host->rescan_entered = 0;
		1070	mmc_card_set_removed(card);
		1071	_mmc_detect_change(host, 0, false);
		1072	return 1;
		1073	}
		1074
		1075	/*
		1076	* A single func driver has been probed, then let's skip the heavy
		1077	* hotplug dance above and execute the reset immediately.
		1078	*/
		1079	mmc_power_cycle(host, card->ocr);
1054	return mmc_sdio_reinit_card(host);	1080	return mmc_sdio_reinit_card(host);
1055	}	1081	}
1056		1082

drivers/mmc/core/sdio_bus.c+8−1

 	if (ret)
 		return ret;
+	atomic_inc(&func->card->sdio_funcs_probed);
 	/* Unbound SDIO functions are always suspended.
 	 * During probe, the function is set active and the usage count
 	 * is incremented.  If the driver supports runtime PM,
 	/* Set the default block size so the driver is sure it's something
 	 * sensible. */
 	sdio_claim_host(func);
-	ret = sdio_set_block_size(func, 0);
+	if (mmc_card_removed(func->card))
+		ret = -ENOMEDIUM;
+	else
+		ret = sdio_set_block_size(func, 0);
 	sdio_release_host(func);
 	if (ret)
 		goto disable_runtimepm;
 	return 0;
 disable_runtimepm:
+	atomic_dec(&func->card->sdio_funcs_probed);
 	if (func->card->host->caps & MMC_CAP_POWER_OFF_CARD)
 		pm_runtime_put_noidle(dev);
 	dev_pm_domain_detach(dev, false);
 		pm_runtime_get_sync(dev);
 	drv->remove(func);
+	atomic_dec(&func->card->sdio_funcs_probed);
 	if (func->irq_handler) {
 		pr_warn("WARNING: driver %s did not remove its interrupt handler!\n",

drivers/mmc/host/Kconfig+21−0

 	tristate "SDHCI OF support for the ASPEED SDHCI controller"
 	depends on MMC_SDHCI_PLTFM
 	depends on OF && OF_ADDRESS
+	select MMC_SDHCI_IO_ACCESSORS
 	help
 	  This selects the ASPEED Secure Digital Host Controller Interface.
 	  If unsure, say N.
+config MMC_SDHCI_MILBEAUT
+	tristate "SDHCI support for Socionext Milbeaut Serieas using F_SDH30"
+	depends on MMC_SDHCI_PLTFM
+	depends on OF
+	help
+	  This selects the Secure Digital Host Controller Interface (SDHCI)
+	  Needed by Milbeaut SoC for MMC / SD / SDIO support.
+	  If you have a controller with this interface, say Y or M here.
+	  If unsure, say N.
 config MMC_SDHCI_IPROC
 	tristate "SDHCI support for the BCM2835 & iProc SD/MMC Controller"
 	depends on ARCH_BCM2835 || ARCH_BCM_IPROC || COMPILE_TEST
 	tristate "Support for the SDHCI Controller in TI's AM654 SOCs"
 	depends on MMC_SDHCI_PLTFM && OF && REGMAP_MMIO
 	select MMC_SDHCI_IO_ACCESSORS
+	select MMC_CQHCI
 	help
 	  This selects the Secure Digital Host Controller Interface (SDHCI)
 	  support present in TI's AM654 SOCs. The controller supports
 	  If you have a controller with this interface, say Y or M here.
 	  If unsure, say N.
+config MMC_OWL
+	tristate "Actions Semi Owl SD/MMC Host Controller support"
+	depends on HAS_DMA
+	depends on ARCH_ACTIONS || COMPILE_TEST
+	help
+	  This selects support for the SD/MMC Host Controller on
+	  Actions Semi Owl SoCs.

drivers/mmc/host/Makefile+2−0

 obj-$(CONFIG_MMC_SDHCI_S3C)	+= sdhci-s3c.o
 obj-$(CONFIG_MMC_SDHCI_SIRF)   	+= sdhci-sirf.o
 obj-$(CONFIG_MMC_SDHCI_F_SDH30)	+= sdhci_f_sdh30.o
+obj-$(CONFIG_MMC_SDHCI_MILBEAUT)	+= sdhci-milbeaut.o
 obj-$(CONFIG_MMC_SDHCI_SPEAR)	+= sdhci-spear.o
 obj-$(CONFIG_MMC_SDHCI_AM654)	+= sdhci_am654.o
 obj-$(CONFIG_MMC_WBSD)		+= wbsd.o
 obj-$(CONFIG_MMC_USDHI6ROL0)	+= usdhi6rol0.o
 obj-$(CONFIG_MMC_TOSHIBA_PCI)	+= toshsd.o
 obj-$(CONFIG_MMC_BCM2835)	+= bcm2835.o
+obj-$(CONFIG_MMC_OWL)		+= owl-mmc.o
 obj-$(CONFIG_MMC_REALTEK_PCI)	+= rtsx_pci_sdmmc.o
 obj-$(CONFIG_MMC_REALTEK_USB)	+= rtsx_usb_sdmmc.o

drivers/mmc/host/atmel-mci.c+1−2

@@ -2347,8 +2347,7 @@ static void atmci_cleanup_slot(struct atmel_mci_slot *slot, · 2346 unmodified lines
2347		2347
2348	static int atmci_configure_dma(struct atmel_mci *host)	2348	static int atmci_configure_dma(struct atmel_mci *host)
2349	{	2349	{
2350	host->dma.chan = dma_request_slave_channel_reason(&host->pdev->dev,	2350	host->dma.chan = dma_request_chan(&host->pdev->dev, "rxtx");
2351	"rxtx");
2352		2351
2353	if (PTR_ERR(host->dma.chan) == -ENODEV) {	2352	if (PTR_ERR(host->dma.chan) == -ENODEV) {
2354	struct mci_platform_data *pdata = host->pdev->dev.platform_data;	2353	struct mci_platform_data *pdata = host->pdev->dev.platform_data;

drivers/mmc/host/bcm2835.c+1−3

 {
 	struct device *dev = &pdev->dev;
 	struct clk *clk;
-	struct resource *iomem;
 	struct bcm2835_host *host;
 	struct mmc_host *mmc;
 	const __be32 *regaddr_p;
 	host->pdev = pdev;
 	spin_lock_init(&host->lock);
-	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	host->ioaddr = devm_platform_ioremap_resource(pdev, 0);
-	host->ioaddr = devm_ioremap_resource(dev, iomem);
 	if (IS_ERR(host->ioaddr)) {
 		ret = PTR_ERR(host->ioaddr);
 		goto err;

drivers/mmc/host/cavium-octeon.c+2−13

 {
 	struct device_node *cn, *node = pdev->dev.of_node;
 	struct cvm_mmc_host *host;
-	struct resource	*res;
 	void __iomem *base;
 	int mmc_irq[9];
 	int i, ret = 0;
 	host->last_slot = -1;
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	base = devm_platform_ioremap_resource(pdev, 0);
-	if (!res) {
-		dev_err(&pdev->dev, "Platform resource[0] is missing\n");
-		return -ENXIO;
-	}
-	base = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(base))
 		return PTR_ERR(base);
 	host->base = (void __iomem *)base;
 	host->reg_off = 0;
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	base = devm_platform_ioremap_resource(pdev, 1);
-	if (!res) {
-		dev_err(&pdev->dev, "Platform resource[1] is missing\n");
-		return -EINVAL;
-	}
-	base = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(base))
 		return PTR_ERR(base);
 	host->dma_base = (void __iomem *)base;

drivers/mmc/host/dw_mmc.c+2−2

@@ -3441,8 +3441,8 @@ int dw_mci_runtime_resume(struct device *dev) · 3440 unmodified lines
3441	* Restore the initial value at FIFOTH register	3441	* Restore the initial value at FIFOTH register
3442	* And Invalidate the prev_blksz with zero	3442	* And Invalidate the prev_blksz with zero
3443	*/	3443	*/
3444	mci_writel(host, FIFOTH, host->fifoth_val);	3444	mci_writel(host, FIFOTH, host->fifoth_val);
3445	host->prev_blksz = 0;	3445	host->prev_blksz = 0;
3446		3446
3447	/* Put in max timeout */	3447	/* Put in max timeout */
3448	mci_writel(host, TMOUT, 0xFFFFFFFF);	3448	mci_writel(host, TMOUT, 0xFFFFFFFF);

drivers/mmc/host/jz4740_mmc.c+38−3

 #define JZ_REG_MMC_RESP_FIFO	0x34
 #define JZ_REG_MMC_RXFIFO	0x38
 #define JZ_REG_MMC_TXFIFO	0x3C
+#define JZ_REG_MMC_LPM		0x40
 #define JZ_REG_MMC_DMAC		0x44
 #define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7)
 #define JZ_MMC_CMDAT_IO_ABORT BIT(11)
 #define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10)
+#define JZ_MMC_CMDAT_BUS_WIDTH_8BIT (BIT(10) | BIT(9))
+#define	JZ_MMC_CMDAT_BUS_WIDTH_MASK (BIT(10) | BIT(9))
 #define JZ_MMC_CMDAT_DMA_EN BIT(8)
 #define JZ_MMC_CMDAT_INIT BIT(7)
 #define JZ_MMC_CMDAT_BUSY BIT(6)
 #define JZ_MMC_DMAC_DMA_SEL BIT(1)
 #define JZ_MMC_DMAC_DMA_EN BIT(0)
+#define	JZ_MMC_LPM_DRV_RISING BIT(31)
+#define	JZ_MMC_LPM_DRV_RISING_QTR_PHASE_DLY BIT(31)
+#define	JZ_MMC_LPM_DRV_RISING_1NS_DLY BIT(30)
+#define	JZ_MMC_LPM_SMP_RISING_QTR_OR_HALF_PHASE_DLY BIT(29)
+#define	JZ_MMC_LPM_LOW_POWER_MODE_EN BIT(0)
 #define JZ_MMC_CLK_RATE 24000000
 enum jz4740_mmc_version {
 	JZ_MMC_JZ4740,
 	JZ_MMC_JZ4725B,
+	JZ_MMC_JZ4760,
 	JZ_MMC_JZ4780,
+	JZ_MMC_X1000,
 };
 enum jz4740_mmc_state {
 	}
 	writew(div, host->base + JZ_REG_MMC_CLKRT);
+	if (real_rate > 25000000) {
+		if (host->version >= JZ_MMC_X1000) {
+			writel(JZ_MMC_LPM_DRV_RISING_QTR_PHASE_DLY |
+				   JZ_MMC_LPM_SMP_RISING_QTR_OR_HALF_PHASE_DLY |
+				   JZ_MMC_LPM_LOW_POWER_MODE_EN,
+				   host->base + JZ_REG_MMC_LPM);
+		} else if (host->version >= JZ_MMC_JZ4760) {
+			writel(JZ_MMC_LPM_DRV_RISING |
+				   JZ_MMC_LPM_LOW_POWER_MODE_EN,
+				   host->base + JZ_REG_MMC_LPM);
+		} else if (host->version >= JZ_MMC_JZ4725B)
+			writel(JZ_MMC_LPM_LOW_POWER_MODE_EN,
+				   host->base + JZ_REG_MMC_LPM);
+	}
 	return real_rate;
 }
 	switch (ios->bus_width) {
 	case MMC_BUS_WIDTH_1:
-		host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
+		host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_MASK;
 		break;
 	case MMC_BUS_WIDTH_4:
+		host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_MASK;
 		host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
 		break;
+	case MMC_BUS_WIDTH_8:
+		host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_MASK;
+		host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_8BIT;
+		break;
 	default:
 		break;
 	}
 static const struct of_device_id jz4740_mmc_of_match[] = {
 	{ .compatible = "ingenic,jz4740-mmc", .data = (void *) JZ_MMC_JZ4740 },
 	{ .compatible = "ingenic,jz4725b-mmc", .data = (void *)JZ_MMC_JZ4725B },
+	{ .compatible = "ingenic,jz4760-mmc", .data = (void *) JZ_MMC_JZ4760 },
 	{ .compatible = "ingenic,jz4780-mmc", .data = (void *) JZ_MMC_JZ4780 },
+	{ .compatible = "ingenic,x1000-mmc", .data = (void *) JZ_MMC_X1000 },
 	{},
 };
 MODULE_DEVICE_TABLE(of, jz4740_mmc_of_match);
 		dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret);
 		goto err_release_dma;
 	}
-	dev_info(&pdev->dev, "JZ SD/MMC card driver registered\n");
+	dev_info(&pdev->dev, "Ingenic SD/MMC card driver registered\n");
 	dev_info(&pdev->dev, "Using %s, %d-bit mode\n",
 		 host->use_dma ? "DMA" : "PIO",
-		 (mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1);
+		 (mmc->caps & MMC_CAP_8_BIT_DATA) ? 8 :
+		 ((mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1));
 	return 0;

drivers/mmc/host/mmc_spi.c+1−1

@@ -1421,7 +1421,7 @@ static int mmc_spi_probe(struct spi_device *spi) · 1420 unmodified lines
1421	* Index 0 is card detect	1421	* Index 0 is card detect
1422	* Old boardfiles were specifying 1 ms as debounce	1422	* Old boardfiles were specifying 1 ms as debounce
1423	*/	1423	*/
1424	status = mmc_gpiod_request_cd(mmc, NULL, 0, false, 1, NULL);	1424	status = mmc_gpiod_request_cd(mmc, NULL, 0, false, 1000, NULL);
1425	if (status == -EPROBE_DEFER)	1425	if (status == -EPROBE_DEFER)
1426	goto fail_add_host;	1426	goto fail_add_host;
1427	if (!status) {	1427	if (!status) {

drivers/mmc/host/mmci.c+122−76

@@ -44,6 +44,7 @@ · 43 unmodified lines
44	#define DRIVER_NAME "mmci-pl18x"	44	#define DRIVER_NAME "mmci-pl18x"
45		45
46	static void mmci_variant_init(struct mmci_host *host);	46	static void mmci_variant_init(struct mmci_host *host);
		47	static void ux500_variant_init(struct mmci_host *host);
47	static void ux500v2_variant_init(struct mmci_host *host);	48	static void ux500v2_variant_init(struct mmci_host *host);
48		49
49	static unsigned int fmax = 515633;	50	static unsigned int fmax = 515633;
@@ -184,7 +185,7 @@ static struct variant_data variant_ux500 = { · 134 unmodified lines
184	.irq_pio_mask = MCI_IRQ_PIO_MASK,	185	.irq_pio_mask = MCI_IRQ_PIO_MASK,
185	.start_err = MCI_STARTBITERR,	186	.start_err = MCI_STARTBITERR,
186	.opendrain = MCI_OD,	187	.opendrain = MCI_OD,
187	.init = mmci_variant_init,	188	.init = ux500_variant_init,
188	};	189	};
189		190
190	static struct variant_data variant_ux500v2 = {	191	static struct variant_data variant_ux500v2 = {
@@ -261,6 +262,10 @@ static struct variant_data variant_stm32_sdmmc = { · 70 unmodified lines
261	.datalength_bits = 25,	262	.datalength_bits = 25,
262	.datactrl_blocksz = 14,	263	.datactrl_blocksz = 14,
263	.stm32_idmabsize_mask = GENMASK(12, 5),	264	.stm32_idmabsize_mask = GENMASK(12, 5),
		265	.busy_timeout = true,
		266	.busy_detect = true,
		267	.busy_detect_flag = MCI_STM32_BUSYD0,
		268	.busy_detect_mask = MCI_STM32_BUSYD0ENDMASK,
264	.init = sdmmc_variant_init,	269	.init = sdmmc_variant_init,
265	};	270	};
266		271
@@ -419,7 +424,7 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) · 152 unmodified lines
419	mmci_write_clkreg(host, clk);	424	mmci_write_clkreg(host, clk);
420	}	425	}
421		426
422	void mmci_dma_release(struct mmci_host *host)	427	static void mmci_dma_release(struct mmci_host *host)
423	{	428	{
424	if (host->ops && host->ops->dma_release)	429	if (host->ops && host->ops->dma_release)
425	host->ops->dma_release(host);	430	host->ops->dma_release(host);
@@ -427,7 +432,7 @@ void mmci_dma_release(struct mmci_host *host) · 1 unmodified line
427	host->use_dma = false;	432	host->use_dma = false;
428	}	433	}
429		434
430	void mmci_dma_setup(struct mmci_host *host)	435	static void mmci_dma_setup(struct mmci_host *host)
431	{	436	{
432	if (!host->ops \|\| !host->ops->dma_setup)	437	if (!host->ops \|\| !host->ops->dma_setup)
433	return;	438	return;
@@ -462,7 +467,7 @@ static int mmci_validate_data(struct mmci_host *host, · 28 unmodified lines
462	return 0;	467	return 0;
463	}	468	}
464		469
465	int mmci_prep_data(struct mmci_host host, struct mmc_data data, bool next)	470	static int mmci_prep_data(struct mmci_host host, struct mmc_data data, bool next)
466	{	471	{
467	int err;	472	int err;
468		473
@@ -478,7 +483,7 @@ int mmci_prep_data(struct mmci_host host, struct mmc_data data, bool next) · 9 unmodified lines
478	return err;	483	return err;
479	}	484	}
480		485
481	void mmci_unprep_data(struct mmci_host host, struct mmc_data data,	486	static void mmci_unprep_data(struct mmci_host host, struct mmc_data data,
482	int err)	487	int err)
483	{	488	{
484	if (host->ops && host->ops->unprep_data)	489	if (host->ops && host->ops->unprep_data)
@@ -487,7 +492,7 @@ void mmci_unprep_data(struct mmci_host host, struct mmc_data data, · 2 unmodified lines
487	data->host_cookie = 0;	492	data->host_cookie = 0;
488	}	493	}
489		494
490	void mmci_get_next_data(struct mmci_host host, struct mmc_data data)	495	static void mmci_get_next_data(struct mmci_host host, struct mmc_data data)
491	{	496	{
492	WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie);	497	WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie);
493		498
@@ -495,7 +500,7 @@ void mmci_get_next_data(struct mmci_host host, struct mmc_data data) · 1 unmodified line
495	host->ops->get_next_data(host, data);	500	host->ops->get_next_data(host, data);
496	}	501	}
497		502
498	int mmci_dma_start(struct mmci_host *host, unsigned int datactrl)	503	static int mmci_dma_start(struct mmci_host *host, unsigned int datactrl)
499	{	504	{
500	struct mmc_data *data = host->data;	505	struct mmc_data *data = host->data;
501	int ret;	506	int ret;
@@ -530,7 +535,7 @@ int mmci_dma_start(struct mmci_host *host, unsigned int datactrl) · 28 unmodified lines
530	return 0;	535	return 0;
531	}	536	}
532		537
533	void mmci_dma_finalize(struct mmci_host host, struct mmc_data data)	538	static void mmci_dma_finalize(struct mmci_host host, struct mmc_data data)
534	{	539	{
535	if (!host->use_dma)	540	if (!host->use_dma)
536	return;	541	return;
@@ -539,7 +544,7 @@ void mmci_dma_finalize(struct mmci_host host, struct mmc_data data) · 2 unmodified lines
539	host->ops->dma_finalize(host, data);	544	host->ops->dma_finalize(host, data);
540	}	545	}
541		546
542	void mmci_dma_error(struct mmci_host *host)	547	static void mmci_dma_error(struct mmci_host *host)
543	{	548	{
544	if (!host->use_dma)	549	if (!host->use_dma)
545	return;	550	return;
@@ -610,6 +615,67 @@ static u32 ux500v2_get_dctrl_cfg(struct mmci_host *host) · 64 unmodified lines
610	return MCI_DPSM_ENABLE \| (host->data->blksz << 16);	615	return MCI_DPSM_ENABLE \| (host->data->blksz << 16);
611	}	616	}
612		617
		618	static bool ux500_busy_complete(struct mmci_host *host, u32 status, u32 err_msk)
		619	{
		620	void __iomem *base = host->base;
		621
		622	/*
		623	* Before unmasking for the busy end IRQ, confirm that the
		624	* command was sent successfully. To keep track of having a
		625	* command in-progress, waiting for busy signaling to end,
		626	* store the status in host->busy_status.
		627	*
		628	* Note that, the card may need a couple of clock cycles before
		629	* it starts signaling busy on DAT0, hence re-read the
		630	* MMCISTATUS register here, to allow the busy bit to be set.
		631	* Potentially we may even need to poll the register for a
		632	* while, to allow it to be set, but tests indicates that it
		633	* isn't needed.
		634	*/
		635	if (!host->busy_status && !(status & err_msk) &&
		636	(readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) {
		637	writel(readl(base + MMCIMASK0) \|
		638	host->variant->busy_detect_mask,
		639	base + MMCIMASK0);
		640
		641	host->busy_status = status & (MCI_CMDSENT \| MCI_CMDRESPEND);
		642	return false;
		643	}
		644
		645	/*
		646	* If there is a command in-progress that has been successfully
		647	* sent, then bail out if busy status is set and wait for the
		648	* busy end IRQ.
		649	*
		650	* Note that, the HW triggers an IRQ on both edges while
		651	* monitoring DAT0 for busy completion, but there is only one
		652	* status bit in MMCISTATUS for the busy state. Therefore
		653	* both the start and the end interrupts needs to be cleared,
		654	* one after the other. So, clear the busy start IRQ here.
		655	*/
		656	if (host->busy_status &&
		657	(status & host->variant->busy_detect_flag)) {
		658	writel(host->variant->busy_detect_mask, base + MMCICLEAR);
		659	return false;
		660	}
		661
		662	/*
		663	* If there is a command in-progress that has been successfully
		664	* sent and the busy bit isn't set, it means we have received
		665	* the busy end IRQ. Clear and mask the IRQ, then continue to
		666	* process the command.
		667	*/
		668	if (host->busy_status) {
		669	writel(host->variant->busy_detect_mask, base + MMCICLEAR);
		670
		671	writel(readl(base + MMCIMASK0) &
		672	~host->variant->busy_detect_mask, base + MMCIMASK0);
		673	host->busy_status = 0;
		674	}
		675
		676	return true;
		677	}
		678
613	/*	679	/*
614	* All the DMA operation mode stuff goes inside this ifdef.	680	* All the DMA operation mode stuff goes inside this ifdef.
615	* This assumes that you have a generic DMA device interface,	681	* This assumes that you have a generic DMA device interface,
@@ -948,14 +1014,21 @@ static struct mmci_host_ops mmci_variant_ops = { · 332 unmodified lines
948	};	1014	};
949	#endif	1015	#endif
950		1016
951	void mmci_variant_init(struct mmci_host *host)	1017	static void mmci_variant_init(struct mmci_host *host)
		1018	{
		1019	host->ops = &mmci_variant_ops;
		1020	}
		1021
		1022	static void ux500_variant_init(struct mmci_host *host)
952	{	1023	{
953	host->ops = &mmci_variant_ops;	1024	host->ops = &mmci_variant_ops;
		1025	host->ops->busy_complete = ux500_busy_complete;
954	}	1026	}
955		1027
956	void ux500v2_variant_init(struct mmci_host *host)	1028	static void ux500v2_variant_init(struct mmci_host *host)
957	{	1029	{
958	host->ops = &mmci_variant_ops;	1030	host->ops = &mmci_variant_ops;
		1031	host->ops->busy_complete = ux500_busy_complete;
959	host->ops->get_datactrl_cfg = ux500v2_get_dctrl_cfg;	1032	host->ops->get_datactrl_cfg = ux500v2_get_dctrl_cfg;
960	}	1033	}
961		1034
@@ -1075,6 +1148,7 @@ static void · 113 unmodified lines
1075	mmci_start_command(struct mmci_host host, struct mmc_command cmd, u32 c)	1148	mmci_start_command(struct mmci_host host, struct mmc_command cmd, u32 c)
1076	{	1149	{
1077	void __iomem *base = host->base;	1150	void __iomem *base = host->base;
		1151	unsigned long long clks;
1078		1152
1079	dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",	1153	dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
1080	cmd->opcode, cmd->arg, cmd->flags);	1154	cmd->opcode, cmd->arg, cmd->flags);
@@ -1097,6 +1171,16 @@ mmci_start_command(struct mmci_host host, struct mmc_command cmd, u32 c) · 16 unmodified lines
1097	else	1171	else
1098	c \|= host->variant->cmdreg_srsp;	1172	c \|= host->variant->cmdreg_srsp;
1099	}	1173	}
		1174
		1175	if (host->variant->busy_timeout && cmd->flags & MMC_RSP_BUSY) {
		1176	if (!cmd->busy_timeout)
		1177	cmd->busy_timeout = 10 * MSEC_PER_SEC;
		1178
		1179	clks = (unsigned long long)cmd->busy_timeout * host->cclk;
		1180	do_div(clks, MSEC_PER_SEC);
		1181	writel_relaxed(clks, host->base + MMCIDATATIMER);
		1182	}
		1183
1100	if (/interrupt/0)	1184	if (/interrupt/0)
1101	c \|= MCI_CPSM_INTERRUPT;	1185	c \|= MCI_CPSM_INTERRUPT;
1102		1186
@@ -1201,6 +1285,7 @@ static void · 98 unmodified lines
1201	mmci_cmd_irq(struct mmci_host host, struct mmc_command cmd,	1285	mmci_cmd_irq(struct mmci_host host, struct mmc_command cmd,
1202	unsigned int status)	1286	unsigned int status)
1203	{	1287	{
		1288	u32 err_msk = MCI_CMDCRCFAIL \| MCI_CMDTIMEOUT;
1204	void __iomem *base = host->base;	1289	void __iomem *base = host->base;
1205	bool sbc, busy_resp;	1290	bool sbc, busy_resp;
1206		1291
@@ -1215,74 +1300,17 @@ mmci_cmd_irq(struct mmci_host host, struct mmc_command cmd, · 8 unmodified lines
1215	* handling. Note that we tag on any latent IRQs postponed	1300	* handling. Note that we tag on any latent IRQs postponed
1216	* due to waiting for busy status.	1301	* due to waiting for busy status.
1217	*/	1302	*/
1218	if (!((status\|host->busy_status) &	1303	if (host->variant->busy_timeout && busy_resp)
1219	(MCI_CMDCRCFAIL\|MCI_CMDTIMEOUT\|MCI_CMDSENT\|MCI_CMDRESPEND)))	1304	err_msk \|= MCI_DATATIMEOUT;
		1305
		1306	if (!((status \| host->busy_status) &
		1307	(err_msk \| MCI_CMDSENT \| MCI_CMDRESPEND)))
1220	return;	1308	return;
1221		1309
1222	/* Handle busy detection on DAT0 if the variant supports it. */	1310	/* Handle busy detection on DAT0 if the variant supports it. */
1223	if (busy_resp && host->variant->busy_detect) {	1311	if (busy_resp && host->variant->busy_detect)
1224		1312	if (!host->ops->busy_complete(host, status, err_msk))
1225	/*
1226	* Before unmasking for the busy end IRQ, confirm that the
1227	* command was sent successfully. To keep track of having a
1228	* command in-progress, waiting for busy signaling to end,
1229	* store the status in host->busy_status.
1230	*
1231	* Note that, the card may need a couple of clock cycles before
1232	* it starts signaling busy on DAT0, hence re-read the
1233	* MMCISTATUS register here, to allow the busy bit to be set.
1234	* Potentially we may even need to poll the register for a
1235	* while, to allow it to be set, but tests indicates that it
1236	* isn't needed.
1237	*/
1238	if (!host->busy_status &&
1239	!(status & (MCI_CMDCRCFAIL\|MCI_CMDTIMEOUT)) &&
1240	(readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) {
1241
1242	writel(readl(base + MMCIMASK0) \|
1243	host->variant->busy_detect_mask,
1244	base + MMCIMASK0);
1245
1246	host->busy_status =
1247	status & (MCI_CMDSENT\|MCI_CMDRESPEND);
1248	return;
1249	}
1250
1251	/*
1252	* If there is a command in-progress that has been successfully
1253	* sent, then bail out if busy status is set and wait for the
1254	* busy end IRQ.
1255	*
1256	* Note that, the HW triggers an IRQ on both edges while
1257	* monitoring DAT0 for busy completion, but there is only one
1258	* status bit in MMCISTATUS for the busy state. Therefore
1259	* both the start and the end interrupts needs to be cleared,
1260	* one after the other. So, clear the busy start IRQ here.
1261	*/
1262	if (host->busy_status &&
1263	(status & host->variant->busy_detect_flag)) {
1264	writel(host->variant->busy_detect_mask,
1265	host->base + MMCICLEAR);
1266	return;	1313	return;
1267	}
1268
1269	/*
1270	* If there is a command in-progress that has been successfully
1271	* sent and the busy bit isn't set, it means we have received
1272	* the busy end IRQ. Clear and mask the IRQ, then continue to
1273	* process the command.
1274	*/
1275	if (host->busy_status) {
1276
1277	writel(host->variant->busy_detect_mask,
1278	host->base + MMCICLEAR);
1279
1280	writel(readl(base + MMCIMASK0) &
1281	~host->variant->busy_detect_mask,
1282	base + MMCIMASK0);
1283	host->busy_status = 0;
1284	}
1285	}
1286		1314
1287	host->cmd = NULL;	1315	host->cmd = NULL;
1288		1316
@@ -1290,6 +1318,9 @@ mmci_cmd_irq(struct mmci_host host, struct mmc_command cmd, · 1 unmodified line
1290	cmd->error = -ETIMEDOUT;	1318	cmd->error = -ETIMEDOUT;
1291	} else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {	1319	} else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
1292	cmd->error = -EILSEQ;	1320	cmd->error = -EILSEQ;
		1321	} else if (host->variant->busy_timeout && busy_resp &&
		1322	status & MCI_DATATIMEOUT) {
		1323	cmd->error = -ETIMEDOUT;
1293	} else {	1324	} else {
1294	cmd->resp[0] = readl(base + MMCIRESPONSE0);	1325	cmd->resp[0] = readl(base + MMCIRESPONSE0);
1295	cmd->resp[1] = readl(base + MMCIRESPONSE1);	1326	cmd->resp[1] = readl(base + MMCIRESPONSE1);
@@ -1583,6 +1614,20 @@ static void mmci_request(struct mmc_host mmc, struct mmc_request mrq) · 287 unmodified lines
1583	spin_unlock_irqrestore(&host->lock, flags);	1614	spin_unlock_irqrestore(&host->lock, flags);
1584	}	1615	}
1585		1616
		1617	static void mmci_set_max_busy_timeout(struct mmc_host *mmc)
		1618	{
		1619	struct mmci_host *host = mmc_priv(mmc);
		1620	u32 max_busy_timeout = 0;
		1621
		1622	if (!host->variant->busy_detect)
		1623	return;
		1624
		1625	if (host->variant->busy_timeout && mmc->actual_clock)
		1626	max_busy_timeout = ~0UL / (mmc->actual_clock / MSEC_PER_SEC);
		1627
		1628	mmc->max_busy_timeout = max_busy_timeout;
		1629	}
		1630
1586	static void mmci_set_ios(struct mmc_host mmc, struct mmc_ios ios)	1631	static void mmci_set_ios(struct mmc_host mmc, struct mmc_ios ios)
1587	{	1632	{
1588	struct mmci_host *host = mmc_priv(mmc);	1633	struct mmci_host *host = mmc_priv(mmc);
@@ -1687,6 +1732,8 @@ static void mmci_set_ios(struct mmc_host mmc, struct mmc_ios ios) · 98 unmodified lines
1687	else	1732	else
1688	mmci_set_clkreg(host, ios->clock);	1733	mmci_set_clkreg(host, ios->clock);
1689		1734
		1735	mmci_set_max_busy_timeout(mmc);
		1736
1690	if (host->ops && host->ops->set_pwrreg)	1737	if (host->ops && host->ops->set_pwrreg)
1691	host->ops->set_pwrreg(host, pwr);	1738	host->ops->set_pwrreg(host, pwr);
1692	else	1739	else
@@ -1957,7 +2004,6 @@ static int mmci_probe(struct amba_device *dev, · 264 unmodified lines
1957	mmci_write_datactrlreg(host,	2004	mmci_write_datactrlreg(host,
1958	host->variant->busy_dpsm_flag);	2005	host->variant->busy_dpsm_flag);
1959	mmc->caps \|= MMC_CAP_WAIT_WHILE_BUSY;	2006	mmc->caps \|= MMC_CAP_WAIT_WHILE_BUSY;
1960	mmc->max_busy_timeout = 0;
1961	}	2007	}
1962		2008
1963	/* Prepare a CMD12 - needed to clear the DPSM on some variants. */	2009	/* Prepare a CMD12 - needed to clear the DPSM on some variants. */

drivers/mmc/host/mmci.h+5−0

 #define MCI_ST_CARDBUSY		(1 << 24)
 /* Extended status bits for the STM32 variants */
 #define MCI_STM32_BUSYD0	BIT(20)
+#define MCI_STM32_BUSYD0END	BIT(21)
 #define MMCICLEAR		0x038
 #define MCI_CMDCRCFAILCLR	(1 << 0)
  * @signal_direction: input/out direction of bus signals can be indicated
  * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
  * @busy_detect: true if the variant supports busy detection on DAT0.
+ * @busy_timeout: true if the variant starts data timer when the DPSM
+ *		  enter in Wait_R or Busy state.
  * @busy_dpsm_flag: bitmask enabling busy detection in the DPSM
  * @busy_detect_flag: bitmask identifying the bit in the MMCISTATUS register
  *		      indicating that the card is busy
 	u8			signal_direction:1;
 	u8			pwrreg_clkgate:1;
 	u8			busy_detect:1;
+	u8			busy_timeout:1;
 	u32			busy_dpsm_flag;
 	u32			busy_detect_flag;
 	u32			busy_detect_mask;
 	void (*dma_error)(struct mmci_host *host);
 	void (*set_clkreg)(struct mmci_host *host, unsigned int desired);
 	void (*set_pwrreg)(struct mmci_host *host, unsigned int pwr);
+	bool (*busy_complete)(struct mmci_host *host, u32 status, u32 err_msk);
 };
 struct mmci_host {

drivers/mmc/host/mmci_stm32_sdmmc.c+44−2

@@ -25,8 +25,8 @@ struct sdmmc_priv { · 24 unmodified lines
25	void *sg_cpu;	25	void *sg_cpu;
26	};	26	};
27		27
28	int sdmmc_idma_validate_data(struct mmci_host *host,	28	static int sdmmc_idma_validate_data(struct mmci_host *host,
29	struct mmc_data *data)	29	struct mmc_data *data)
30	{	30	{
31	struct scatterlist *sg;	31	struct scatterlist *sg;
32	int i;	32	int i;
@@ -282,6 +282,47 @@ static u32 sdmmc_get_dctrl_cfg(struct mmci_host *host) · 249 unmodified lines
282	return datactrl;	282	return datactrl;
283	}	283	}
284		284
		285	static bool sdmmc_busy_complete(struct mmci_host *host, u32 status, u32 err_msk)
		286	{
		287	void __iomem *base = host->base;
		288	u32 busy_d0, busy_d0end, mask, sdmmc_status;
		289
		290	mask = readl_relaxed(base + MMCIMASK0);
		291	sdmmc_status = readl_relaxed(base + MMCISTATUS);
		292	busy_d0end = sdmmc_status & MCI_STM32_BUSYD0END;
		293	busy_d0 = sdmmc_status & MCI_STM32_BUSYD0;
		294
		295	/* complete if there is an error or busy_d0end */
		296	if ((status & err_msk) \|\| busy_d0end)
		297	goto complete;
		298
		299	/*
		300	* On response the busy signaling is reflected in the BUSYD0 flag.
		301	* if busy_d0 is in-progress we must activate busyd0end interrupt
		302	* to wait this completion. Else this request has no busy step.
		303	*/
		304	if (busy_d0) {
		305	if (!host->busy_status) {
		306	writel_relaxed(mask \| host->variant->busy_detect_mask,
		307	base + MMCIMASK0);
		308	host->busy_status = status &
		309	(MCI_CMDSENT \| MCI_CMDRESPEND);
		310	}
		311	return false;
		312	}
		313
		314	complete:
		315	if (host->busy_status) {
		316	writel_relaxed(mask & ~host->variant->busy_detect_mask,
		317	base + MMCIMASK0);
		318	writel_relaxed(host->variant->busy_detect_mask,
		319	base + MMCICLEAR);
		320	host->busy_status = 0;
		321	}
		322
		323	return true;
		324	}
		325
285	static struct mmci_host_ops sdmmc_variant_ops = {	326	static struct mmci_host_ops sdmmc_variant_ops = {
286	.validate_data = sdmmc_idma_validate_data,	327	.validate_data = sdmmc_idma_validate_data,
287	.prep_data = sdmmc_idma_prep_data,	328	.prep_data = sdmmc_idma_prep_data,
@@ -292,6 +333,7 @@ static struct mmci_host_ops sdmmc_variant_ops = { · 4 unmodified lines
292	.dma_finalize = sdmmc_idma_finalize,	333	.dma_finalize = sdmmc_idma_finalize,
293	.set_clkreg = mmci_sdmmc_set_clkreg,	334	.set_clkreg = mmci_sdmmc_set_clkreg,
294	.set_pwrreg = mmci_sdmmc_set_pwrreg,	335	.set_pwrreg = mmci_sdmmc_set_pwrreg,
		336	.busy_complete = sdmmc_busy_complete,
295	};	337	};
296		338
297	void sdmmc_variant_init(struct mmci_host *host)	339	void sdmmc_variant_init(struct mmci_host *host)

drivers/mmc/host/moxart-mmc.c+2−2

@@ -608,8 +608,8 @@ static int moxart_probe(struct platform_device *pdev) · 607 unmodified lines
608	host->timeout = msecs_to_jiffies(1000);	608	host->timeout = msecs_to_jiffies(1000);
609	host->sysclk = clk_get_rate(clk);	609	host->sysclk = clk_get_rate(clk);
610	host->fifo_width = readl(host->base + REG_FEATURE) << 2;	610	host->fifo_width = readl(host->base + REG_FEATURE) << 2;
611	host->dma_chan_tx = dma_request_slave_channel_reason(dev, "tx");	611	host->dma_chan_tx = dma_request_chan(dev, "tx");
612	host->dma_chan_rx = dma_request_slave_channel_reason(dev, "rx");	612	host->dma_chan_rx = dma_request_chan(dev, "rx");
613		613
614	spin_lock_init(&host->lock);	614	spin_lock_init(&host->lock);
615		615

drivers/mmc/host/omap_hsmmc.c+29−2

@@ -1510,8 +1510,35 @@ static void omap_hsmmc_init_card(struct mmc_host mmc, struct mmc_card card) · 1509 unmodified lines
1510	{	1510	{
1511	struct omap_hsmmc_host *host = mmc_priv(mmc);	1511	struct omap_hsmmc_host *host = mmc_priv(mmc);
1512		1512
1513	if (mmc_pdata(host)->init_card)	1513	if (card->type == MMC_TYPE_SDIO \|\| card->type == MMC_TYPE_SD_COMBO) {
1514	mmc_pdata(host)->init_card(card);	1514	struct device_node *np = mmc_dev(mmc)->of_node;
		1515
		1516	/*
		1517	* REVISIT: should be moved to sdio core and made more
		1518	* general e.g. by expanding the DT bindings of child nodes
		1519	* to provide a mechanism to provide this information:
		1520	* Documentation/devicetree/bindings/mmc/mmc-card.txt
		1521	*/
		1522
		1523	np = of_get_compatible_child(np, "ti,wl1251");
		1524	if (np) {
		1525	/*
		1526	* We have TI wl1251 attached to MMC3. Pass this
		1527	* information to the SDIO core because it can't be
		1528	* probed by normal methods.
		1529	*/
		1530
		1531	dev_info(host->dev, "found wl1251\n");
		1532	card->quirks \|= MMC_QUIRK_NONSTD_SDIO;
		1533	card->cccr.wide_bus = 1;
		1534	card->cis.vendor = 0x104c;
		1535	card->cis.device = 0x9066;
		1536	card->cis.blksize = 512;
		1537	card->cis.max_dtr = 24000000;
		1538	card->ocr = 0x80;
		1539	of_node_put(np);
		1540	}
		1541	}
1515	}	1542	}
1516		1543
1517	static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)	1544	static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)

drivers/mmc/host/owl-mmc.c+696−0

@@ -0,0 +1,696 @@
	1	// SPDX-License-Identifier: GPL-2.0-or-later
	2	/*
	3	* Actions Semi Owl SoCs SD/MMC driver
	4	*
	5	* Copyright (c) 2014 Actions Semi Inc.
	6	* Copyright (c) 2019 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
	7	*
	8	* TODO: SDIO support
	9	*/
	10
	11	#include <linux/clk.h>
	12	#include <linux/delay.h>
	13	#include <linux/dmaengine.h>
	14	#include <linux/dma-direction.h>
	15	#include <linux/dma-mapping.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/mmc/host.h>
	18	#include <linux/mmc/slot-gpio.h>
	19	#include <linux/module.h>
	20	#include <linux/of_platform.h>
	21	#include <linux/reset.h>
	22	#include <linux/spinlock.h>
	23
	24	/*
	25	* SDC registers
	26	*/
	27	#define OWL_REG_SD_EN 0x0000
	28	#define OWL_REG_SD_CTL 0x0004
	29	#define OWL_REG_SD_STATE 0x0008
	30	#define OWL_REG_SD_CMD 0x000c
	31	#define OWL_REG_SD_ARG 0x0010
	32	#define OWL_REG_SD_RSPBUF0 0x0014
	33	#define OWL_REG_SD_RSPBUF1 0x0018
	34	#define OWL_REG_SD_RSPBUF2 0x001c
	35	#define OWL_REG_SD_RSPBUF3 0x0020
	36	#define OWL_REG_SD_RSPBUF4 0x0024
	37	#define OWL_REG_SD_DAT 0x0028
	38	#define OWL_REG_SD_BLK_SIZE 0x002c
	39	#define OWL_REG_SD_BLK_NUM 0x0030
	40	#define OWL_REG_SD_BUF_SIZE 0x0034
	41
	42	/* SD_EN Bits */
	43	#define OWL_SD_EN_RANE BIT(31)
	44	#define OWL_SD_EN_RAN_SEED(x) (((x) & 0x3f) << 24)
	45	#define OWL_SD_EN_S18EN BIT(12)
	46	#define OWL_SD_EN_RESE BIT(10)
	47	#define OWL_SD_EN_DAT1_S BIT(9)
	48	#define OWL_SD_EN_CLK_S BIT(8)
	49	#define OWL_SD_ENABLE BIT(7)
	50	#define OWL_SD_EN_BSEL BIT(6)
	51	#define OWL_SD_EN_SDIOEN BIT(3)
	52	#define OWL_SD_EN_DDREN BIT(2)
	53	#define OWL_SD_EN_DATAWID(x) (((x) & 0x3) << 0)
	54
	55	/* SD_CTL Bits */
	56	#define OWL_SD_CTL_TOUTEN BIT(31)
	57	#define OWL_SD_CTL_TOUTCNT(x) (((x) & 0x7f) << 24)
	58	#define OWL_SD_CTL_DELAY_MSK GENMASK(23, 16)
	59	#define OWL_SD_CTL_RDELAY(x) (((x) & 0xf) << 20)
	60	#define OWL_SD_CTL_WDELAY(x) (((x) & 0xf) << 16)
	61	#define OWL_SD_CTL_CMDLEN BIT(13)
	62	#define OWL_SD_CTL_SCC BIT(12)
	63	#define OWL_SD_CTL_TCN(x) (((x) & 0xf) << 8)
	64	#define OWL_SD_CTL_TS BIT(7)
	65	#define OWL_SD_CTL_LBE BIT(6)
	66	#define OWL_SD_CTL_C7EN BIT(5)
	67	#define OWL_SD_CTL_TM(x) (((x) & 0xf) << 0)
	68
	69	#define OWL_SD_DELAY_LOW_CLK 0x0f
	70	#define OWL_SD_DELAY_MID_CLK 0x0a
	71	#define OWL_SD_DELAY_HIGH_CLK 0x09
	72	#define OWL_SD_RDELAY_DDR50 0x0a
	73	#define OWL_SD_WDELAY_DDR50 0x08
	74
	75	/* SD_STATE Bits */
	76	#define OWL_SD_STATE_DAT1BS BIT(18)
	77	#define OWL_SD_STATE_SDIOB_P BIT(17)
	78	#define OWL_SD_STATE_SDIOB_EN BIT(16)
	79	#define OWL_SD_STATE_TOUTE BIT(15)
	80	#define OWL_SD_STATE_BAEP BIT(14)
	81	#define OWL_SD_STATE_MEMRDY BIT(12)
	82	#define OWL_SD_STATE_CMDS BIT(11)
	83	#define OWL_SD_STATE_DAT1AS BIT(10)
	84	#define OWL_SD_STATE_SDIOA_P BIT(9)
	85	#define OWL_SD_STATE_SDIOA_EN BIT(8)
	86	#define OWL_SD_STATE_DAT0S BIT(7)
	87	#define OWL_SD_STATE_TEIE BIT(6)
	88	#define OWL_SD_STATE_TEI BIT(5)
	89	#define OWL_SD_STATE_CLNR BIT(4)
	90	#define OWL_SD_STATE_CLC BIT(3)
	91	#define OWL_SD_STATE_WC16ER BIT(2)
	92	#define OWL_SD_STATE_RC16ER BIT(1)
	93	#define OWL_SD_STATE_CRC7ER BIT(0)
	94
	95	struct owl_mmc_host {
	96	struct device *dev;
	97	struct reset_control *reset;
	98	void __iomem *base;
	99	struct clk *clk;
	100	struct completion sdc_complete;
	101	spinlock_t lock;
	102	int irq;
	103	u32 clock;
	104	bool ddr_50;
	105
	106	enum dma_data_direction dma_dir;
	107	struct dma_chan *dma;
	108	struct dma_async_tx_descriptor *desc;
	109	struct dma_slave_config dma_cfg;
	110	struct completion dma_complete;
	111
	112	struct mmc_host *mmc;
	113	struct mmc_request *mrq;
	114	struct mmc_command *cmd;
	115	struct mmc_data *data;
	116	};
	117
	118	static void owl_mmc_update_reg(void __iomem *reg, unsigned int val, bool state)
	119	{
	120	unsigned int regval;
	121
	122	regval = readl(reg);
	123
	124	if (state)
	125	regval \|= val;
	126	else
	127	regval &= ~val;
	128
	129	writel(regval, reg);
	130	}
	131
	132	static irqreturn_t owl_irq_handler(int irq, void *devid)
	133	{
	134	struct owl_mmc_host *owl_host = devid;
	135	unsigned long flags;
	136	u32 state;
	137
	138	spin_lock_irqsave(&owl_host->lock, flags);
	139
	140	state = readl(owl_host->base + OWL_REG_SD_STATE);
	141	if (state & OWL_SD_STATE_TEI) {
	142	state = readl(owl_host->base + OWL_REG_SD_STATE);
	143	state \|= OWL_SD_STATE_TEI;
	144	writel(state, owl_host->base + OWL_REG_SD_STATE);
	145	complete(&owl_host->sdc_complete);
	146	}
	147
	148	spin_unlock_irqrestore(&owl_host->lock, flags);
	149
	150	return IRQ_HANDLED;
	151	}
	152
	153	static void owl_mmc_finish_request(struct owl_mmc_host *owl_host)
	154	{
	155	struct mmc_request *mrq = owl_host->mrq;
	156	struct mmc_data *data = mrq->data;
	157
	158	/* Should never be NULL */
	159	WARN_ON(!mrq);
	160
	161	owl_host->mrq = NULL;
	162
	163	if (data)
	164	dma_unmap_sg(owl_host->dma->device->dev, data->sg, data->sg_len,
	165	owl_host->dma_dir);
	166
	167	/* Finally finish request */
	168	mmc_request_done(owl_host->mmc, mrq);
	169	}
	170
	171	static void owl_mmc_send_cmd(struct owl_mmc_host *owl_host,
	172	struct mmc_command *cmd,
	173	struct mmc_data *data)
	174	{
	175	u32 mode, state, resp[2];
	176	u32 cmd_rsp_mask = 0;
	177
	178	init_completion(&owl_host->sdc_complete);
	179
	180	switch (mmc_resp_type(cmd)) {
	181	case MMC_RSP_NONE:
	182	mode = OWL_SD_CTL_TM(0);
	183	break;
	184
	185	case MMC_RSP_R1:
	186	if (data) {
	187	if (data->flags & MMC_DATA_READ)
	188	mode = OWL_SD_CTL_TM(4);
	189	else
	190	mode = OWL_SD_CTL_TM(5);
	191	} else {
	192	mode = OWL_SD_CTL_TM(1);
	193	}
	194	cmd_rsp_mask = OWL_SD_STATE_CLNR \| OWL_SD_STATE_CRC7ER;
	195
	196	break;
	197
	198	case MMC_RSP_R1B:
	199	mode = OWL_SD_CTL_TM(3);
	200	cmd_rsp_mask = OWL_SD_STATE_CLNR \| OWL_SD_STATE_CRC7ER;
	201	break;
	202
	203	case MMC_RSP_R2:
	204	mode = OWL_SD_CTL_TM(2);
	205	cmd_rsp_mask = OWL_SD_STATE_CLNR \| OWL_SD_STATE_CRC7ER;
	206	break;
	207
	208	case MMC_RSP_R3:
	209	mode = OWL_SD_CTL_TM(1);
	210	cmd_rsp_mask = OWL_SD_STATE_CLNR;
	211	break;
	212
	213	default:
	214	dev_warn(owl_host->dev, "Unknown MMC command\n");
	215	cmd->error = -EINVAL;
	216	return;
	217	}
	218
	219	/* Keep current WDELAY and RDELAY */
	220	mode \|= (readl(owl_host->base + OWL_REG_SD_CTL) & (0xff << 16));
	221
	222	/* Start to send corresponding command type */
	223	writel(cmd->arg, owl_host->base + OWL_REG_SD_ARG);
	224	writel(cmd->opcode, owl_host->base + OWL_REG_SD_CMD);
	225
	226	/* Set LBE to send clk at the end of last read block */
	227	if (data) {
	228	mode \|= (OWL_SD_CTL_TS \| OWL_SD_CTL_LBE \| 0x64000000);
	229	} else {
	230	mode &= ~(OWL_SD_CTL_TOUTEN \| OWL_SD_CTL_LBE);
	231	mode \|= OWL_SD_CTL_TS;
	232	}
	233
	234	owl_host->cmd = cmd;
	235
	236	/* Start transfer */
	237	writel(mode, owl_host->base + OWL_REG_SD_CTL);
	238
	239	if (data)
	240	return;
	241
	242	if (!wait_for_completion_timeout(&owl_host->sdc_complete, 30 * HZ)) {
	243	dev_err(owl_host->dev, "CMD interrupt timeout\n");
	244	cmd->error = -ETIMEDOUT;
	245	return;
	246	}
	247
	248	state = readl(owl_host->base + OWL_REG_SD_STATE);
	249	if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) {
	250	if (cmd_rsp_mask & state) {
	251	if (state & OWL_SD_STATE_CLNR) {
	252	dev_err(owl_host->dev, "Error CMD_NO_RSP\n");
	253	cmd->error = -EILSEQ;
	254	return;
	255	}
	256
	257	if (state & OWL_SD_STATE_CRC7ER) {
	258	dev_err(owl_host->dev, "Error CMD_RSP_CRC\n");
	259	cmd->error = -EILSEQ;
	260	return;
	261	}
	262	}
	263
	264	if (mmc_resp_type(cmd) & MMC_RSP_136) {
	265	cmd->resp[3] = readl(owl_host->base + OWL_REG_SD_RSPBUF0);
	266	cmd->resp[2] = readl(owl_host->base + OWL_REG_SD_RSPBUF1);
	267	cmd->resp[1] = readl(owl_host->base + OWL_REG_SD_RSPBUF2);
	268	cmd->resp[0] = readl(owl_host->base + OWL_REG_SD_RSPBUF3);
	269	} else {
	270	resp[0] = readl(owl_host->base + OWL_REG_SD_RSPBUF0);
	271	resp[1] = readl(owl_host->base + OWL_REG_SD_RSPBUF1);
	272	cmd->resp[0] = resp[1] << 24 \| resp[0] >> 8;
	273	cmd->resp[1] = resp[1] >> 8;
	274	}
	275	}
	276	}
	277
	278	static void owl_mmc_dma_complete(void *param)
	279	{
	280	struct owl_mmc_host *owl_host = param;
	281	struct mmc_data *data = owl_host->data;
	282
	283	if (data)
	284	complete(&owl_host->dma_complete);
	285	}
	286
	287	static int owl_mmc_prepare_data(struct owl_mmc_host *owl_host,
	288	struct mmc_data *data)
	289	{
	290	u32 total;
	291
	292	owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN, OWL_SD_EN_BSEL,
	293	true);
	294	writel(data->blocks, owl_host->base + OWL_REG_SD_BLK_NUM);
	295	writel(data->blksz, owl_host->base + OWL_REG_SD_BLK_SIZE);
	296	total = data->blksz * data->blocks;
	297
	298	if (total < 512)
	299	writel(total, owl_host->base + OWL_REG_SD_BUF_SIZE);
	300	else
	301	writel(512, owl_host->base + OWL_REG_SD_BUF_SIZE);
	302
	303	if (data->flags & MMC_DATA_WRITE) {
	304	owl_host->dma_dir = DMA_TO_DEVICE;
	305	owl_host->dma_cfg.direction = DMA_MEM_TO_DEV;
	306	} else {
	307	owl_host->dma_dir = DMA_FROM_DEVICE;
	308	owl_host->dma_cfg.direction = DMA_DEV_TO_MEM;
	309	}
	310
	311	dma_map_sg(owl_host->dma->device->dev, data->sg,
	312	data->sg_len, owl_host->dma_dir);
	313
	314	dmaengine_slave_config(owl_host->dma, &owl_host->dma_cfg);
	315	owl_host->desc = dmaengine_prep_slave_sg(owl_host->dma, data->sg,
	316	data->sg_len,
	317	owl_host->dma_cfg.direction,
	318	DMA_PREP_INTERRUPT \|
	319	DMA_CTRL_ACK);
	320	if (!owl_host->desc) {
	321	dev_err(owl_host->dev, "Can't prepare slave sg\n");
	322	return -EBUSY;
	323	}
	324
	325	owl_host->data = data;
	326
	327	owl_host->desc->callback = owl_mmc_dma_complete;
	328	owl_host->desc->callback_param = (void *)owl_host;
	329	data->error = 0;
	330
	331	return 0;
	332	}
	333
	334	static void owl_mmc_request(struct mmc_host mmc, struct mmc_request mrq)
	335	{
	336	struct owl_mmc_host *owl_host = mmc_priv(mmc);
	337	struct mmc_data *data = mrq->data;
	338	int ret;
	339
	340	owl_host->mrq = mrq;
	341	if (mrq->data) {
	342	ret = owl_mmc_prepare_data(owl_host, data);
	343	if (ret < 0) {
	344	data->error = ret;
	345	goto err_out;
	346	}
	347
	348	init_completion(&owl_host->dma_complete);
	349	dmaengine_submit(owl_host->desc);
	350	dma_async_issue_pending(owl_host->dma);
	351	}
	352
	353	owl_mmc_send_cmd(owl_host, mrq->cmd, data);
	354
	355	if (data) {
	356	if (!wait_for_completion_timeout(&owl_host->sdc_complete,
	357	10 * HZ)) {
	358	dev_err(owl_host->dev, "CMD interrupt timeout\n");
	359	mrq->cmd->error = -ETIMEDOUT;
	360	dmaengine_terminate_all(owl_host->dma);
	361	goto err_out;
	362	}
	363
	364	if (!wait_for_completion_timeout(&owl_host->dma_complete,
	365	5 * HZ)) {
	366	dev_err(owl_host->dev, "DMA interrupt timeout\n");
	367	mrq->cmd->error = -ETIMEDOUT;
	368	dmaengine_terminate_all(owl_host->dma);
	369	goto err_out;
	370	}
	371
	372	if (data->stop)
	373	owl_mmc_send_cmd(owl_host, data->stop, NULL);
	374
	375	data->bytes_xfered = data->blocks * data->blksz;
	376	}
	377
	378	err_out:
	379	owl_mmc_finish_request(owl_host);
	380	}
	381
	382	static int owl_mmc_set_clk_rate(struct owl_mmc_host *owl_host,
	383	unsigned int rate)
	384	{
	385	unsigned long clk_rate;
	386	int ret;
	387	u32 reg;
	388
	389	reg = readl(owl_host->base + OWL_REG_SD_CTL);
	390	reg &= ~OWL_SD_CTL_DELAY_MSK;
	391
	392	/* Set RDELAY and WDELAY based on the clock */
	393	if (rate <= 1000000) {
	394	writel(reg \| OWL_SD_CTL_RDELAY(OWL_SD_DELAY_LOW_CLK) \|
	395	OWL_SD_CTL_WDELAY(OWL_SD_DELAY_LOW_CLK),
	396	owl_host->base + OWL_REG_SD_CTL);
	397	} else if ((rate > 1000000) && (rate <= 26000000)) {
	398	writel(reg \| OWL_SD_CTL_RDELAY(OWL_SD_DELAY_MID_CLK) \|
	399	OWL_SD_CTL_WDELAY(OWL_SD_DELAY_MID_CLK),
	400	owl_host->base + OWL_REG_SD_CTL);
	401	} else if ((rate > 26000000) && (rate <= 52000000) && !owl_host->ddr_50) {
	402	writel(reg \| OWL_SD_CTL_RDELAY(OWL_SD_DELAY_HIGH_CLK) \|
	403	OWL_SD_CTL_WDELAY(OWL_SD_DELAY_HIGH_CLK),
	404	owl_host->base + OWL_REG_SD_CTL);
	405	/* DDR50 mode has special delay chain */
	406	} else if ((rate > 26000000) && (rate <= 52000000) && owl_host->ddr_50) {
	407	writel(reg \| OWL_SD_CTL_RDELAY(OWL_SD_RDELAY_DDR50) \|
	408	OWL_SD_CTL_WDELAY(OWL_SD_WDELAY_DDR50),
	409	owl_host->base + OWL_REG_SD_CTL);
	410	} else {
	411	dev_err(owl_host->dev, "SD clock rate not supported\n");
	412	return -EINVAL;
	413	}
	414
	415	clk_rate = clk_round_rate(owl_host->clk, rate << 1);
	416	ret = clk_set_rate(owl_host->clk, clk_rate);
	417
	418	return ret;
	419	}
	420
	421	static void owl_mmc_set_clk(struct owl_mmc_host owl_host, struct mmc_ios ios)
	422	{
	423	if (!ios->clock)
	424	return;
	425
	426	owl_host->clock = ios->clock;
	427	owl_mmc_set_clk_rate(owl_host, ios->clock);
	428	}
	429
	430	static void owl_mmc_set_bus_width(struct owl_mmc_host *owl_host,
	431	struct mmc_ios *ios)
	432	{
	433	u32 reg;
	434
	435	reg = readl(owl_host->base + OWL_REG_SD_EN);
	436	reg &= ~0x03;
	437	switch (ios->bus_width) {
	438	case MMC_BUS_WIDTH_1:
	439	break;
	440	case MMC_BUS_WIDTH_4:
	441	reg \|= OWL_SD_EN_DATAWID(1);
	442	break;
	443	case MMC_BUS_WIDTH_8:
	444	reg \|= OWL_SD_EN_DATAWID(2);
	445	break;
	446	}
	447
	448	writel(reg, owl_host->base + OWL_REG_SD_EN);
	449	}
	450
	451	static void owl_mmc_ctr_reset(struct owl_mmc_host *owl_host)
	452	{
	453	reset_control_assert(owl_host->reset);
	454	udelay(20);
	455	reset_control_deassert(owl_host->reset);
	456	}
	457
	458	static void owl_mmc_power_on(struct owl_mmc_host *owl_host)
	459	{
	460	u32 mode;
	461
	462	init_completion(&owl_host->sdc_complete);
	463
	464	/* Enable transfer end IRQ */
	465	owl_mmc_update_reg(owl_host->base + OWL_REG_SD_STATE,
	466	OWL_SD_STATE_TEIE, true);
	467
	468	/* Send init clk */
	469	mode = (readl(owl_host->base + OWL_REG_SD_CTL) & (0xff << 16));
	470	mode \|= OWL_SD_CTL_TS \| OWL_SD_CTL_TCN(5) \| OWL_SD_CTL_TM(8);
	471	writel(mode, owl_host->base + OWL_REG_SD_CTL);
	472
	473	if (!wait_for_completion_timeout(&owl_host->sdc_complete, HZ)) {
	474	dev_err(owl_host->dev, "CMD interrupt timeout\n");
	475	return;
	476	}
	477	}
	478
	479	static void owl_mmc_set_ios(struct mmc_host mmc, struct mmc_ios ios)
	480	{
	481	struct owl_mmc_host *owl_host = mmc_priv(mmc);
	482
	483	switch (ios->power_mode) {
	484	case MMC_POWER_UP:
	485	dev_dbg(owl_host->dev, "Powering card up\n");
	486
	487	/* Reset the SDC controller to clear all previous states */
	488	owl_mmc_ctr_reset(owl_host);
	489	clk_prepare_enable(owl_host->clk);
	490	writel(OWL_SD_ENABLE \| OWL_SD_EN_RESE,
	491	owl_host->base + OWL_REG_SD_EN);
	492
	493	break;
	494
	495	case MMC_POWER_ON:
	496	dev_dbg(owl_host->dev, "Powering card on\n");
	497	owl_mmc_power_on(owl_host);
	498
	499	break;
	500
	501	case MMC_POWER_OFF:
	502	dev_dbg(owl_host->dev, "Powering card off\n");
	503	clk_disable_unprepare(owl_host->clk);
	504
	505	return;
	506
	507	default:
	508	dev_dbg(owl_host->dev, "Ignoring unknown card power state\n");
	509	break;
	510	}
	511
	512	if (ios->clock != owl_host->clock)
	513	owl_mmc_set_clk(owl_host, ios);
	514
	515	owl_mmc_set_bus_width(owl_host, ios);
	516
	517	/* Enable DDR mode if requested */
	518	if (ios->timing == MMC_TIMING_UHS_DDR50) {
	519	owl_host->ddr_50 = 1;
	520	owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN,
	521	OWL_SD_EN_DDREN, true);
	522	} else {
	523	owl_host->ddr_50 = 0;
	524	}
	525	}
	526
	527	static int owl_mmc_start_signal_voltage_switch(struct mmc_host *mmc,
	528	struct mmc_ios *ios)
	529	{
	530	struct owl_mmc_host *owl_host = mmc_priv(mmc);
	531
	532	/* It is enough to change the pad ctrl bit for voltage switch */
	533	switch (ios->signal_voltage) {
	534	case MMC_SIGNAL_VOLTAGE_330:
	535	owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN,
	536	OWL_SD_EN_S18EN, false);
	537	break;
	538	case MMC_SIGNAL_VOLTAGE_180:
	539	owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN,
	540	OWL_SD_EN_S18EN, true);
	541	break;
	542	default:
	543	return -ENOTSUPP;
	544	}
	545
	546	return 0;
	547	}
	548
	549	static const struct mmc_host_ops owl_mmc_ops = {
	550	.request = owl_mmc_request,
	551	.set_ios = owl_mmc_set_ios,
	552	.get_ro = mmc_gpio_get_ro,
	553	.get_cd = mmc_gpio_get_cd,
	554	.start_signal_voltage_switch = owl_mmc_start_signal_voltage_switch,
	555	};
	556
	557	static int owl_mmc_probe(struct platform_device *pdev)
	558	{
	559	struct owl_mmc_host *owl_host;
	560	struct mmc_host *mmc;
	561	struct resource *res;
	562	int ret;
	563
	564	mmc = mmc_alloc_host(sizeof(struct owl_mmc_host), &pdev->dev);
	565	if (!mmc) {
	566	dev_err(&pdev->dev, "mmc alloc host failed\n");
	567	return -ENOMEM;
	568	}
	569	platform_set_drvdata(pdev, mmc);
	570
	571	owl_host = mmc_priv(mmc);
	572	owl_host->dev = &pdev->dev;
	573	owl_host->mmc = mmc;
	574	spin_lock_init(&owl_host->lock);
	575
	576	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	577	owl_host->base = devm_ioremap_resource(&pdev->dev, res);
	578	if (IS_ERR(owl_host->base)) {
	579	dev_err(&pdev->dev, "Failed to remap registers\n");
	580	ret = PTR_ERR(owl_host->base);
	581	goto err_free_host;
	582	}
	583
	584	owl_host->clk = devm_clk_get(&pdev->dev, NULL);
	585	if (IS_ERR(owl_host->clk)) {
	586	dev_err(&pdev->dev, "No clock defined\n");
	587	ret = PTR_ERR(owl_host->clk);
	588	goto err_free_host;
	589	}
	590
	591	owl_host->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
	592	if (IS_ERR(owl_host->reset)) {
	593	dev_err(&pdev->dev, "Could not get reset control\n");
	594	ret = PTR_ERR(owl_host->reset);
	595	goto err_free_host;
	596	}
	597
	598	mmc->ops = &owl_mmc_ops;
	599	mmc->max_blk_count = 512;
	600	mmc->max_blk_size = 512;
	601	mmc->max_segs = 256;
	602	mmc->max_seg_size = 262144;
	603	mmc->max_req_size = 262144;
	604	/* 100kHz ~ 52MHz */
	605	mmc->f_min = 100000;
	606	mmc->f_max = 52000000;
	607	mmc->caps \|= MMC_CAP_MMC_HIGHSPEED \| MMC_CAP_SD_HIGHSPEED \|
	608	MMC_CAP_4_BIT_DATA;
	609	mmc->caps2 = (MMC_CAP2_BOOTPART_NOACC \| MMC_CAP2_NO_SDIO);
	610	mmc->ocr_avail = MMC_VDD_32_33 \| MMC_VDD_33_34 \|
	611	MMC_VDD_165_195;
	612
	613	ret = mmc_of_parse(mmc);
	614	if (ret)
	615	goto err_free_host;
	616
	617	pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
	618	pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
	619	owl_host->dma = dma_request_slave_channel(&pdev->dev, "mmc");
	620	if (!owl_host->dma) {
	621	dev_err(owl_host->dev, "Failed to get external DMA channel.\n");
	622	ret = -ENXIO;
	623	goto err_free_host;
	624	}
	625
	626	dev_info(&pdev->dev, "Using %s for DMA transfers\n",
	627	dma_chan_name(owl_host->dma));
	628
	629	owl_host->dma_cfg.src_addr = res->start + OWL_REG_SD_DAT;
	630	owl_host->dma_cfg.dst_addr = res->start + OWL_REG_SD_DAT;
	631	owl_host->dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	632	owl_host->dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	633	owl_host->dma_cfg.device_fc = false;
	634
	635	owl_host->irq = platform_get_irq(pdev, 0);
	636	if (owl_host->irq < 0) {
	637	ret = -EINVAL;
	638	goto err_free_host;
	639	}
	640
	641	ret = devm_request_irq(&pdev->dev, owl_host->irq, owl_irq_handler,
	642	0, dev_name(&pdev->dev), owl_host);
	643	if (ret) {
	644	dev_err(&pdev->dev, "Failed to request irq %d\n",
	645	owl_host->irq);
	646	goto err_free_host;
	647	}
	648
	649	ret = mmc_add_host(mmc);
	650	if (ret) {
	651	dev_err(&pdev->dev, "Failed to add host\n");
	652	goto err_free_host;
	653	}
	654
	655	dev_dbg(&pdev->dev, "Owl MMC Controller Initialized\n");
	656
	657	return 0;
	658
	659	err_free_host:
	660	mmc_free_host(mmc);
	661
	662	return ret;
	663	}
	664
	665	static int owl_mmc_remove(struct platform_device *pdev)
	666	{
	667	struct mmc_host *mmc = platform_get_drvdata(pdev);
	668	struct owl_mmc_host *owl_host = mmc_priv(mmc);
	669
	670	mmc_remove_host(mmc);
	671	disable_irq(owl_host->irq);
	672	mmc_free_host(mmc);
	673
	674	return 0;
	675	}
	676
	677	static const struct of_device_id owl_mmc_of_match[] = {
	678	{.compatible = "actions,owl-mmc",},
	679	{ /* sentinel */ }
	680	};
	681	MODULE_DEVICE_TABLE(of, owl_mmc_of_match);
	682
	683	static struct platform_driver owl_mmc_driver = {
	684	.driver = {
	685	.name = "owl_mmc",
	686	.of_match_table = of_match_ptr(owl_mmc_of_match),
	687	},
	688	.probe = owl_mmc_probe,
	689	.remove = owl_mmc_remove,
	690	};
	691	module_platform_driver(owl_mmc_driver);
	692
	693	MODULE_DESCRIPTION("Actions Semi Owl SoCs SD/MMC Driver");
	694	MODULE_AUTHOR("Actions Semi");
	695	MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
	696	MODULE_LICENSE("GPL");

drivers/mmc/host/renesas_sdhi_internal_dmac.c+1−0

@@ -308,6 +308,7 @@ static const struct soc_device_attribute soc_whitelist[] = { · 307 unmodified lines
308	.data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) },	308	.data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) },
309	/* generic ones */	309	/* generic ones */
310	{ .soc_id = "r8a774a1" },	310	{ .soc_id = "r8a774a1" },
		311	{ .soc_id = "r8a774b1" },
311	{ .soc_id = "r8a774c0" },	312	{ .soc_id = "r8a774c0" },
312	{ .soc_id = "r8a77470" },	313	{ .soc_id = "r8a77470" },
313	{ .soc_id = "r8a7795" },	314	{ .soc_id = "r8a7795" },

drivers/mmc/host/sdhci-esdhc.h+14−0

@@ -51,6 +51,11 @@ · 50 unmodified lines
51	#define ESDHC_CLOCK_HCKEN 0x00000002	51	#define ESDHC_CLOCK_HCKEN 0x00000002
52	#define ESDHC_CLOCK_IPGEN 0x00000001	52	#define ESDHC_CLOCK_IPGEN 0x00000001
53		53
		54	/* System Control 2 Register */
		55	#define ESDHC_SYSTEM_CONTROL_2 0x3c
		56	#define ESDHC_SMPCLKSEL 0x00800000
		57	#define ESDHC_EXTN 0x00400000
		58
54	/* Host Controller Capabilities Register 2 */	59	/* Host Controller Capabilities Register 2 */
55	#define ESDHC_CAPABILITIES_1 0x114	60	#define ESDHC_CAPABILITIES_1 0x114
56		61
@@ -59,7 +64,16 @@ · 2 unmodified lines
59	#define ESDHC_HS400_WNDW_ADJUST 0x00000040	64	#define ESDHC_HS400_WNDW_ADJUST 0x00000040
60	#define ESDHC_HS400_MODE 0x00000010	65	#define ESDHC_HS400_MODE 0x00000010
61	#define ESDHC_TB_EN 0x00000004	66	#define ESDHC_TB_EN 0x00000004
		67	#define ESDHC_TB_MODE_MASK 0x00000003
		68	#define ESDHC_TB_MODE_SW 0x00000003
		69	#define ESDHC_TB_MODE_3 0x00000002
		70
		71	#define ESDHC_TBSTAT 0x124
		72
62	#define ESDHC_TBPTR 0x128	73	#define ESDHC_TBPTR 0x128
		74	#define ESDHC_WNDW_STRT_PTR_SHIFT 8
		75	#define ESDHC_WNDW_STRT_PTR_MASK (0x7f << 8)
		76	#define ESDHC_WNDW_END_PTR_MASK 0x7f
63		77
64	/* SD Clock Control Register */	78	/* SD Clock Control Register */
65	#define ESDHC_SDCLKCTL 0x144	79	#define ESDHC_SDCLKCTL 0x144

drivers/mmc/host/sdhci-milbeaut.c+362−0

@@ -0,0 +1,362 @@
	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) 2013 - 2015 Fujitsu Semiconductor, Ltd
	4	* Vincent Yang <vincent.yang@tw.fujitsu.com>
	5	* Copyright (C) 2015 Linaro Ltd Andy Green <andy.green@linaro.org>
	6	* Copyright (C) 2019 Socionext Inc.
	7	* Takao Orito <orito.takao@socionext.com>
	8	*/
	9
	10	#include <linux/bits.h>
	11	#include <linux/clk.h>
	12	#include <linux/delay.h>
	13	#include <linux/err.h>
	14	#include <linux/gpio/consumer.h>
	15	#include <linux/module.h>
	16	#include <linux/of.h>
	17	#include <linux/property.h>
	18
	19	#include "sdhci-pltfm.h"
	20	#include "sdhci_f_sdh30.h"
	21
	22	/* milbeaut bridge controller register */
	23	#define MLB_SOFT_RESET 0x0200
	24	#define MLB_SOFT_RESET_RSTX BIT(0)
	25
	26	#define MLB_WP_CD_LED_SET 0x0210
	27	#define MLB_WP_CD_LED_SET_LED_INV BIT(2)
	28
	29	#define MLB_CR_SET 0x0220
	30	#define MLB_CR_SET_CR_TOCLKUNIT BIT(24)
	31	#define MLB_CR_SET_CR_TOCLKFREQ_SFT (16)
	32	#define MLB_CR_SET_CR_TOCLKFREQ_MASK (0x3F << MLB_CR_SET_CR_TOCLKFREQ_SFT)
	33	#define MLB_CR_SET_CR_BCLKFREQ_SFT (8)
	34	#define MLB_CR_SET_CR_BCLKFREQ_MASK (0xFF << MLB_CR_SET_CR_BCLKFREQ_SFT)
	35	#define MLB_CR_SET_CR_RTUNTIMER_SFT (4)
	36	#define MLB_CR_SET_CR_RTUNTIMER_MASK (0xF << MLB_CR_SET_CR_RTUNTIMER_SFT)
	37
	38	#define MLB_SD_TOCLK_I_DIV 16
	39	#define MLB_TOCLKFREQ_UNIT_THRES 16000000
	40	#define MLB_CAL_TOCLKFREQ_MHZ(rate) (rate / MLB_SD_TOCLK_I_DIV / 1000000)
	41	#define MLB_CAL_TOCLKFREQ_KHZ(rate) (rate / MLB_SD_TOCLK_I_DIV / 1000)
	42	#define MLB_TOCLKFREQ_MAX 63
	43	#define MLB_TOCLKFREQ_MIN 1
	44
	45	#define MLB_SD_BCLK_I_DIV 4
	46	#define MLB_CAL_BCLKFREQ(rate) (rate / MLB_SD_BCLK_I_DIV / 1000000)
	47	#define MLB_BCLKFREQ_MAX 255
	48	#define MLB_BCLKFREQ_MIN 1
	49
	50	#define MLB_CDR_SET 0x0230
	51	#define MLB_CDR_SET_CLK2POW16 3
	52
	53	struct f_sdhost_priv {
	54	struct clk *clk_iface;
	55	struct clk *clk;
	56	struct device *dev;
	57	bool enable_cmd_dat_delay;
	58	};
	59
	60	static void sdhci_milbeaut_soft_voltage_switch(struct sdhci_host *host)
	61	{
	62	u32 ctrl = 0;
	63
	64	usleep_range(2500, 3000);
	65	ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2);
	66	ctrl \|= F_SDH30_CRES_O_DN;
	67	sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
	68	ctrl \|= F_SDH30_MSEL_O_1_8;
	69	sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
	70
	71	ctrl &= ~F_SDH30_CRES_O_DN;
	72	sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
	73	usleep_range(2500, 3000);
	74
	75	ctrl = sdhci_readl(host, F_SDH30_TUNING_SETTING);
	76	ctrl \|= F_SDH30_CMD_CHK_DIS;
	77	sdhci_writel(host, ctrl, F_SDH30_TUNING_SETTING);
	78	}
	79
	80	static unsigned int sdhci_milbeaut_get_min_clock(struct sdhci_host *host)
	81	{
	82	return F_SDH30_MIN_CLOCK;
	83	}
	84
	85	static void sdhci_milbeaut_reset(struct sdhci_host *host, u8 mask)
	86	{
	87	struct f_sdhost_priv *priv = sdhci_priv(host);
	88	u16 clk;
	89	u32 ctl;
	90	ktime_t timeout;
	91
	92	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
	93	clk = (clk & ~SDHCI_CLOCK_CARD_EN) \| SDHCI_CLOCK_INT_EN;
	94	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	95
	96	sdhci_reset(host, mask);
	97
	98	clk \|= SDHCI_CLOCK_CARD_EN;
	99	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	100
	101	timeout = ktime_add_ms(ktime_get(), 10);
	102	while (1) {
	103	bool timedout = ktime_after(ktime_get(), timeout);
	104
	105	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
	106	if (clk & SDHCI_CLOCK_INT_STABLE)
	107	break;
	108	if (timedout) {
	109	pr_err("%s: Internal clock never stabilised.\n",
	110	mmc_hostname(host->mmc));
	111	sdhci_dumpregs(host);
	112	return;
	113	}
	114	udelay(10);
	115	}
	116
	117	if (priv->enable_cmd_dat_delay) {
	118	ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL);
	119	ctl \|= F_SDH30_CMD_DAT_DELAY;
	120	sdhci_writel(host, ctl, F_SDH30_ESD_CONTROL);
	121	}
	122	}
	123
	124	static void sdhci_milbeaut_set_power(struct sdhci_host *host,
	125	unsigned char mode, unsigned short vdd)
	126	{
	127	if (!IS_ERR(host->mmc->supply.vmmc)) {
	128	struct mmc_host *mmc = host->mmc;
	129
	130	mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
	131	}
	132	sdhci_set_power_noreg(host, mode, vdd);
	133	}
	134
	135	static const struct sdhci_ops sdhci_milbeaut_ops = {
	136	.voltage_switch = sdhci_milbeaut_soft_voltage_switch,
	137	.get_min_clock = sdhci_milbeaut_get_min_clock,
	138	.reset = sdhci_milbeaut_reset,
	139	.set_clock = sdhci_set_clock,
	140	.set_bus_width = sdhci_set_bus_width,
	141	.set_uhs_signaling = sdhci_set_uhs_signaling,
	142	.set_power = sdhci_milbeaut_set_power,
	143	};
	144
	145	static void sdhci_milbeaut_bridge_reset(struct sdhci_host *host,
	146	int reset_flag)
	147	{
	148	if (reset_flag)
	149	sdhci_writel(host, 0, MLB_SOFT_RESET);
	150	else
	151	sdhci_writel(host, MLB_SOFT_RESET_RSTX, MLB_SOFT_RESET);
	152	}
	153
	154	static void sdhci_milbeaut_bridge_init(struct sdhci_host *host,
	155	int rate)
	156	{
	157	u32 val, clk;
	158
	159	/* IO_SDIO_CR_SET should be set while reset */
	160	val = sdhci_readl(host, MLB_CR_SET);
	161	val &= ~(MLB_CR_SET_CR_TOCLKFREQ_MASK \| MLB_CR_SET_CR_TOCLKUNIT \|
	162	MLB_CR_SET_CR_BCLKFREQ_MASK);
	163	if (rate >= MLB_TOCLKFREQ_UNIT_THRES) {
	164	clk = MLB_CAL_TOCLKFREQ_MHZ(rate);
	165	clk = min_t(u32, MLB_TOCLKFREQ_MAX, clk);
	166	val \|= MLB_CR_SET_CR_TOCLKUNIT \|
	167	(clk << MLB_CR_SET_CR_TOCLKFREQ_SFT);
	168	} else {
	169	clk = MLB_CAL_TOCLKFREQ_KHZ(rate);
	170	clk = min_t(u32, MLB_TOCLKFREQ_MAX, clk);
	171	clk = max_t(u32, MLB_TOCLKFREQ_MIN, clk);
	172	val \|= clk << MLB_CR_SET_CR_TOCLKFREQ_SFT;
	173	}
	174
	175	clk = MLB_CAL_BCLKFREQ(rate);
	176	clk = min_t(u32, MLB_BCLKFREQ_MAX, clk);
	177	clk = max_t(u32, MLB_BCLKFREQ_MIN, clk);
	178	val \|= clk << MLB_CR_SET_CR_BCLKFREQ_SFT;
	179	val &= ~MLB_CR_SET_CR_RTUNTIMER_MASK;
	180	sdhci_writel(host, val, MLB_CR_SET);
	181
	182	sdhci_writel(host, MLB_CDR_SET_CLK2POW16, MLB_CDR_SET);
	183
	184	sdhci_writel(host, MLB_WP_CD_LED_SET_LED_INV, MLB_WP_CD_LED_SET);
	185	}
	186
	187	static void sdhci_milbeaut_vendor_init(struct sdhci_host *host)
	188	{
	189	struct f_sdhost_priv *priv = sdhci_priv(host);
	190	u32 ctl;
	191
	192	ctl = sdhci_readl(host, F_SDH30_IO_CONTROL2);
	193	ctl \|= F_SDH30_CRES_O_DN;
	194	sdhci_writel(host, ctl, F_SDH30_IO_CONTROL2);
	195	ctl &= ~F_SDH30_MSEL_O_1_8;
	196	sdhci_writel(host, ctl, F_SDH30_IO_CONTROL2);
	197	ctl &= ~F_SDH30_CRES_O_DN;
	198	sdhci_writel(host, ctl, F_SDH30_IO_CONTROL2);
	199
	200	ctl = sdhci_readw(host, F_SDH30_AHB_CONFIG);
	201	ctl \|= F_SDH30_SIN \| F_SDH30_AHB_INCR_16 \| F_SDH30_AHB_INCR_8 \|
	202	F_SDH30_AHB_INCR_4;
	203	ctl &= ~(F_SDH30_AHB_BIGED \| F_SDH30_BUSLOCK_EN);
	204	sdhci_writew(host, ctl, F_SDH30_AHB_CONFIG);
	205
	206	if (priv->enable_cmd_dat_delay) {
	207	ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL);
	208	ctl \|= F_SDH30_CMD_DAT_DELAY;
	209	sdhci_writel(host, ctl, F_SDH30_ESD_CONTROL);
	210	}
	211	}
	212
	213	static const struct of_device_id mlb_dt_ids[] = {
	214	{
	215	.compatible = "socionext,milbeaut-m10v-sdhci-3.0",
	216	},
	217	{ /* sentinel */ }
	218	};
	219	MODULE_DEVICE_TABLE(of, mlb_dt_ids);
	220
	221	static void sdhci_milbeaut_init(struct sdhci_host *host)
	222	{
	223	struct f_sdhost_priv *priv = sdhci_priv(host);
	224	int rate = clk_get_rate(priv->clk);
	225	u16 ctl;
	226
	227	sdhci_milbeaut_bridge_reset(host, 0);
	228
	229	ctl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
	230	ctl &= ~(SDHCI_CLOCK_CARD_EN \| SDHCI_CLOCK_INT_EN);
	231	sdhci_writew(host, ctl, SDHCI_CLOCK_CONTROL);
	232
	233	sdhci_milbeaut_bridge_reset(host, 1);
	234
	235	sdhci_milbeaut_bridge_init(host, rate);
	236	sdhci_milbeaut_bridge_reset(host, 0);
	237
	238	sdhci_milbeaut_vendor_init(host);
	239	}
	240
	241	static int sdhci_milbeaut_probe(struct platform_device *pdev)
	242	{
	243	struct sdhci_host *host;
	244	struct device *dev = &pdev->dev;
	245	struct resource *res;
	246	int irq, ret = 0;
	247	struct f_sdhost_priv *priv;
	248
	249	irq = platform_get_irq(pdev, 0);
	250	if (irq < 0) {
	251	dev_err(dev, "%s: no irq specified\n", __func__);
	252	return irq;
	253	}
	254
	255	host = sdhci_alloc_host(dev, sizeof(struct f_sdhost_priv));
	256	if (IS_ERR(host))
	257	return PTR_ERR(host);
	258
	259	priv = sdhci_priv(host);
	260	priv->dev = dev;
	261
	262	host->quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC \|
	263	SDHCI_QUIRK_INVERTED_WRITE_PROTECT \|
	264	SDHCI_QUIRK_CLOCK_BEFORE_RESET \|
	265	SDHCI_QUIRK_DELAY_AFTER_POWER;
	266	host->quirks2 = SDHCI_QUIRK2_SUPPORT_SINGLE \|
	267	SDHCI_QUIRK2_TUNING_WORK_AROUND \|
	268	SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
	269
	270	priv->enable_cmd_dat_delay = device_property_read_bool(dev,
	271	"fujitsu,cmd-dat-delay-select");
	272
	273	ret = mmc_of_parse(host->mmc);
	274	if (ret)
	275	goto err;
	276
	277	platform_set_drvdata(pdev, host);
	278
	279	host->hw_name = "f_sdh30";
	280	host->ops = &sdhci_milbeaut_ops;
	281	host->irq = irq;
	282
	283	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	284	host->ioaddr = devm_ioremap_resource(&pdev->dev, res);
	285	if (IS_ERR(host->ioaddr)) {
	286	ret = PTR_ERR(host->ioaddr);
	287	goto err;
	288	}
	289
	290	if (dev_of_node(dev)) {
	291	sdhci_get_of_property(pdev);
	292
	293	priv->clk_iface = devm_clk_get(&pdev->dev, "iface");
	294	if (IS_ERR(priv->clk_iface)) {
	295	ret = PTR_ERR(priv->clk_iface);
	296	goto err;
	297	}
	298
	299	ret = clk_prepare_enable(priv->clk_iface);
	300	if (ret)
	301	goto err;
	302
	303	priv->clk = devm_clk_get(&pdev->dev, "core");
	304	if (IS_ERR(priv->clk)) {
	305	ret = PTR_ERR(priv->clk);
	306	goto err_clk;
	307	}
	308
	309	ret = clk_prepare_enable(priv->clk);
	310	if (ret)
	311	goto err_clk;
	312	}
	313
	314	sdhci_milbeaut_init(host);
	315
	316	ret = sdhci_add_host(host);
	317	if (ret)
	318	goto err_add_host;
	319
	320	return 0;
	321
	322	err_add_host:
	323	clk_disable_unprepare(priv->clk);
	324	err_clk:
	325	clk_disable_unprepare(priv->clk_iface);
	326	err:
	327	sdhci_free_host(host);
	328	return ret;
	329	}
	330
	331	static int sdhci_milbeaut_remove(struct platform_device *pdev)
	332	{
	333	struct sdhci_host *host = platform_get_drvdata(pdev);
	334	struct f_sdhost_priv *priv = sdhci_priv(host);
	335
	336	sdhci_remove_host(host, readl(host->ioaddr + SDHCI_INT_STATUS) ==
	337	0xffffffff);
	338
	339	clk_disable_unprepare(priv->clk_iface);
	340	clk_disable_unprepare(priv->clk);
	341
	342	sdhci_free_host(host);
	343	platform_set_drvdata(pdev, NULL);
	344
	345	return 0;
	346	}
	347
	348	static struct platform_driver sdhci_milbeaut_driver = {
	349	.driver = {
	350	.name = "sdhci-milbeaut",
	351	.of_match_table = of_match_ptr(mlb_dt_ids),
	352	},
	353	.probe = sdhci_milbeaut_probe,
	354	.remove = sdhci_milbeaut_remove,
	355	};
	356
	357	module_platform_driver(sdhci_milbeaut_driver);
	358
	359	MODULE_DESCRIPTION("MILBEAUT SD Card Controller driver");
	360	MODULE_AUTHOR("Takao Orito <orito.takao@socionext.com>");
	361	MODULE_LICENSE("GPL v2");
	362	MODULE_ALIAS("platform:sdhci-milbeaut");

drivers/mmc/host/sdhci-of-arasan.c+465−28

@@ -22,6 +22,7 @@ · 21 unmodified lines
22	#include <linux/phy/phy.h>	22	#include <linux/phy/phy.h>
23	#include <linux/regmap.h>	23	#include <linux/regmap.h>
24	#include <linux/of.h>	24	#include <linux/of.h>
		25	#include <linux/firmware/xlnx-zynqmp.h>
25		26
26	#include "cqhci.h"	27	#include "cqhci.h"
27	#include "sdhci-pltfm.h"	28	#include "sdhci-pltfm.h"
@@ -32,6 +33,10 @@ · 4 unmodified lines
32		33
33	#define PHY_CLK_TOO_SLOW_HZ 400000	34	#define PHY_CLK_TOO_SLOW_HZ 400000
34		35
		36	/* Default settings for ZynqMP Clock Phases */
		37	#define ZYNQMP_ICLK_PHASE {0, 63, 63, 0, 63, 0, 0, 183, 54, 0, 0}
		38	#define ZYNQMP_OCLK_PHASE {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0}
		39
35	/*	40	/*
36	* On some SoCs the syscon area has a feature where the upper 16-bits of	41	* On some SoCs the syscon area has a feature where the upper 16-bits of
37	* each 32-bit register act as a write mask for the lower 16-bits. This allows	42	* each 32-bit register act as a write mask for the lower 16-bits. This allows
@@ -71,14 +76,39 @@ struct sdhci_arasan_soc_ctl_map { · 33 unmodified lines
71	bool hiword_update;	76	bool hiword_update;
72	};	77	};
73		78
		79	/**
		80	* struct sdhci_arasan_clk_data
		81	* @sdcardclk_hw: Struct for the clock we might provide to a PHY.
		82	* @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw.
		83	* @sampleclk_hw: Struct for the clock we might provide to a PHY.
		84	* @sampleclk: Pointer to normal 'struct clock' for sampleclk_hw.
		85	* @clk_phase_in: Array of Input Clock Phase Delays for all speed modes
		86	* @clk_phase_out: Array of Output Clock Phase Delays for all speed modes
		87	* @set_clk_delays: Function pointer for setting Clock Delays
		88	* @clk_of_data: Platform specific runtime clock data storage pointer
		89	*/
		90	struct sdhci_arasan_clk_data {
		91	struct clk_hw sdcardclk_hw;
		92	struct clk *sdcardclk;
		93	struct clk_hw sampleclk_hw;
		94	struct clk *sampleclk;
		95	int clk_phase_in[MMC_TIMING_MMC_HS400 + 1];
		96	int clk_phase_out[MMC_TIMING_MMC_HS400 + 1];
		97	void (set_clk_delays)(struct sdhci_host host);
		98	void *clk_of_data;
		99	};
		100
		101	struct sdhci_arasan_zynqmp_clk_data {
		102	const struct zynqmp_eemi_ops *eemi_ops;
		103	};
		104
74	/**	105	/**
75	* struct sdhci_arasan_data	106	* struct sdhci_arasan_data
76	* @host: Pointer to the main SDHCI host structure.	107	* @host: Pointer to the main SDHCI host structure.
77	* @clk_ahb: Pointer to the AHB clock	108	* @clk_ahb: Pointer to the AHB clock
78	* @phy: Pointer to the generic phy	109	* @phy: Pointer to the generic phy
79	* @is_phy_on: True if the PHY is on; false if not.	110	* @is_phy_on: True if the PHY is on; false if not.
80	* @sdcardclk_hw: Struct for the clock we might provide to a PHY.	111	* @clk_data: Struct for the Arasan Controller Clock Data.
81	* @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw.
82	* @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers.	112	* @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers.
83	* @soc_ctl_map: Map to get offsets into soc_ctl registers.	113	* @soc_ctl_map: Map to get offsets into soc_ctl registers.
84	*/	114	*/
@@ -89,8 +119,7 @@ struct sdhci_arasan_data { · 4 unmodified lines
89	bool is_phy_on;	119	bool is_phy_on;
90		120
91	bool has_cqe;	121	bool has_cqe;
92	struct clk_hw sdcardclk_hw;	122	struct sdhci_arasan_clk_data clk_data;
93	struct clk *sdcardclk;
94		123
95	struct regmap *soc_ctl_base;	124	struct regmap *soc_ctl_base;
96	const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;	125	const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
@@ -120,6 +149,12 @@ static const struct sdhci_arasan_soc_ctl_map intel_lgm_emmc_soc_ctl_map = { · 23 unmodified lines
120	.hiword_update = false,	149	.hiword_update = false,
121	};	150	};
122		151
		152	static const struct sdhci_arasan_soc_ctl_map intel_lgm_sdxc_soc_ctl_map = {
		153	.baseclkfreq = { .reg = 0x80, .width = 8, .shift = 2 },
		154	.clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
		155	.hiword_update = false,
		156	};
		157
123	/**	158	/**
124	* sdhci_arasan_syscon_write - Write to a field in soc_ctl registers	159	* sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
125	*	160	*
@@ -174,6 +209,7 @@ static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock) · 48 unmodified lines
174	{	209	{
175	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);	210	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
176	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);	211	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
		212	struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
177	bool ctrl_phy = false;	213	bool ctrl_phy = false;
178		214
179	if (!IS_ERR(sdhci_arasan->phy)) {	215	if (!IS_ERR(sdhci_arasan->phy)) {
@@ -215,6 +251,10 @@ static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock) · 35 unmodified lines
215	sdhci_arasan->is_phy_on = false;	251	sdhci_arasan->is_phy_on = false;
216	}	252	}
217		253
		254	/* Set the Input and Output Clock Phase Delays */
		255	if (clk_data->set_clk_delays)
		256	clk_data->set_clk_delays(host);
		257
218	sdhci_set_clock(host, clock);	258	sdhci_set_clock(host, clock);
219		259
220	if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE)	260	if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE)
@@ -384,6 +424,11 @@ static struct sdhci_arasan_of_data intel_lgm_emmc_data = { · 163 unmodified lines
384	.pdata = &sdhci_arasan_cqe_pdata,	424	.pdata = &sdhci_arasan_cqe_pdata,
385	};	425	};
386		426
		427	static struct sdhci_arasan_of_data intel_lgm_sdxc_data = {
		428	.soc_ctl_map = &intel_lgm_sdxc_soc_ctl_map,
		429	.pdata = &sdhci_arasan_cqe_pdata,
		430	};
		431
387	#ifdef CONFIG_PM_SLEEP	432	#ifdef CONFIG_PM_SLEEP
388	/**	433	/**
389	* sdhci_arasan_suspend - Suspend method for the driver	434	* sdhci_arasan_suspend - Suspend method for the driver
@@ -489,6 +534,10 @@ static const struct of_device_id sdhci_arasan_of_match[] = { · 99 unmodified lines
489	.compatible = "intel,lgm-sdhci-5.1-emmc",	534	.compatible = "intel,lgm-sdhci-5.1-emmc",
490	.data = &intel_lgm_emmc_data,	535	.data = &intel_lgm_emmc_data,
491	},	536	},
		537	{
		538	.compatible = "intel,lgm-sdhci-5.1-sdxc",
		539	.data = &intel_lgm_sdxc_data,
		540	},
492	/* Generic compatible below here */	541	/* Generic compatible below here */
493	{	542	{
494	.compatible = "arasan,sdhci-8.9a",	543	.compatible = "arasan,sdhci-8.9a",
@@ -502,6 +551,10 @@ static const struct of_device_id sdhci_arasan_of_match[] = { · 7 unmodified lines
502	.compatible = "arasan,sdhci-4.9a",	551	.compatible = "arasan,sdhci-4.9a",
503	.data = &sdhci_arasan_data,	552	.data = &sdhci_arasan_data,
504	},	553	},
		554	{
		555	.compatible = "xlnx,zynqmp-8.9a",
		556	.data = &sdhci_arasan_data,
		557	},
505	{ /* sentinel */ }	558	{ /* sentinel */ }
506	};	559	};
507	MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);	560	MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);
@@ -520,8 +573,10 @@ static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw, · 12 unmodified lines
520	unsigned long parent_rate)	573	unsigned long parent_rate)
521		574
522	{	575	{
		576	struct sdhci_arasan_clk_data *clk_data =
		577	container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
523	struct sdhci_arasan_data *sdhci_arasan =	578	struct sdhci_arasan_data *sdhci_arasan =
524	container_of(hw, struct sdhci_arasan_data, sdcardclk_hw);	579	container_of(clk_data, struct sdhci_arasan_data, clk_data);
525	struct sdhci_host *host = sdhci_arasan->host;	580	struct sdhci_host *host = sdhci_arasan->host;
526		581
527	return host->mmc->actual_clock;	582	return host->mmc->actual_clock;
@@ -531,6 +586,177 @@ static const struct clk_ops arasan_sdcardclk_ops = { · 3 unmodified lines
531	.recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,	586	.recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
532	};	587	};
533		588
		589	/**
		590	* sdhci_arasan_sampleclk_recalc_rate - Return the sampling clock rate
		591	*
		592	* Return the current actual rate of the sampling clock. This can be used
		593	* to communicate with out PHY.
		594	*
		595	* @hw: Pointer to the hardware clock structure.
		596	* @parent_rate The parent rate (should be rate of clk_xin).
		597	* Returns the sample clock rate.
		598	*/
		599	static unsigned long sdhci_arasan_sampleclk_recalc_rate(struct clk_hw *hw,
		600	unsigned long parent_rate)
		601
		602	{
		603	struct sdhci_arasan_clk_data *clk_data =
		604	container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
		605	struct sdhci_arasan_data *sdhci_arasan =
		606	container_of(clk_data, struct sdhci_arasan_data, clk_data);
		607	struct sdhci_host *host = sdhci_arasan->host;
		608
		609	return host->mmc->actual_clock;
		610	}
		611
		612	static const struct clk_ops arasan_sampleclk_ops = {
		613	.recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
		614	};
		615
		616	/**
		617	* sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
		618	*
		619	* Set the SD Output Clock Tap Delays for Output path
		620	*
		621	* @hw: Pointer to the hardware clock structure.
		622	* @degrees The clock phase shift between 0 - 359.
		623	* Return: 0 on success and error value on error
		624	*/
		625	static int sdhci_zynqmp_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
		626
		627	{
		628	struct sdhci_arasan_clk_data *clk_data =
		629	container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
		630	struct sdhci_arasan_data *sdhci_arasan =
		631	container_of(clk_data, struct sdhci_arasan_data, clk_data);
		632	struct sdhci_host *host = sdhci_arasan->host;
		633	struct sdhci_arasan_zynqmp_clk_data *zynqmp_clk_data =
		634	clk_data->clk_of_data;
		635	const struct zynqmp_eemi_ops *eemi_ops = zynqmp_clk_data->eemi_ops;
		636	const char *clk_name = clk_hw_get_name(hw);
		637	u32 node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1;
		638	u8 tap_delay, tap_max = 0;
		639	int ret;
		640
		641	/*
		642	* This is applicable for SDHCI_SPEC_300 and above
		643	* ZynqMP does not set phase for <=25MHz clock.
		644	* If degrees is zero, no need to do anything.
		645	*/
		646	if (host->version < SDHCI_SPEC_300 \|\|
		647	host->timing == MMC_TIMING_LEGACY \|\|
		648	host->timing == MMC_TIMING_UHS_SDR12 \|\| !degrees)
		649	return 0;
		650
		651	switch (host->timing) {
		652	case MMC_TIMING_MMC_HS:
		653	case MMC_TIMING_SD_HS:
		654	case MMC_TIMING_UHS_SDR25:
		655	case MMC_TIMING_UHS_DDR50:
		656	case MMC_TIMING_MMC_DDR52:
		657	/* For 50MHz clock, 30 Taps are available */
		658	tap_max = 30;
		659	break;
		660	case MMC_TIMING_UHS_SDR50:
		661	/* For 100MHz clock, 15 Taps are available */
		662	tap_max = 15;
		663	break;
		664	case MMC_TIMING_UHS_SDR104:
		665	case MMC_TIMING_MMC_HS200:
		666	/* For 200MHz clock, 8 Taps are available */
		667	tap_max = 8;
		668	default:
		669	break;
		670	}
		671
		672	tap_delay = (degrees * tap_max) / 360;
		673
		674	/* Set the Clock Phase */
		675	ret = eemi_ops->ioctl(node_id, IOCTL_SET_SD_TAPDELAY,
		676	PM_TAPDELAY_OUTPUT, tap_delay, NULL);
		677	if (ret)
		678	pr_err("Error setting Output Tap Delay\n");
		679
		680	return ret;
		681	}
		682
		683	static const struct clk_ops zynqmp_sdcardclk_ops = {
		684	.recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
		685	.set_phase = sdhci_zynqmp_sdcardclk_set_phase,
		686	};
		687
		688	/**
		689	* sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
		690	*
		691	* Set the SD Input Clock Tap Delays for Input path
		692	*
		693	* @hw: Pointer to the hardware clock structure.
		694	* @degrees The clock phase shift between 0 - 359.
		695	* Return: 0 on success and error value on error
		696	*/
		697	static int sdhci_zynqmp_sampleclk_set_phase(struct clk_hw *hw, int degrees)
		698
		699	{
		700	struct sdhci_arasan_clk_data *clk_data =
		701	container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
		702	struct sdhci_arasan_data *sdhci_arasan =
		703	container_of(clk_data, struct sdhci_arasan_data, clk_data);
		704	struct sdhci_host *host = sdhci_arasan->host;
		705	struct sdhci_arasan_zynqmp_clk_data *zynqmp_clk_data =
		706	clk_data->clk_of_data;
		707	const struct zynqmp_eemi_ops *eemi_ops = zynqmp_clk_data->eemi_ops;
		708	const char *clk_name = clk_hw_get_name(hw);
		709	u32 node_id = !strcmp(clk_name, "clk_in_sd0") ? NODE_SD_0 : NODE_SD_1;
		710	u8 tap_delay, tap_max = 0;
		711	int ret;
		712
		713	/*
		714	* This is applicable for SDHCI_SPEC_300 and above
		715	* ZynqMP does not set phase for <=25MHz clock.
		716	* If degrees is zero, no need to do anything.
		717	*/
		718	if (host->version < SDHCI_SPEC_300 \|\|
		719	host->timing == MMC_TIMING_LEGACY \|\|
		720	host->timing == MMC_TIMING_UHS_SDR12 \|\| !degrees)
		721	return 0;
		722
		723	switch (host->timing) {
		724	case MMC_TIMING_MMC_HS:
		725	case MMC_TIMING_SD_HS:
		726	case MMC_TIMING_UHS_SDR25:
		727	case MMC_TIMING_UHS_DDR50:
		728	case MMC_TIMING_MMC_DDR52:
		729	/* For 50MHz clock, 120 Taps are available */
		730	tap_max = 120;
		731	break;
		732	case MMC_TIMING_UHS_SDR50:
		733	/* For 100MHz clock, 60 Taps are available */
		734	tap_max = 60;
		735	break;
		736	case MMC_TIMING_UHS_SDR104:
		737	case MMC_TIMING_MMC_HS200:
		738	/* For 200MHz clock, 30 Taps are available */
		739	tap_max = 30;
		740	default:
		741	break;
		742	}
		743
		744	tap_delay = (degrees * tap_max) / 360;
		745
		746	/* Set the Clock Phase */
		747	ret = eemi_ops->ioctl(node_id, IOCTL_SET_SD_TAPDELAY,
		748	PM_TAPDELAY_INPUT, tap_delay, NULL);
		749	if (ret)
		750	pr_err("Error setting Input Tap Delay\n");
		751
		752	return ret;
		753	}
		754
		755	static const struct clk_ops zynqmp_sampleclk_ops = {
		756	.recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
		757	.set_phase = sdhci_zynqmp_sampleclk_set_phase,
		758	};
		759
534	/**	760	/**
535	* sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier	761	* sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
536	*	762	*
@@ -609,39 +835,128 @@ static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host) · 72 unmodified lines
609	sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);	835	sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);
610	}	836	}
611		837
		838	static void sdhci_arasan_set_clk_delays(struct sdhci_host *host)
		839	{
		840	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
		841	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
		842	struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
		843
		844	clk_set_phase(clk_data->sampleclk,
		845	clk_data->clk_phase_in[host->timing]);
		846	clk_set_phase(clk_data->sdcardclk,
		847	clk_data->clk_phase_out[host->timing]);
		848	}
		849
		850	static void arasan_dt_read_clk_phase(struct device *dev,
		851	struct sdhci_arasan_clk_data *clk_data,
		852	unsigned int timing, const char *prop)
		853	{
		854	struct device_node *np = dev->of_node;
		855
		856	int clk_phase[2] = {0};
		857
		858	/*
		859	* Read Tap Delay values from DT, if the DT does not contain the
		860	* Tap Values then use the pre-defined values.
		861	*/
		862	if (of_property_read_variable_u32_array(np, prop, &clk_phase[0],
		863	2, 0)) {
		864	dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n",
		865	prop, clk_data->clk_phase_in[timing],
		866	clk_data->clk_phase_out[timing]);
		867	return;
		868	}
		869
		870	/* The values read are Input and Output Clock Delays in order */
		871	clk_data->clk_phase_in[timing] = clk_phase[0];
		872	clk_data->clk_phase_out[timing] = clk_phase[1];
		873	}
		874
612	/**	875	/**
613	* sdhci_arasan_register_sdclk - Register the sdclk for a PHY to use	876	* arasan_dt_parse_clk_phases - Read Clock Delay values from DT
		877	*
		878	* Called at initialization to parse the values of Clock Delays.
		879	*
		880	* @dev: Pointer to our struct device.
		881	* @clk_data: Pointer to the Clock Data structure
		882	*/
		883	static void arasan_dt_parse_clk_phases(struct device *dev,
		884	struct sdhci_arasan_clk_data *clk_data)
		885	{
		886	int iclk_phase, oclk_phase;
		887	u32 mio_bank = 0;
		888	int i;
		889
		890	/*
		891	* This has been kept as a pointer and is assigned a function here.
		892	* So that different controller variants can assign their own handling
		893	* function.
		894	*/
		895	clk_data->set_clk_delays = sdhci_arasan_set_clk_delays;
		896
		897	if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) {
		898	iclk_phase = (int [MMC_TIMING_MMC_HS400 + 1]) ZYNQMP_ICLK_PHASE;
		899	oclk_phase = (int [MMC_TIMING_MMC_HS400 + 1]) ZYNQMP_OCLK_PHASE;
		900
		901	of_property_read_u32(dev->of_node, "xlnx,mio-bank", &mio_bank);
		902	if (mio_bank == 2) {
		903	oclk_phase[MMC_TIMING_UHS_SDR104] = 90;
		904	oclk_phase[MMC_TIMING_MMC_HS200] = 90;
		905	}
		906
		907	for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
		908	clk_data->clk_phase_in[i] = iclk_phase[i];
		909	clk_data->clk_phase_out[i] = oclk_phase[i];
		910	}
		911	}
		912
		913	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_LEGACY,
		914	"clk-phase-legacy");
		915	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS,
		916	"clk-phase-mmc-hs");
		917	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_SD_HS,
		918	"clk-phase-sd-hs");
		919	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR12,
		920	"clk-phase-uhs-sdr12");
		921	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR25,
		922	"clk-phase-uhs-sdr25");
		923	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR50,
		924	"clk-phase-uhs-sdr50");
		925	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR104,
		926	"clk-phase-uhs-sdr104");
		927	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_DDR50,
		928	"clk-phase-uhs-ddr50");
		929	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_DDR52,
		930	"clk-phase-mmc-ddr52");
		931	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS200,
		932	"clk-phase-mmc-hs200");
		933	arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS400,
		934	"clk-phase-mmc-hs400");
		935	}
		936
		937	/**
		938	* sdhci_arasan_register_sdcardclk - Register the sdcardclk for a PHY to use
614	*	939	*
615	* Some PHY devices need to know what the actual card clock is. In order for	940	* Some PHY devices need to know what the actual card clock is. In order for
616	* them to find out, we'll provide a clock through the common clock framework	941	* them to find out, we'll provide a clock through the common clock framework
617	* for them to query.	942	* for them to query.
618	*	943	*
619	* Note: without seriously re-architecting SDHCI's clock code and testing on
620	* all platforms, there's no way to create a totally beautiful clock here
621	* with all clock ops implemented. Instead, we'll just create a clock that can
622	* be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
623	* framework that we're doing things behind its back. This should be sufficient
624	* to create nice clean device tree bindings and later (if needed) we can try
625	* re-architecting SDHCI if we see some benefit to it.
626	*
627	* @sdhci_arasan: Our private data structure.	944	* @sdhci_arasan: Our private data structure.
628	* @clk_xin: Pointer to the functional clock	945	* @clk_xin: Pointer to the functional clock
629	* @dev: Pointer to our struct device.	946	* @dev: Pointer to our struct device.
630	* Returns 0 on success and error value on error	947	* Returns 0 on success and error value on error
631	*/	948	*/
632	static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,	949	static int
633	struct clk *clk_xin,	950	sdhci_arasan_register_sdcardclk(struct sdhci_arasan_data *sdhci_arasan,
634	struct device *dev)	951	struct clk *clk_xin,
		952	struct device *dev)
635	{	953	{
		954	struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
636	struct device_node *np = dev->of_node;	955	struct device_node *np = dev->of_node;
637	struct clk_init_data sdcardclk_init;	956	struct clk_init_data sdcardclk_init;
638	const char *parent_clk_name;	957	const char *parent_clk_name;
639	int ret;	958	int ret;
640		959
641	/* Providing a clock to the PHY is optional; no error if missing */
642	if (!of_find_property(np, "#clock-cells", NULL))
643	return 0;
644
645	ret = of_property_read_string_index(np, "clock-output-names", 0,	960	ret = of_property_read_string_index(np, "clock-output-names", 0,
646	&sdcardclk_init.name);	961	&sdcardclk_init.name);
647	if (ret) {	962	if (ret) {
@@ -653,17 +968,72 @@ static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan, · 5 unmodified lines
653	sdcardclk_init.parent_names = &parent_clk_name;	968	sdcardclk_init.parent_names = &parent_clk_name;
654	sdcardclk_init.num_parents = 1;	969	sdcardclk_init.num_parents = 1;
655	sdcardclk_init.flags = CLK_GET_RATE_NOCACHE;	970	sdcardclk_init.flags = CLK_GET_RATE_NOCACHE;
656	sdcardclk_init.ops = &arasan_sdcardclk_ops;	971	if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a"))
		972	sdcardclk_init.ops = &zynqmp_sdcardclk_ops;
		973	else
		974	sdcardclk_init.ops = &arasan_sdcardclk_ops;
		975
		976	clk_data->sdcardclk_hw.init = &sdcardclk_init;
		977	clk_data->sdcardclk =
		978	devm_clk_register(dev, &clk_data->sdcardclk_hw);
		979	clk_data->sdcardclk_hw.init = NULL;
		980
		981	ret = of_clk_add_provider(np, of_clk_src_simple_get,
		982	clk_data->sdcardclk);
		983	if (ret)
		984	dev_err(dev, "Failed to add sdcard clock provider\n");
		985
		986	return ret;
		987	}
		988
		989	/**
		990	* sdhci_arasan_register_sampleclk - Register the sampleclk for a PHY to use
		991	*
		992	* Some PHY devices need to know what the actual card clock is. In order for
		993	* them to find out, we'll provide a clock through the common clock framework
		994	* for them to query.
		995	*
		996	* @sdhci_arasan: Our private data structure.
		997	* @clk_xin: Pointer to the functional clock
		998	* @dev: Pointer to our struct device.
		999	* Returns 0 on success and error value on error
		1000	*/
		1001	static int
		1002	sdhci_arasan_register_sampleclk(struct sdhci_arasan_data *sdhci_arasan,
		1003	struct clk *clk_xin,
		1004	struct device *dev)
		1005	{
		1006	struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
		1007	struct device_node *np = dev->of_node;
		1008	struct clk_init_data sampleclk_init;
		1009	const char *parent_clk_name;
		1010	int ret;
657		1011
658	sdhci_arasan->sdcardclk_hw.init = &sdcardclk_init;	1012	ret = of_property_read_string_index(np, "clock-output-names", 1,
659	sdhci_arasan->sdcardclk =	1013	&sampleclk_init.name);
660	devm_clk_register(dev, &sdhci_arasan->sdcardclk_hw);	1014	if (ret) {
661	sdhci_arasan->sdcardclk_hw.init = NULL;	1015	dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
		1016	return ret;
		1017	}
		1018
		1019	parent_clk_name = __clk_get_name(clk_xin);
		1020	sampleclk_init.parent_names = &parent_clk_name;
		1021	sampleclk_init.num_parents = 1;
		1022	sampleclk_init.flags = CLK_GET_RATE_NOCACHE;
		1023	if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a"))
		1024	sampleclk_init.ops = &zynqmp_sampleclk_ops;
		1025	else
		1026	sampleclk_init.ops = &arasan_sampleclk_ops;
		1027
		1028	clk_data->sampleclk_hw.init = &sampleclk_init;
		1029	clk_data->sampleclk =
		1030	devm_clk_register(dev, &clk_data->sampleclk_hw);
		1031	clk_data->sampleclk_hw.init = NULL;
662		1032
663	ret = of_clk_add_provider(np, of_clk_src_simple_get,	1033	ret = of_clk_add_provider(np, of_clk_src_simple_get,
664	sdhci_arasan->sdcardclk);	1034	clk_data->sampleclk);
665	if (ret)	1035	if (ret)
666	dev_err(dev, "Failed to add clock provider\n");	1036	dev_err(dev, "Failed to add sample clock provider\n");
667		1037
668	return ret;	1038	return ret;
669	}	1039	}
@@ -686,6 +1056,54 @@ static void sdhci_arasan_unregister_sdclk(struct device *dev) · 16 unmodified lines
686	of_clk_del_provider(dev->of_node);	1056	of_clk_del_provider(dev->of_node);
687	}	1057	}
688		1058
		1059	/**
		1060	* sdhci_arasan_register_sdclk - Register the sdcardclk for a PHY to use
		1061	*
		1062	* Some PHY devices need to know what the actual card clock is. In order for
		1063	* them to find out, we'll provide a clock through the common clock framework
		1064	* for them to query.
		1065	*
		1066	* Note: without seriously re-architecting SDHCI's clock code and testing on
		1067	* all platforms, there's no way to create a totally beautiful clock here
		1068	* with all clock ops implemented. Instead, we'll just create a clock that can
		1069	* be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
		1070	* framework that we're doing things behind its back. This should be sufficient
		1071	* to create nice clean device tree bindings and later (if needed) we can try
		1072	* re-architecting SDHCI if we see some benefit to it.
		1073	*
		1074	* @sdhci_arasan: Our private data structure.
		1075	* @clk_xin: Pointer to the functional clock
		1076	* @dev: Pointer to our struct device.
		1077	* Returns 0 on success and error value on error
		1078	*/
		1079	static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,
		1080	struct clk *clk_xin,
		1081	struct device *dev)
		1082	{
		1083	struct device_node *np = dev->of_node;
		1084	u32 num_clks = 0;
		1085	int ret;
		1086
		1087	/* Providing a clock to the PHY is optional; no error if missing */
		1088	if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0)
		1089	return 0;
		1090
		1091	ret = sdhci_arasan_register_sdcardclk(sdhci_arasan, clk_xin, dev);
		1092	if (ret)
		1093	return ret;
		1094
		1095	if (num_clks) {
		1096	ret = sdhci_arasan_register_sampleclk(sdhci_arasan, clk_xin,
		1097	dev);
		1098	if (ret) {
		1099	sdhci_arasan_unregister_sdclk(dev);
		1100	return ret;
		1101	}
		1102	}
		1103
		1104	return 0;
		1105	}
		1106
689	static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan)	1107	static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan)
690	{	1108	{
691	struct sdhci_host *host = sdhci_arasan->host;	1109	struct sdhci_host *host = sdhci_arasan->host;
@@ -814,6 +1232,25 @@ static int sdhci_arasan_probe(struct platform_device *pdev) · 122 unmodified lines
814	if (ret)	1232	if (ret)
815	goto clk_disable_all;	1233	goto clk_disable_all;
816		1234
		1235	if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) {
		1236	struct sdhci_arasan_zynqmp_clk_data *zynqmp_clk_data;
		1237	const struct zynqmp_eemi_ops *eemi_ops;
		1238
		1239	zynqmp_clk_data = devm_kzalloc(&pdev->dev,
		1240	sizeof(*zynqmp_clk_data),
		1241	GFP_KERNEL);
		1242	eemi_ops = zynqmp_pm_get_eemi_ops();
		1243	if (IS_ERR(eemi_ops)) {
		1244	ret = PTR_ERR(eemi_ops);
		1245	goto unreg_clk;
		1246	}
		1247
		1248	zynqmp_clk_data->eemi_ops = eemi_ops;
		1249	sdhci_arasan->clk_data.clk_of_data = zynqmp_clk_data;
		1250	}
		1251
		1252	arasan_dt_parse_clk_phases(&pdev->dev, &sdhci_arasan->clk_data);
		1253
817	ret = mmc_of_parse(host->mmc);	1254	ret = mmc_of_parse(host->mmc);
818	if (ret) {	1255	if (ret) {
819	if (ret != -EPROBE_DEFER)	1256	if (ret != -EPROBE_DEFER)

drivers/mmc/host/sdhci-of-aspeed.c+12−0

@@ -111,7 +111,19 @@ static void aspeed_sdhci_set_bus_width(struct sdhci_host *host, int width) · 110 unmodified lines
111	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);	111	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
112	}	112	}
113		113
		114	static u32 aspeed_sdhci_readl(struct sdhci_host *host, int reg)
		115	{
		116	u32 val = readl(host->ioaddr + reg);
		117
		118	if (unlikely(reg == SDHCI_PRESENT_STATE) &&
		119	(host->mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH))
		120	val ^= SDHCI_CARD_PRESENT;
		121
		122	return val;
		123	}
		124
114	static const struct sdhci_ops aspeed_sdhci_ops = {	125	static const struct sdhci_ops aspeed_sdhci_ops = {
		126	.read_l = aspeed_sdhci_readl,
115	.set_clock = aspeed_sdhci_set_clock,	127	.set_clock = aspeed_sdhci_set_clock,
116	.get_max_clock = aspeed_sdhci_get_max_clock,	128	.get_max_clock = aspeed_sdhci_get_max_clock,
117	.set_bus_width = aspeed_sdhci_set_bus_width,	129	.set_bus_width = aspeed_sdhci_set_bus_width,

drivers/mmc/host/sdhci-of-at91.c+19−0

 #define SDMMC_CACR	0x230
 #define		SDMMC_CACR_CAPWREN	BIT(0)
 #define		SDMMC_CACR_KEY		(0x46 << 8)
+#define SDMMC_CALCR	0x240
+#define		SDMMC_CALCR_EN		BIT(0)
+#define		SDMMC_CALCR_ALWYSON	BIT(4)
 #define SDHCI_AT91_PRESET_COMMON_CONF	0x400 /* drv type B, programmable clock mode */
 	struct clk *gck;
 	struct clk *mainck;
 	bool restore_needed;
+	bool cal_always_on;
 };
 static void sdhci_at91_set_force_card_detect(struct sdhci_host *host)
 static void sdhci_at91_reset(struct sdhci_host *host, u8 mask)
 {
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
 	sdhci_reset(host, mask);
 	if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
 		sdhci_at91_set_force_card_detect(host);
+	if (priv->cal_always_on && (mask & SDHCI_RESET_ALL))
+		sdhci_writel(host, SDMMC_CALCR_ALWYSON | SDMMC_CALCR_EN,
+			     SDMMC_CALCR);
 }
 static const struct sdhci_ops sdhci_at91_sama5d2_ops = {
 	priv->restore_needed = false;
+	/*
+	 * if SDCAL pin is wrongly connected, we must enable
+	 * the analog calibration cell permanently.
+	 */
+	priv->cal_always_on =
+		device_property_read_bool(&pdev->dev,
+					  "microchip,sdcal-inverted");
 	ret = mmc_of_parse(host->mmc);
 	if (ret)
 		goto clocks_disable_unprepare;

drivers/mmc/host/sdhci-of-esdhc.c+217−40

@@ -77,8 +77,10 @@ struct sdhci_esdhc { · 76 unmodified lines
77	bool quirk_incorrect_hostver;	77	bool quirk_incorrect_hostver;
78	bool quirk_limited_clk_division;	78	bool quirk_limited_clk_division;
79	bool quirk_unreliable_pulse_detection;	79	bool quirk_unreliable_pulse_detection;
80	bool quirk_fixup_tuning;	80	bool quirk_tuning_erratum_type1;
		81	bool quirk_tuning_erratum_type2;
81	bool quirk_ignore_data_inhibit;	82	bool quirk_ignore_data_inhibit;
		83	bool in_sw_tuning;
82	unsigned int peripheral_clock;	84	unsigned int peripheral_clock;
83	const struct esdhc_clk_fixup *clk_fixup;	85	const struct esdhc_clk_fixup *clk_fixup;
84	u32 div_ratio;	86	u32 div_ratio;
@@ -408,6 +410,8 @@ static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg) · 323 unmodified lines
408		410
409	static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg)	411	static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg)
410	{	412	{
		413	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
		414	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
411	int base = reg & ~0x3;	415	int base = reg & ~0x3;
412	u32 value;	416	u32 value;
413	u32 ret;	417	u32 ret;
@@ -416,10 +420,24 @@ static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg) · 2 unmodified lines
416	ret = esdhc_writew_fixup(host, reg, val, value);	420	ret = esdhc_writew_fixup(host, reg, val, value);
417	if (reg != SDHCI_TRANSFER_MODE)	421	if (reg != SDHCI_TRANSFER_MODE)
418	iowrite32be(ret, host->ioaddr + base);	422	iowrite32be(ret, host->ioaddr + base);
		423
		424	/* Starting SW tuning requires ESDHC_SMPCLKSEL to be set
		425	* 1us later after ESDHC_EXTN is set.
		426	*/
		427	if (base == ESDHC_SYSTEM_CONTROL_2) {
		428	if (!(value & ESDHC_EXTN) && (ret & ESDHC_EXTN) &&
		429	esdhc->in_sw_tuning) {
		430	udelay(1);
		431	ret \|= ESDHC_SMPCLKSEL;
		432	iowrite32be(ret, host->ioaddr + base);
		433	}
		434	}
419	}	435	}
420		436
421	static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg)	437	static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg)
422	{	438	{
		439	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
		440	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
423	int base = reg & ~0x3;	441	int base = reg & ~0x3;
424	u32 value;	442	u32 value;
425	u32 ret;	443	u32 ret;
@@ -428,6 +446,18 @@ static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg) · 2 unmodified lines
428	ret = esdhc_writew_fixup(host, reg, val, value);	446	ret = esdhc_writew_fixup(host, reg, val, value);
429	if (reg != SDHCI_TRANSFER_MODE)	447	if (reg != SDHCI_TRANSFER_MODE)
430	iowrite32(ret, host->ioaddr + base);	448	iowrite32(ret, host->ioaddr + base);
		449
		450	/* Starting SW tuning requires ESDHC_SMPCLKSEL to be set
		451	* 1us later after ESDHC_EXTN is set.
		452	*/
		453	if (base == ESDHC_SYSTEM_CONTROL_2) {
		454	if (!(value & ESDHC_EXTN) && (ret & ESDHC_EXTN) &&
		455	esdhc->in_sw_tuning) {
		456	udelay(1);
		457	ret \|= ESDHC_SMPCLKSEL;
		458	iowrite32(ret, host->ioaddr + base);
		459	}
		460	}
431	}	461	}
432		462
433	static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg)	463	static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg)
@@ -560,6 +590,32 @@ static void esdhc_clock_enable(struct sdhci_host *host, bool enable) · 126 unmodified lines
560	}	590	}
561	}	591	}
562		592
		593	static void esdhc_flush_async_fifo(struct sdhci_host *host)
		594	{
		595	ktime_t timeout;
		596	u32 val;
		597
		598	val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
		599	val \|= ESDHC_FLUSH_ASYNC_FIFO;
		600	sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
		601
		602	/* Wait max 20 ms */
		603	timeout = ktime_add_ms(ktime_get(), 20);
		604	while (1) {
		605	bool timedout = ktime_after(ktime_get(), timeout);
		606
		607	if (!(sdhci_readl(host, ESDHC_DMA_SYSCTL) &
		608	ESDHC_FLUSH_ASYNC_FIFO))
		609	break;
		610	if (timedout) {
		611	pr_err("%s: flushing asynchronous FIFO timeout.\n",
		612	mmc_hostname(host->mmc));
		613	break;
		614	}
		615	usleep_range(10, 20);
		616	}
		617	}
		618
563	static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)	619	static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
564	{	620	{
565	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);	621	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
@@ -652,9 +708,7 @@ static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock) · 86 unmodified lines
652	sdhci_writel(host, temp \| ESDHC_HS400_WNDW_ADJUST, ESDHC_TBCTL);	708	sdhci_writel(host, temp \| ESDHC_HS400_WNDW_ADJUST, ESDHC_TBCTL);
653		709
654	esdhc_clock_enable(host, false);	710	esdhc_clock_enable(host, false);
655	temp = sdhci_readl(host, ESDHC_DMA_SYSCTL);	711	esdhc_flush_async_fifo(host);
656	temp \|= ESDHC_FLUSH_ASYNC_FIFO;
657	sdhci_writel(host, temp, ESDHC_DMA_SYSCTL);
658	}	712	}
659		713
660	/* Wait max 20 ms */	714	/* Wait max 20 ms */
@@ -796,16 +850,21 @@ static int esdhc_signal_voltage_switch(struct mmc_host *mmc, · 135 unmodified lines
796	}	850	}
797	}	851	}
798		852
799	static struct soc_device_attribute soc_fixup_tuning[] = {	853	static struct soc_device_attribute soc_tuning_erratum_type1[] = {
		854	{ .family = "QorIQ T1023", .revision = "1.0", },
800	{ .family = "QorIQ T1040", .revision = "1.0", },	855	{ .family = "QorIQ T1040", .revision = "1.0", },
801	{ .family = "QorIQ T2080", .revision = "1.0", },	856	{ .family = "QorIQ T2080", .revision = "1.0", },
802	{ .family = "QorIQ T1023", .revision = "1.0", },
803	{ .family = "QorIQ LS1021A", .revision = "1.0", },	857	{ .family = "QorIQ LS1021A", .revision = "1.0", },
804	{ .family = "QorIQ LS1080A", .revision = "1.0", },	858	{ },
805	{ .family = "QorIQ LS2080A", .revision = "1.0", },	859	};
		860
		861	static struct soc_device_attribute soc_tuning_erratum_type2[] = {
806	{ .family = "QorIQ LS1012A", .revision = "1.0", },	862	{ .family = "QorIQ LS1012A", .revision = "1.0", },
807	{ .family = "QorIQ LS1043A", .revision = "1.*", },	863	{ .family = "QorIQ LS1043A", .revision = "1.*", },
808	{ .family = "QorIQ LS1046A", .revision = "1.0", },	864	{ .family = "QorIQ LS1046A", .revision = "1.0", },
		865	{ .family = "QorIQ LS1080A", .revision = "1.0", },
		866	{ .family = "QorIQ LS2080A", .revision = "1.0", },
		867	{ .family = "QorIQ LA1575A", .revision = "1.0", },
809	{ },	868	{ },
810	};	869	};
811		870
@@ -814,10 +873,7 @@ static void esdhc_tuning_block_enable(struct sdhci_host *host, bool enable) · 2 unmodified lines
814	u32 val;	873	u32 val;
815		874
816	esdhc_clock_enable(host, false);	875	esdhc_clock_enable(host, false);
817		876	esdhc_flush_async_fifo(host);
818	val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
819	val \|= ESDHC_FLUSH_ASYNC_FIFO;
820	sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
821		877
822	val = sdhci_readl(host, ESDHC_TBCTL);	878	val = sdhci_readl(host, ESDHC_TBCTL);
823	if (enable)	879	if (enable)
@@ -829,15 +885,97 @@ static void esdhc_tuning_block_enable(struct sdhci_host *host, bool enable) · 5 unmodified lines
829	esdhc_clock_enable(host, true);	885	esdhc_clock_enable(host, true);
830	}	886	}
831		887
		888	static void esdhc_prepare_sw_tuning(struct sdhci_host host, u8 window_start,
		889	u8 *window_end)
		890	{
		891	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
		892	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
		893	u8 tbstat_15_8, tbstat_7_0;
		894	u32 val;
		895
		896	if (esdhc->quirk_tuning_erratum_type1) {
		897	window_start = 5 esdhc->div_ratio;
		898	window_end = 3 esdhc->div_ratio;
		899	return;
		900	}
		901
		902	/* Write TBCTL[11:8]=4'h8 */
		903	val = sdhci_readl(host, ESDHC_TBCTL);
		904	val &= ~(0xf << 8);
		905	val \|= 8 << 8;
		906	sdhci_writel(host, val, ESDHC_TBCTL);
		907
		908	mdelay(1);
		909
		910	/* Read TBCTL[31:0] register and rewrite again */
		911	val = sdhci_readl(host, ESDHC_TBCTL);
		912	sdhci_writel(host, val, ESDHC_TBCTL);
		913
		914	mdelay(1);
		915
		916	/* Read the TBSTAT[31:0] register twice */
		917	val = sdhci_readl(host, ESDHC_TBSTAT);
		918	val = sdhci_readl(host, ESDHC_TBSTAT);
		919
		920	/* Reset data lines by setting ESDHCCTL[RSTD] */
		921	sdhci_reset(host, SDHCI_RESET_DATA);
		922	/* Write 32'hFFFF_FFFF to IRQSTAT register */
		923	sdhci_writel(host, 0xFFFFFFFF, SDHCI_INT_STATUS);
		924
		925	/* If TBSTAT[15:8]-TBSTAT[7:0] > 4 * div_ratio
		926	* or TBSTAT[7:0]-TBSTAT[15:8] > 4 * div_ratio,
		927	* then program TBPTR[TB_WNDW_END_PTR] = 4 * div_ratio
		928	* and program TBPTR[TB_WNDW_START_PTR] = 8 * div_ratio.
		929	*/
		930	tbstat_7_0 = val & 0xff;
		931	tbstat_15_8 = (val >> 8) & 0xff;
		932
		933	if (abs(tbstat_15_8 - tbstat_7_0) > (4 * esdhc->div_ratio)) {
		934	window_start = 8 esdhc->div_ratio;
		935	window_end = 4 esdhc->div_ratio;
		936	} else {
		937	window_start = 5 esdhc->div_ratio;
		938	window_end = 3 esdhc->div_ratio;
		939	}
		940	}
		941
		942	static int esdhc_execute_sw_tuning(struct mmc_host *mmc, u32 opcode,
		943	u8 window_start, u8 window_end)
		944	{
		945	struct sdhci_host *host = mmc_priv(mmc);
		946	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
		947	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
		948	u32 val;
		949	int ret;
		950
		951	/* Program TBPTR[TB_WNDW_END_PTR] and TBPTR[TB_WNDW_START_PTR] */
		952	val = ((u32)window_start << ESDHC_WNDW_STRT_PTR_SHIFT) &
		953	ESDHC_WNDW_STRT_PTR_MASK;
		954	val \|= window_end & ESDHC_WNDW_END_PTR_MASK;
		955	sdhci_writel(host, val, ESDHC_TBPTR);
		956
		957	/* Program the software tuning mode by setting TBCTL[TB_MODE]=2'h3 */
		958	val = sdhci_readl(host, ESDHC_TBCTL);
		959	val &= ~ESDHC_TB_MODE_MASK;
		960	val \|= ESDHC_TB_MODE_SW;
		961	sdhci_writel(host, val, ESDHC_TBCTL);
		962
		963	esdhc->in_sw_tuning = true;
		964	ret = sdhci_execute_tuning(mmc, opcode);
		965	esdhc->in_sw_tuning = false;
		966	return ret;
		967	}
		968
832	static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)	969	static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
833	{	970	{
834	struct sdhci_host *host = mmc_priv(mmc);	971	struct sdhci_host *host = mmc_priv(mmc);
835	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);	972	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
836	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);	973	struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
		974	u8 window_start, window_end;
		975	int ret, retries = 1;
837	bool hs400_tuning;	976	bool hs400_tuning;
838	unsigned int clk;	977	unsigned int clk;
839	u32 val;	978	u32 val;
840	int ret;
841		979
842	/* For tuning mode, the sd clock divisor value	980	/* For tuning mode, the sd clock divisor value
843	* must be larger than 3 according to reference manual.	981	* must be larger than 3 according to reference manual.
@@ -846,39 +984,73 @@ static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) · 2 unmodified lines
846	if (host->clock > clk)	984	if (host->clock > clk)
847	esdhc_of_set_clock(host, clk);	985	esdhc_of_set_clock(host, clk);
848		986
849	if (esdhc->quirk_limited_clk_division &&
850	host->flags & SDHCI_HS400_TUNING)
851	esdhc_of_set_clock(host, host->clock);
852
853	esdhc_tuning_block_enable(host, true);	987	esdhc_tuning_block_enable(host, true);
854		988
855	hs400_tuning = host->flags & SDHCI_HS400_TUNING;	989	hs400_tuning = host->flags & SDHCI_HS400_TUNING;
856	ret = sdhci_execute_tuning(mmc, opcode);
857		990
858	if (hs400_tuning) {	991	do {
859	val = sdhci_readl(host, ESDHC_SDTIMNGCTL);	992	if (esdhc->quirk_limited_clk_division &&
860	val \|= ESDHC_FLW_CTL_BG;	993	hs400_tuning)
861	sdhci_writel(host, val, ESDHC_SDTIMNGCTL);	994	esdhc_of_set_clock(host, host->clock);
862	}
863		995
864	if (host->tuning_err == -EAGAIN && esdhc->quirk_fixup_tuning) {	996	/* Do HW tuning */
		997	val = sdhci_readl(host, ESDHC_TBCTL);
		998	val &= ~ESDHC_TB_MODE_MASK;
		999	val \|= ESDHC_TB_MODE_3;
		1000	sdhci_writel(host, val, ESDHC_TBCTL);
865		1001
866	/* program TBPTR[TB_WNDW_END_PTR] = 3*DIV_RATIO and	1002	ret = sdhci_execute_tuning(mmc, opcode);
867	* program TBPTR[TB_WNDW_START_PTR] = 5*DIV_RATIO	1003	if (ret)
868	*/	1004	break;
869	val = sdhci_readl(host, ESDHC_TBPTR);
870	val = (val & ~((0x7f << 8) \| 0x7f)) \|
871	(3 * esdhc->div_ratio) \| ((5 * esdhc->div_ratio) << 8);
872	sdhci_writel(host, val, ESDHC_TBPTR);
873		1005
874	/* program the software tuning mode by setting	1006	/* If HW tuning fails and triggers erratum,
875	* TBCTL[TB_MODE]=2'h3	1007	* try workaround.
876	*/	1008	*/
877	val = sdhci_readl(host, ESDHC_TBCTL);	1009	ret = host->tuning_err;
878	val \|= 0x3;	1010	if (ret == -EAGAIN &&
879	sdhci_writel(host, val, ESDHC_TBCTL);	1011	(esdhc->quirk_tuning_erratum_type1 \|\|
880	sdhci_execute_tuning(mmc, opcode);	1012	esdhc->quirk_tuning_erratum_type2)) {
		1013	/* Recover HS400 tuning flag */
		1014	if (hs400_tuning)
		1015	host->flags \|= SDHCI_HS400_TUNING;
		1016	pr_info("%s: Hold on to use fixed sampling clock. Try SW tuning!\n",
		1017	mmc_hostname(mmc));
		1018	/* Do SW tuning */
		1019	esdhc_prepare_sw_tuning(host, &window_start,
		1020	&window_end);
		1021	ret = esdhc_execute_sw_tuning(mmc, opcode,
		1022	window_start,
		1023	window_end);
		1024	if (ret)
		1025	break;
		1026
		1027	/* Retry both HW/SW tuning with reduced clock. */
		1028	ret = host->tuning_err;
		1029	if (ret == -EAGAIN && retries) {
		1030	/* Recover HS400 tuning flag */
		1031	if (hs400_tuning)
		1032	host->flags \|= SDHCI_HS400_TUNING;
		1033
		1034	clk = host->max_clk / (esdhc->div_ratio + 1);
		1035	esdhc_of_set_clock(host, clk);
		1036	pr_info("%s: Hold on to use fixed sampling clock. Try tuning with reduced clock!\n",
		1037	mmc_hostname(mmc));
		1038	} else {
		1039	break;
		1040	}
		1041	} else {
		1042	break;
		1043	}
		1044	} while (retries--);
		1045
		1046	if (ret) {
		1047	esdhc_tuning_block_enable(host, false);
		1048	} else if (hs400_tuning) {
		1049	val = sdhci_readl(host, ESDHC_SDTIMNGCTL);
		1050	val \|= ESDHC_FLW_CTL_BG;
		1051	sdhci_writel(host, val, ESDHC_SDTIMNGCTL);
881	}	1052	}
		1053
882	return ret;	1054	return ret;
883	}	1055	}
884		1056
@@ -1114,10 +1286,15 @@ static int sdhci_esdhc_probe(struct platform_device *pdev) · 229 unmodified lines
1114		1286
1115	pltfm_host = sdhci_priv(host);	1287	pltfm_host = sdhci_priv(host);
1116	esdhc = sdhci_pltfm_priv(pltfm_host);	1288	esdhc = sdhci_pltfm_priv(pltfm_host);
1117	if (soc_device_match(soc_fixup_tuning))	1289	if (soc_device_match(soc_tuning_erratum_type1))
1118	esdhc->quirk_fixup_tuning = true;	1290	esdhc->quirk_tuning_erratum_type1 = true;
		1291	else
		1292	esdhc->quirk_tuning_erratum_type1 = false;
		1293
		1294	if (soc_device_match(soc_tuning_erratum_type2))
		1295	esdhc->quirk_tuning_erratum_type2 = true;
1119	else	1296	else
1120	esdhc->quirk_fixup_tuning = false;	1297	esdhc->quirk_tuning_erratum_type2 = false;
1121		1298
1122	if (esdhc->vendor_ver == VENDOR_V_22)	1299	if (esdhc->vendor_ver == VENDOR_V_22)
1123	host->quirks2 \|= SDHCI_QUIRK2_HOST_NO_CMD23;	1300	host->quirks2 \|= SDHCI_QUIRK2_HOST_NO_CMD23;

drivers/mmc/host/sdhci-pci-core.c+52−1

@@ -21,6 +21,7 @@ · 20 unmodified lines
21	#include <linux/mmc/mmc.h>	21	#include <linux/mmc/mmc.h>
22	#include <linux/scatterlist.h>	22	#include <linux/scatterlist.h>
23	#include <linux/io.h>	23	#include <linux/io.h>
		24	#include <linux/iopoll.h>
24	#include <linux/gpio.h>	25	#include <linux/gpio.h>
25	#include <linux/pm_runtime.h>	26	#include <linux/pm_runtime.h>
26	#include <linux/mmc/slot-gpio.h>	27	#include <linux/mmc/slot-gpio.h>
@@ -1590,11 +1591,59 @@ static int amd_probe(struct sdhci_pci_chip *chip) · 1563 unmodified lines
1590	return 0;	1591	return 0;
1591	}	1592	}
1592		1593
		1594	static u32 sdhci_read_present_state(struct sdhci_host *host)
		1595	{
		1596	return sdhci_readl(host, SDHCI_PRESENT_STATE);
		1597	}
		1598
		1599	static void amd_sdhci_reset(struct sdhci_host *host, u8 mask)
		1600	{
		1601	struct sdhci_pci_slot *slot = sdhci_priv(host);
		1602	struct pci_dev *pdev = slot->chip->pdev;
		1603	u32 present_state;
		1604
		1605	/*
		1606	* SDHC 0x7906 requires a hard reset to clear all internal state.
		1607	* Otherwise it can get into a bad state where the DATA lines are always
		1608	* read as zeros.
		1609	*/
		1610	if (pdev->device == 0x7906 && (mask & SDHCI_RESET_ALL)) {
		1611	pci_clear_master(pdev);
		1612
		1613	pci_save_state(pdev);
		1614
		1615	pci_set_power_state(pdev, PCI_D3cold);
		1616	pr_debug("%s: power_state=%u\n", mmc_hostname(host->mmc),
		1617	pdev->current_state);
		1618	pci_set_power_state(pdev, PCI_D0);
		1619
		1620	pci_restore_state(pdev);
		1621
		1622	/*
		1623	* SDHCI_RESET_ALL says the card detect logic should not be
		1624	* reset, but since we need to reset the entire controller
		1625	* we should wait until the card detect logic has stabilized.
		1626	*
		1627	* This normally takes about 40ms.
		1628	*/
		1629	readx_poll_timeout(
		1630	sdhci_read_present_state,
		1631	host,
		1632	present_state,
		1633	present_state & SDHCI_CD_STABLE,
		1634	10000,
		1635	100000
		1636	);
		1637	}
		1638
		1639	return sdhci_reset(host, mask);
		1640	}
		1641
1593	static const struct sdhci_ops amd_sdhci_pci_ops = {	1642	static const struct sdhci_ops amd_sdhci_pci_ops = {
1594	.set_clock = sdhci_set_clock,	1643	.set_clock = sdhci_set_clock,
1595	.enable_dma = sdhci_pci_enable_dma,	1644	.enable_dma = sdhci_pci_enable_dma,
1596	.set_bus_width = sdhci_set_bus_width,	1645	.set_bus_width = sdhci_set_bus_width,
1597	.reset = sdhci_reset,	1646	.reset = amd_sdhci_reset,
1598	.set_uhs_signaling = sdhci_set_uhs_signaling,	1647	.set_uhs_signaling = sdhci_set_uhs_signaling,
1599	};	1648	};
1600		1649
@@ -1673,6 +1722,8 @@ static const struct pci_device_id pci_ids[] = { · 72 unmodified lines
1673	SDHCI_PCI_DEVICE(INTEL, CML_EMMC, intel_glk_emmc),	1722	SDHCI_PCI_DEVICE(INTEL, CML_EMMC, intel_glk_emmc),
1674	SDHCI_PCI_DEVICE(INTEL, CML_SD, intel_byt_sd),	1723	SDHCI_PCI_DEVICE(INTEL, CML_SD, intel_byt_sd),
1675	SDHCI_PCI_DEVICE(INTEL, CMLH_SD, intel_byt_sd),	1724	SDHCI_PCI_DEVICE(INTEL, CMLH_SD, intel_byt_sd),
		1725	SDHCI_PCI_DEVICE(INTEL, JSL_EMMC, intel_glk_emmc),
		1726	SDHCI_PCI_DEVICE(INTEL, JSL_SD, intel_byt_sd),
1676	SDHCI_PCI_DEVICE(O2, 8120, o2),	1727	SDHCI_PCI_DEVICE(O2, 8120, o2),
1677	SDHCI_PCI_DEVICE(O2, 8220, o2),	1728	SDHCI_PCI_DEVICE(O2, 8220, o2),
1678	SDHCI_PCI_DEVICE(O2, 8221, o2),	1729	SDHCI_PCI_DEVICE(O2, 8221, o2),

drivers/mmc/host/sdhci-pci.h+2−0

@@ -55,6 +55,8 @@ · 54 unmodified lines
55	#define PCI_DEVICE_ID_INTEL_CML_EMMC 0x02c4	55	#define PCI_DEVICE_ID_INTEL_CML_EMMC 0x02c4
56	#define PCI_DEVICE_ID_INTEL_CML_SD 0x02f5	56	#define PCI_DEVICE_ID_INTEL_CML_SD 0x02f5
57	#define PCI_DEVICE_ID_INTEL_CMLH_SD 0x06f5	57	#define PCI_DEVICE_ID_INTEL_CMLH_SD 0x06f5
		58	#define PCI_DEVICE_ID_INTEL_JSL_EMMC 0x4dc4
		59	#define PCI_DEVICE_ID_INTEL_JSL_SD 0x4df8
58		60
59	#define PCI_DEVICE_ID_SYSKONNECT_8000 0x8000	61	#define PCI_DEVICE_ID_SYSKONNECT_8000 0x8000
60	#define PCI_DEVICE_ID_VIA_95D0 0x95d0	62	#define PCI_DEVICE_ID_VIA_95D0 0x95d0

drivers/mmc/host/sdhci.c+13−2

 static void sdhci_reinit(struct sdhci_host *host)
 {
+	u32 cd = host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
 	sdhci_init(host, 0);
 	sdhci_enable_card_detection(host);
+	/*
+	 * A change to the card detect bits indicates a change in present state,
+	 * refer sdhci_set_card_detection(). A card detect interrupt might have
+	 * been missed while the host controller was being reset, so trigger a
+	 * rescan to check.
+	 */
+	if (cd != (host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT)))
+		mmc_detect_change(host->mmc, msecs_to_jiffies(200));
 }
 static void __sdhci_led_activate(struct sdhci_host *host)
 		if (!(ctrl & SDHCI_CTRL_VDD_180))
 			return 0;
-		pr_warn("%s: 3.3V regulator output did not became stable\n",
+		pr_warn("%s: 3.3V regulator output did not become stable\n",
 			mmc_hostname(mmc));
 		return -EAGAIN;
 		if (ctrl & SDHCI_CTRL_VDD_180)
 			return 0;
-		pr_warn("%s: 1.8V regulator output did not became stable\n",
+		pr_warn("%s: 1.8V regulator output did not become stable\n",
 			mmc_hostname(mmc));
 		return -EAGAIN;

drivers/mmc/host/sdhci_am654.c+70−1

@@ -12,6 +12,7 @@ · 11 unmodified lines
12	#include <linux/property.h>	12	#include <linux/property.h>
13	#include <linux/regmap.h>	13	#include <linux/regmap.h>
14		14
		15	#include "cqhci.h"
15	#include "sdhci-pltfm.h"	16	#include "sdhci-pltfm.h"
16		17
17	/* CTL_CFG Registers */	18	/* CTL_CFG Registers */
@@ -68,6 +69,9 @@ · 50 unmodified lines
68		69
69	#define CLOCK_TOO_SLOW_HZ 400000	70	#define CLOCK_TOO_SLOW_HZ 400000
70		71
		72	/* Command Queue Host Controller Interface Base address */
		73	#define SDHCI_AM654_CQE_BASE_ADDR 0x200
		74
71	static struct regmap_config sdhci_am654_regmap_config = {	75	static struct regmap_config sdhci_am654_regmap_config = {
72	.reg_bits = 32,	76	.reg_bits = 32,
73	.val_bits = 32,	77	.val_bits = 32,
@@ -259,6 +263,19 @@ static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { · 185 unmodified lines
259	.flags = IOMUX_PRESENT \| FREQSEL_2_BIT \| STRBSEL_4_BIT \| DLL_PRESENT,	263	.flags = IOMUX_PRESENT \| FREQSEL_2_BIT \| STRBSEL_4_BIT \| DLL_PRESENT,
260	};	264	};
261		265
		266	static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask)
		267	{
		268	int cmd_error = 0;
		269	int data_error = 0;
		270
		271	if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
		272	return intmask;
		273
		274	cqhci_irq(host->mmc, intmask, cmd_error, data_error);
		275
		276	return 0;
		277	}
		278
262	static struct sdhci_ops sdhci_j721e_8bit_ops = {	279	static struct sdhci_ops sdhci_j721e_8bit_ops = {
263	.get_max_clock = sdhci_pltfm_clk_get_max_clock,	280	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
264	.get_timeout_clock = sdhci_pltfm_clk_get_max_clock,	281	.get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
@@ -267,6 +284,7 @@ static struct sdhci_ops sdhci_j721e_8bit_ops = { · 2 unmodified lines
267	.set_power = sdhci_am654_set_power,	284	.set_power = sdhci_am654_set_power,
268	.set_clock = sdhci_am654_set_clock,	285	.set_clock = sdhci_am654_set_clock,
269	.write_b = sdhci_am654_write_b,	286	.write_b = sdhci_am654_write_b,
		287	.irq = sdhci_am654_cqhci_irq,
270	.reset = sdhci_reset,	288	.reset = sdhci_reset,
271	};	289	};
272		290
@@ -290,6 +308,7 @@ static struct sdhci_ops sdhci_j721e_4bit_ops = { · 17 unmodified lines
290	.set_power = sdhci_am654_set_power,	308	.set_power = sdhci_am654_set_power,
291	.set_clock = sdhci_j721e_4bit_set_clock,	309	.set_clock = sdhci_j721e_4bit_set_clock,
292	.write_b = sdhci_am654_write_b,	310	.write_b = sdhci_am654_write_b,
		311	.irq = sdhci_am654_cqhci_irq,
293	.reset = sdhci_reset,	312	.reset = sdhci_reset,
294	};	313	};
295		314
@@ -304,6 +323,40 @@ static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = { · 8 unmodified lines
304	.pdata = &sdhci_j721e_4bit_pdata,	323	.pdata = &sdhci_j721e_4bit_pdata,
305	.flags = IOMUX_PRESENT,	324	.flags = IOMUX_PRESENT,
306	};	325	};
		326
		327	static void sdhci_am654_dumpregs(struct mmc_host *mmc)
		328	{
		329	sdhci_dumpregs(mmc_priv(mmc));
		330	}
		331
		332	static const struct cqhci_host_ops sdhci_am654_cqhci_ops = {
		333	.enable = sdhci_cqe_enable,
		334	.disable = sdhci_cqe_disable,
		335	.dumpregs = sdhci_am654_dumpregs,
		336	};
		337
		338	static int sdhci_am654_cqe_add_host(struct sdhci_host *host)
		339	{
		340	struct cqhci_host *cq_host;
		341	int ret;
		342
		343	cq_host = devm_kzalloc(host->mmc->parent, sizeof(struct cqhci_host),
		344	GFP_KERNEL);
		345	if (!cq_host)
		346	return -ENOMEM;
		347
		348	cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR;
		349	cq_host->quirks \|= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
		350	cq_host->caps \|= CQHCI_TASK_DESC_SZ_128;
		351	cq_host->ops = &sdhci_am654_cqhci_ops;
		352
		353	host->mmc->caps2 \|= MMC_CAP2_CQE;
		354
		355	ret = cqhci_init(cq_host, host->mmc, 1);
		356
		357	return ret;
		358	}
		359
307	static int sdhci_am654_init(struct sdhci_host *host)	360	static int sdhci_am654_init(struct sdhci_host *host)
308	{	361	{
309	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);	362	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
@@ -344,7 +397,23 @@ static int sdhci_am654_init(struct sdhci_host *host) · 34 unmodified lines
344	regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,	397	regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
345	ctl_cfg_2);	398	ctl_cfg_2);
346		399
347	return sdhci_add_host(host);	400	ret = sdhci_setup_host(host);
		401	if (ret)
		402	return ret;
		403
		404	ret = sdhci_am654_cqe_add_host(host);
		405	if (ret)
		406	goto err_cleanup_host;
		407
		408	ret = __sdhci_add_host(host);
		409	if (ret)
		410	goto err_cleanup_host;
		411
		412	return 0;
		413
		414	err_cleanup_host:
		415	sdhci_cleanup_host(host);
		416	return ret;
348	}	417	}
349		418
350	static int sdhci_am654_get_of_property(struct platform_device *pdev,	419	static int sdhci_am654_get_of_property(struct platform_device *pdev,

drivers/mmc/host/sdhci_f_sdh30.c+1−25

@@ -16,31 +16,7 @@ · 15 unmodified lines
16	#include <linux/clk.h>	16	#include <linux/clk.h>
17		17
18	#include "sdhci-pltfm.h"	18	#include "sdhci-pltfm.h"
19		19	#include "sdhci_f_sdh30.h"
20	/* F_SDH30 extended Controller registers */
21	#define F_SDH30_AHB_CONFIG 0x100
22	#define F_SDH30_AHB_BIGED 0x00000040
23	#define F_SDH30_BUSLOCK_DMA 0x00000020
24	#define F_SDH30_BUSLOCK_EN 0x00000010
25	#define F_SDH30_SIN 0x00000008
26	#define F_SDH30_AHB_INCR_16 0x00000004
27	#define F_SDH30_AHB_INCR_8 0x00000002
28	#define F_SDH30_AHB_INCR_4 0x00000001
29
30	#define F_SDH30_TUNING_SETTING 0x108
31	#define F_SDH30_CMD_CHK_DIS 0x00010000
32
33	#define F_SDH30_IO_CONTROL2 0x114
34	#define F_SDH30_CRES_O_DN 0x00080000
35	#define F_SDH30_MSEL_O_1_8 0x00040000
36
37	#define F_SDH30_ESD_CONTROL 0x124
38	#define F_SDH30_EMMC_RST 0x00000002
39	#define F_SDH30_EMMC_HS200 0x01000000
40
41	#define F_SDH30_CMD_DAT_DELAY 0x200
42
43	#define F_SDH30_MIN_CLOCK 400000
44		20
45	struct f_sdhost_priv {	21	struct f_sdhost_priv {
46	struct clk *clk_iface;	22	struct clk *clk_iface;

drivers/mmc/host/sdhci_f_sdh30.h+32−0

@@ -0,0 +1,32 @@
	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/*
	3	* Copyright (C) 2013 - 2015 Fujitsu Semiconductor, Ltd
	4	* Vincent Yang <vincent.yang@tw.fujitsu.com>
	5	* Copyright (C) 2015 Linaro Ltd Andy Green <andy.green@linaro.org>
	6	* Copyright (C) 2019 Socionext Inc.
	7	*
	8	*/
	9
	10	/* F_SDH30 extended Controller registers */
	11	#define F_SDH30_AHB_CONFIG 0x100
	12	#define F_SDH30_AHB_BIGED BIT(6)
	13	#define F_SDH30_BUSLOCK_DMA BIT(5)
	14	#define F_SDH30_BUSLOCK_EN BIT(4)
	15	#define F_SDH30_SIN BIT(3)
	16	#define F_SDH30_AHB_INCR_16 BIT(2)
	17	#define F_SDH30_AHB_INCR_8 BIT(1)
	18	#define F_SDH30_AHB_INCR_4 BIT(0)
	19
	20	#define F_SDH30_TUNING_SETTING 0x108
	21	#define F_SDH30_CMD_CHK_DIS BIT(16)
	22
	23	#define F_SDH30_IO_CONTROL2 0x114
	24	#define F_SDH30_CRES_O_DN BIT(19)
	25	#define F_SDH30_MSEL_O_1_8 BIT(18)
	26
	27	#define F_SDH30_ESD_CONTROL 0x124
	28	#define F_SDH30_EMMC_RST BIT(1)
	29	#define F_SDH30_CMD_DAT_DELAY BIT(9)
	30	#define F_SDH30_EMMC_HS200 BIT(24)
	31
	32	#define F_SDH30_MIN_CLOCK 400000

drivers/mmc/host/tmio_mmc_core.c+1−1

@@ -1185,7 +1185,7 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host) · 1184 unmodified lines
1185	if (ret == -EPROBE_DEFER)	1185	if (ret == -EPROBE_DEFER)
1186	return ret;	1186	return ret;
1187		1187
1188	mmc->caps \|= MMC_CAP_4_BIT_DATA \| pdata->capabilities;	1188	mmc->caps \|= MMC_CAP_ERASE \| MMC_CAP_4_BIT_DATA \| pdata->capabilities;
1189	mmc->caps2 \|= pdata->capabilities2;	1189	mmc->caps2 \|= pdata->capabilities2;
1190	mmc->max_segs = pdata->max_segs ? : 32;	1190	mmc->max_segs = pdata->max_segs ? : 32;
1191	mmc->max_blk_size = TMIO_MAX_BLK_SIZE;	1191	mmc->max_blk_size = TMIO_MAX_BLK_SIZE;

drivers/mmc/host/vub300.c+0−7

 	kref_put(&vub300->kref, vub300_delete);
 }
-static void vub300_init_card(struct mmc_host *mmc, struct mmc_card *card)
-{				/* NOT irq */
-	struct vub300_mmc_host *vub300 = mmc_priv(mmc);
-	dev_info(&vub300->udev->dev, "NO host QUIRKS for this card\n");
-}
 static const struct mmc_host_ops vub300_mmc_ops = {
 	.request = vub300_mmc_request,
 	.set_ios = vub300_mmc_set_ios,
 	.get_ro = vub300_mmc_get_ro,
 	.enable_sdio_irq = vub300_enable_sdio_irq,
-	.init_card = vub300_init_card,
 };
 static int vub300_probe(struct usb_interface *interface,

drivers/net/wireless/marvell/mwifiex/main.c+4−1

 	mwifiex_drv_get_driver_version(adapter, fmt, sizeof(fmt) - 1);
 	mwifiex_dbg(adapter, MSG, "driver_version = %s\n", fmt);
+	adapter->is_up = true;
 	goto done;
 err_add_intf:
 	mwifiex_deauthenticate(priv, NULL);
 	mwifiex_uninit_sw(adapter);
+	adapter->is_up = false;
 	if (adapter->if_ops.down_dev)
 		adapter->if_ops.down_dev(adapter);
 	if (!adapter)
 		return 0;
-	mwifiex_uninit_sw(adapter);
+	if (adapter->is_up)
+		mwifiex_uninit_sw(adapter);
 	if (adapter->irq_wakeup >= 0)
 		device_init_wakeup(adapter->dev, false);

drivers/net/wireless/marvell/mwifiex/main.h+1−0

@@ -1017,6 +1017,7 @@ struct mwifiex_adapter { · 1016 unmodified lines
1017		1017
1018	/* For synchronizing FW initialization with device lifecycle. */	1018	/* For synchronizing FW initialization with device lifecycle. */
1019	struct completion *fw_done;	1019	struct completion *fw_done;
		1020	bool is_up;
1020		1021
1021	bool ext_scan;	1022	bool ext_scan;
1022	u8 fw_api_ver;	1023	u8 fw_api_ver;

drivers/net/wireless/marvell/mwifiex/sdio.c+22−11

@@ -444,6 +444,9 @@ static int mwifiex_sdio_suspend(struct device *dev) · 443 unmodified lines
444	return 0;	444	return 0;
445	}	445	}
446		446
		447	if (!adapter->is_up)
		448	return -EBUSY;
		449
447	mwifiex_enable_wake(adapter);	450	mwifiex_enable_wake(adapter);
448		451
449	/* Enable the Host Sleep */	452	/* Enable the Host Sleep */
@@ -2220,22 +2223,30 @@ static void mwifiex_sdio_card_reset_work(struct mwifiex_adapter *adapter) · 1770 unmodified lines
2220	struct sdio_func *func = card->func;	2223	struct sdio_func *func = card->func;
2221	int ret;	2224	int ret;
2222		2225
		2226	/* Prepare the adapter for the reset. */
2223	mwifiex_shutdown_sw(adapter);	2227	mwifiex_shutdown_sw(adapter);
		2228	clear_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP, &card->work_flags);
		2229	clear_bit(MWIFIEX_IFACE_WORK_CARD_RESET, &card->work_flags);
2224		2230
2225	/* power cycle the adapter */	2231	/* Run a HW reset of the SDIO interface. */
2226	sdio_claim_host(func);	2232	sdio_claim_host(func);
2227	mmc_hw_reset(func->card->host);	2233	ret = mmc_hw_reset(func->card->host);
2228	sdio_release_host(func);	2234	sdio_release_host(func);
2229		2235
2230	/* Previous save_adapter won't be valid after this. We will cancel	2236	switch (ret) {
2231	* pending work requests.	2237	case 1:
2232	*/	2238	dev_dbg(&func->dev, "SDIO HW reset asynchronous\n");
2233	clear_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP, &card->work_flags);	2239	complete_all(adapter->fw_done);
2234	clear_bit(MWIFIEX_IFACE_WORK_CARD_RESET, &card->work_flags);	2240	break;
2235		2241	case 0:
2236	ret = mwifiex_reinit_sw(adapter);	2242	ret = mwifiex_reinit_sw(adapter);
2237	if (ret)	2243	if (ret)
2238	dev_err(&func->dev, "reinit failed: %d\n", ret);	2244	dev_err(&func->dev, "reinit failed: %d\n", ret);
		2245	break;
		2246	default:
		2247	dev_err(&func->dev, "SDIO HW reset failed: %d\n", ret);
		2248	break;
		2249	}
2239	}	2250	}
2240		2251
2241	/* This function read/write firmware */	2252	/* This function read/write firmware */

drivers/net/wireless/ti/wl1251/sdio.c+16−9

 #include <linux/irq.h>
 #include <linux/pm_runtime.h>
 #include <linux/gpio.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
+#include <linux/of_irq.h>
 #include "wl1251.h"
-#ifndef SDIO_VENDOR_ID_TI
-#define SDIO_VENDOR_ID_TI		0x104c
-#endif
-#ifndef SDIO_DEVICE_ID_TI_WL1251
-#define SDIO_DEVICE_ID_TI_WL1251	0x9066
-#endif
 struct wl1251_sdio {
 	struct sdio_func *func;
 	u32 elp_val;
 }
 static const struct sdio_device_id wl1251_devices[] = {
-	{ SDIO_DEVICE(SDIO_VENDOR_ID_TI, SDIO_DEVICE_ID_TI_WL1251) },
+	{ SDIO_DEVICE(SDIO_VENDOR_ID_TI_WL1251, SDIO_DEVICE_ID_TI_WL1251) },
 	{}
 };
 MODULE_DEVICE_TABLE(sdio, wl1251_devices);
 	struct ieee80211_hw *hw;
 	struct wl1251_sdio *wl_sdio;
 	const struct wl1251_platform_data *wl1251_board_data;
+	struct device_node *np = func->dev.of_node;
 	hw = wl1251_alloc_hw();
 	if (IS_ERR(hw))
 		wl->power_gpio = wl1251_board_data->power_gpio;
 		wl->irq = wl1251_board_data->irq;
 		wl->use_eeprom = wl1251_board_data->use_eeprom;
+	} else if (np) {
+		wl->use_eeprom = of_property_read_bool(np,
+						       "ti,wl1251-has-eeprom");
+		wl->power_gpio = of_get_named_gpio(np, "ti,power-gpio", 0);
+		wl->irq = of_irq_get(np, 0);
+		if (wl->power_gpio == -EPROBE_DEFER ||
+		    wl->irq == -EPROBE_DEFER) {
+			ret = -EPROBE_DEFER;
+			goto disable;
+		}
 	}
 	if (gpio_is_valid(wl->power_gpio)) {

drivers/net/wireless/ti/wlcore/sdio.c+0−8

@@ -26,14 +26,6 @@ · 25 unmodified lines
26	#include "wl12xx_80211.h"	26	#include "wl12xx_80211.h"
27	#include "io.h"	27	#include "io.h"
28		28
29	#ifndef SDIO_VENDOR_ID_TI
30	#define SDIO_VENDOR_ID_TI 0x0097
31	#endif
32
33	#ifndef SDIO_DEVICE_ID_TI_WL1271
34	#define SDIO_DEVICE_ID_TI_WL1271 0x4076
35	#endif
36
37	static bool dump = false;	29	static bool dump = false;
38		30
39	struct wl12xx_sdio_glue {	31	struct wl12xx_sdio_glue {

include/linux/firmware/xlnx-zynqmp.h+12−1

 };
 enum pm_ioctl_id {
-	IOCTL_SET_PLL_FRAC_MODE = 8,
+	IOCTL_SET_SD_TAPDELAY = 7,
+	IOCTL_SET_PLL_FRAC_MODE,
 	IOCTL_GET_PLL_FRAC_MODE,
 	IOCTL_SET_PLL_FRAC_DATA,
 	IOCTL_GET_PLL_FRAC_DATA,
 	ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING,
 };
+enum pm_node_id {
+	NODE_SD_0 = 39,
+	NODE_SD_1,
+};
+enum tap_delay_type {
+	PM_TAPDELAY_INPUT = 0,
+	PM_TAPDELAY_OUTPUT,
+};
 /**
  * struct zynqmp_pm_query_data - PM query data
  * @qid:	query ID

include/linux/mmc/card.h+2−1

  * MMC Physical partitions
  */
 struct mmc_part {
-	unsigned int	size;	/* partition size (in bytes) */
+	u64		size;	/* partition size (in bytes) */
 	unsigned int	part_cfg;	/* partition type */
 	char	name[MAX_MMC_PART_NAME_LEN];
 	bool	force_ro;	/* to make boot parts RO by default */
 	struct sd_switch_caps	sw_caps;	/* switch (CMD6) caps */
 	unsigned int		sdio_funcs;	/* number of SDIO functions */
+	atomic_t		sdio_funcs_probed; /* number of probed SDIO funcs */
 	struct sdio_cccr	cccr;		/* common card info */
 	struct sdio_cis		cis;		/* common tuple info */
 	struct sdio_func	*sdio_func[SDIO_MAX_FUNCS]; /* SDIO functions (devices) */

include/linux/mmc/sdio_ids.h+2−0

@@ -71,6 +71,8 @@ · 70 unmodified lines
71		71
72	#define SDIO_VENDOR_ID_TI 0x0097	72	#define SDIO_VENDOR_ID_TI 0x0097
73	#define SDIO_DEVICE_ID_TI_WL1271 0x4076	73	#define SDIO_DEVICE_ID_TI_WL1271 0x4076
		74	#define SDIO_VENDOR_ID_TI_WL1251 0x104c
		75	#define SDIO_DEVICE_ID_TI_WL1251 0x9066
74		76
75	#define SDIO_VENDOR_ID_STE 0x0020	77	#define SDIO_VENDOR_ID_STE 0x0020
76	#define SDIO_DEVICE_ID_STE_CW1200 0x2280	78	#define SDIO_DEVICE_ID_STE_CW1200 0x2280

include/linux/platform_data/hsmmc-omap.h+0−3

@@ -67,9 +67,6 @@ struct omap_hsmmc_platform_data { · 66 unmodified lines
67	/* string specifying a particular variant of hardware */	67	/* string specifying a particular variant of hardware */
68	char *version;	68	char *version;
69		69
70	/* if we have special card, init it using this callback */
71	void (init_card)(struct mmc_card card);
72
73	const char *name;	70	const char *name;
74	u32 ocr_mask;	71	u32 ocr_mask;
75	};	72	};

Merge tag 'mmc-v5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc

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