The patch prints 4 PCIE or AER config registers each line, which is part of the EEH log so that it looks a bit more compact.
Unified · Split
| @@ -157,12 +157,13 @@ __setup("eeh=", eeh_setup); · 156 unmodified lines | ||
| 157 | 157 | * This routine captures assorted PCI configuration space data, |
| 158 | 158 | * and puts them into a buffer for RTAS error logging. |
| 159 | 159 | */ |
| 160 | −static size_t eeh_gather_pci_data(struct eeh_dev *edev, char * buf, size_t len) | |
| 160 | +static size_t eeh_gather_pci_data(struct eeh_dev *edev, char *buf, size_t len) | |
| 161 | 161 | { |
| 162 | 162 | struct device_node *dn = eeh_dev_to_of_node(edev); |
| 163 | 163 | u32 cfg; |
| 164 | 164 | int cap, i; |
| 165 | − int n = 0; | |
| 165 | + int n = 0, l = 0; | |
| 166 | + char buffer[128]; | |
| 166 | 167 | |
| 167 | 168 | n += scnprintf(buf+n, len-n, "%s\n", dn->full_name); |
| 168 | 169 | pr_warn("EEH: of node=%s\n", dn->full_name); |
| @@ -207,8 +208,22 @@ static size_t eeh_gather_pci_data(struct eeh_dev *edev, char * buf, size_t len) · 38 unmodified lines | ||
| 207 | 208 | for (i=0; i<=8; i++) { |
| 208 | 209 | eeh_ops->read_config(dn, cap+4*i, 4, &cfg); |
| 209 | 210 | n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); |
| 210 | − pr_warn("EEH: PCI-E %02x: %08x\n", i, cfg); | |
| 211 | + | |
| 212 | + if ((i % 4) == 0) { | |
| 213 | + if (i != 0) | |
| 214 | + pr_warn("%s\n", buffer); | |
| 215 | + | |
| 216 | + l = scnprintf(buffer, sizeof(buffer), | |
| 217 | + "EEH: PCI-E %02x: %08x ", | |
| 218 | + 4*i, cfg); | |
| 219 | + } else { | |
| 220 | + l += scnprintf(buffer+l, sizeof(buffer)-l, | |
| 221 | + "%08x ", cfg); | |
| 222 | + } | |
| 223 | + | |
| 211 | 224 | } |
| 225 | + | |
| 226 | + pr_warn("%s\n", buffer); | |
| 212 | 227 | } |
| 213 | 228 | |
| 214 | 229 | /* If AER capable, dump it */ |
| @@ -217,11 +232,24 @@ static size_t eeh_gather_pci_data(struct eeh_dev *edev, char * buf, size_t len) · 2 unmodified lines | ||
| 217 | 232 | n += scnprintf(buf+n, len-n, "pci-e AER:\n"); |
| 218 | 233 | pr_warn("EEH: PCI-E AER capability register set follows:\n"); |
| 219 | 234 | |
| 220 | − for (i=0; i<14; i++) { | |
| 235 | + for (i=0; i<=13; i++) { | |
| 221 | 236 | eeh_ops->read_config(dn, cap+4*i, 4, &cfg); |
| 222 | 237 | n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); |
| 223 | − pr_warn("EEH: PCI-E AER %02x: %08x\n", i, cfg); | |
| 238 | + | |
| 239 | + if ((i % 4) == 0) { | |
| 240 | + if (i != 0) | |
| 241 | + pr_warn("%s\n", buffer); | |
| 242 | + | |
| 243 | + l = scnprintf(buffer, sizeof(buffer), | |
| 244 | + "EEH: PCI-E AER %02x: %08x ", | |
| 245 | + 4*i, cfg); | |
| 246 | + } else { | |
| 247 | + l += scnprintf(buffer+l, sizeof(buffer)-l, | |
| 248 | + "%08x ", cfg); | |
| 249 | + } | |
| 224 | 250 | } |
| 251 | + | |
| 252 | + pr_warn("%s\n", buffer); | |
| 225 | 253 | } |
| 226 | 254 | |
| 227 | 255 | return n; |