Merge tag 'mips_4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips

Pull MIPS updates from James Hogan: "Here's the main MIPS pull request for 4.11. It contains a few new features such as IRQ stacks, cacheinfo support, and KASLR for Octeon CPUs, and a variety of smaller improvements and fixes including devicetree additions, kexec cleanups, microMIPS stack unwinding fixes, and a bunch of build fixes to clean up continuous integration builds. Its all been in linux-next for at least a couple of days, most of it far longer. Miscellaneous: - Add IRQ stacks - Add cacheinfo support - Add "uzImage.bin" zboot target - Unify performance counter definitions - Export various (mainly assembly) symbols alongside their definitions - Audit and remove unnecessary uses of module.h kexec & kdump: - Lots of improvements and fixes - Add correct copy_regs implementations - Add debug logging of new kernel information Security: - Use Makefile.postlink to insert relocations into vmlinux - Provide plat_post_relocation hook (used for Octeon KASLR) - Add support for tuning mmap randomisation - Relocate DTB microMIPS: - A load of unwind fixes - Add some missing .insn to fix link errors MIPSr6: - Fix MULTU/MADDU/MSUBU sign extension in r2 emulation - Remove r2_emul_return and use ERETNC unconditionally on MIPSr6 - Allow pre-r6 emulation on SMP MIPSr6 kernels Cache management: - Treat physically indexed dcache as non-aliasing - Add return errors to protected cache ops for KVM - CM3: Ensure L1 & L2 cache ECC checking matches - CM3: Indicate inclusive caches - I6400: Treat dcache as physically indexed Memory management: - Ensure bootmem doesn't corrupt reserved memory - Export some TLB exception generation functions for KVM OF: - NULL check initial_boot_params before use in of_scan_flat_dt() - Fix unaligned access in of_alias_scan() SMP: - CPS: Don't BUG if a CPU fails to start Other fixes: - Fix longstanding 64-bit IP checksum carry bug - Fix KERN_CONT fallout in cpu-bugs64.c and sync-r4k.c - Update defconfigs for NF_CT_PROTO_DCCP, DPLITE, CPU_FREQ_STAT,SCSI_DH changes - Disable certain builtin compiler options, stack-check (whole kernel), asynchronous-unwind-tables (VDSO). - A bunch of build fixes from kernelci.org testing - Various other minor cleanups & corrections BMIPS: - Migrate interrupts during bmips_cpu_disable - BCM47xx: Add Luxul devices - BCM47xx: Fix Asus WL-500W button inversion - BCM7xxx: Add SPI device nodes Generic (multiplatform): - Add kexec DTB passing - Fix big endian - Add cpp_its_S in ksym_dep_filter to silence build warning IP22: - Reformat inline assembler code to modern standards - Fix binutils 2.25 build error IP27: - Fix duplicate CAC_BASE definition build error - Disable qlge driver to workaround broken compiler Lantiq: - Refresh defconfig and activate more drivers - Lock DMA register access - Fix cascading IRQ setup - Fix build of VPE loader - xway: Fix ethernet packet header corruption over reboot Loongson1 - Add watchdog support - 1B: Reduce DEFAULT_MEMSIZE to 64MB - 1B: Change OSC clock name to match rest of kernel - 1C: Remove ARCH_WANT_OPTIONAL_GPIOLIB Octeon: - Add KASLR support - Support Octeon III USB controller - Fix large copy_from_user corner case - Enable devtmpfs in defconfig Netlogic: - Fix non-default XLR build error due to netlogic,xlp-pic code - Fix assembler warning from smpboot.S pic32mzda: - Fix linker error when early printk is disabled Pistachio: - Add base device tree - Add Ci40 "Marduk" device tree Ralink: - Support raw appended DTB - Add missing I2C & I2S clocks - Add missing pinmux and fix pinmux function name typo - Add missing clk_round_rate() - Clean up prom_init() - MT7621: Set SoC type - MT7621: Support highmem TXx9: - Modernize printing of kernel messages and resolve KERN_CONT fallout - 7segled: use permission-specific DEVICE_ATTR variants XilFPGA: - Add IRQ controller and UART IRQ - Add AXI I2C and emaclite to DT & defconfig" * tag 'mips_4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips: (148 commits) MIPS: VDSO: Explicitly use -fno-asynchronous-unwind-tables MIPS: BCM47XX: Fix button inversion for Asus WL-500W MIPS: DTS: Add img directory to Makefile MIPS: ip27: Disable qlge driver in defconfig MIPS: pic32mzda: Fix linker error for pic32_get_pbclk() MIPS: Lantiq: Keep ethernet enabled during boot MIPS: OCTEON: Fix copy_from_user fault handling for large buffers MIPS: Fix special case in 64 bit IP checksumming. MIPS: OCTEON: Enable DEVTMPFS MIPS: lantiq: Set physical_memsize MIPS: sysmips: Remove duplicated include from syscall.c Kbuild: Add cpp_its_S in ksym_dep_filter MIPS: Audit and remove any unnecessary uses of module.h MIPS: Unify perf counter register definitions MIPS: Disable stack checks on MIPS kernels MIPS: OCTEON: Platform support for OCTEON III USB controller MIPS: Lantiq: Fix cascaded IRQ setup MIPS: sync-r4k: Fix KERN_CONT fallout MIPS: IRQ Stack: Fix erroneous jal to plat_irq_dispatch MIPS: Fix distclean with Makefile.postlink ...

Linus Torvalds committed 9 years ago

Commit 0f002fd2 parents 252b95c cfd75c2253 files · +4091 −1030Browse files

Unified · Split

253 files

Documentation/devicetree/bindings/mips/img/pistachio-marduk.txt +10 −0
MAINTAINERS +7 −1
arch/mips/Kconfig +29 −12
arch/mips/Makefile +21 −14
arch/mips/Makefile.postlink +35 −0
arch/mips/alchemy/board-gpr.c +0 −1
arch/mips/alchemy/common/dbdma.c +1 −1
arch/mips/alchemy/common/dma.c +1 −1
arch/mips/alchemy/common/gpiolib.c +0 −1
arch/mips/alchemy/common/prom.c +0 −1
arch/mips/alchemy/common/usb.c +1 −1
arch/mips/alchemy/common/vss.c +1 −1
arch/mips/alchemy/devboards/bcsr.c +2 −1
arch/mips/ar7/clock.c +1 −1
arch/mips/ar7/gpio.c +2 −1
arch/mips/ar7/memory.c +0 −1
arch/mips/ar7/platform.c +0 −1
arch/mips/ar7/prom.c +1 −1
arch/mips/ath79/clock.c +6 −4
arch/mips/ath79/common.c +1 −1
arch/mips/bcm47xx/board.c +9 −0
arch/mips/bcm47xx/buttons.c +80 −2
arch/mips/bcm47xx/leds.c +81 −0
arch/mips/bcm63xx/clk.c +2 −1
arch/mips/bcm63xx/cpu.c +1 −1
arch/mips/bcm63xx/cs.c +2 −1
arch/mips/bcm63xx/gpio.c +1 −1
arch/mips/bcm63xx/irq.c +0 −1
arch/mips/bcm63xx/reset.c +2 −1
arch/mips/bcm63xx/timer.c +2 −1
arch/mips/boot/compressed/Makefile +7 −3
arch/mips/boot/dts/Makefile +1 −0
arch/mips/boot/dts/brcm/bcm7125.dtsi +46 −3
arch/mips/boot/dts/brcm/bcm7346.dtsi +43 −0
arch/mips/boot/dts/brcm/bcm7358.dtsi +43 −0
arch/mips/boot/dts/brcm/bcm7360.dtsi +43 −0
arch/mips/boot/dts/brcm/bcm7362.dtsi +43 −0
arch/mips/boot/dts/brcm/bcm7420.dtsi +46 −3
arch/mips/boot/dts/brcm/bcm7425.dtsi +43 −0
arch/mips/boot/dts/brcm/bcm7435.dtsi +43 −0
arch/mips/boot/dts/brcm/bcm97125cbmb.dts +4 −0
arch/mips/boot/dts/brcm/bcm97346dbsmb.dts +4 −0
arch/mips/boot/dts/brcm/bcm97358svmb.dts +36 −0
arch/mips/boot/dts/brcm/bcm97360svmb.dts +36 −0
arch/mips/boot/dts/brcm/bcm97362svmb.dts +4 −0
arch/mips/boot/dts/brcm/bcm97420c.dts +4 −0
arch/mips/boot/dts/brcm/bcm97425svmb.dts +36 −0
arch/mips/boot/dts/brcm/bcm97435svmb.dts +4 −0
arch/mips/boot/dts/img/Makefile +9 −0
arch/mips/boot/dts/img/pistachio.dtsi +924 −0
arch/mips/boot/dts/img/pistachio_marduk.dts +163 −0
arch/mips/boot/dts/xilfpga/nexys4ddr.dts +63 −0
arch/mips/cavium-octeon/Makefile +1 −0
arch/mips/cavium-octeon/crypto/octeon-crypto.c +1 −1
arch/mips/cavium-octeon/dma-octeon.c +5 −10
arch/mips/cavium-octeon/executive/cvmx-bootmem.c +1 −1
arch/mips/cavium-octeon/executive/cvmx-helper-errata.c +1 −1
arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c +1 −2
arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c +1 −2
arch/mips/cavium-octeon/executive/cvmx-helper-spi.c +1 −2
arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c +1 −2
arch/mips/cavium-octeon/executive/cvmx-helper.c +1 −46
arch/mips/cavium-octeon/executive/cvmx-sysinfo.c +1 −1
arch/mips/cavium-octeon/octeon-memcpy.S +17 −8
arch/mips/cavium-octeon/octeon-platform.c +1 −0
arch/mips/cavium-octeon/octeon-usb.c +552 −0
arch/mips/cavium-octeon/setup.c +23 −0
arch/mips/cavium-octeon/smp.c +20 −4
arch/mips/configs/cavium_octeon_defconfig +1 −0
arch/mips/configs/ip22_defconfig +2 −2
arch/mips/configs/ip27_defconfig +1 −2
arch/mips/configs/lemote2f_defconfig +1 −1
arch/mips/configs/loongson1b_defconfig +4 −0
arch/mips/configs/loongson1c_defconfig +4 −0
arch/mips/configs/malta_defconfig +2 −2
arch/mips/configs/malta_kvm_defconfig +2 −2
arch/mips/configs/malta_kvm_guest_defconfig +2 −2
arch/mips/configs/maltaup_xpa_defconfig +2 −2
arch/mips/configs/nlm_xlp_defconfig +1 −1
arch/mips/configs/nlm_xlr_defconfig +1 −1
arch/mips/configs/xilfpga_defconfig +36 −1
arch/mips/configs/xway_defconfig +13 −8
arch/mips/dec/prom/identify.c +1 −1
arch/mips/dec/setup.c +1 −1
arch/mips/dec/wbflush.c +1 −3
arch/mips/emma/markeins/setup.c +1 −1
arch/mips/generic/Makefile +1 −0
arch/mips/generic/init.c +13 −0
arch/mips/generic/kexec.c +44 −0
arch/mips/include/asm/Kbuild +2 −0
arch/mips/include/asm/asm-prototypes.h +5 −0
arch/mips/include/asm/asm.h +6 −4
arch/mips/include/asm/bootinfo.h +13 −0
arch/mips/include/asm/checksum.h +2 −0
arch/mips/include/asm/elf.h +9 −0
arch/mips/include/asm/highmem.h +0 −3
arch/mips/include/asm/i8259.h +0 −1
arch/mips/include/asm/irq.h +12 −0
arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h +9 −0
arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h +13 −2
arch/mips/include/asm/mach-ip27/spaces.h +4 −2
arch/mips/include/asm/mach-loongson32/loongson1.h +5 −4
arch/mips/include/asm/mach-loongson32/platform.h +5 −4
arch/mips/include/asm/mach-loongson32/regs-rtc.h +23 −0
arch/mips/include/asm/mach-ralink/mt7620.h +6 −1
arch/mips/include/asm/mips-cm.h +7 −0
arch/mips/include/asm/mipsregs.h +33 −0
arch/mips/include/asm/octeon/cvmx-gpio-defs.h +6 −2
arch/mips/include/asm/octeon/cvmx-helper-rgmii.h +1 −2
arch/mips/include/asm/octeon/cvmx-helper-sgmii.h +1 −2
arch/mips/include/asm/octeon/cvmx-helper-spi.h +1 −2
arch/mips/include/asm/octeon/cvmx-helper-xaui.h +1 −2
arch/mips/include/asm/octeon/cvmx-helper.h +1 −13
arch/mips/include/asm/pgalloc.h +1 −15
arch/mips/include/asm/r4kcache.h +39 −22
arch/mips/include/asm/smp.h +1 −9
arch/mips/include/asm/stackframe.h +11 −8
arch/mips/include/asm/switch_to.h +12 −6
arch/mips/include/asm/thread_info.h +0 −1
arch/mips/include/asm/tlbex.h +26 −0
arch/mips/include/asm/uaccess.h +18 −0
arch/mips/include/asm/uasm.h +5 −0
arch/mips/include/asm/unaligned.h +0 −28
arch/mips/jazz/jazzdma.c +1 −1
arch/mips/jz4740/gpio.c +1 −1
arch/mips/jz4740/prom.c +0 −1
arch/mips/jz4740/timer.c +2 −1
arch/mips/kernel/Makefile +2 −2
arch/mips/kernel/asm-offsets.c +1 −1
arch/mips/kernel/cacheinfo.c +87 −0
arch/mips/kernel/cpu-bugs64.c +12 −12
arch/mips/kernel/crash.c +1 −1
arch/mips/kernel/entry.S +0 −18
arch/mips/kernel/genex.S +76 −5
arch/mips/kernel/irq.c +11 −0
arch/mips/kernel/linux32.c +3 −8
arch/mips/kernel/machine_kexec.c +22 −0
arch/mips/kernel/mcount.S +3 −0
arch/mips/kernel/mips-mt-fpaff.c +3 −2
arch/mips/kernel/mips-r2-to-r6-emul.c +6 −6
arch/mips/kernel/mips_ksyms.c +0 −94
arch/mips/kernel/perf_event_mipsxx.c +23 −32
arch/mips/kernel/process.c +157 −57
arch/mips/kernel/prom.c +7 −0
arch/mips/kernel/ptrace.c +2 −32
arch/mips/kernel/r2300_switch.S +2 −0
arch/mips/kernel/r4k_switch.S +3 −0
arch/mips/kernel/relocate.c +55 −1
arch/mips/kernel/setup.c +91 −3
arch/mips/kernel/smp-bmips.c +1 −1
arch/mips/kernel/smp-cps.c +5 −2
arch/mips/kernel/smp.c +9 −25
arch/mips/kernel/sync-r4k.c +2 −2
arch/mips/kernel/syscall.c +2 −10
arch/mips/kernel/traps.c +60 −5
arch/mips/kernel/uprobes.c +1 −1
arch/mips/kernel/vmlinux.lds.S +1 −1
arch/mips/lantiq/irq.c +17 −21
arch/mips/lantiq/prom.c +6 −0
arch/mips/lantiq/xway/dma.c +21 −20
arch/mips/lantiq/xway/gptu.c +1 −2
arch/mips/lantiq/xway/sysctrl.c +6 −6
arch/mips/lasat/at93c.c +0 −1
arch/mips/lasat/sysctl.c +0 −1
arch/mips/lib/csum_partial.S +6 −0
arch/mips/lib/memcpy.S +9 −0
arch/mips/lib/memset.S +5 −0
arch/mips/lib/strlen_user.S +4 −0
arch/mips/lib/strncpy_user.S +7 −0
arch/mips/lib/strnlen_user.S +7 −0
arch/mips/loongson32/common/platform.c +28 −17
arch/mips/loongson32/ls1b/board.c +4 −3
arch/mips/loongson32/ls1c/board.c +4 −3
arch/mips/loongson64/common/cs5536/cs5536_mfgpt.c +1 −1
arch/mips/loongson64/common/dma-swiotlb.c +6 −14
arch/mips/loongson64/common/env.c +1 −1
arch/mips/loongson64/common/setup.c +2 −1
arch/mips/loongson64/common/uart_base.c +1 −1
arch/mips/loongson64/lemote-2f/ec_kb3310b.c +2 −1
arch/mips/loongson64/lemote-2f/irq.c +2 −1
arch/mips/loongson64/lemote-2f/pm.c +1 −1
arch/mips/loongson64/loongson-3/irq.c +1 −1
arch/mips/loongson64/loongson-3/numa.c +1 −1
arch/mips/loongson64/loongson-3/smp.c +0 −1
arch/mips/mm/Makefile +1 −1
arch/mips/mm/c-r4k.c +5 −1
arch/mips/mm/init.c +3 −0
arch/mips/mm/mmap.c +5 −5
arch/mips/mm/page-funcs.S +3 −0
arch/mips/mm/page.c +2 −0
arch/mips/mm/pgtable-64.c +2 −0
arch/mips/mm/pgtable.c +25 −0
arch/mips/mm/sc-ip22.c +34 −20
arch/mips/mm/sc-mips.c +1 −0
arch/mips/mm/tlbex.c +23 −21
arch/mips/mti-malta/malta-platform.c +0 −1
arch/mips/netlogic/common/irq.c +2 −2
arch/mips/netlogic/common/smpboot.S +2 −2
arch/mips/netlogic/xlp/wakeup.c +1 −1
arch/mips/oprofile/op_model_mipsxx.c +13 −27
arch/mips/pci/pci-tx4927.c +11 −11
arch/mips/pci/pci-tx4938.c +15 −15
arch/mips/pci/pci-tx4939.c +5 −5
arch/mips/pic32/pic32mzda/Makefile +2 −3
arch/mips/pmcs-msp71xx/msp_prom.c +1 −1
arch/mips/pmcs-msp71xx/msp_time.c +0 −1
arch/mips/ralink/Kconfig +1 −0
arch/mips/ralink/clk.c +8 −1
arch/mips/ralink/irq.c +2 −2
arch/mips/ralink/mt7620.c +20 −12
arch/mips/ralink/mt7621.c +1 −2
arch/mips/ralink/of.c +12 −4
arch/mips/ralink/prom.c +4 −5
arch/mips/ralink/rt288x.c +1 −11
arch/mips/ralink/rt305x.c +4 −12
arch/mips/ralink/rt3883.c +3 −12
arch/mips/ralink/timer.c +0 −14
arch/mips/rb532/irq.c +0 −1
arch/mips/rb532/prom.c +1 −1
arch/mips/sgi-ip22/Platform +1 −1
arch/mips/sgi-ip22/ip22-hpc.c +1 −1
arch/mips/sgi-ip22/ip22-mc.c +2 −1
arch/mips/sgi-ip22/ip22-nvram.c +1 −1
arch/mips/sgi-ip22/ip22-reset.c +0 −1
arch/mips/sgi-ip22/ip22-setup.c +0 −1
arch/mips/sgi-ip27/ip27-berr.c +0 −2
arch/mips/sgi-ip27/ip27-init.c +1 −1
arch/mips/sgi-ip27/ip27-klnuma.c +1 −1
arch/mips/sgi-ip27/ip27-memory.c +1 −1
arch/mips/sgi-ip32/crime.c +1 −1
arch/mips/sgi-ip32/ip32-irq.c +2 −2
arch/mips/sibyte/bcm1480/setup.c +1 −1
arch/mips/sibyte/sb1250/setup.c +1 −1
arch/mips/txx9/generic/7segled.c +2 −2
arch/mips/txx9/generic/pci.c +13 −15
arch/mips/txx9/generic/setup.c +1 −1
arch/mips/txx9/generic/setup_tx3927.c +3 −3
arch/mips/txx9/generic/setup_tx4927.c +9 −11
arch/mips/txx9/generic/setup_tx4938.c +13 −15
arch/mips/txx9/generic/setup_tx4939.c +4 −4
arch/mips/txx9/generic/smsc_fdc37m81x.c +7 −10
arch/mips/txx9/jmr3927/prom.c +1 −1
arch/mips/txx9/jmr3927/setup.c +5 −6
arch/mips/txx9/rbtx4938/setup.c +7 −7
arch/mips/vdso/Makefile +6 −2
arch/mips/vr41xx/common/bcu.c +2 −1
arch/mips/vr41xx/common/cmu.c +1 −1
arch/mips/vr41xx/common/icu.c +1 −1
arch/mips/vr41xx/common/irq.c +1 −1
arch/mips/xilfpga/intc.c +2 −5
drivers/of/base.c +1 −1
drivers/of/fdt.c +6 −3
scripts/Kbuild.include +1 −1

Documentation/devicetree/bindings/mips/img/pistachio-marduk.txt+10−0

@@ -0,0 +1,10 @@
	1	+Imagination Technologies' Pistachio SoC based Marduk Board
	2	+==========================================================
	3	+
	4	+Compatible string must be "img,pistachio-marduk", "img,pistachio"
	5	+
	6	+Hardware and other related documentation is available at
	7	+https://docs.creatordev.io/ci40/
	8	+
	9	+It is also known as Creator Ci40. Marduk is legacy name and will
	10	+be there for decades.

MAINTAINERS+7−1

@@ -7707,6 +7707,12 @@ W: http://www.kernel.org/doc/man-pages · 7706 unmodified lines
7707	7707	L: linux-man@vger.kernel.org
7708	7708	S: Maintained
7709	7709
	7710	+MARDUK (CREATOR CI40) DEVICE TREE SUPPORT
	7711	+M: Rahul Bedarkar <rahul.bedarkar@imgtec.com>
	7712	+L: linux-mips@linux-mips.org
	7713	+S: Maintained
	7714	+F: arch/mips/boot/dts/img/pistachio_marduk.dts
	7715	+
7710	7716	MARVELL 88E6XXX ETHERNET SWITCH FABRIC DRIVER
7711	7717	M: Andrew Lunn <andrew@lunn.ch>
7712	7718	M: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
@@ -9795,7 +9801,7 @@ L: linux-mips@linux-mips.org · 2082 unmodified lines
9795	9801	S: Maintained
9796	9802	F: arch/mips/pistachio/
9797	9803	F: arch/mips/include/asm/mach-pistachio/
9798		−F: arch/mips/boot/dts/pistachio/
	9804	+F: arch/mips/boot/dts/img/pistachio*
9799	9805	F: arch/mips/configs/pistachio*_defconfig
9800	9806
9801	9807	PKTCDVD DRIVER

arch/mips/Kconfig+29−12

@@ -9,10 +9,13 @@ config MIPS · 8 unmodified lines
9	9	select HAVE_CONTEXT_TRACKING
10	10	select HAVE_GENERIC_DMA_COHERENT
11	11	select HAVE_IDE
	12	+ select HAVE_IRQ_EXIT_ON_IRQ_STACK
12	13	select HAVE_OPROFILE
13	14	select HAVE_PERF_EVENTS
14	15	select PERF_USE_VMALLOC
15	16	select HAVE_ARCH_KGDB
	17	+ select HAVE_ARCH_MMAP_RND_BITS if MMU
	18	+ select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
16	19	select HAVE_ARCH_SECCOMP_FILTER
17	20	select HAVE_ARCH_TRACEHOOK
18	21	select HAVE_CBPF_JIT if !CPU_MICROMIPS
@@ -94,6 +97,7 @@ config MIPS_GENERIC · 75 unmodified lines
94	97	select PCI_DRIVERS_GENERIC
95	98	select PINCTRL
96	99	select SMP_UP if SMP
	100	+ select SWAP_IO_SPACE
97	101	select SYS_HAS_CPU_MIPS32_R1
98	102	select SYS_HAS_CPU_MIPS32_R2
99	103	select SYS_HAS_CPU_MIPS32_R6
@@ -478,6 +482,7 @@ config MACH_XILFPGA · 378 unmodified lines
478	482	select SYS_SUPPORTS_ZBOOT_UART16550
479	483	select USE_OF
480	484	select USE_GENERIC_EARLY_PRINTK_8250
	485	+ select XILINX_INTC
481	486	help
482	487	This enables support for the IMG University Program MIPSfpga platform.
483	488
@@ -909,6 +914,7 @@ config CAVIUM_OCTEON_SOC · 425 unmodified lines
909	914	select NR_CPUS_DEFAULT_16
910	915	select BUILTIN_DTB
911	916	select MTD_COMPLEX_MAPPINGS
	917	+ select SYS_SUPPORTS_RELOCATABLE
912	918	help
913	919	This option supports all of the Octeon reference boards from Cavium
914	920	Networks. It builds a kernel that dynamically determines the Octeon
@@ -1427,7 +1433,6 @@ config CPU_LOONGSON1C · 512 unmodified lines
1427	1433	bool "Loongson 1C"
1428	1434	depends on SYS_HAS_CPU_LOONGSON1C
1429	1435	select CPU_LOONGSON1
1430		− select ARCH_WANT_OPTIONAL_GPIOLIB
1431	1436	select LEDS_GPIO_REGISTER
1432	1437	help
1433	1438	The Loongson 1C is a 32-bit SoC, which implements the MIPS32
@@ -2288,7 +2293,7 @@ config MIPS_MT_FPAFF · 854 unmodified lines
2288	2293
2289	2294	config MIPSR2_TO_R6_EMULATOR
2290	2295	bool "MIPS R2-to-R6 emulator"
2291		− depends on CPU_MIPSR6 && !SMP
	2296	+ depends on CPU_MIPSR6
2292	2297	default y
2293	2298	help
2294	2299	Choose this option if you want to run non-R6 MIPS userland code.
@@ -2296,8 +2301,6 @@ config MIPSR2_TO_R6_EMULATOR · 1 unmodified line
2296	2301	default. You can enable it using the 'mipsr2emu' kernel option.
2297	2302	The only reason this is a build-time option is to save ~14K from the
2298	2303	final kernel image.
2299		−comment "MIPS R2-to-R6 emulator is only available for UP kernels"
2300		− depends on SMP && CPU_MIPSR6
2301	2304
2302	2305	config MIPS_VPE_LOADER
2303	2306	bool "VPE loader support."
@@ -2572,7 +2575,7 @@ config SYS_SUPPORTS_NUMA · 268 unmodified lines
2572	2575
2573	2576	config RELOCATABLE
2574	2577	bool "Relocatable kernel"
2575		− depends on SYS_SUPPORTS_RELOCATABLE && (CPU_MIPS32_R2 \|\| CPU_MIPS64_R2 \|\| CPU_MIPS32_R6 \|\| CPU_MIPS64_R6)
	2578	+ depends on SYS_SUPPORTS_RELOCATABLE && (CPU_MIPS32_R2 \|\| CPU_MIPS64_R2 \|\| CPU_MIPS32_R6 \|\| CPU_MIPS64_R6 \|\| CAVIUM_OCTEON_SOC)
2576	2579	help
2577	2580	This builds a kernel image that retains relocation information
2578	2581	so it can be loaded someplace besides the default 1MB.
@@ -2828,8 +2831,8 @@ config KEXEC · 249 unmodified lines
2828	2831	made.
2829	2832
2830	2833	config CRASH_DUMP
2831		− bool "Kernel crash dumps"
2832		− help
	2834	+ bool "Kernel crash dumps"
	2835	+ help
2833	2836	Generate crash dump after being started by kexec.
2834	2837	This should be normally only set in special crash dump kernels
2835	2838	which are loaded in the main kernel with kexec-tools into
@@ -2839,11 +2842,11 @@ config CRASH_DUMP · 3 unmodified lines
2839	2842	PHYSICAL_START.
2840	2843
2841	2844	config PHYSICAL_START
2842		− hex "Physical address where the kernel is loaded"
2843		− default "0xffffffff84000000" if 64BIT
2844		− default "0x84000000" if 32BIT
2845		− depends on CRASH_DUMP
2846		− help
	2845	+ hex "Physical address where the kernel is loaded"
	2846	+ default "0xffffffff84000000" if 64BIT
	2847	+ default "0x84000000" if 32BIT
	2848	+ depends on CRASH_DUMP
	2849	+ help
2847	2850	This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
2848	2851	If you plan to use kernel for capturing the crash dump change
2849	2852	this value to start of the reserved region (the "X" value as
@@ -3075,6 +3078,20 @@ config MMU · 225 unmodified lines
3075	3078	bool
3076	3079	default y
3077	3080
	3081	+config ARCH_MMAP_RND_BITS_MIN
	3082	+ default 12 if 64BIT
	3083	+ default 8
	3084	+
	3085	+config ARCH_MMAP_RND_BITS_MAX
	3086	+ default 18 if 64BIT
	3087	+ default 15
	3088	+
	3089	+config ARCH_MMAP_RND_COMPAT_BITS_MIN
	3090	+ default 8
	3091	+
	3092	+config ARCH_MMAP_RND_COMPAT_BITS_MAX
	3093	+ default 15
	3094	+
3078	3095	config I8253
3079	3096	bool
3080	3097	select CLKSRC_I8253

arch/mips/Makefile+21−14

@@ -131,6 +131,21 @@ cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += $(shell $(CC) -dumpmachine \|grep -q 'mips. · 130 unmodified lines
131	131
132	132	cflags-$(CONFIG_SB1XXX_CORELIS) += $(call cc-option,-mno-sched-prolog) \
133	133	-fno-omit-frame-pointer
	134	+
	135	+# Some distribution-specific toolchains might pass the -fstack-check
	136	+# option during the build, which adds a simple stack-probe at the beginning
	137	+# of every function. This stack probe is to ensure that there is enough
	138	+# stack space, else a SEGV is generated. This is not desirable for MIPS
	139	+# as kernel stacks are small, placed in unmapped virtual memory, and do not
	140	+# grow when overflowed. Especially on SGI IP27 platforms, this check will
	141	+# lead to a NULL pointer dereference in _raw_spin_lock_irq.
	142	+#
	143	+# In disassembly, this stack probe appears at the top of a function as:
	144	+# sd zero,<offset>(sp)
	145	+# Where <offset> is a negative value.
	146	+#
	147	+cflags-y += -fno-stack-check
	148	+
134	149	#
135	150	# CPU-dependent compiler/assembler options for optimization.
136	151	#
@@ -320,6 +335,9 @@ bootz-y := vmlinuz · 183 unmodified lines
320	335	bootz-y += vmlinuz.bin
321	336	bootz-y += vmlinuz.ecoff
322	337	bootz-y += vmlinuz.srec
	338	+ifeq ($(shell expr $(zload-y) \< 0xffffffff80000000 2> /dev/null), 0)
	339	+bootz-y += uzImage.bin
	340	+endif
323	341
324	342	ifdef CONFIG_LASAT
325	343	rom.bin rom.sw: vmlinux
@@ -327,10 +345,6 @@ rom.bin rom.sw: vmlinux · 1 unmodified line
327	345	$(bootvars-y) $@
328	346	endif
329	347
330		−CMD_RELOCS = arch/mips/boot/tools/relocs
331		−quiet_cmd_relocs = RELOCS $<
332		− cmd_relocs = $(CMD_RELOCS) $<
333		−
334	348	#
335	349	# Some machines like the Indy need 32-bit ELF binaries for booting purposes.
336	350	# Other need ECOFF, so we build a 32-bit ELF binary for them which we then
@@ -339,11 +353,6 @@ quiet_cmd_relocs = RELOCS $< · 2 unmodified lines
339	353	quiet_cmd_32 = OBJCOPY $@
340	354	cmd_32 = $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
341	355	vmlinux.32: vmlinux
342		−ifeq ($(CONFIG_RELOCATABLE)$(CONFIG_64BIT),yy)
343		−# Currently, objcopy fails to handle the relocations in the elf64
344		−# So the relocs tool must be run here to remove them first
345		− $(call cmd,relocs)
346		−endif
347	356	$(call cmd,32)
348	357
349	358	#
@@ -359,9 +368,6 @@ all: $(all-y) · 9 unmodified lines
359	368
360	369	# boot
361	370	$(boot-y): $(vmlinux-32) FORCE
362		−ifeq ($(CONFIG_RELOCATABLE)$(CONFIG_32BIT),yy)
363		− $(call cmd,relocs)
364		−endif
365	371	$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) \
366	372	$(bootvars-y) arch/mips/boot/$@
367	373
@@ -395,11 +401,11 @@ dtbs_install: · 27 unmodified lines
395	401
396	402	archprepare:
397	403	ifdef CONFIG_MIPS32_N32
398		− @echo ' Checking missing-syscalls for N32'
	404	+ @$(kecho) ' Checking missing-syscalls for N32'
399	405	$(Q)$(MAKE) $(build)=. missing-syscalls missing_syscalls_flags="-mabi=n32"
400	406	endif
401	407	ifdef CONFIG_MIPS32_O32
402		− @echo ' Checking missing-syscalls for O32'
	408	+ @$(kecho) ' Checking missing-syscalls for O32'
403	409	$(Q)$(MAKE) $(build)=. missing-syscalls missing_syscalls_flags="-mabi=32"
404	410	endif
405	411
@@ -433,6 +439,7 @@ define archhelp · 27 unmodified lines
433	439	echo ' uImage.gz - U-Boot image (gzip)'
434	440	echo ' uImage.lzma - U-Boot image (lzma)'
435	441	echo ' uImage.lzo - U-Boot image (lzo)'
	442	+ echo ' uzImage.bin - U-Boot image (self-extracting)'
436	443	echo ' dtbs - Device-tree blobs for enabled boards'
437	444	echo ' dtbs_install - Install dtbs to $(INSTALL_DTBS_PATH)'
438	445	echo

arch/mips/Makefile.postlink+35−0

@@ -0,0 +1,35 @@
	1	+# ===========================================================================
	2	+# Post-link MIPS pass
	3	+# ===========================================================================
	4	+#
	5	+# 1. Insert relocations into vmlinux
	6	+
	7	+PHONY := __archpost
	8	+__archpost:
	9	+
	10	+-include include/config/auto.conf
	11	+include scripts/Kbuild.include
	12	+
	13	+CMD_RELOCS = arch/mips/boot/tools/relocs
	14	+quiet_cmd_relocs = RELOCS $@
	15	+ cmd_relocs = $(CMD_RELOCS) $@
	16	+
	17	+# `@true` prevents complaint when there is nothing to be done
	18	+
	19	+vmlinux: FORCE
	20	+ @true
	21	+ifeq ($(CONFIG_RELOCATABLE),y)
	22	+ $(call if_changed,relocs)
	23	+endif
	24	+
	25	+%.ko: FORCE
	26	+ @true
	27	+
	28	+clean:
	29	+ @true
	30	+
	31	+PHONY += FORCE clean
	32	+
	33	+FORCE:
	34	+
	35	+.PHONY: $(PHONY)

arch/mips/alchemy/board-gpr.c+0−1

@@ -236,7 +236,6 @@ static struct platform_device gpr_i2c_device = { · 235 unmodified lines
236	236	static struct i2c_board_info gpr_i2c_info[] __initdata = {
237	237	{
238	238	I2C_BOARD_INFO("lm83", 0x18),
239		− .type = "lm83"
240	239	}
241	240	};
242	241

arch/mips/alchemy/common/dbdma.c+1−1

@@ -35,7 +35,7 @@ · 34 unmodified lines
35	35	#include <linux/slab.h>
36	36	#include <linux/spinlock.h>
37	37	#include <linux/interrupt.h>
38		−#include <linux/module.h>
	38	+#include <linux/export.h>
39	39	#include <linux/syscore_ops.h>
40	40	#include <asm/mach-au1x00/au1000.h>
41	41	#include <asm/mach-au1x00/au1xxx_dbdma.h>

arch/mips/alchemy/common/dma.c+1−1

@@ -31,7 +31,7 @@ · 30 unmodified lines
31	31	*/
32	32
33	33	#include <linux/init.h>
34		−#include <linux/module.h>
	34	+#include <linux/export.h>
35	35	#include <linux/kernel.h>
36	36	#include <linux/errno.h>
37	37	#include <linux/spinlock.h>

arch/mips/alchemy/common/gpiolib.c+0−1

@@ -32,7 +32,6 @@ · 31 unmodified lines
32	32
33	33	#include <linux/init.h>
34	34	#include <linux/kernel.h>
35		−#include <linux/module.h>
36	35	#include <linux/types.h>
37	36	#include <linux/gpio.h>
38	37	#include <asm/mach-au1x00/gpio-au1000.h>

arch/mips/alchemy/common/prom.c+0−1

@@ -33,7 +33,6 @@ · 32 unmodified lines
33	33	* 675 Mass Ave, Cambridge, MA 02139, USA.
34	34	*/
35	35
36		−#include <linux/module.h>
37	36	#include <linux/init.h>
38	37	#include <linux/string.h>
39	38

arch/mips/alchemy/common/usb.c+1−1

@@ -10,9 +10,9 @@ · 9 unmodified lines
10	10	*/
11	11
12	12	#include <linux/clk.h>
	13	+#include <linux/export.h>
13	14	#include <linux/init.h>
14	15	#include <linux/io.h>
15		−#include <linux/module.h>
16	16	#include <linux/spinlock.h>
17	17	#include <linux/syscore_ops.h>
18	18	#include <asm/cpu.h>

arch/mips/alchemy/common/vss.c+1−1

@@ -6,7 +6,7 @@ · 5 unmodified lines
6	6	* for various media blocks are enabled/disabled.
7	7	*/
8	8
9		−#include <linux/module.h>
	9	+#include <linux/export.h>
10	10	#include <linux/spinlock.h>
11	11	#include <asm/mach-au1x00/au1000.h>
12	12

arch/mips/alchemy/devboards/bcsr.c+2−1

@@ -9,7 +9,8 @@ · 8 unmodified lines
9	9
10	10	#include <linux/interrupt.h>
11	11	#include <linux/irqchip/chained_irq.h>
12		−#include <linux/module.h>
	12	+#include <linux/init.h>
	13	+#include <linux/export.h>
13	14	#include <linux/spinlock.h>
14	15	#include <linux/irq.h>
15	16	#include <asm/addrspace.h>

arch/mips/ar7/clock.c+1−1

@@ -21,7 +21,7 @@ · 20 unmodified lines
21	21	#include <linux/kernel.h>
22	22	#include <linux/init.h>
23	23	#include <linux/types.h>
24		−#include <linux/module.h>
	24	+#include <linux/export.h>
25	25	#include <linux/delay.h>
26	26	#include <linux/gcd.h>
27	27	#include <linux/io.h>

arch/mips/ar7/gpio.c+2−1

@@ -18,7 +18,8 @@ · 17 unmodified lines
18	18	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19	19	*/
20	20
21		−#include <linux/module.h>
	21	+#include <linux/init.h>
	22	+#include <linux/export.h>
22	23	#include <linux/gpio.h>
23	24
24	25	#include <asm/mach-ar7/ar7.h>

arch/mips/ar7/memory.c+0−1

@@ -19,7 +19,6 @@ · 18 unmodified lines
19	19	#include <linux/bootmem.h>
20	20	#include <linux/init.h>
21	21	#include <linux/mm.h>
22		−#include <linux/module.h>
23	22	#include <linux/pfn.h>
24	23	#include <linux/proc_fs.h>
25	24	#include <linux/string.h>

arch/mips/ar7/platform.c+0−1

@@ -19,7 +19,6 @@ · 18 unmodified lines
19	19
20	20	#include <linux/init.h>
21	21	#include <linux/types.h>
22		−#include <linux/module.h>
23	22	#include <linux/delay.h>
24	23	#include <linux/dma-mapping.h>
25	24	#include <linux/platform_device.h>

arch/mips/ar7/prom.c+1−1

@@ -21,7 +21,7 @@ · 20 unmodified lines
21	21	#include <linux/kernel.h>
22	22	#include <linux/serial_reg.h>
23	23	#include <linux/spinlock.h>
24		−#include <linux/module.h>
	24	+#include <linux/export.h>
25	25	#include <linux/string.h>
26	26	#include <linux/io.h>
27	27	#include <asm/bootinfo.h>

arch/mips/ath79/clock.c+6−4

@@ -12,7 +12,6 @@ · 11 unmodified lines
12	12	*/
13	13
14	14	#include <linux/kernel.h>
15		−#include <linux/module.h>
16	15	#include <linux/init.h>
17	16	#include <linux/err.h>
18	17	#include <linux/clk.h>
@@ -45,7 +44,7 @@ static struct clk *__init ath79_add_sys_clkdev( · 26 unmodified lines
45	44	int err;
46	45
47	46	clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate);
48		− if (!clk)
	47	+ if (IS_ERR(clk))
49	48	panic("failed to allocate %s clock structure", id);
50	49
51	50	err = clk_register_clkdev(clk, id, NULL);
@@ -508,16 +507,19 @@ static void __init ath79_clocks_init_dt_ng(struct device_node *np) · 456 unmodified lines
508	507	ar9330_clk_init(ref_clk, pll_base);
509	508	else {
510	509	pr_err("%s: could not find any appropriate clk_init()\n", dnfn);
511		− goto err_clk;
	510	+ goto err_iounmap;
512	511	}
513	512
514	513	if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
515	514	pr_err("%s: could not register clk provider\n", dnfn);
516		− goto err_clk;
	515	+ goto err_iounmap;
517	516	}
518	517
519	518	return;
520	519
	520	+err_iounmap:
	521	+ iounmap(pll_base);
	522	+
521	523	err_clk:
522	524	clk_put(ref_clk);
523	525

arch/mips/ath79/common.c+1−1

@@ -13,7 +13,7 @@ · 12 unmodified lines
13	13	*/
14	14
15	15	#include <linux/kernel.h>
16		−#include <linux/module.h>
	16	+#include <linux/export.h>
17	17	#include <linux/types.h>
18	18	#include <linux/spinlock.h>
19	19

arch/mips/bcm47xx/board.c+9−0

@@ -149,6 +149,15 @@ struct bcm47xx_board_type_list2 bcm47xx_board_list_boot_hw[] __initconst = { · 148 unmodified lines
149	149	/* board_id */
150	150	static const
151	151	struct bcm47xx_board_type_list1 bcm47xx_board_list_board_id[] __initconst = {
	152	+ {{BCM47XX_BOARD_LUXUL_ABR_4400_V1, "Luxul ABR-4400 V1"}, "luxul_abr4400_v1"},
	153	+ {{BCM47XX_BOARD_LUXUL_XAP_310_V1, "Luxul XAP-310 V1"}, "luxul_xap310_v1"},
	154	+ {{BCM47XX_BOARD_LUXUL_XAP_1210_V1, "Luxul XAP-1210 V1"}, "luxul_xap1210_v1"},
	155	+ {{BCM47XX_BOARD_LUXUL_XAP_1230_V1, "Luxul XAP-1230 V1"}, "luxul_xap1230_v1"},
	156	+ {{BCM47XX_BOARD_LUXUL_XAP_1240_V1, "Luxul XAP-1240 V1"}, "luxul_xap1240_v1"},
	157	+ {{BCM47XX_BOARD_LUXUL_XAP_1500_V1, "Luxul XAP-1500 V1"}, "luxul_xap1500_v1"},
	158	+ {{BCM47XX_BOARD_LUXUL_XBR_4400_V1, "Luxul XBR-4400 V1"}, "luxul_xbr4400_v1"},
	159	+ {{BCM47XX_BOARD_LUXUL_XVW_P30_V1, "Luxul XVW-P30 V1"}, "luxul_xvwp30_v1"},
	160	+ {{BCM47XX_BOARD_LUXUL_XWR_600_V1, "Luxul XWR-600 V1"}, "luxul_xwr600_v1"},
152	161	{{BCM47XX_BOARD_LUXUL_XWR_1750_V1, "Luxul XWR-1750 V1"}, "luxul_xwr1750_v1"},
153	162	{{BCM47XX_BOARD_NETGEAR_WGR614V8, "Netgear WGR614 V8"}, "U12H072T00_NETGEAR"},
154	163	{{BCM47XX_BOARD_NETGEAR_WGR614V9, "Netgear WGR614 V9"}, "U12H094T00_NETGEAR"},

arch/mips/bcm47xx/buttons.c+80−2

@@ -17,6 +17,12 @@ · 16 unmodified lines
17	17	.active_low = 1, \
18	18	}
19	19
	20	+#define BCM47XX_GPIO_KEY_H(_gpio, _code) \
	21	+ { \
	22	+ .code = _code, \
	23	+ .gpio = _gpio, \
	24	+ }
	25	+
20	26	/* Asus */
21	27
22	28	static const struct gpio_keys_button
@@ -79,8 +85,8 @@ bcm47xx_buttons_asus_wl500gpv2[] __initconst = { · 56 unmodified lines
79	85
80	86	static const struct gpio_keys_button
81	87	bcm47xx_buttons_asus_wl500w[] __initconst = {
82		− BCM47XX_GPIO_KEY(6, KEY_RESTART),
83		− BCM47XX_GPIO_KEY(7, KEY_WPS_BUTTON),
	88	+ BCM47XX_GPIO_KEY_H(6, KEY_RESTART),
	89	+ BCM47XX_GPIO_KEY_H(7, KEY_WPS_BUTTON),
84	90	};
85	91
86	92	static const struct gpio_keys_button
@@ -301,6 +307,51 @@ bcm47xx_buttons_linksys_wrtsl54gs[] __initconst = { · 214 unmodified lines
301	307
302	308	/* Luxul */
303	309
	310	+static const struct gpio_keys_button
	311	+bcm47xx_buttons_luxul_abr_4400_v1[] = {
	312	+ BCM47XX_GPIO_KEY(14, KEY_RESTART),
	313	+};
	314	+
	315	+static const struct gpio_keys_button
	316	+bcm47xx_buttons_luxul_xap_310_v1[] = {
	317	+ BCM47XX_GPIO_KEY(20, KEY_RESTART),
	318	+};
	319	+
	320	+static const struct gpio_keys_button
	321	+bcm47xx_buttons_luxul_xap_1210_v1[] = {
	322	+ BCM47XX_GPIO_KEY(8, KEY_RESTART),
	323	+};
	324	+
	325	+static const struct gpio_keys_button
	326	+bcm47xx_buttons_luxul_xap_1230_v1[] = {
	327	+ BCM47XX_GPIO_KEY(8, KEY_RESTART),
	328	+};
	329	+
	330	+static const struct gpio_keys_button
	331	+bcm47xx_buttons_luxul_xap_1240_v1[] = {
	332	+ BCM47XX_GPIO_KEY(8, KEY_RESTART),
	333	+};
	334	+
	335	+static const struct gpio_keys_button
	336	+bcm47xx_buttons_luxul_xap_1500_v1[] = {
	337	+ BCM47XX_GPIO_KEY(14, KEY_RESTART),
	338	+};
	339	+
	340	+static const struct gpio_keys_button
	341	+bcm47xx_buttons_luxul_xbr_4400_v1[] = {
	342	+ BCM47XX_GPIO_KEY(14, KEY_RESTART),
	343	+};
	344	+
	345	+static const struct gpio_keys_button
	346	+bcm47xx_buttons_luxul_xvw_p30_v1[] = {
	347	+ BCM47XX_GPIO_KEY(20, KEY_RESTART),
	348	+};
	349	+
	350	+static const struct gpio_keys_button
	351	+bcm47xx_buttons_luxul_xwr_600_v1[] = {
	352	+ BCM47XX_GPIO_KEY(8, KEY_RESTART),
	353	+};
	354	+
304	355	static const struct gpio_keys_button
305	356	bcm47xx_buttons_luxul_xwr_1750_v1[] = {
306	357	BCM47XX_GPIO_KEY(14, BTN_TASK),
@@ -561,6 +612,33 @@ int __init bcm47xx_buttons_register(void) · 254 unmodified lines
561	612	err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrtsl54gs);
562	613	break;
563	614
	615	+ case BCM47XX_BOARD_LUXUL_ABR_4400_V1:
	616	+ err = bcm47xx_copy_bdata(bcm47xx_buttons_luxul_abr_4400_v1);
	617	+ break;
	618	+ case BCM47XX_BOARD_LUXUL_XAP_310_V1:
	619	+ err = bcm47xx_copy_bdata(bcm47xx_buttons_luxul_xap_310_v1);
	620	+ break;
	621	+ case BCM47XX_BOARD_LUXUL_XAP_1210_V1:
	622	+ err = bcm47xx_copy_bdata(bcm47xx_buttons_luxul_xap_1210_v1);
	623	+ break;
	624	+ case BCM47XX_BOARD_LUXUL_XAP_1230_V1:
	625	+ err = bcm47xx_copy_bdata(bcm47xx_buttons_luxul_xap_1230_v1);
	626	+ break;
	627	+ case BCM47XX_BOARD_LUXUL_XAP_1240_V1:
	628	+ err = bcm47xx_copy_bdata(bcm47xx_buttons_luxul_xap_1240_v1);
	629	+ break;
	630	+ case BCM47XX_BOARD_LUXUL_XAP_1500_V1:
	631	+ err = bcm47xx_copy_bdata(bcm47xx_buttons_luxul_xap_1500_v1);
	632	+ break;
	633	+ case BCM47XX_BOARD_LUXUL_XBR_4400_V1:
	634	+ err = bcm47xx_copy_bdata(bcm47xx_buttons_luxul_xbr_4400_v1);
	635	+ break;
	636	+ case BCM47XX_BOARD_LUXUL_XVW_P30_V1:
	637	+ err = bcm47xx_copy_bdata(bcm47xx_buttons_luxul_xvw_p30_v1);
	638	+ break;
	639	+ case BCM47XX_BOARD_LUXUL_XWR_600_V1:
	640	+ err = bcm47xx_copy_bdata(bcm47xx_buttons_luxul_xwr_600_v1);
	641	+ break;
564	642	case BCM47XX_BOARD_LUXUL_XWR_1750_V1:
565	643	err = bcm47xx_copy_bdata(bcm47xx_buttons_luxul_xwr_1750_v1);
566	644	break;

arch/mips/bcm47xx/leds.c+81−0

@@ -372,6 +372,60 @@ bcm47xx_leds_linksys_wrtsl54gs[] __initconst = { · 371 unmodified lines
372	372
373	373	/* Luxul */
374	374
	375	+static const struct gpio_led
	376	+bcm47xx_leds_luxul_abr_4400_v1[] __initconst = {
	377	+ BCM47XX_GPIO_LED(12, "green", "usb", 0, LEDS_GPIO_DEFSTATE_OFF),
	378	+ BCM47XX_GPIO_LED_TRIGGER(15, "green", "status", 0, "timer"),
	379	+};
	380	+
	381	+static const struct gpio_led
	382	+bcm47xx_leds_luxul_xap_310_v1[] __initconst = {
	383	+ BCM47XX_GPIO_LED_TRIGGER(6, "green", "status", 1, "timer"),
	384	+};
	385	+
	386	+static const struct gpio_led
	387	+bcm47xx_leds_luxul_xap_1210_v1[] __initconst = {
	388	+ BCM47XX_GPIO_LED_TRIGGER(6, "green", "status", 1, "timer"),
	389	+};
	390	+
	391	+static const struct gpio_led
	392	+bcm47xx_leds_luxul_xap_1230_v1[] __initconst = {
	393	+ BCM47XX_GPIO_LED(3, "blue", "2ghz", 0, LEDS_GPIO_DEFSTATE_OFF),
	394	+ BCM47XX_GPIO_LED(4, "green", "bridge", 0, LEDS_GPIO_DEFSTATE_OFF),
	395	+ BCM47XX_GPIO_LED_TRIGGER(6, "green", "status", 1, "timer"),
	396	+};
	397	+
	398	+static const struct gpio_led
	399	+bcm47xx_leds_luxul_xap_1240_v1[] __initconst = {
	400	+ BCM47XX_GPIO_LED(3, "blue", "2ghz", 0, LEDS_GPIO_DEFSTATE_OFF),
	401	+ BCM47XX_GPIO_LED(4, "green", "bridge", 0, LEDS_GPIO_DEFSTATE_OFF),
	402	+ BCM47XX_GPIO_LED_TRIGGER(6, "green", "status", 1, "timer"),
	403	+};
	404	+
	405	+static const struct gpio_led
	406	+bcm47xx_leds_luxul_xap_1500_v1[] __initconst = {
	407	+ BCM47XX_GPIO_LED_TRIGGER(13, "green", "status", 1, "timer"),
	408	+};
	409	+
	410	+static const struct gpio_led
	411	+bcm47xx_leds_luxul_xbr_4400_v1[] __initconst = {
	412	+ BCM47XX_GPIO_LED(12, "green", "usb", 0, LEDS_GPIO_DEFSTATE_OFF),
	413	+ BCM47XX_GPIO_LED_TRIGGER(15, "green", "status", 0, "timer"),
	414	+};
	415	+
	416	+static const struct gpio_led
	417	+bcm47xx_leds_luxul_xvw_p30_v1[] __initconst = {
	418	+ BCM47XX_GPIO_LED_TRIGGER(0, "blue", "status", 1, "timer"),
	419	+ BCM47XX_GPIO_LED(1, "green", "link", 1, LEDS_GPIO_DEFSTATE_OFF),
	420	+};
	421	+
	422	+static const struct gpio_led
	423	+bcm47xx_leds_luxul_xwr_600_v1[] __initconst = {
	424	+ BCM47XX_GPIO_LED(3, "green", "wps", 0, LEDS_GPIO_DEFSTATE_OFF),
	425	+ BCM47XX_GPIO_LED_TRIGGER(6, "green", "status", 1, "timer"),
	426	+ BCM47XX_GPIO_LED(9, "green", "usb", 0, LEDS_GPIO_DEFSTATE_OFF),
	427	+};
	428	+
375	429	static const struct gpio_led
376	430	bcm47xx_leds_luxul_xwr_1750_v1[] __initconst = {
377	431	BCM47XX_GPIO_LED(5, "green", "5ghz", 0, LEDS_GPIO_DEFSTATE_OFF),
@@ -633,6 +687,33 @@ void __init bcm47xx_leds_register(void) · 255 unmodified lines
633	687	bcm47xx_set_pdata(bcm47xx_leds_linksys_wrtsl54gs);
634	688	break;
635	689
	690	+ case BCM47XX_BOARD_LUXUL_ABR_4400_V1:
	691	+ bcm47xx_set_pdata(bcm47xx_leds_luxul_abr_4400_v1);
	692	+ break;
	693	+ case BCM47XX_BOARD_LUXUL_XAP_310_V1:
	694	+ bcm47xx_set_pdata(bcm47xx_leds_luxul_xap_310_v1);
	695	+ break;
	696	+ case BCM47XX_BOARD_LUXUL_XAP_1210_V1:
	697	+ bcm47xx_set_pdata(bcm47xx_leds_luxul_xap_1210_v1);
	698	+ break;
	699	+ case BCM47XX_BOARD_LUXUL_XAP_1230_V1:
	700	+ bcm47xx_set_pdata(bcm47xx_leds_luxul_xap_1230_v1);
	701	+ break;
	702	+ case BCM47XX_BOARD_LUXUL_XAP_1240_V1:
	703	+ bcm47xx_set_pdata(bcm47xx_leds_luxul_xap_1240_v1);
	704	+ break;
	705	+ case BCM47XX_BOARD_LUXUL_XAP_1500_V1:
	706	+ bcm47xx_set_pdata(bcm47xx_leds_luxul_xap_1500_v1);
	707	+ break;
	708	+ case BCM47XX_BOARD_LUXUL_XBR_4400_V1:
	709	+ bcm47xx_set_pdata(bcm47xx_leds_luxul_xbr_4400_v1);
	710	+ break;
	711	+ case BCM47XX_BOARD_LUXUL_XVW_P30_V1:
	712	+ bcm47xx_set_pdata(bcm47xx_leds_luxul_xvw_p30_v1);
	713	+ break;
	714	+ case BCM47XX_BOARD_LUXUL_XWR_600_V1:
	715	+ bcm47xx_set_pdata(bcm47xx_leds_luxul_xwr_600_v1);
	716	+ break;
636	717	case BCM47XX_BOARD_LUXUL_XWR_1750_V1:
637	718	bcm47xx_set_pdata(bcm47xx_leds_luxul_xwr_1750_v1);
638	719	break;

arch/mips/bcm63xx/clk.c+2−1

@@ -6,7 +6,8 @@ · 5 unmodified lines
6	6	* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7	7	*/
8	8
9		−#include <linux/module.h>
	9	+#include <linux/init.h>
	10	+#include <linux/export.h>
10	11	#include <linux/mutex.h>
11	12	#include <linux/err.h>
12	13	#include <linux/clk.h>

arch/mips/bcm63xx/cpu.c+1−1

@@ -8,7 +8,7 @@ · 7 unmodified lines
8	8	*/
9	9
10	10	#include <linux/kernel.h>
11		−#include <linux/module.h>
	11	+#include <linux/export.h>
12	12	#include <linux/cpu.h>
13	13	#include <asm/cpu.h>
14	14	#include <asm/cpu-info.h>

arch/mips/bcm63xx/cs.c+2−1

@@ -7,7 +7,8 @@ · 6 unmodified lines
7	7	*/
8	8
9	9	#include <linux/kernel.h>
10		−#include <linux/module.h>
	10	+#include <linux/errno.h>
	11	+#include <linux/export.h>
11	12	#include <linux/spinlock.h>
12	13	#include <linux/log2.h>
13	14	#include <bcm63xx_cpu.h>

arch/mips/bcm63xx/gpio.c+1−1

@@ -8,7 +8,7 @@ · 7 unmodified lines
8	8	*/
9	9
10	10	#include <linux/kernel.h>
11		−#include <linux/module.h>
	11	+#include <linux/init.h>
12	12	#include <linux/spinlock.h>
13	13	#include <linux/platform_device.h>
14	14	#include <linux/gpio/driver.h>

arch/mips/bcm63xx/irq.c+0−1

@@ -10,7 +10,6 @@ · 9 unmodified lines
10	10	#include <linux/kernel.h>
11	11	#include <linux/init.h>
12	12	#include <linux/interrupt.h>
13		−#include <linux/module.h>
14	13	#include <linux/irq.h>
15	14	#include <linux/spinlock.h>
16	15	#include <asm/irq_cpu.h>

arch/mips/bcm63xx/reset.c+2−1

@@ -6,7 +6,8 @@ · 5 unmodified lines
6	6	* Copyright (C) 2012 Jonas Gorski <jonas.gorski@gmail.com>
7	7	*/
8	8
9		−#include <linux/module.h>
	9	+#include <linux/init.h>
	10	+#include <linux/export.h>
10	11	#include <linux/mutex.h>
11	12	#include <linux/err.h>
12	13	#include <linux/clk.h>

arch/mips/bcm63xx/timer.c+2−1

@@ -8,7 +8,8 @@ · 7 unmodified lines
8	8
9	9	#include <linux/kernel.h>
10	10	#include <linux/err.h>
11		−#include <linux/module.h>
	11	+#include <linux/init.h>
	12	+#include <linux/export.h>
12	13	#include <linux/spinlock.h>
13	14	#include <linux/interrupt.h>
14	15	#include <linux/clk.h>

arch/mips/boot/compressed/Makefile+7−3

@@ -18,14 +18,14 @@ include $(srctree)/arch/mips/Kbuild.platforms · 17 unmodified lines
18	18	BOOT_HEAP_SIZE := 0x400000
19	19
20	20	# Disable Function Tracer
21		−KBUILD_CFLAGS := $(shell echo $(KBUILD_CFLAGS) \| sed -e "s/-pg//")
	21	+KBUILD_CFLAGS := $(filter-out -pg, $(KBUILD_CFLAGS))
22	22
23	23	KBUILD_CFLAGS := $(filter-out -fstack-protector, $(KBUILD_CFLAGS))
24	24
25		−KBUILD_CFLAGS := $(LINUXINCLUDE) $(KBUILD_CFLAGS) -D__KERNEL__ \
	25	+KBUILD_CFLAGS := $(KBUILD_CFLAGS) -D__KERNEL__ \
26	26	-DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) -D"VMLINUX_LOAD_ADDRESS_ULL=$(VMLINUX_LOAD_ADDRESS)ull"
27	27
28		−KBUILD_AFLAGS := $(LINUXINCLUDE) $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
	28	+KBUILD_AFLAGS := $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
29	29	-DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) \
30	30	-DKERNEL_ENTRY=$(VMLINUX_ENTRY_ADDRESS)
31	31
@@ -84,6 +84,7 @@ else · 52 unmodified lines
84	84	VMLINUZ_LOAD_ADDRESS = $(shell $(obj)/calc_vmlinuz_load_addr \
85	85	$(obj)/vmlinux.bin $(VMLINUX_LOAD_ADDRESS))
86	86	endif
	87	+UIMAGE_LOADADDR = $(VMLINUZ_LOAD_ADDRESS)
87	88
88	89	vmlinuzobjs-y += $(obj)/piggy.o
89	90
@@ -129,4 +130,7 @@ OBJCOPYFLAGS_vmlinuz.srec := $(OBJCOPYFLAGS) -S -O srec · 39 unmodified lines
129	130	vmlinuz.srec: vmlinuz
130	131	$(call cmd,objcopy)
131	132
	133	+uzImage.bin: vmlinuz.bin FORCE
	134	+ $(call if_changed,uimage,none)
	135	+
132	136	clean-files := $(objtree)/vmlinuz $(objtree)/vmlinuz.{32,ecoff,bin,srec}

arch/mips/boot/dts/Makefile+1−0

@@ -1,5 +1,6 @@
1	1	dts-dirs += brcm
2	2	dts-dirs += cavium-octeon
	3	+dts-dirs += img
3	4	dts-dirs += ingenic
4	5	dts-dirs += lantiq
5	6	dts-dirs += mti

arch/mips/boot/dts/brcm/bcm7125.dtsi+46−3

@@ -91,15 +91,15 @@ · 90 unmodified lines
91	91	compatible = "brcm,bcm7120-l2-intc";
92	92	reg = <0x406780 0x8>;
93	93
94		− brcm,int-map-mask = <0x44>, <0xf000000>;
	94	+ brcm,int-map-mask = <0x44>, <0xf000000>, <0x100000>;
95	95	brcm,int-fwd-mask = <0x70000>;
96	96
97	97	interrupt-controller;
98	98	#interrupt-cells = <1>;
99	99
100	100	interrupt-parent = <&periph_intc>;
101		− interrupts = <18>, <19>;
102		− interrupt-names = "upg_main", "upg_bsc";
	101	+ interrupts = <18>, <19>, <20>;
	102	+ interrupt-names = "upg_main", "upg_bsc", "upg_spi";
103	103	};
104	104
105	105	sun_top_ctrl: syscon@404000 {
@@ -226,5 +226,48 @@ · 120 unmodified lines
226	226	interrupts = <61>;
227	227	status = "disabled";
228	228	};
	229	+
	230	+ spi_l2_intc: interrupt-controller@411d00 {
	231	+ compatible = "brcm,l2-intc";
	232	+ reg = <0x411d00 0x30>;
	233	+ interrupt-controller;
	234	+ #interrupt-cells = <1>;
	235	+ interrupt-parent = <&periph_intc>;
	236	+ interrupts = <79>;
	237	+ };
	238	+
	239	+ qspi: spi@443000 {
	240	+ #address-cells = <0x1>;
	241	+ #size-cells = <0x0>;
	242	+ compatible = "brcm,spi-bcm-qspi",
	243	+ "brcm,spi-brcmstb-qspi";
	244	+ clocks = <&upg_clk>;
	245	+ reg = <0x440920 0x4 0x443200 0x188 0x443000 0x50>;
	246	+ reg-names = "cs_reg", "hif_mspi", "bspi";
	247	+ interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
	248	+ interrupt-parent = <&spi_l2_intc>;
	249	+ interrupt-names = "spi_lr_fullness_reached",
	250	+ "spi_lr_session_aborted",
	251	+ "spi_lr_impatient",
	252	+ "spi_lr_session_done",
	253	+ "spi_lr_overread",
	254	+ "mspi_done",
	255	+ "mspi_halted";
	256	+ status = "disabled";
	257	+ };
	258	+
	259	+ mspi: spi@406400 {
	260	+ #address-cells = <1>;
	261	+ #size-cells = <0>;
	262	+ compatible = "brcm,spi-bcm-qspi",
	263	+ "brcm,spi-brcmstb-mspi";
	264	+ clocks = <&upg_clk>;
	265	+ reg = <0x406400 0x180>;
	266	+ reg-names = "mspi";
	267	+ interrupts = <0x14>;
	268	+ interrupt-parent = <&upg_irq0_intc>;
	269	+ interrupt-names = "mspi_done";
	270	+ status = "disabled";
	271	+ };
229	272	};
230	273	};

arch/mips/boot/dts/brcm/bcm7346.dtsi+43−0

@@ -439,5 +439,48 @@ · 438 unmodified lines
439	439	interrupts = <85>;
440	440	status = "disabled";
441	441	};
	442	+
	443	+ spi_l2_intc: interrupt-controller@411d00 {
	444	+ compatible = "brcm,l2-intc";
	445	+ reg = <0x411d00 0x30>;
	446	+ interrupt-controller;
	447	+ #interrupt-cells = <1>;
	448	+ interrupt-parent = <&periph_intc>;
	449	+ interrupts = <31>;
	450	+ };
	451	+
	452	+ qspi: spi@413000 {
	453	+ #address-cells = <0x1>;
	454	+ #size-cells = <0x0>;
	455	+ compatible = "brcm,spi-bcm-qspi",
	456	+ "brcm,spi-brcmstb-qspi";
	457	+ clocks = <&upg_clk>;
	458	+ reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
	459	+ reg-names = "cs_reg", "hif_mspi", "bspi";
	460	+ interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
	461	+ interrupt-parent = <&spi_l2_intc>;
	462	+ interrupt-names = "spi_lr_fullness_reached",
	463	+ "spi_lr_session_aborted",
	464	+ "spi_lr_impatient",
	465	+ "spi_lr_session_done",
	466	+ "spi_lr_overread",
	467	+ "mspi_done",
	468	+ "mspi_halted";
	469	+ status = "disabled";
	470	+ };
	471	+
	472	+ mspi: spi@408a00 {
	473	+ #address-cells = <1>;
	474	+ #size-cells = <0>;
	475	+ compatible = "brcm,spi-bcm-qspi",
	476	+ "brcm,spi-brcmstb-mspi";
	477	+ clocks = <&upg_clk>;
	478	+ reg = <0x408a00 0x180>;
	479	+ reg-names = "mspi";
	480	+ interrupts = <0x14>;
	481	+ interrupt-parent = <&upg_aon_irq0_intc>;
	482	+ interrupt-names = "mspi_done";
	483	+ status = "disabled";
	484	+ };
442	485	};
443	486	};

arch/mips/boot/dts/brcm/bcm7358.dtsi+43−0

@@ -318,5 +318,48 @@ · 317 unmodified lines
318	318	interrupts = <24>;
319	319	status = "disabled";
320	320	};
	321	+
	322	+ spi_l2_intc: interrupt-controller@411d00 {
	323	+ compatible = "brcm,l2-intc";
	324	+ reg = <0x411d00 0x30>;
	325	+ interrupt-controller;
	326	+ #interrupt-cells = <1>;
	327	+ interrupt-parent = <&periph_intc>;
	328	+ interrupts = <31>;
	329	+ };
	330	+
	331	+ qspi: spi@413000 {
	332	+ #address-cells = <0x1>;
	333	+ #size-cells = <0x0>;
	334	+ compatible = "brcm,spi-bcm-qspi",
	335	+ "brcm,spi-brcmstb-qspi";
	336	+ clocks = <&upg_clk>;
	337	+ reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
	338	+ reg-names = "cs_reg", "hif_mspi", "bspi";
	339	+ interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
	340	+ interrupt-parent = <&spi_l2_intc>;
	341	+ interrupt-names = "spi_lr_fullness_reached",
	342	+ "spi_lr_session_aborted",
	343	+ "spi_lr_impatient",
	344	+ "spi_lr_session_done",
	345	+ "spi_lr_overread",
	346	+ "mspi_done",
	347	+ "mspi_halted";
	348	+ status = "disabled";
	349	+ };
	350	+
	351	+ mspi: spi@408a00 {
	352	+ #address-cells = <1>;
	353	+ #size-cells = <0>;
	354	+ compatible = "brcm,spi-bcm-qspi",
	355	+ "brcm,spi-brcmstb-mspi";
	356	+ clocks = <&upg_clk>;
	357	+ reg = <0x408a00 0x180>;
	358	+ reg-names = "mspi";
	359	+ interrupts = <0x14>;
	360	+ interrupt-parent = <&upg_aon_irq0_intc>;
	361	+ interrupt-names = "mspi_done";
	362	+ status = "disabled";
	363	+ };
321	364	};
322	365	};

arch/mips/boot/dts/brcm/bcm7360.dtsi+43−0

@@ -358,5 +358,48 @@ · 357 unmodified lines
358	358	interrupts = <82>;
359	359	status = "disabled";
360	360	};
	361	+
	362	+ spi_l2_intc: interrupt-controller@411d00 {
	363	+ compatible = "brcm,l2-intc";
	364	+ reg = <0x411d00 0x30>;
	365	+ interrupt-controller;
	366	+ #interrupt-cells = <1>;
	367	+ interrupt-parent = <&periph_intc>;
	368	+ interrupts = <31>;
	369	+ };
	370	+
	371	+ qspi: spi@413000 {
	372	+ #address-cells = <0x1>;
	373	+ #size-cells = <0x0>;
	374	+ compatible = "brcm,spi-bcm-qspi",
	375	+ "brcm,spi-brcmstb-qspi";
	376	+ clocks = <&upg_clk>;
	377	+ reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
	378	+ reg-names = "cs_reg", "hif_mspi", "bspi";
	379	+ interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
	380	+ interrupt-parent = <&spi_l2_intc>;
	381	+ interrupt-names = "spi_lr_fullness_reached",
	382	+ "spi_lr_session_aborted",
	383	+ "spi_lr_impatient",
	384	+ "spi_lr_session_done",
	385	+ "spi_lr_overread",
	386	+ "mspi_done",
	387	+ "mspi_halted";
	388	+ status = "disabled";
	389	+ };
	390	+
	391	+ mspi: spi@408a00 {
	392	+ #address-cells = <1>;
	393	+ #size-cells = <0>;
	394	+ compatible = "brcm,spi-bcm-qspi",
	395	+ "brcm,spi-brcmstb-mspi";
	396	+ clocks = <&upg_clk>;
	397	+ reg = <0x408a00 0x180>;
	398	+ reg-names = "mspi";
	399	+ interrupts = <0x14>;
	400	+ interrupt-parent = <&upg_aon_irq0_intc>;
	401	+ interrupt-names = "mspi_done";
	402	+ status = "disabled";
	403	+ };
361	404	};
362	405	};

arch/mips/boot/dts/brcm/bcm7362.dtsi+43−0

@@ -354,5 +354,48 @@ · 353 unmodified lines
354	354	interrupts = <82>;
355	355	status = "disabled";
356	356	};
	357	+
	358	+ spi_l2_intc: interrupt-controller@411d00 {
	359	+ compatible = "brcm,l2-intc";
	360	+ reg = <0x411d00 0x30>;
	361	+ interrupt-controller;
	362	+ #interrupt-cells = <1>;
	363	+ interrupt-parent = <&periph_intc>;
	364	+ interrupts = <31>;
	365	+ };
	366	+
	367	+ qspi: spi@413000 {
	368	+ #address-cells = <0x1>;
	369	+ #size-cells = <0x0>;
	370	+ compatible = "brcm,spi-bcm-qspi",
	371	+ "brcm,spi-brcmstb-qspi";
	372	+ clocks = <&upg_clk>;
	373	+ reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
	374	+ reg-names = "cs_reg", "hif_mspi", "bspi";
	375	+ interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
	376	+ interrupt-parent = <&spi_l2_intc>;
	377	+ interrupt-names = "spi_lr_fullness_reached",
	378	+ "spi_lr_session_aborted",
	379	+ "spi_lr_impatient",
	380	+ "spi_lr_session_done",
	381	+ "spi_lr_overread",
	382	+ "mspi_done",
	383	+ "mspi_halted";
	384	+ status = "disabled";
	385	+ };
	386	+
	387	+ mspi: spi@408a00 {
	388	+ #address-cells = <1>;
	389	+ #size-cells = <0>;
	390	+ compatible = "brcm,spi-bcm-qspi",
	391	+ "brcm,spi-brcmstb-mspi";
	392	+ clocks = <&upg_clk>;
	393	+ reg = <0x408a00 0x180>;
	394	+ reg-names = "mspi";
	395	+ interrupts = <0x14>;
	396	+ interrupt-parent = <&upg_aon_irq0_intc>;
	397	+ interrupt-names = "mspi_done";
	398	+ status = "disabled";
	399	+ };
357	400	};
358	401	};

arch/mips/boot/dts/brcm/bcm7420.dtsi+46−3

@@ -92,15 +92,15 @@ · 91 unmodified lines
92	92	compatible = "brcm,bcm7120-l2-intc";
93	93	reg = <0x406780 0x8>;
94	94
95		− brcm,int-map-mask = <0x44>, <0x1f000000>;
	95	+ brcm,int-map-mask = <0x44>, <0x1f000000>, <0x100000>;
96	96	brcm,int-fwd-mask = <0x70000>;
97	97
98	98	interrupt-controller;
99	99	#interrupt-cells = <1>;
100	100
101	101	interrupt-parent = <&periph_intc>;
102		− interrupts = <18>, <19>;
103		− interrupt-names = "upg_main", "upg_bsc";
	102	+ interrupts = <18>, <19>, <20>;
	103	+ interrupt-names = "upg_main", "upg_bsc", "upg_spi";
104	104	};
105	105
106	106	sun_top_ctrl: syscon@404000 {
@@ -287,5 +287,48 @@ · 180 unmodified lines
287	287	interrupts = <62>;
288	288	status = "disabled";
289	289	};
	290	+
	291	+ spi_l2_intc: interrupt-controller@411d00 {
	292	+ compatible = "brcm,l2-intc";
	293	+ reg = <0x411d00 0x30>;
	294	+ interrupt-controller;
	295	+ #interrupt-cells = <1>;
	296	+ interrupt-parent = <&periph_intc>;
	297	+ interrupts = <78>;
	298	+ };
	299	+
	300	+ qspi: spi@443000 {
	301	+ #address-cells = <0x1>;
	302	+ #size-cells = <0x0>;
	303	+ compatible = "brcm,spi-bcm-qspi",
	304	+ "brcm,spi-brcmstb-qspi";
	305	+ clocks = <&upg_clk>;
	306	+ reg = <0x440920 0x4 0x443200 0x188 0x443000 0x50>;
	307	+ reg-names = "cs_reg", "hif_mspi", "bspi";
	308	+ interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
	309	+ interrupt-parent = <&spi_l2_intc>;
	310	+ interrupt-names = "spi_lr_fullness_reached",
	311	+ "spi_lr_session_aborted",
	312	+ "spi_lr_impatient",
	313	+ "spi_lr_session_done",
	314	+ "spi_lr_overread",
	315	+ "mspi_done",
	316	+ "mspi_halted";
	317	+ status = "disabled";
	318	+ };
	319	+
	320	+ mspi: spi@406400 {
	321	+ #address-cells = <1>;
	322	+ #size-cells = <0>;
	323	+ compatible = "brcm,spi-bcm-qspi",
	324	+ "brcm,spi-brcmstb-mspi";
	325	+ clocks = <&upg_clk>;
	326	+ reg = <0x406400 0x180>;
	327	+ reg-names = "mspi";
	328	+ interrupts = <0x14>;
	329	+ interrupt-parent = <&upg_irq0_intc>;
	330	+ interrupt-names = "mspi_done";
	331	+ status = "disabled";
	332	+ };
290	333	};
291	334	};

arch/mips/boot/dts/brcm/bcm7425.dtsi+43−0

@@ -450,5 +450,48 @@ · 449 unmodified lines
450	450	mmc-hs200-1_8v;
451	451	status = "disabled";
452	452	};
	453	+
	454	+ spi_l2_intc: interrupt-controller@41ad00 {
	455	+ compatible = "brcm,l2-intc";
	456	+ reg = <0x41ad00 0x30>;
	457	+ interrupt-controller;
	458	+ #interrupt-cells = <1>;
	459	+ interrupt-parent = <&periph_intc>;
	460	+ interrupts = <25>;
	461	+ };
	462	+
	463	+ qspi: spi@41c000 {
	464	+ #address-cells = <0x1>;
	465	+ #size-cells = <0x0>;
	466	+ compatible = "brcm,spi-bcm-qspi",
	467	+ "brcm,spi-brcmstb-qspi";
	468	+ clocks = <&upg_clk>;
	469	+ reg = <0x419920 0x4 0x41c200 0x188 0x41c000 0x50>;
	470	+ reg-names = "cs_reg", "hif_mspi", "bspi";
	471	+ interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
	472	+ interrupt-parent = <&spi_l2_intc>;
	473	+ interrupt-names = "spi_lr_fullness_reached",
	474	+ "spi_lr_session_aborted",
	475	+ "spi_lr_impatient",
	476	+ "spi_lr_session_done",
	477	+ "spi_lr_overread",
	478	+ "mspi_done",
	479	+ "mspi_halted";
	480	+ status = "disabled";
	481	+ };
	482	+
	483	+ mspi: spi@409200 {
	484	+ #address-cells = <1>;
	485	+ #size-cells = <0>;
	486	+ compatible = "brcm,spi-bcm-qspi",
	487	+ "brcm,spi-brcmstb-mspi";
	488	+ clocks = <&upg_clk>;
	489	+ reg = <0x409200 0x180>;
	490	+ reg-names = "mspi";
	491	+ interrupts = <0x14>;
	492	+ interrupt-parent = <&upg_aon_irq0_intc>;
	493	+ interrupt-names = "mspi_done";
	494	+ status = "disabled";
	495	+ };
453	496	};
454	497	};

arch/mips/boot/dts/brcm/bcm7435.dtsi+43−0

@@ -465,5 +465,48 @@ · 464 unmodified lines
465	465	mmc-hs200-1_8v;
466	466	status = "disabled";
467	467	};
	468	+
	469	+ spi_l2_intc: interrupt-controller@41bd00 {
	470	+ compatible = "brcm,l2-intc";
	471	+ reg = <0x41bd00 0x30>;
	472	+ interrupt-controller;
	473	+ #interrupt-cells = <1>;
	474	+ interrupt-parent = <&periph_intc>;
	475	+ interrupts = <25>;
	476	+ };
	477	+
	478	+ qspi: spi@41d200 {
	479	+ #address-cells = <0x1>;
	480	+ #size-cells = <0x0>;
	481	+ compatible = "brcm,spi-bcm-qspi",
	482	+ "brcm,spi-brcmstb-qspi";
	483	+ clocks = <&upg_clk>;
	484	+ reg = <0x41a920 0x4 0x41d400 0x188 0x41d200 0x50>;
	485	+ reg-names = "cs_reg", "hif_mspi", "bspi";
	486	+ interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
	487	+ interrupt-parent = <&spi_l2_intc>;
	488	+ interrupt-names = "spi_lr_fullness_reached",
	489	+ "spi_lr_session_aborted",
	490	+ "spi_lr_impatient",
	491	+ "spi_lr_session_done",
	492	+ "spi_lr_overread",
	493	+ "mspi_done",
	494	+ "mspi_halted";
	495	+ status = "disabled";
	496	+ };
	497	+
	498	+ mspi: spi@409200 {
	499	+ #address-cells = <1>;
	500	+ #size-cells = <0>;
	501	+ compatible = "brcm,spi-bcm-qspi",
	502	+ "brcm,spi-brcmstb-mspi";
	503	+ clocks = <&upg_clk>;
	504	+ reg = <0x409200 0x180>;
	505	+ reg-names = "mspi";
	506	+ interrupts = <0x14>;
	507	+ interrupt-parent = <&upg_aon_irq0_intc>;
	508	+ interrupt-names = "mspi_done";
	509	+ status = "disabled";
	510	+ };
468	511	};
469	512	};

arch/mips/boot/dts/brcm/bcm97125cbmb.dts+4−0

@@ -57,3 +57,7 @@ · 56 unmodified lines
57	57	&ohci0 {
58	58	status = "disabled";
59	59	};
	60	+
	61	+&mspi {
	62	+ status = "okay";
	63	+};

arch/mips/boot/dts/brcm/bcm97346dbsmb.dts+4−0

@@ -109,3 +109,7 @@ · 108 unmodified lines
109	109	&sdhci0 {
110	110	status = "okay";
111	111	};
	112	+
	113	+&mspi {
	114	+ status = "okay";
	115	+};

arch/mips/boot/dts/brcm/bcm97358svmb.dts+36−0

@@ -69,3 +69,39 @@ · 68 unmodified lines
69	69	&nand {
70	70	status = "okay";
71	71	};
	72	+
	73	+&qspi {
	74	+ status = "okay";
	75	+
	76	+ m25p80@0 {
	77	+ compatible = "m25p80";
	78	+ reg = <0>;
	79	+ spi-max-frequency = <40000000>;
	80	+ spi-cpol;
	81	+ spi-cpha;
	82	+ use-bspi;
	83	+ m25p,fast-read;
	84	+
	85	+ partitions {
	86	+ compatible = "fixed-partitions";
	87	+ #address-cells = <1>;
	88	+ #size-cells = <1>;
	89	+
	90	+ flash0.cfe@0 {
	91	+ reg = <0x0 0x200000>;
	92	+ };
	93	+
	94	+ flash0.mac@200000 {
	95	+ reg = <0x200000 0x40000>;
	96	+ };
	97	+
	98	+ flash0.nvram@240000 {
	99	+ reg = <0x240000 0x10000>;
	100	+ };
	101	+ };
	102	+ };
	103	+};
	104	+
	105	+&mspi {
	106	+ status = "okay";
	107	+};

arch/mips/boot/dts/brcm/bcm97360svmb.dts+36−0

@@ -72,3 +72,39 @@ · 71 unmodified lines
72	72	&sdhci0 {
73	73	status = "okay";
74	74	};
	75	+
	76	+&qspi {
	77	+ status = "okay";
	78	+
	79	+ m25p80@0 {
	80	+ compatible = "m25p80";
	81	+ reg = <0>;
	82	+ spi-max-frequency = <40000000>;
	83	+ spi-cpol;
	84	+ spi-cpha;
	85	+ use-bspi;
	86	+ m25p,fast-read;
	87	+
	88	+ partitions {
	89	+ compatible = "fixed-partitions";
	90	+ #address-cells = <1>;
	91	+ #size-cells = <1>;
	92	+
	93	+ flash0.cfe@0 {
	94	+ reg = <0x0 0x200000>;
	95	+ };
	96	+
	97	+ flash0.mac@200000 {
	98	+ reg = <0x200000 0x40000>;
	99	+ };
	100	+
	101	+ flash0.nvram@240000 {
	102	+ reg = <0x240000 0x10000>;
	103	+ };
	104	+ };
	105	+ };
	106	+};
	107	+
	108	+&mspi {
	109	+ status = "okay";
	110	+};

arch/mips/boot/dts/brcm/bcm97362svmb.dts+4−0

@@ -73,3 +73,7 @@ · 72 unmodified lines
73	73	&sdhci0 {
74	74	status = "okay";
75	75	};
	76	+
	77	+&mspi {
	78	+ status = "okay";
	79	+};

arch/mips/boot/dts/brcm/bcm97420c.dts+4−0

@@ -79,3 +79,7 @@ · 78 unmodified lines
79	79	&ohci1 {
80	80	status = "okay";
81	81	};
	82	+
	83	+&mspi {
	84	+ status = "okay";
	85	+};

arch/mips/boot/dts/brcm/bcm97425svmb.dts+36−0

@@ -107,3 +107,39 @@ · 106 unmodified lines
107	107	&sdhci1 {
108	108	status = "okay";
109	109	};
	110	+
	111	+&qspi {
	112	+ status = "okay";
	113	+
	114	+ m25p80@0 {
	115	+ compatible = "m25p80";
	116	+ reg = <0>;
	117	+ spi-max-frequency = <40000000>;
	118	+ spi-cpol;
	119	+ spi-cpha;
	120	+ use-bspi;
	121	+ m25p,fast-read;
	122	+
	123	+ partitions {
	124	+ compatible = "fixed-partitions";
	125	+ #address-cells = <1>;
	126	+ #size-cells = <1>;
	127	+
	128	+ flash0.cfe@0 {
	129	+ reg = <0x0 0x200000>;
	130	+ };
	131	+
	132	+ flash0.mac@200000 {
	133	+ reg = <0x200000 0x40000>;
	134	+ };
	135	+
	136	+ flash0.nvram@240000 {
	137	+ reg = <0x240000 0x10000>;
	138	+ };
	139	+ };
	140	+ };
	141	+};
	142	+
	143	+&mspi {
	144	+ status = "okay";
	145	+};

arch/mips/boot/dts/brcm/bcm97435svmb.dts+4−0

@@ -115,3 +115,7 @@ · 114 unmodified lines
115	115	&sdhci1 {
116	116	status = "okay";
117	117	};
	118	+
	119	+&mspi {
	120	+ status = "okay";
	121	+};

arch/mips/boot/dts/img/Makefile+9−0

@@ -0,0 +1,9 @@
	1	+dtb-$(CONFIG_MACH_PISTACHIO) += pistachio_marduk.dtb
	2	+
	3	+obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
	4	+
	5	+# Force kbuild to make empty built-in.o if necessary
	6	+obj- += dummy.o
	7	+
	8	+always := $(dtb-y)
	9	+clean-files := .dtb .dtb.S

arch/mips/boot/dts/img/pistachio.dtsi+924−0

@@ -0,0 +1,924 @@
	1	+/*
	2	+ * Copyright (C) 2015, 2016 Imagination Technologies Ltd.
	3	+ * Copyright (C) 2015 Google, Inc.
	4	+ *
	5	+ * This program is free software; you can redistribute it and/or modify
	6	+ * it under the terms of the GNU General Public License version 2 as
	7	+ * published by the Free Software Foundation.
	8	+ */
	9	+
	10	+#include <dt-bindings/clock/pistachio-clk.h>
	11	+#include <dt-bindings/gpio/gpio.h>
	12	+#include <dt-bindings/interrupt-controller/irq.h>
	13	+#include <dt-bindings/interrupt-controller/mips-gic.h>
	14	+#include <dt-bindings/reset/pistachio-resets.h>
	15	+
	16	+/ {
	17	+ compatible = "img,pistachio";
	18	+
	19	+ #address-cells = <1>;
	20	+ #size-cells = <1>;
	21	+
	22	+ interrupt-parent = <&gic>;
	23	+
	24	+ cpus {
	25	+ #address-cells = <1>;
	26	+ #size-cells = <0>;
	27	+
	28	+ cpu0: cpu@0 {
	29	+ device_type = "cpu";
	30	+ compatible = "mti,interaptiv";
	31	+ reg = <0>;
	32	+ clocks = <&clk_core CLK_MIPS_PLL>;
	33	+ clock-names = "cpu";
	34	+ clock-latency = <1000>;
	35	+ operating-points = <
	36	+ /* kHz uV(dummy) */
	37	+ 546000 1150000
	38	+ 520000 1100000
	39	+ 494000 1000000
	40	+ 468000 950000
	41	+ 442000 900000
	42	+ 416000 800000
	43	+ >;
	44	+ };
	45	+ };
	46	+
	47	+ i2c0: i2c@18100000 {
	48	+ compatible = "img,scb-i2c";
	49	+ reg = <0x18100000 0x200>;
	50	+ interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;
	51	+ clocks = <&clk_periph PERIPH_CLK_I2C0>,
	52	+ <&cr_periph SYS_CLK_I2C0>;
	53	+ clock-names = "scb", "sys";
	54	+ assigned-clocks = <&clk_periph PERIPH_CLK_I2C0_PRE_DIV>,
	55	+ <&clk_periph PERIPH_CLK_I2C0_DIV>;
	56	+ assigned-clock-rates = <100000000>, <33333334>;
	57	+ status = "disabled";
	58	+ pinctrl-names = "default";
	59	+ pinctrl-0 = <&i2c0_pins>;
	60	+
	61	+ #address-cells = <1>;
	62	+ #size-cells = <0>;
	63	+ };
	64	+
	65	+ i2c1: i2c@18100200 {
	66	+ compatible = "img,scb-i2c";
	67	+ reg = <0x18100200 0x200>;
	68	+ interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
	69	+ clocks = <&clk_periph PERIPH_CLK_I2C1>,
	70	+ <&cr_periph SYS_CLK_I2C1>;
	71	+ clock-names = "scb", "sys";
	72	+ assigned-clocks = <&clk_periph PERIPH_CLK_I2C1_PRE_DIV>,
	73	+ <&clk_periph PERIPH_CLK_I2C1_DIV>;
	74	+ assigned-clock-rates = <100000000>, <33333334>;
	75	+ status = "disabled";
	76	+ pinctrl-names = "default";
	77	+ pinctrl-0 = <&i2c1_pins>;
	78	+
	79	+ #address-cells = <1>;
	80	+ #size-cells = <0>;
	81	+ };
	82	+
	83	+ i2c2: i2c@18100400 {
	84	+ compatible = "img,scb-i2c";
	85	+ reg = <0x18100400 0x200>;
	86	+ interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
	87	+ clocks = <&clk_periph PERIPH_CLK_I2C2>,
	88	+ <&cr_periph SYS_CLK_I2C2>;
	89	+ clock-names = "scb", "sys";
	90	+ assigned-clocks = <&clk_periph PERIPH_CLK_I2C2_PRE_DIV>,
	91	+ <&clk_periph PERIPH_CLK_I2C2_DIV>;
	92	+ assigned-clock-rates = <100000000>, <33333334>;
	93	+ status = "disabled";
	94	+ pinctrl-names = "default";
	95	+ pinctrl-0 = <&i2c2_pins>;
	96	+
	97	+ #address-cells = <1>;
	98	+ #size-cells = <0>;
	99	+ };
	100	+
	101	+ i2c3: i2c@18100600 {
	102	+ compatible = "img,scb-i2c";
	103	+ reg = <0x18100600 0x200>;
	104	+ interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
	105	+ clocks = <&clk_periph PERIPH_CLK_I2C3>,
	106	+ <&cr_periph SYS_CLK_I2C3>;
	107	+ clock-names = "scb", "sys";
	108	+ assigned-clocks = <&clk_periph PERIPH_CLK_I2C3_PRE_DIV>,
	109	+ <&clk_periph PERIPH_CLK_I2C3_DIV>;
	110	+ assigned-clock-rates = <100000000>, <33333334>;
	111	+ status = "disabled";
	112	+ pinctrl-names = "default";
	113	+ pinctrl-0 = <&i2c3_pins>;
	114	+
	115	+ #address-cells = <1>;
	116	+ #size-cells = <0>;
	117	+ };
	118	+
	119	+ i2s_in: i2s-in@18100800 {
	120	+ compatible = "img,i2s-in";
	121	+ reg = <0x18100800 0x200>;
	122	+ interrupts = <GIC_SHARED 7 IRQ_TYPE_LEVEL_HIGH>;
	123	+ dmas = <&mdc 30 0xffffffff 0>;
	124	+ dma-names = "rx";
	125	+ clocks = <&cr_periph SYS_CLK_I2S_IN>;
	126	+ clock-names = "sys";
	127	+ img,i2s-channels = <6>;
	128	+ pinctrl-names = "default";
	129	+ pinctrl-0 = <&i2s_in_pins>;
	130	+ status = "disabled";
	131	+
	132	+ #sound-dai-cells = <0>;
	133	+ };
	134	+
	135	+ i2s_out: i2s-out@18100a00 {
	136	+ compatible = "img,i2s-out";
	137	+ reg = <0x18100a00 0x200>;
	138	+ interrupts = <GIC_SHARED 13 IRQ_TYPE_LEVEL_HIGH>;
	139	+ dmas = <&mdc 23 0xffffffff 0>;
	140	+ dma-names = "tx";
	141	+ clocks = <&cr_periph SYS_CLK_I2S_OUT>,
	142	+ <&clk_core CLK_I2S>;
	143	+ clock-names = "sys", "ref";
	144	+ assigned-clocks = <&clk_core CLK_I2S_DIV>;
	145	+ assigned-clock-rates = <12288000>;
	146	+ img,i2s-channels = <6>;
	147	+ pinctrl-names = "default";
	148	+ pinctrl-0 = <&i2s_out_pins>;
	149	+ status = "disabled";
	150	+ resets = <&pistachio_reset PISTACHIO_RESET_I2S_OUT>;
	151	+ reset-names = "rst";
	152	+ #sound-dai-cells = <0>;
	153	+ };
	154	+
	155	+ parallel_out: parallel-audio-out@18100c00 {
	156	+ compatible = "img,parallel-out";
	157	+ reg = <0x18100c00 0x100>;
	158	+ interrupts = <GIC_SHARED 19 IRQ_TYPE_LEVEL_HIGH>;
	159	+ dmas = <&mdc 16 0xffffffff 0>;
	160	+ dma-names = "tx";
	161	+ clocks = <&cr_periph SYS_CLK_PAUD_OUT>,
	162	+ <&clk_core CLK_AUDIO_DAC>;
	163	+ clock-names = "sys", "ref";
	164	+ assigned-clocks = <&clk_core CLK_AUDIO_DAC_DIV>;
	165	+ assigned-clock-rates = <12288000>;
	166	+ status = "disabled";
	167	+ resets = <&pistachio_reset PISTACHIO_RESET_PRL_OUT>;
	168	+ reset-names = "rst";
	169	+ #sound-dai-cells = <0>;
	170	+ };
	171	+
	172	+ spdif_out: spdif-out@18100d00 {
	173	+ compatible = "img,spdif-out";
	174	+ reg = <0x18100d00 0x100>;
	175	+ interrupts = <GIC_SHARED 21 IRQ_TYPE_LEVEL_HIGH>;
	176	+ dmas = <&mdc 14 0xffffffff 0>;
	177	+ dma-names = "tx";
	178	+ clocks = <&cr_periph SYS_CLK_SPDIF_OUT>,
	179	+ <&clk_core CLK_SPDIF>;
	180	+ clock-names = "sys", "ref";
	181	+ assigned-clocks = <&clk_core CLK_SPDIF_DIV>;
	182	+ assigned-clock-rates = <12288000>;
	183	+ pinctrl-names = "default";
	184	+ pinctrl-0 = <&spdif_out_pin>;
	185	+ status = "disabled";
	186	+ resets = <&pistachio_reset PISTACHIO_RESET_SPDIF_OUT>;
	187	+ reset-names = "rst";
	188	+ #sound-dai-cells = <0>;
	189	+ };
	190	+
	191	+ spdif_in: spdif-in@18100e00 {
	192	+ compatible = "img,spdif-in";
	193	+ reg = <0x18100e00 0x100>;
	194	+ interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
	195	+ dmas = <&mdc 15 0xffffffff 0>;
	196	+ dma-names = "rx";
	197	+ clocks = <&cr_periph SYS_CLK_SPDIF_IN>;
	198	+ clock-names = "sys";
	199	+ pinctrl-names = "default";
	200	+ pinctrl-0 = <&spdif_in_pin>;
	201	+ status = "disabled";
	202	+
	203	+ #sound-dai-cells = <0>;
	204	+ };
	205	+
	206	+ internal_dac: internal-dac {
	207	+ compatible = "img,pistachio-internal-dac";
	208	+ img,cr-top = <&cr_top>;
	209	+ img,voltage-select = <1>;
	210	+
	211	+ #sound-dai-cells = <0>;
	212	+ };
	213	+
	214	+ spfi0: spi@18100f00 {
	215	+ compatible = "img,spfi";
	216	+ reg = <0x18100f00 0x100>;
	217	+ interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
	218	+ clocks = <&clk_core CLK_SPI0>, <&cr_periph SYS_CLK_SPI0_MASTER>;
	219	+ clock-names = "sys", "spfi";
	220	+ dmas = <&mdc 9 0xffffffff 0>, <&mdc 10 0xffffffff 0>;
	221	+ dma-names = "rx", "tx";
	222	+ spfi-max-frequency = <50000000>;
	223	+ status = "disabled";
	224	+
	225	+ #address-cells = <1>;
	226	+ #size-cells = <0>;
	227	+ };
	228	+
	229	+ spfi1: spi@18101000 {
	230	+ compatible = "img,spfi";
	231	+ reg = <0x18101000 0x100>;
	232	+ interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
	233	+ clocks = <&clk_core CLK_SPI1>, <&cr_periph SYS_CLK_SPI1>;
	234	+ clock-names = "sys", "spfi";
	235	+ dmas = <&mdc 1 0xffffffff 0>, <&mdc 2 0xffffffff 0>;
	236	+ dma-names = "rx", "tx";
	237	+ img,supports-quad-mode;
	238	+ spfi-max-frequency = <50000000>;
	239	+ status = "disabled";
	240	+
	241	+ #address-cells = <1>;
	242	+ #size-cells = <0>;
	243	+ };
	244	+
	245	+ pwm: pwm@18101300 {
	246	+ compatible = "img,pistachio-pwm";
	247	+ reg = <0x18101300 0x100>;
	248	+ clocks = <&clk_periph PERIPH_CLK_PWM>,
	249	+ <&cr_periph SYS_CLK_PWM>;
	250	+ clock-names = "pwm", "sys";
	251	+ img,cr-periph = <&cr_periph>;
	252	+ #pwm-cells = <2>;
	253	+ status = "disabled";
	254	+ };
	255	+
	256	+ uart0: uart@18101400 {
	257	+ compatible = "snps,dw-apb-uart";
	258	+ reg = <0x18101400 0x100>;
	259	+ interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
	260	+ clocks = <&clk_core CLK_UART0>, <&cr_periph SYS_CLK_UART0>;
	261	+ clock-names = "baudclk", "apb_pclk";
	262	+ assigned-clocks = <&clk_core CLK_UART0_INTERNAL_DIV>,
	263	+ <&clk_core CLK_UART0_DIV>;
	264	+ reg-shift = <2>;
	265	+ reg-io-width = <4>;
	266	+ pinctrl-0 = <&uart0_pins>, <&uart0_rts_cts_pins>;
	267	+ pinctrl-names = "default";
	268	+ status = "disabled";
	269	+ };
	270	+
	271	+ uart1: uart@18101500 {
	272	+ compatible = "snps,dw-apb-uart";
	273	+ reg = <0x18101500 0x100>;
	274	+ interrupts = <GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
	275	+ clocks = <&clk_core CLK_UART1>, <&cr_periph SYS_CLK_UART1>;
	276	+ clock-names = "baudclk", "apb_pclk";
	277	+ assigned-clocks = <&clk_core CLK_UART1_INTERNAL_DIV>,
	278	+ <&clk_core CLK_UART1_DIV>;
	279	+ assigned-clock-rates = <114278400>, <1843200>;
	280	+ reg-shift = <2>;
	281	+ reg-io-width = <4>;
	282	+ pinctrl-0 = <&uart1_pins>;
	283	+ pinctrl-names = "default";
	284	+ status = "disabled";
	285	+ };
	286	+
	287	+ adc: adc@18101600 {
	288	+ compatible = "cosmic,10001-adc";
	289	+ reg = <0x18101600 0x24>;
	290	+ adc-reserved-channels = <0x30>;
	291	+ clocks = <&clk_core CLK_AUX_ADC>;
	292	+ clock-names = "adc";
	293	+ assigned-clocks = <&clk_core CLK_AUX_ADC_INTERNAL_DIV>,
	294	+ <&clk_core CLK_AUX_ADC_DIV>;
	295	+ assigned-clock-rates = <100000000>, <1000000>;
	296	+ status = "disabled";
	297	+
	298	+ #io-channel-cells = <1>;
	299	+ };
	300	+
	301	+ pinctrl: pinctrl@18101c00 {
	302	+ compatible = "img,pistachio-system-pinctrl";
	303	+ reg = <0x18101c00 0x400>;
	304	+
	305	+ gpio0: gpio0 {
	306	+ interrupts = <GIC_SHARED 71 IRQ_TYPE_LEVEL_HIGH>;
	307	+
	308	+ gpio-controller;
	309	+ #gpio-cells = <2>;
	310	+ gpio-ranges = <&pinctrl 0 0 16>;
	311	+
	312	+ interrupt-controller;
	313	+ #interrupt-cells = <2>;
	314	+ };
	315	+
	316	+ gpio1: gpio1 {
	317	+ interrupts = <GIC_SHARED 72 IRQ_TYPE_LEVEL_HIGH>;
	318	+
	319	+ gpio-controller;
	320	+ #gpio-cells = <2>;
	321	+ gpio-ranges = <&pinctrl 0 16 16>;
	322	+
	323	+ interrupt-controller;
	324	+ #interrupt-cells = <2>;
	325	+ };
	326	+
	327	+ gpio2: gpio2 {
	328	+ interrupts = <GIC_SHARED 73 IRQ_TYPE_LEVEL_HIGH>;
	329	+
	330	+ gpio-controller;
	331	+ #gpio-cells = <2>;
	332	+ gpio-ranges = <&pinctrl 0 32 16>;
	333	+
	334	+ interrupt-controller;
	335	+ #interrupt-cells = <2>;
	336	+ };
	337	+
	338	+ gpio3: gpio3 {
	339	+ interrupts = <GIC_SHARED 74 IRQ_TYPE_LEVEL_HIGH>;
	340	+
	341	+ gpio-controller;
	342	+ #gpio-cells = <2>;
	343	+ gpio-ranges = <&pinctrl 0 48 16>;
	344	+
	345	+ interrupt-controller;
	346	+ #interrupt-cells = <2>;
	347	+ };
	348	+
	349	+ gpio4: gpio4 {
	350	+ interrupts = <GIC_SHARED 75 IRQ_TYPE_LEVEL_HIGH>;
	351	+
	352	+ gpio-controller;
	353	+ #gpio-cells = <2>;
	354	+ gpio-ranges = <&pinctrl 0 64 16>;
	355	+
	356	+ interrupt-controller;
	357	+ #interrupt-cells = <2>;
	358	+ };
	359	+
	360	+ gpio5: gpio5 {
	361	+ interrupts = <GIC_SHARED 76 IRQ_TYPE_LEVEL_HIGH>;
	362	+
	363	+ gpio-controller;
	364	+ #gpio-cells = <2>;
	365	+ gpio-ranges = <&pinctrl 0 80 10>;
	366	+
	367	+ interrupt-controller;
	368	+ #interrupt-cells = <2>;
	369	+ };
	370	+
	371	+ i2c0_pins: i2c0-pins {
	372	+ pin_i2c0: i2c0 {
	373	+ pins = "mfio28", "mfio29";
	374	+ function = "i2c0";
	375	+ drive-strength = <4>;
	376	+ };
	377	+ };
	378	+
	379	+ i2c1_pins: i2c1-pins {
	380	+ pin_i2c1: i2c1 {
	381	+ pins = "mfio30", "mfio31";
	382	+ function = "i2c1";
	383	+ drive-strength = <4>;
	384	+ };
	385	+ };
	386	+
	387	+ i2c2_pins: i2c2-pins {
	388	+ pin_i2c2: i2c2 {
	389	+ pins = "mfio32", "mfio33";
	390	+ function = "i2c2";
	391	+ drive-strength = <4>;
	392	+ };
	393	+ };
	394	+
	395	+ i2c3_pins: i2c3-pins {
	396	+ pin_i2c3: i2c3 {
	397	+ pins = "mfio34", "mfio35";
	398	+ function = "i2c3";
	399	+ drive-strength = <4>;
	400	+ };
	401	+ };
	402	+
	403	+ spim0_pins: spim0-pins {
	404	+ pin_spim0: spim0 {
	405	+ pins = "mfio9", "mfio10";
	406	+ function = "spim0";
	407	+ drive-strength = <4>;
	408	+ };
	409	+ spim0_clk: spim0-clk {
	410	+ pins = "mfio8";
	411	+ function = "spim0";
	412	+ drive-strength = <4>;
	413	+ };
	414	+ };
	415	+
	416	+ spim0_cs0_alt_pin: spim0-cs0-alt-pin {
	417	+ spim0-cs0 {
	418	+ pins = "mfio2";
	419	+ drive-strength = <2>;
	420	+ };
	421	+ };
	422	+
	423	+ spim0_cs1_pin: spim0-cs1-pin {
	424	+ spim0-cs1 {
	425	+ pins = "mfio1";
	426	+ drive-strength = <2>;
	427	+ };
	428	+ };
	429	+
	430	+ spim0_cs2_pin: spim0-cs2-pin {
	431	+ spim0-cs2 {
	432	+ pins = "mfio55";
	433	+ drive-strength = <2>;
	434	+ };
	435	+ };
	436	+
	437	+ spim0_cs2_alt_pin: spim0-cs2-alt-pin {
	438	+ spim0-cs2 {
	439	+ pins = "mfio28";
	440	+ drive-strength = <2>;
	441	+ };
	442	+ };
	443	+
	444	+ spim0_cs3_pin: spim0-cs3-pin {
	445	+ spim0-cs3 {
	446	+ pins = "mfio56";
	447	+ drive-strength = <2>;
	448	+ };
	449	+ };
	450	+
	451	+ spim0_cs3_alt_pin: spim0-cs3-alt-pin {
	452	+ spim0-cs3 {
	453	+ pins = "mfio29";
	454	+ drive-strength = <2>;
	455	+ };
	456	+ };
	457	+
	458	+ spim0_cs4_pin: spim0-cs4-pin {
	459	+ spim0-cs4 {
	460	+ pins = "mfio57";
	461	+ drive-strength = <2>;
	462	+ };
	463	+ };
	464	+
	465	+ spim0_cs4_alt_pin: spim0-cs4-alt-pin {
	466	+ spim0-cs4 {
	467	+ pins = "mfio30";
	468	+ drive-strength = <2>;
	469	+ };
	470	+ };
	471	+
	472	+ spim1_pins: spim1-pins {
	473	+ spim1 {
	474	+ pins = "mfio3", "mfio4", "mfio5";
	475	+ function = "spim1";
	476	+ drive-strength = <2>;
	477	+ };
	478	+ };
	479	+
	480	+ spim1_quad_pins: spim1-quad-pins {
	481	+ spim1-quad {
	482	+ pins = "mfio6", "mfio7";
	483	+ function = "spim1";
	484	+ drive-strength = <2>;
	485	+ };
	486	+ };
	487	+
	488	+ spim1_cs0_pin: spim1-cs0-pins {
	489	+ spim1-cs0 {
	490	+ pins = "mfio0";
	491	+ function = "spim1";
	492	+ drive-strength = <2>;
	493	+ };
	494	+ };
	495	+
	496	+ spim1_cs1_pin: spim1-cs1-pin {
	497	+ spim1-cs1 {
	498	+ pins = "mfio1";
	499	+ function = "spim1";
	500	+ drive-strength = <2>;
	501	+ };
	502	+ };
	503	+
	504	+ spim1_cs1_alt_pin: spim1-cs1-alt-pin {
	505	+ spim1-cs1 {
	506	+ pins = "mfio58";
	507	+ function = "spim1";
	508	+ drive-strength = <2>;
	509	+ };
	510	+ };
	511	+
	512	+ spim1_cs2_pin: spim1-cs2-pin {
	513	+ spim1-cs2 {
	514	+ pins = "mfio2";
	515	+ function = "spim1";
	516	+ drive-strength = <2>;
	517	+ };
	518	+ };
	519	+
	520	+ spim1_cs2_alt0_pin: spim1-cs2-alt0-pin {
	521	+ spim1-cs2 {
	522	+ pins = "mfio31";
	523	+ function = "spim1";
	524	+ drive-strength = <2>;
	525	+ };
	526	+ };
	527	+
	528	+ spim1_cs2_alt1_pin: spim1-cs2-alt1-pin {
	529	+ spim1-cs2 {
	530	+ pins = "mfio55";
	531	+ function = "spim1";
	532	+ drive-strength = <2>;
	533	+ };
	534	+ };
	535	+
	536	+ spim1_cs3_pin: spim1-cs3-pin {
	537	+ spim1-cs3 {
	538	+ pins = "mfio56";
	539	+ function = "spim1";
	540	+ drive-strength = <2>;
	541	+ };
	542	+ };
	543	+
	544	+ spim1_cs4_pin: spim1-cs4-pin {
	545	+ spim1-cs4 {
	546	+ pins = "mfio57";
	547	+ function = "spim1";
	548	+ drive-strength = <2>;
	549	+ };
	550	+ };
	551	+
	552	+ uart0_pins: uart0-pins {
	553	+ uart0 {
	554	+ pins = "mfio55", "mfio56";
	555	+ function = "uart0";
	556	+ drive-strength = <2>;
	557	+ };
	558	+ };
	559	+
	560	+ uart0_rts_cts_pins: uart0-rts-cts-pins {
	561	+ uart0-rts-cts {
	562	+ pins = "mfio57", "mfio58";
	563	+ function = "uart0";
	564	+ drive-strength = <2>;
	565	+ };
	566	+ };
	567	+
	568	+ uart1_pins: uart1-pins {
	569	+ uart1 {
	570	+ pins = "mfio59", "mfio60";
	571	+ function = "uart1";
	572	+ drive-strength = <2>;
	573	+ };
	574	+ };
	575	+
	576	+ uart1_rts_cts_pins: uart1-rts-cts-pins {
	577	+ uart1-rts-cts {
	578	+ pins = "mfio1", "mfio2";
	579	+ function = "uart1";
	580	+ drive-strength = <2>;
	581	+ };
	582	+ };
	583	+
	584	+ enet_pins: enet-pins {
	585	+ pin_enet: enet {
	586	+ pins = "mfio63", "mfio64", "mfio65", "mfio66",
	587	+ "mfio67", "mfio68", "mfio69", "mfio70";
	588	+ function = "eth";
	589	+ slew-rate = <1>;
	590	+ drive-strength = <4>;
	591	+ };
	592	+ pin_enet_phy_clk: enet-phy-clk {
	593	+ pins = "mfio71";
	594	+ function = "eth";
	595	+ slew-rate = <1>;
	596	+ drive-strength = <8>;
	597	+ };
	598	+ };
	599	+
	600	+ sdhost_pins: sdhost-pins {
	601	+ pin_sdhost_clk: sdhost-clk {
	602	+ pins = "mfio15";
	603	+ function = "sdhost";
	604	+ slew-rate = <1>;
	605	+ drive-strength = <4>;
	606	+ };
	607	+ pin_sdhost_cmd: sdhost-cmd {
	608	+ pins = "mfio16";
	609	+ function = "sdhost";
	610	+ slew-rate = <1>;
	611	+ drive-strength = <4>;
	612	+ };
	613	+ pin_sdhost_data: sdhost-data {
	614	+ pins = "mfio17", "mfio18", "mfio19", "mfio20",
	615	+ "mfio21", "mfio22", "mfio23", "mfio24";
	616	+ function = "sdhost";
	617	+ slew-rate = <1>;
	618	+ drive-strength = <4>;
	619	+ };
	620	+ pin_sdhost_power_select: sdhost-power-select {
	621	+ pins = "mfio25";
	622	+ function = "sdhost";
	623	+ slew-rate = <1>;
	624	+ drive-strength = <2>;
	625	+ };
	626	+ pin_sdhost_card_detect: sdhost-card-detect {
	627	+ pins = "mfio26";
	628	+ function = "sdhost";
	629	+ drive-strength = <2>;
	630	+ };
	631	+ pin_sdhost_write_protect: sdhost-write-protect {
	632	+ pins = "mfio27";
	633	+ function = "sdhost";
	634	+ drive-strength = <2>;
	635	+ };
	636	+ };
	637	+
	638	+ ir_pin: ir-pin {
	639	+ ir-data {
	640	+ pins = "mfio72";
	641	+ function = "ir";
	642	+ drive-strength = <2>;
	643	+ };
	644	+ };
	645	+
	646	+ pwmpdm0_pin: pwmpdm0-pin {
	647	+ pwmpdm0 {
	648	+ pins = "mfio73";
	649	+ function = "pwmpdm";
	650	+ drive-strength = <2>;
	651	+ };
	652	+ };
	653	+
	654	+ pwmpdm1_pin: pwmpdm1-pin {
	655	+ pwmpdm1 {
	656	+ pins = "mfio74";
	657	+ function = "pwmpdm";
	658	+ drive-strength = <2>;
	659	+ };
	660	+ };
	661	+
	662	+ pwmpdm2_pin: pwmpdm2-pin {
	663	+ pwmpdm2 {
	664	+ pins = "mfio75";
	665	+ function = "pwmpdm";
	666	+ drive-strength = <2>;
	667	+ };
	668	+ };
	669	+
	670	+ pwmpdm3_pin: pwmpdm3-pin {
	671	+ pwmpdm3 {
	672	+ pins = "mfio76";
	673	+ function = "pwmpdm";
	674	+ drive-strength = <2>;
	675	+ };
	676	+ };
	677	+
	678	+ dac_clk_pin: dac-clk-pin {
	679	+ pin_dac_clk: dac-clk {
	680	+ pins = "mfio45";
	681	+ function = "i2s_dac_clk";
	682	+ drive-strength = <4>;
	683	+ };
	684	+ };
	685	+
	686	+ i2s_mclk_pin: i2s-mclk-pin {
	687	+ pin_i2s_mclk: i2s-mclk {
	688	+ pins = "mfio36";
	689	+ function = "i2s_out";
	690	+ drive-strength = <4>;
	691	+ };
	692	+ };
	693	+
	694	+ spdif_out_pin: spdif-out-pin {
	695	+ spdif-out {
	696	+ pins = "mfio61";
	697	+ function = "spdif_out";
	698	+ slew-rate = <1>;
	699	+ drive-strength = <2>;
	700	+ };
	701	+ };
	702	+
	703	+ spdif_in_pin: spdif-in-pin {
	704	+ spdif-in {
	705	+ pins = "mfio62";
	706	+ function = "spdif_in";
	707	+ drive-strength = <2>;
	708	+ };
	709	+ };
	710	+
	711	+ i2s_out_pins: i2s-out-pins {
	712	+ pins_i2s_out_clk: i2s-out-clk {
	713	+ pins = "mfio37", "mfio38";
	714	+ function = "i2s_out";
	715	+ drive-strength = <4>;
	716	+ };
	717	+ pins_i2s_out: i2s-out {
	718	+ pins = "mfio39", "mfio40",
	719	+ "mfio41", "mfio42",
	720	+ "mfio43", "mfio44";
	721	+ function = "i2s_out";
	722	+ drive-strength = <2>;
	723	+ };
	724	+ };
	725	+
	726	+ i2s_in_pins: i2s-in-pins {
	727	+ i2s-in {
	728	+ pins = "mfio47", "mfio48", "mfio49",
	729	+ "mfio50", "mfio51", "mfio52",
	730	+ "mfio53", "mfio54";
	731	+ function = "i2s_in";
	732	+ drive-strength = <2>;
	733	+ };
	734	+ };
	735	+ };
	736	+
	737	+ timer: timer@18102000 {
	738	+ compatible = "img,pistachio-gptimer";
	739	+ reg = <0x18102000 0x100>;
	740	+ interrupts = <GIC_SHARED 60 IRQ_TYPE_LEVEL_HIGH>;
	741	+ clocks = <&clk_periph PERIPH_CLK_COUNTER_FAST>,
	742	+ <&cr_periph SYS_CLK_TIMER>;
	743	+ clock-names = "fast", "sys";
	744	+ img,cr-periph = <&cr_periph>;
	745	+ };
	746	+
	747	+ wdt: watchdog@18102100 {
	748	+ compatible = "img,pdc-wdt";
	749	+ reg = <0x18102100 0x100>;
	750	+ interrupts = <GIC_SHARED 52 IRQ_TYPE_LEVEL_HIGH>;
	751	+ clocks = <&clk_periph PERIPH_CLK_WD>, <&cr_periph SYS_CLK_WD>;
	752	+ clock-names = "wdt", "sys";
	753	+ assigned-clocks = <&clk_periph PERIPH_CLK_WD_PRE_DIV>,
	754	+ <&clk_periph PERIPH_CLK_WD_DIV>;
	755	+ assigned-clock-rates = <4000000>, <32768>;
	756	+ };
	757	+
	758	+ ir: ir@18102200 {
	759	+ compatible = "img,ir-rev1";
	760	+ reg = <0x18102200 0x100>;
	761	+ interrupts = <GIC_SHARED 51 IRQ_TYPE_LEVEL_HIGH>;
	762	+ clocks = <&clk_periph PERIPH_CLK_IR>, <&cr_periph SYS_CLK_IR>;
	763	+ clock-names = "core", "sys";
	764	+ assigned-clocks = <&clk_periph PERIPH_CLK_IR_PRE_DIV>,
	765	+ <&clk_periph PERIPH_CLK_IR_DIV>;
	766	+ assigned-clock-rates = <4000000>, <32768>;
	767	+ pinctrl-0 = <&ir_pin>;
	768	+ pinctrl-names = "default";
	769	+ status = "disabled";
	770	+ };
	771	+
	772	+ usb: usb@18120000 {
	773	+ compatible = "snps,dwc2";
	774	+ reg = <0x18120000 0x1c000>;
	775	+ interrupts = <GIC_SHARED 49 IRQ_TYPE_LEVEL_HIGH>;
	776	+ phys = <&usb_phy>;
	777	+ phy-names = "usb2-phy";
	778	+ g-tx-fifo-size = <256 256 256 256>;
	779	+ status = "disabled";
	780	+ };
	781	+
	782	+ enet: ethernet@18140000 {
	783	+ compatible = "snps,dwmac";
	784	+ reg = <0x18140000 0x2000>;
	785	+ interrupts = <GIC_SHARED 50 IRQ_TYPE_LEVEL_HIGH>;
	786	+ interrupt-names = "macirq";
	787	+ clocks = <&clk_core CLK_ENET>, <&cr_periph SYS_CLK_ENET>;
	788	+ clock-names = "stmmaceth", "pclk";
	789	+ assigned-clocks = <&clk_core CLK_ENET_MUX>,
	790	+ <&clk_core CLK_ENET_DIV>;
	791	+ assigned-clock-parents = <&clk_core CLK_SYS_INTERNAL_DIV>;
	792	+ assigned-clock-rates = <0>, <50000000>;
	793	+ pinctrl-0 = <&enet_pins>;
	794	+ pinctrl-names = "default";
	795	+ phy-mode = "rmii";
	796	+ status = "disabled";
	797	+ };
	798	+
	799	+ sdhost: mmc@18142000 {
	800	+ compatible = "img,pistachio-dw-mshc";
	801	+ reg = <0x18142000 0x400>;
	802	+ interrupts = <GIC_SHARED 39 IRQ_TYPE_LEVEL_HIGH>;
	803	+ clocks = <&clk_core CLK_SD_HOST>, <&cr_periph SYS_CLK_SD_HOST>;
	804	+ clock-names = "ciu", "biu";
	805	+ pinctrl-0 = <&sdhost_pins>;
	806	+ pinctrl-names = "default";
	807	+ fifo-depth = <0x20>;
	808	+ num-slots = <1>;
	809	+ clock-frequency = <50000000>;
	810	+ bus-width = <8>;
	811	+ cap-mmc-highspeed;
	812	+ cap-sd-highspeed;
	813	+ status = "disabled";
	814	+ };
	815	+
	816	+ sram: sram@1b000000 {
	817	+ compatible = "mmio-sram";
	818	+ reg = <0x1b000000 0x10000>;
	819	+ };
	820	+
	821	+ mdc: dma-controller@18143000 {
	822	+ compatible = "img,pistachio-mdc-dma";
	823	+ reg = <0x18143000 0x1000>;
	824	+ interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>,
	825	+ <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>,
	826	+ <GIC_SHARED 29 IRQ_TYPE_LEVEL_HIGH>,
	827	+ <GIC_SHARED 30 IRQ_TYPE_LEVEL_HIGH>,
	828	+ <GIC_SHARED 31 IRQ_TYPE_LEVEL_HIGH>,
	829	+ <GIC_SHARED 32 IRQ_TYPE_LEVEL_HIGH>,
	830	+ <GIC_SHARED 33 IRQ_TYPE_LEVEL_HIGH>,
	831	+ <GIC_SHARED 34 IRQ_TYPE_LEVEL_HIGH>,
	832	+ <GIC_SHARED 35 IRQ_TYPE_LEVEL_HIGH>,
	833	+ <GIC_SHARED 36 IRQ_TYPE_LEVEL_HIGH>,
	834	+ <GIC_SHARED 37 IRQ_TYPE_LEVEL_HIGH>,
	835	+ <GIC_SHARED 38 IRQ_TYPE_LEVEL_HIGH>;
	836	+ clocks = <&cr_periph SYS_CLK_MDC>;
	837	+ clock-names = "sys";
	838	+
	839	+ img,max-burst-multiplier = <16>;
	840	+ img,cr-periph = <&cr_periph>;
	841	+
	842	+ #dma-cells = <3>;
	843	+ };
	844	+
	845	+ clk_core: clk@18144000 {
	846	+ compatible = "img,pistachio-clk", "syscon";
	847	+ clocks = <&xtal>, <&cr_top EXT_CLK_AUDIO_IN>,
	848	+ <&cr_top EXT_CLK_ENET_IN>;
	849	+ clock-names = "xtal", "audio_refclk_ext_gate",
	850	+ "ext_enet_in_gate";
	851	+ reg = <0x18144000 0x800>;
	852	+ #clock-cells = <1>;
	853	+ };
	854	+
	855	+ clk_periph: clk@18144800 {
	856	+ compatible = "img,pistachio-clk-periph";
	857	+ reg = <0x18144800 0x1000>;
	858	+ clocks = <&clk_core CLK_PERIPH_SYS>;
	859	+ clock-names = "periph_sys_core";
	860	+ #clock-cells = <1>;
	861	+ };
	862	+
	863	+ cr_periph: clk@18148000 {
	864	+ compatible = "img,pistachio-cr-periph", "syscon", "simple-bus";
	865	+ reg = <0x18148000 0x1000>;
	866	+ clocks = <&clk_periph PERIPH_CLK_SYS>;
	867	+ clock-names = "sys";
	868	+ #clock-cells = <1>;
	869	+
	870	+ pistachio_reset: reset-controller {
	871	+ compatible = "img,pistachio-reset";
	872	+ #reset-cells = <1>;
	873	+ };
	874	+ };
	875	+
	876	+ cr_top: clk@18149000 {
	877	+ compatible = "img,pistachio-cr-top", "syscon";
	878	+ reg = <0x18149000 0x200>;
	879	+ #clock-cells = <1>;
	880	+ };
	881	+
	882	+ hash: hash@18149600 {
	883	+ compatible = "img,hash-accelerator";
	884	+ reg = <0x18149600 0x100>, <0x18101100 0x4>;
	885	+ interrupts = <GIC_SHARED 59 IRQ_TYPE_LEVEL_HIGH>;
	886	+ dmas = <&mdc 8 0xffffffff 0>;
	887	+ dma-names = "tx";
	888	+ clocks = <&cr_periph SYS_CLK_HASH>,
	889	+ <&clk_periph PERIPH_CLK_ROM>;
	890	+ clock-names = "sys", "hash";
	891	+ };
	892	+
	893	+ gic: interrupt-controller@1bdc0000 {
	894	+ compatible = "mti,gic";
	895	+ reg = <0x1bdc0000 0x20000>;
	896	+
	897	+ interrupt-controller;
	898	+ #interrupt-cells = <3>;
	899	+
	900	+ timer {
	901	+ compatible = "mti,gic-timer";
	902	+ interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
	903	+ clocks = <&clk_core CLK_MIPS>;
	904	+ };
	905	+ };
	906	+
	907	+ usb_phy: usb-phy {
	908	+ compatible = "img,pistachio-usb-phy";
	909	+ clocks = <&clk_core CLK_USB_PHY>;
	910	+ clock-names = "usb_phy";
	911	+ assigned-clocks = <&clk_core CLK_USB_PHY_DIV>;
	912	+ assigned-clock-rates = <50000000>;
	913	+ img,refclk = <0x2>;
	914	+ img,cr-top = <&cr_top>;
	915	+ #phy-cells = <0>;
	916	+ };
	917	+
	918	+ xtal: xtal {
	919	+ compatible = "fixed-clock";
	920	+ #clock-cells = <0>;
	921	+ clock-frequency = <52000000>;
	922	+ clock-output-names = "xtal";
	923	+ };
	924	+};

arch/mips/boot/dts/img/pistachio_marduk.dts+163−0

@@ -0,0 +1,163 @@
	1	+/*
	2	+ * Copyright (C) 2015, 2016 Imagination Technologies Ltd.
	3	+ *
	4	+ * This program is free software; you can redistribute it and/or modify
	5	+ * it under the terms of the GNU General Public License version 2 as
	6	+ * published by the Free Software Foundation.
	7	+ *
	8	+ * IMG Marduk board is also known as Creator Ci40.
	9	+ */
	10	+
	11	+/dts-v1/;
	12	+
	13	+#include "pistachio.dtsi"
	14	+
	15	+/ {
	16	+ model = "IMG Marduk (Creator Ci40)";
	17	+ compatible = "img,pistachio-marduk", "img,pistachio";
	18	+
	19	+ aliases {
	20	+ serial0 = &uart0;
	21	+ serial1 = &uart1;
	22	+ ethernet0 = &enet;
	23	+ spi0 = &spfi0;
	24	+ spi1 = &spfi1;
	25	+ };
	26	+
	27	+ chosen {
	28	+ bootargs = "root=/dev/sda1 rootwait ro lpj=723968";
	29	+ stdout-path = "serial1:115200";
	30	+ };
	31	+
	32	+ memory {
	33	+ device_type = "memory";
	34	+ reg = <0x00000000 0x10000000>;
	35	+ };
	36	+
	37	+ reg_1v8: fixed-regulator {
	38	+ compatible = "regulator-fixed";
	39	+ regulator-name = "aux_adc_vref";
	40	+ regulator-min-microvolt = <1800000>;
	41	+ regulator-max-microvolt = <1800000>;
	42	+ regulator-boot-on;
	43	+ };
	44	+
	45	+ internal_dac_supply: internal-dac-supply {
	46	+ compatible = "regulator-fixed";
	47	+ regulator-name = "internal_dac_supply";
	48	+ regulator-min-microvolt = <1800000>;
	49	+ regulator-max-microvolt = <1800000>;
	50	+ };
	51	+
	52	+ leds {
	53	+ compatible = "pwm-leds";
	54	+ heartbeat {
	55	+ label = "marduk:red:heartbeat";
	56	+ pwms = <&pwm 3 300000>;
	57	+ max-brightness = <255>;
	58	+ linux,default-trigger = "heartbeat";
	59	+ };
	60	+ };
	61	+
	62	+ keys {
	63	+ compatible = "gpio-keys";
	64	+ button@1 {
	65	+ label = "Button 1";
	66	+ linux,code = <0x101>; /* BTN_1 */
	67	+ gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
	68	+ };
	69	+ button@2 {
	70	+ label = "Button 2";
	71	+ linux,code = <0x102>; /* BTN_2 */
	72	+ gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
	73	+ };
	74	+ };
	75	+};
	76	+
	77	+&internal_dac {
	78	+ VDD-supply = <&internal_dac_supply>;
	79	+};
	80	+
	81	+&spfi1 {
	82	+ status = "okay";
	83	+
	84	+ pinctrl-0 = <&spim1_pins>, <&spim1_quad_pins>, <&spim1_cs0_pin>,
	85	+ <&spim1_cs1_pin>;
	86	+ pinctrl-names = "default";
	87	+ cs-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>, <&gpio0 1 GPIO_ACTIVE_HIGH>;
	88	+
	89	+ flash@0 {
	90	+ compatible = "spansion,s25fl016k", "jedec,spi-nor";
	91	+ reg = <0>;
	92	+ spi-max-frequency = <50000000>;
	93	+ };
	94	+};
	95	+
	96	+&uart0 {
	97	+ status = "okay";
	98	+ assigned-clock-rates = <114278400>, <1843200>;
	99	+};
	100	+
	101	+&uart1 {
	102	+ status = "okay";
	103	+};
	104	+
	105	+&usb {
	106	+ status = "okay";
	107	+};
	108	+
	109	+&enet {
	110	+ status = "okay";
	111	+};
	112	+
	113	+&pin_enet {
	114	+ drive-strength = <2>;
	115	+};
	116	+
	117	+&pin_enet_phy_clk {
	118	+ drive-strength = <2>;
	119	+};
	120	+
	121	+&sdhost {
	122	+ status = "okay";
	123	+ bus-width = <4>;
	124	+ disable-wp;
	125	+};
	126	+
	127	+&pin_sdhost_cmd {
	128	+ drive-strength = <2>;
	129	+};
	130	+
	131	+&pin_sdhost_data {
	132	+ drive-strength = <2>;
	133	+};
	134	+
	135	+&pwm {
	136	+ status = "okay";
	137	+
	138	+ pinctrl-0 = <&pwmpdm0_pin>, <&pwmpdm1_pin>, <&pwmpdm2_pin>,
	139	+ <&pwmpdm3_pin>;
	140	+ pinctrl-names = "default";
	141	+};
	142	+
	143	+&adc {
	144	+ status = "okay";
	145	+ vref-supply = <&reg_1v8>;
	146	+ adc-reserved-channels = <0x10>;
	147	+};
	148	+
	149	+&i2c2 {
	150	+ status = "okay";
	151	+ clock-frequency = <400000>;
	152	+
	153	+ tpm@20 {
	154	+ compatible = "infineon,slb9645tt";
	155	+ reg = <0x20>;
	156	+ };
	157	+
	158	+};
	159	+
	160	+&i2c3 {
	161	+ status = "okay";
	162	+ clock-frequency = <400000>;
	163	+};

arch/mips/boot/dts/xilfpga/nexys4ddr.dts+63−0

@@ -17,6 +17,18 @@ · 16 unmodified lines
17	17	compatible = "mti,cpu-interrupt-controller";
18	18	};
19	19
	20	+ axi_intc: interrupt-controller@10200000 {
	21	+ #interrupt-cells = <1>;
	22	+ compatible = "xlnx,xps-intc-1.00.a";
	23	+ interrupt-controller;
	24	+ reg = <0x10200000 0x10000>;
	25	+ xlnx,kind-of-intr = <0x0>;
	26	+ xlnx,num-intr-inputs = <0x6>;
	27	+
	28	+ interrupt-parent = <&cpuintc>;
	29	+ interrupts = <6>;
	30	+ };
	31	+
20	32	axi_gpio: gpio@10600000 {
21	33	#gpio-cells = <1>;
22	34	compatible = "xlnx,xps-gpio-1.00.a";
@@ -30,6 +42,32 @@ · 7 unmodified lines
30	42	xlnx,tri-default = <0xffffffff>;
31	43	} ;
32	44
	45	+ axi_ethernetlite: ethernet@10e00000 {
	46	+ compatible = "xlnx,xps-ethernetlite-3.00.a";
	47	+ device_type = "network";
	48	+ interrupt-parent = <&axi_intc>;
	49	+ interrupts = <1>;
	50	+ phy-handle = <&phy0>;
	51	+ reg = <0x10e00000 0x10000>;
	52	+ xlnx,duplex = <0x1>;
	53	+ xlnx,include-global-buffers = <0x1>;
	54	+ xlnx,include-internal-loopback = <0x0>;
	55	+ xlnx,include-mdio = <0x1>;
	56	+ xlnx,instance = "axi_ethernetlite_inst";
	57	+ xlnx,rx-ping-pong = <0x1>;
	58	+ xlnx,s-axi-id-width = <0x1>;
	59	+ xlnx,tx-ping-pong = <0x1>;
	60	+ xlnx,use-internal = <0x0>;
	61	+ mdio {
	62	+ #address-cells = <1>;
	63	+ #size-cells = <0>;
	64	+ phy0: phy@1 {
	65	+ device_type = "ethernet-phy";
	66	+ reg = <1>;
	67	+ };
	68	+ };
	69	+ };
	70	+
33	71	axi_uart16550: serial@10400000 {
34	72	compatible = "ns16550a";
35	73	reg = <0x10400000 0x10000>;
@@ -38,7 +76,32 @@ · 2 unmodified lines
38	76	reg-offset = <0x1000>;
39	77
40	78	clocks = <&ext>;
	79	+
	80	+ interrupt-parent = <&axi_intc>;
	81	+ interrupts = <0>;
41	82	};
	83	+
	84	+ axi_i2c: i2c@10A00000 {
	85	+ compatible = "xlnx,xps-iic-2.00.a";
	86	+ interrupt-parent = <&axi_intc>;
	87	+ interrupts = <4>;
	88	+ reg = < 0x10A00000 0x10000 >;
	89	+ clocks = <&ext>;
	90	+ xlnx,clk-freq = <0x5f5e100>;
	91	+ xlnx,family = "Artix7";
	92	+ xlnx,gpo-width = <0x1>;
	93	+ xlnx,iic-freq = <0x186a0>;
	94	+ xlnx,scl-inertial-delay = <0x0>;
	95	+ xlnx,sda-inertial-delay = <0x0>;
	96	+ xlnx,ten-bit-adr = <0x0>;
	97	+ #address-cells = <1>;
	98	+ #size-cells = <0>;
	99	+
	100	+ ad7420@4B {
	101	+ compatible = "adi,adt7420";
	102	+ reg = <0x4B>;
	103	+ };
	104	+ } ;
42	105	};
43	106
44	107	&ext {

arch/mips/cavium-octeon/Makefile+1−0

@@ -18,3 +18,4 @@ obj-y += crypto/ · 17 unmodified lines
18	18	obj-$(CONFIG_MTD) += flash_setup.o
19	19	obj-$(CONFIG_SMP) += smp.o
20	20	obj-$(CONFIG_OCTEON_ILM) += oct_ilm.o
	21	+obj-$(CONFIG_USB) += octeon-usb.o

arch/mips/cavium-octeon/crypto/octeon-crypto.c+1−1

@@ -7,7 +7,7 @@ · 6 unmodified lines
7	7	*/
8	8
9	9	#include <asm/cop2.h>
10		−#include <linux/module.h>
	10	+#include <linux/export.h>
11	11	#include <linux/interrupt.h>
12	12
13	13	#include "octeon-crypto.h"

arch/mips/cavium-octeon/dma-octeon.c+5−10

@@ -164,19 +164,14 @@ static void octeon_dma_alloc_coherent(struct device dev, size_t size, · 163 unmodified lines
164	164	/* ignore region specifiers */
165	165	gfp &= ~(__GFP_DMA \| __GFP_DMA32 \| __GFP_HIGHMEM);
166	166
167		−#ifdef CONFIG_ZONE_DMA
168		− if (dev == NULL)
	167	+ if (IS_ENABLED(CONFIG_ZONE_DMA) && dev == NULL)
169	168	gfp \|= __GFP_DMA;
170		− else if (dev->coherent_dma_mask <= DMA_BIT_MASK(24))
	169	+ else if (IS_ENABLED(CONFIG_ZONE_DMA) &&
	170	+ dev->coherent_dma_mask <= DMA_BIT_MASK(24))
171	171	gfp \|= __GFP_DMA;
172		− else
173		−#endif
174		−#ifdef CONFIG_ZONE_DMA32
175		− if (dev->coherent_dma_mask <= DMA_BIT_MASK(32))
	172	+ else if (IS_ENABLED(CONFIG_ZONE_DMA32) &&
	173	+ dev->coherent_dma_mask <= DMA_BIT_MASK(32))
176	174	gfp \|= __GFP_DMA32;
177		− else
178		−#endif
179		− ;
180	175
181	176	/* Don't invoke OOM killer */
182	177	gfp \|= __GFP_NORETRY;

arch/mips/cavium-octeon/executive/cvmx-bootmem.c+1−1

@@ -30,8 +30,8 @@ · 29 unmodified lines
30	30	* application start time.
31	31	*/
32	32
	33	+#include <linux/export.h>
33	34	#include <linux/kernel.h>
34		−#include <linux/module.h>
35	35
36	36	#include <asm/octeon/cvmx.h>
37	37	#include <asm/octeon/cvmx-spinlock.h>

arch/mips/cavium-octeon/executive/cvmx-helper-errata.c+1−1

@@ -33,7 +33,7 @@ · 32 unmodified lines
33	33	* these functions directly.
34	34	*
35	35	*/
36		−#include <linux/module.h>
	36	+#include <linux/export.h>
37	37
38	38	#include <asm/octeon/octeon.h>
39	39

arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c+1−2

@@ -287,8 +287,7 @@ cvmx_helper_link_info_t __cvmx_helper_rgmii_link_get(int ipd_port) · 286 unmodified lines
287	287	* Configure an IPD/PKO port for the specified link state. This
288	288	* function does not influence auto negotiation at the PHY level.
289	289	* The passed link state must always match the link state returned
290		− * by cvmx_helper_link_get(). It is normally best to use
291		− * cvmx_helper_link_autoconf() instead.
	290	+ * by cvmx_helper_link_get().
292	291	*
293	292	* @ipd_port: IPD/PKO port to configure
294	293	* @link_info: The new link state

arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c+1−2

@@ -500,8 +500,7 @@ cvmx_helper_link_info_t __cvmx_helper_sgmii_link_get(int ipd_port) · 499 unmodified lines
500	500	* Configure an IPD/PKO port for the specified link state. This
501	501	* function does not influence auto negotiation at the PHY level.
502	502	* The passed link state must always match the link state returned
503		− * by cvmx_helper_link_get(). It is normally best to use
504		− * cvmx_helper_link_autoconf() instead.
	503	+ * by cvmx_helper_link_get().
505	504	*
506	505	* @ipd_port: IPD/PKO port to configure
507	506	* @link_info: The new link state

arch/mips/cavium-octeon/executive/cvmx-helper-spi.c+1−2

@@ -188,8 +188,7 @@ cvmx_helper_link_info_t __cvmx_helper_spi_link_get(int ipd_port) · 187 unmodified lines
188	188	* Configure an IPD/PKO port for the specified link state. This
189	189	* function does not influence auto negotiation at the PHY level.
190	190	* The passed link state must always match the link state returned
191		− * by cvmx_helper_link_get(). It is normally best to use
192		− * cvmx_helper_link_autoconf() instead.
	191	+ * by cvmx_helper_link_get().
193	192	*
194	193	* @ipd_port: IPD/PKO port to configure
195	194	* @link_info: The new link state

arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c+1−2

@@ -295,8 +295,7 @@ cvmx_helper_link_info_t __cvmx_helper_xaui_link_get(int ipd_port) · 294 unmodified lines
295	295	* Configure an IPD/PKO port for the specified link state. This
296	296	* function does not influence auto negotiation at the PHY level.
297	297	* The passed link state must always match the link state returned
298		− * by cvmx_helper_link_get(). It is normally best to use
299		− * cvmx_helper_link_autoconf() instead.
	298	+ * by cvmx_helper_link_get().
300	299	*
301	300	* @ipd_port: IPD/PKO port to configure
302	301	* @link_info: The new link state

arch/mips/cavium-octeon/executive/cvmx-helper.c+1−46

@@ -69,10 +69,6 @@ void (*cvmx_override_ipd_port_setup) (int ipd_port); · 68 unmodified lines
69	69	/* Port count per interface */
70	70	static int interface_port_count[5];
71	71
72		−/* Port last configured link info index by IPD/PKO port */
73		−static cvmx_helper_link_info_t
74		− port_link_info[CVMX_PIP_NUM_INPUT_PORTS];
75		−
76	72	/**
77	73	* Return the number of interfaces the chip has. Each interface
78	74	* may have multiple ports. Most chips support two interfaces,
@@ -1135,41 +1131,6 @@ int cvmx_helper_initialize_packet_io_local(void) · 1056 unmodified lines
1135	1131	return cvmx_pko_initialize_local();
1136	1132	}
1137	1133
1138		−/**
1139		− * Auto configure an IPD/PKO port link state and speed. This
1140		− * function basically does the equivalent of:
1141		− * cvmx_helper_link_set(ipd_port, cvmx_helper_link_get(ipd_port));
1142		− *
1143		− * @ipd_port: IPD/PKO port to auto configure
1144		− *
1145		− * Returns Link state after configure
1146		− */
1147		−cvmx_helper_link_info_t cvmx_helper_link_autoconf(int ipd_port)
1148		−{
1149		− cvmx_helper_link_info_t link_info;
1150		− int interface = cvmx_helper_get_interface_num(ipd_port);
1151		− int index = cvmx_helper_get_interface_index_num(ipd_port);
1152		−
1153		− if (index >= cvmx_helper_ports_on_interface(interface)) {
1154		− link_info.u64 = 0;
1155		− return link_info;
1156		− }
1157		−
1158		− link_info = cvmx_helper_link_get(ipd_port);
1159		− if (link_info.u64 == port_link_info[ipd_port].u64)
1160		− return link_info;
1161		−
1162		− /* If we fail to set the link speed, port_link_info will not change */
1163		− cvmx_helper_link_set(ipd_port, link_info);
1164		−
1165		− /*
1166		− * port_link_info should be the current value, which will be
1167		− * different than expect if cvmx_helper_link_set() failed.
1168		− */
1169		− return port_link_info[ipd_port];
1170		−}
1171		−EXPORT_SYMBOL_GPL(cvmx_helper_link_autoconf);
1172		−
1173	1134	/**
1174	1135	* Return the link state of an IPD/PKO port as returned by
1175	1136	* auto negotiation. The result of this function may not match
@@ -1233,8 +1194,7 @@ EXPORT_SYMBOL_GPL(cvmx_helper_link_get); · 57 unmodified lines
1233	1194	* Configure an IPD/PKO port for the specified link state. This
1234	1195	* function does not influence auto negotiation at the PHY level.
1235	1196	* The passed link state must always match the link state returned
1236		− * by cvmx_helper_link_get(). It is normally best to use
1237		− * cvmx_helper_link_autoconf() instead.
	1197	+ * by cvmx_helper_link_get().
1238	1198	*
1239	1199	* @ipd_port: IPD/PKO port to configure
1240	1200	* @link_info: The new link state
@@ -1276,11 +1236,6 @@ int cvmx_helper_link_set(int ipd_port, cvmx_helper_link_info_t link_info) · 35 unmodified lines
1276	1236	case CVMX_HELPER_INTERFACE_MODE_LOOP:
1277	1237	break;
1278	1238	}
1279		− /* Set the port_link_info here so that the link status is updated
1280		− no matter how cvmx_helper_link_set is called. We don't change
1281		− the value if link_set failed */
1282		− if (result == 0)
1283		− port_link_info[ipd_port].u64 = link_info.u64;
1284	1239	return result;
1285	1240	}
1286	1241	EXPORT_SYMBOL_GPL(cvmx_helper_link_set);

arch/mips/cavium-octeon/executive/cvmx-sysinfo.c+1−1

@@ -29,7 +29,7 @@ · 28 unmodified lines
29	29	* This module provides system/board/application information obtained
30	30	* by the bootloader.
31	31	*/
32		−#include <linux/module.h>
	32	+#include <linux/export.h>
33	33
34	34	#include <asm/octeon/cvmx.h>
35	35	#include <asm/octeon/cvmx-sysinfo.h>

arch/mips/cavium-octeon/octeon-memcpy.S+17−8

@@ -15,6 +15,7 @@ · 14 unmodified lines
15	15
16	16	#include <asm/asm.h>
17	17	#include <asm/asm-offsets.h>
	18	+#include <asm/export.h>
18	19	#include <asm/regdef.h>
19	20
20	21	#define dst a0
@@ -142,6 +143,7 @@ · 121 unmodified lines
142	143	* t7 is used as a flag to note inatomic mode.
143	144	*/
144	145	LEAF(__copy_user_inatomic)
	146	+EXPORT_SYMBOL(__copy_user_inatomic)
145	147	b __copy_user_common
146	148	li t7, 1
147	149	END(__copy_user_inatomic)
@@ -154,9 +156,11 @@ LEAF(__copy_user_inatomic) · 6 unmodified lines
154	156	*/
155	157	.align 5
156	158	LEAF(memcpy) /* a0=dst a1=src a2=len */
	159	+EXPORT_SYMBOL(memcpy)
157	160	move v0, dst /* return value */
158	161	__memcpy:
159	162	FEXPORT(__copy_user)
	163	+EXPORT_SYMBOL(__copy_user)
160	164	li t7, 0 /* not inatomic */
161	165	__copy_user_common:
162	166	/*
@@ -208,18 +212,18 @@ EXC( STORE t2, UNIT(6)(dst), s_exc_p10u) · 45 unmodified lines
208	212	ADD src, src, 16*NBYTES
209	213	EXC( STORE t3, UNIT(7)(dst), s_exc_p9u)
210	214	ADD dst, dst, 16*NBYTES
211		−EXC( LOAD t0, UNIT(-8)(src), l_exc_copy)
212		−EXC( LOAD t1, UNIT(-7)(src), l_exc_copy)
213		−EXC( LOAD t2, UNIT(-6)(src), l_exc_copy)
214		−EXC( LOAD t3, UNIT(-5)(src), l_exc_copy)
	215	+EXC( LOAD t0, UNIT(-8)(src), l_exc_copy_rewind16)
	216	+EXC( LOAD t1, UNIT(-7)(src), l_exc_copy_rewind16)
	217	+EXC( LOAD t2, UNIT(-6)(src), l_exc_copy_rewind16)
	218	+EXC( LOAD t3, UNIT(-5)(src), l_exc_copy_rewind16)
215	219	EXC( STORE t0, UNIT(-8)(dst), s_exc_p8u)
216	220	EXC( STORE t1, UNIT(-7)(dst), s_exc_p7u)
217	221	EXC( STORE t2, UNIT(-6)(dst), s_exc_p6u)
218	222	EXC( STORE t3, UNIT(-5)(dst), s_exc_p5u)
219		−EXC( LOAD t0, UNIT(-4)(src), l_exc_copy)
220		−EXC( LOAD t1, UNIT(-3)(src), l_exc_copy)
221		−EXC( LOAD t2, UNIT(-2)(src), l_exc_copy)
222		−EXC( LOAD t3, UNIT(-1)(src), l_exc_copy)
	223	+EXC( LOAD t0, UNIT(-4)(src), l_exc_copy_rewind16)
	224	+EXC( LOAD t1, UNIT(-3)(src), l_exc_copy_rewind16)
	225	+EXC( LOAD t2, UNIT(-2)(src), l_exc_copy_rewind16)
	226	+EXC( LOAD t3, UNIT(-1)(src), l_exc_copy_rewind16)
223	227	EXC( STORE t0, UNIT(-4)(dst), s_exc_p4u)
224	228	EXC( STORE t1, UNIT(-3)(dst), s_exc_p3u)
225	229	EXC( STORE t2, UNIT(-2)(dst), s_exc_p2u)
@@ -383,6 +387,10 @@ done: · 157 unmodified lines
383	387	nop
384	388	END(memcpy)
385	389
	390	+l_exc_copy_rewind16:
	391	+ /* Rewind src and dst by 16NBYTES for l_exc_copy /
	392	+ SUB src, src, 16*NBYTES
	393	+ SUB dst, dst, 16*NBYTES
386	394	l_exc_copy:
387	395	/*
388	396	* Copy bytes from src until faulting load address (or until a
@@ -459,6 +467,7 @@ s_exc: · 70 unmodified lines
459	467
460	468	.align 5
461	469	LEAF(memmove)
	470	+EXPORT_SYMBOL(memmove)
462	471	ADD t0, a0, a2
463	472	ADD t1, a1, a2
464	473	sltu t0, a1, t0 # dst + len <= src -> memcpy

arch/mips/cavium-octeon/octeon-platform.c+1−0

@@ -448,6 +448,7 @@ static struct of_device_id __initdata octeon_ids[] = { · 447 unmodified lines
448	448	{ .compatible = "cavium,octeon-3860-bootbus", },
449	449	{ .compatible = "cavium,mdio-mux", },
450	450	{ .compatible = "gpio-leds", },
	451	+ { .compatible = "cavium,octeon-7130-usb-uctl", },
451	452	{},
452	453	};
453	454

arch/mips/cavium-octeon/octeon-usb.c+552−0

@@ -0,0 +1,552 @@
	1	+/*
	2	+ * XHCI HCD glue for Cavium Octeon III SOCs.
	3	+ *
	4	+ * Copyright (C) 2010-2017 Cavium Networks
	5	+ *
	6	+ * This file is subject to the terms and conditions of the GNU General Public
	7	+ * License. See the file "COPYING" in the main directory of this archive
	8	+ * for more details.
	9	+ */
	10	+
	11	+#include <linux/module.h>
	12	+#include <linux/device.h>
	13	+#include <linux/mutex.h>
	14	+#include <linux/delay.h>
	15	+#include <linux/of_platform.h>
	16	+
	17	+#include <asm/octeon/octeon.h>
	18	+#include <asm/octeon/cvmx-gpio-defs.h>
	19	+
	20	+/* USB Control Register */
	21	+union cvm_usbdrd_uctl_ctl {
	22	+ uint64_t u64;
	23	+ struct cvm_usbdrd_uctl_ctl_s {
	24	+ /* 1 = BIST and set all USB RAMs to 0x0, 0 = BIST */
	25	+ __BITFIELD_FIELD(uint64_t clear_bist:1,
	26	+ /* 1 = Start BIST and cleared by hardware */
	27	+ __BITFIELD_FIELD(uint64_t start_bist:1,
	28	+ /* Reference clock select for SuperSpeed and HighSpeed PLLs:
	29	+ * 0x0 = Both PLLs use DLMC_REF_CLK0 for reference clock
	30	+ * 0x1 = Both PLLs use DLMC_REF_CLK1 for reference clock
	31	+ * 0x2 = SuperSpeed PLL uses DLMC_REF_CLK0 for reference clock &
	32	+ * HighSpeed PLL uses PLL_REF_CLK for reference clck
	33	+ * 0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock &
	34	+ * HighSpeed PLL uses PLL_REF_CLK for reference clck
	35	+ */
	36	+ __BITFIELD_FIELD(uint64_t ref_clk_sel:2,
	37	+ /* 1 = Spread-spectrum clock enable, 0 = SS clock disable */
	38	+ __BITFIELD_FIELD(uint64_t ssc_en:1,
	39	+ /* Spread-spectrum clock modulation range:
	40	+ * 0x0 = -4980 ppm downspread
	41	+ * 0x1 = -4492 ppm downspread
	42	+ * 0x2 = -4003 ppm downspread
	43	+ * 0x3 - 0x7 = Reserved
	44	+ */
	45	+ __BITFIELD_FIELD(uint64_t ssc_range:3,
	46	+ /* Enable non-standard oscillator frequencies:
	47	+ * [55:53] = modules -1
	48	+ * [52:47] = 2's complement push amount, 0 = Feature disabled
	49	+ */
	50	+ __BITFIELD_FIELD(uint64_t ssc_ref_clk_sel:9,
	51	+ /* Reference clock multiplier for non-standard frequencies:
	52	+ * 0x19 = 100MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
	53	+ * 0x28 = 125MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
	54	+ * 0x32 = 50MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
	55	+ * Other Values = Reserved
	56	+ */
	57	+ __BITFIELD_FIELD(uint64_t mpll_multiplier:7,
	58	+ /* Enable reference clock to prescaler for SuperSpeed functionality.
	59	+ * Should always be set to "1"
	60	+ */
	61	+ __BITFIELD_FIELD(uint64_t ref_ssp_en:1,
	62	+ /* Divide the reference clock by 2 before entering the
	63	+ * REF_CLK_FSEL divider:
	64	+ * If REF_CLK_SEL = 0x0 or 0x1, then only 0x0 is legal
	65	+ * If REF_CLK_SEL = 0x2 or 0x3, then:
	66	+ * 0x1 = DLMC_REF_CLK* is 125MHz
	67	+ * 0x0 = DLMC_REF_CLK* is another supported frequency
	68	+ */
	69	+ __BITFIELD_FIELD(uint64_t ref_clk_div2:1,
	70	+ /* Select reference clock freqnuency for both PLL blocks:
	71	+ * 0x27 = REF_CLK_SEL is 0x0 or 0x1
	72	+ * 0x07 = REF_CLK_SEL is 0x2 or 0x3
	73	+ */
	74	+ __BITFIELD_FIELD(uint64_t ref_clk_fsel:6,
	75	+ /* Reserved */
	76	+ __BITFIELD_FIELD(uint64_t reserved_31_31:1,
	77	+ /* Controller clock enable. */
	78	+ __BITFIELD_FIELD(uint64_t h_clk_en:1,
	79	+ /* Select bypass input to controller clock divider:
	80	+ * 0x0 = Use divided coprocessor clock from H_CLKDIV
	81	+ * 0x1 = Use clock from GPIO pins
	82	+ */
	83	+ __BITFIELD_FIELD(uint64_t h_clk_byp_sel:1,
	84	+ /* Reset controller clock divider. */
	85	+ __BITFIELD_FIELD(uint64_t h_clkdiv_rst:1,
	86	+ /* Reserved */
	87	+ __BITFIELD_FIELD(uint64_t reserved_27_27:1,
	88	+ /* Clock divider select:
	89	+ * 0x0 = divide by 1
	90	+ * 0x1 = divide by 2
	91	+ * 0x2 = divide by 4
	92	+ * 0x3 = divide by 6
	93	+ * 0x4 = divide by 8
	94	+ * 0x5 = divide by 16
	95	+ * 0x6 = divide by 24
	96	+ * 0x7 = divide by 32
	97	+ */
	98	+ __BITFIELD_FIELD(uint64_t h_clkdiv_sel:3,
	99	+ /* Reserved */
	100	+ __BITFIELD_FIELD(uint64_t reserved_22_23:2,
	101	+ /* USB3 port permanently attached: 0x0 = No, 0x1 = Yes */
	102	+ __BITFIELD_FIELD(uint64_t usb3_port_perm_attach:1,
	103	+ /* USB2 port permanently attached: 0x0 = No, 0x1 = Yes */
	104	+ __BITFIELD_FIELD(uint64_t usb2_port_perm_attach:1,
	105	+ /* Reserved */
	106	+ __BITFIELD_FIELD(uint64_t reserved_19_19:1,
	107	+ /* Disable SuperSpeed PHY: 0x0 = No, 0x1 = Yes */
	108	+ __BITFIELD_FIELD(uint64_t usb3_port_disable:1,
	109	+ /* Reserved */
	110	+ __BITFIELD_FIELD(uint64_t reserved_17_17:1,
	111	+ /* Disable HighSpeed PHY: 0x0 = No, 0x1 = Yes */
	112	+ __BITFIELD_FIELD(uint64_t usb2_port_disable:1,
	113	+ /* Reserved */
	114	+ __BITFIELD_FIELD(uint64_t reserved_15_15:1,
	115	+ /* Enable PHY SuperSpeed block power: 0x0 = No, 0x1 = Yes */
	116	+ __BITFIELD_FIELD(uint64_t ss_power_en:1,
	117	+ /* Reserved */
	118	+ __BITFIELD_FIELD(uint64_t reserved_13_13:1,
	119	+ /* Enable PHY HighSpeed block power: 0x0 = No, 0x1 = Yes */
	120	+ __BITFIELD_FIELD(uint64_t hs_power_en:1,
	121	+ /* Reserved */
	122	+ __BITFIELD_FIELD(uint64_t reserved_5_11:7,
	123	+ /* Enable USB UCTL interface clock: 0xx = No, 0x1 = Yes */
	124	+ __BITFIELD_FIELD(uint64_t csclk_en:1,
	125	+ /* Controller mode: 0x0 = Host, 0x1 = Device */
	126	+ __BITFIELD_FIELD(uint64_t drd_mode:1,
	127	+ /* PHY reset */
	128	+ __BITFIELD_FIELD(uint64_t uphy_rst:1,
	129	+ /* Software reset UAHC */
	130	+ __BITFIELD_FIELD(uint64_t uahc_rst:1,
	131	+ /* Software resets UCTL */
	132	+ __BITFIELD_FIELD(uint64_t uctl_rst:1,
	133	+ ;)))))))))))))))))))))))))))))))))
	134	+ } s;
	135	+};
	136	+
	137	+/* UAHC Configuration Register */
	138	+union cvm_usbdrd_uctl_host_cfg {
	139	+ uint64_t u64;
	140	+ struct cvm_usbdrd_uctl_host_cfg_s {
	141	+ /* Reserved */
	142	+ __BITFIELD_FIELD(uint64_t reserved_60_63:4,
	143	+ /* Indicates minimum value of all received BELT values */
	144	+ __BITFIELD_FIELD(uint64_t host_current_belt:12,
	145	+ /* Reserved */
	146	+ __BITFIELD_FIELD(uint64_t reserved_38_47:10,
	147	+ /* HS jitter adjustment */
	148	+ __BITFIELD_FIELD(uint64_t fla:6,
	149	+ /* Reserved */
	150	+ __BITFIELD_FIELD(uint64_t reserved_29_31:3,
	151	+ /* Bus-master enable: 0x0 = Disabled (stall DMAs), 0x1 = enabled */
	152	+ __BITFIELD_FIELD(uint64_t bme:1,
	153	+ /* Overcurrent protection enable: 0x0 = unavailable, 0x1 = available */
	154	+ __BITFIELD_FIELD(uint64_t oci_en:1,
	155	+ /* Overcurrent sene selection:
	156	+ * 0x0 = Overcurrent indication from off-chip is active-low
	157	+ * 0x1 = Overcurrent indication from off-chip is active-high
	158	+ */
	159	+ __BITFIELD_FIELD(uint64_t oci_active_high_en:1,
	160	+ /* Port power control enable: 0x0 = unavailable, 0x1 = available */
	161	+ __BITFIELD_FIELD(uint64_t ppc_en:1,
	162	+ /* Port power control sense selection:
	163	+ * 0x0 = Port power to off-chip is active-low
	164	+ * 0x1 = Port power to off-chip is active-high
	165	+ */
	166	+ __BITFIELD_FIELD(uint64_t ppc_active_high_en:1,
	167	+ /* Reserved */
	168	+ __BITFIELD_FIELD(uint64_t reserved_0_23:24,
	169	+ ;)))))))))))
	170	+ } s;
	171	+};
	172	+
	173	+/* UCTL Shim Features Register */
	174	+union cvm_usbdrd_uctl_shim_cfg {
	175	+ uint64_t u64;
	176	+ struct cvm_usbdrd_uctl_shim_cfg_s {
	177	+ /* Out-of-bound UAHC register access: 0 = read, 1 = write */
	178	+ __BITFIELD_FIELD(uint64_t xs_ncb_oob_wrn:1,
	179	+ /* Reserved */
	180	+ __BITFIELD_FIELD(uint64_t reserved_60_62:3,
	181	+ /* SRCID error log for out-of-bound UAHC register access:
	182	+ * [59:58] = chipID
	183	+ * [57] = Request source: 0 = core, 1 = NCB-device
	184	+ * [56:51] = Core/NCB-device number, [56] always 0 for NCB devices
	185	+ * [50:48] = SubID
	186	+ */
	187	+ __BITFIELD_FIELD(uint64_t xs_ncb_oob_osrc:12,
	188	+ /* Error log for bad UAHC DMA access: 0 = Read log, 1 = Write log */
	189	+ __BITFIELD_FIELD(uint64_t xm_bad_dma_wrn:1,
	190	+ /* Reserved */
	191	+ __BITFIELD_FIELD(uint64_t reserved_44_46:3,
	192	+ /* Encoded error type for bad UAHC DMA */
	193	+ __BITFIELD_FIELD(uint64_t xm_bad_dma_type:4,
	194	+ /* Reserved */
	195	+ __BITFIELD_FIELD(uint64_t reserved_13_39:27,
	196	+ /* Select the IOI read command used by DMA accesses */
	197	+ __BITFIELD_FIELD(uint64_t dma_read_cmd:1,
	198	+ /* Reserved */
	199	+ __BITFIELD_FIELD(uint64_t reserved_10_11:2,
	200	+ /* Select endian format for DMA accesses to the L2c:
	201	+ * 0x0 = Little endian
	202	+ *` 0x1 = Big endian
	203	+ * 0x2 = Reserved
	204	+ * 0x3 = Reserved
	205	+ */
	206	+ __BITFIELD_FIELD(uint64_t dma_endian_mode:2,
	207	+ /* Reserved */
	208	+ __BITFIELD_FIELD(uint64_t reserved_2_7:6,
	209	+ /* Select endian format for IOI CSR access to UAHC:
	210	+ * 0x0 = Little endian
	211	+ *` 0x1 = Big endian
	212	+ * 0x2 = Reserved
	213	+ * 0x3 = Reserved
	214	+ */
	215	+ __BITFIELD_FIELD(uint64_t csr_endian_mode:2,
	216	+ ;))))))))))))
	217	+ } s;
	218	+};
	219	+
	220	+#define OCTEON_H_CLKDIV_SEL 8
	221	+#define OCTEON_MIN_H_CLK_RATE 150000000
	222	+#define OCTEON_MAX_H_CLK_RATE 300000000
	223	+
	224	+static DEFINE_MUTEX(dwc3_octeon_clocks_mutex);
	225	+static uint8_t clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32};
	226	+
	227	+
	228	+static int dwc3_octeon_config_power(struct device *dev, u64 base)
	229	+{
	230	+#define UCTL_HOST_CFG 0xe0
	231	+ union cvm_usbdrd_uctl_host_cfg uctl_host_cfg;
	232	+ union cvmx_gpio_bit_cfgx gpio_bit;
	233	+ uint32_t gpio_pwr[3];
	234	+ int gpio, len, power_active_low;
	235	+ struct device_node *node = dev->of_node;
	236	+ int index = (base >> 24) & 1;
	237	+
	238	+ if (of_find_property(node, "power", &len) != NULL) {
	239	+ if (len == 12) {
	240	+ of_property_read_u32_array(node, "power", gpio_pwr, 3);
	241	+ power_active_low = gpio_pwr[2] & 0x01;
	242	+ gpio = gpio_pwr[1];
	243	+ } else if (len == 8) {
	244	+ of_property_read_u32_array(node, "power", gpio_pwr, 2);
	245	+ power_active_low = 0;
	246	+ gpio = gpio_pwr[1];
	247	+ } else {
	248	+ dev_err(dev, "dwc3 controller clock init failure.\n");
	249	+ return -EINVAL;
	250	+ }
	251	+ if ((OCTEON_IS_MODEL(OCTEON_CN73XX) \|\|
	252	+ OCTEON_IS_MODEL(OCTEON_CNF75XX))
	253	+ && gpio <= 31) {
	254	+ gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio));
	255	+ gpio_bit.s.tx_oe = 1;
	256	+ gpio_bit.cn73xx.output_sel = (index == 0 ? 0x14 : 0x15);
	257	+ cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64);
	258	+ } else if (gpio <= 15) {
	259	+ gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio));
	260	+ gpio_bit.s.tx_oe = 1;
	261	+ gpio_bit.cn70xx.output_sel = (index == 0 ? 0x14 : 0x19);
	262	+ cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64);
	263	+ } else {
	264	+ gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(gpio));
	265	+ gpio_bit.s.tx_oe = 1;
	266	+ gpio_bit.cn70xx.output_sel = (index == 0 ? 0x14 : 0x19);
	267	+ cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(gpio), gpio_bit.u64);
	268	+ }
	269	+
	270	+ /* Enable XHCI power control and set if active high or low. */
	271	+ uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG);
	272	+ uctl_host_cfg.s.ppc_en = 1;
	273	+ uctl_host_cfg.s.ppc_active_high_en = !power_active_low;
	274	+ cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64);
	275	+ } else {
	276	+ /* Disable XHCI power control and set if active high. */
	277	+ uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG);
	278	+ uctl_host_cfg.s.ppc_en = 0;
	279	+ uctl_host_cfg.s.ppc_active_high_en = 0;
	280	+ cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64);
	281	+ dev_warn(dev, "dwc3 controller clock init failure.\n");
	282	+ }
	283	+ return 0;
	284	+}
	285	+
	286	+static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
	287	+{
	288	+ union cvm_usbdrd_uctl_ctl uctl_ctl;
	289	+ int ref_clk_sel = 2;
	290	+ u64 div;
	291	+ u32 clock_rate;
	292	+ int mpll_mul;
	293	+ int i;
	294	+ u64 h_clk_rate;
	295	+ u64 uctl_ctl_reg = base;
	296	+
	297	+ if (dev->of_node) {
	298	+ const char *ss_clock_type;
	299	+ const char *hs_clock_type;
	300	+
	301	+ i = of_property_read_u32(dev->of_node,
	302	+ "refclk-frequency", &clock_rate);
	303	+ if (i) {
	304	+ pr_err("No UCTL \"refclk-frequency\"\n");
	305	+ return -EINVAL;
	306	+ }
	307	+ i = of_property_read_string(dev->of_node,
	308	+ "refclk-type-ss", &ss_clock_type);
	309	+ if (i) {
	310	+ pr_err("No UCTL \"refclk-type-ss\"\n");
	311	+ return -EINVAL;
	312	+ }
	313	+ i = of_property_read_string(dev->of_node,
	314	+ "refclk-type-hs", &hs_clock_type);
	315	+ if (i) {
	316	+ pr_err("No UCTL \"refclk-type-hs\"\n");
	317	+ return -EINVAL;
	318	+ }
	319	+ if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) {
	320	+ if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0)
	321	+ ref_clk_sel = 0;
	322	+ else if (strcmp(hs_clock_type, "pll_ref_clk") == 0)
	323	+ ref_clk_sel = 2;
	324	+ else
	325	+ pr_err("Invalid HS clock type %s, using pll_ref_clk instead\n",
	326	+ hs_clock_type);
	327	+ } else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) {
	328	+ if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0)
	329	+ ref_clk_sel = 1;
	330	+ else if (strcmp(hs_clock_type, "pll_ref_clk") == 0)
	331	+ ref_clk_sel = 3;
	332	+ else {
	333	+ pr_err("Invalid HS clock type %s, using pll_ref_clk instead\n",
	334	+ hs_clock_type);
	335	+ ref_clk_sel = 3;
	336	+ }
	337	+ } else
	338	+ pr_err("Invalid SS clock type %s, using dlmc_ref_clk0 instead\n",
	339	+ ss_clock_type);
	340	+
	341	+ if ((ref_clk_sel == 0 \|\| ref_clk_sel == 1) &&
	342	+ (clock_rate != 100000000))
	343	+ pr_err("Invalid UCTL clock rate of %u, using 100000000 instead\n",
	344	+ clock_rate);
	345	+
	346	+ } else {
	347	+ pr_err("No USB UCTL device node\n");
	348	+ return -EINVAL;
	349	+ }
	350	+
	351	+ /*
	352	+ * Step 1: Wait for all voltages to be stable...that surely
	353	+ * happened before starting the kernel. SKIP
	354	+ */
	355	+
	356	+ /* Step 2: Select GPIO for overcurrent indication, if desired. SKIP */
	357	+
	358	+ /* Step 3: Assert all resets. */
	359	+ uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
	360	+ uctl_ctl.s.uphy_rst = 1;
	361	+ uctl_ctl.s.uahc_rst = 1;
	362	+ uctl_ctl.s.uctl_rst = 1;
	363	+ cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
	364	+
	365	+ /* Step 4a: Reset the clock dividers. */
	366	+ uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
	367	+ uctl_ctl.s.h_clkdiv_rst = 1;
	368	+ cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
	369	+
	370	+ /* Step 4b: Select controller clock frequency. */
	371	+ for (div = 0; div < OCTEON_H_CLKDIV_SEL; div++) {
	372	+ h_clk_rate = octeon_get_io_clock_rate() / clk_div[div];
	373	+ if (h_clk_rate <= OCTEON_MAX_H_CLK_RATE &&
	374	+ h_clk_rate >= OCTEON_MIN_H_CLK_RATE)
	375	+ break;
	376	+ }
	377	+ uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
	378	+ uctl_ctl.s.h_clkdiv_sel = div;
	379	+ uctl_ctl.s.h_clk_en = 1;
	380	+ cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
	381	+ uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
	382	+ if ((div != uctl_ctl.s.h_clkdiv_sel) \|\| (!uctl_ctl.s.h_clk_en)) {
	383	+ dev_err(dev, "dwc3 controller clock init failure.\n");
	384	+ return -EINVAL;
	385	+ }
	386	+
	387	+ /* Step 4c: Deassert the controller clock divider reset. */
	388	+ uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
	389	+ uctl_ctl.s.h_clkdiv_rst = 0;
	390	+ cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
	391	+
	392	+ /* Step 5a: Reference clock configuration. */
	393	+ uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
	394	+ uctl_ctl.s.ref_clk_sel = ref_clk_sel;
	395	+ uctl_ctl.s.ref_clk_fsel = 0x07;
	396	+ uctl_ctl.s.ref_clk_div2 = 0;
	397	+ switch (clock_rate) {
	398	+ default:
	399	+ dev_err(dev, "Invalid ref_clk %u, using 100000000 instead\n",
	400	+ clock_rate);
	401	+ case 100000000:
	402	+ mpll_mul = 0x19;
	403	+ if (ref_clk_sel < 2)
	404	+ uctl_ctl.s.ref_clk_fsel = 0x27;
	405	+ break;
	406	+ case 50000000:
	407	+ mpll_mul = 0x32;
	408	+ break;
	409	+ case 125000000:
	410	+ mpll_mul = 0x28;
	411	+ break;
	412	+ }
	413	+ uctl_ctl.s.mpll_multiplier = mpll_mul;
	414	+
	415	+ /* Step 5b: Configure and enable spread-spectrum for SuperSpeed. */
	416	+ uctl_ctl.s.ssc_en = 1;
	417	+
	418	+ /* Step 5c: Enable SuperSpeed. */
	419	+ uctl_ctl.s.ref_ssp_en = 1;
	420	+
	421	+ /* Step 5d: Cofngiure PHYs. SKIP */
	422	+
	423	+ /* Step 6a & 6b: Power up PHYs. */
	424	+ uctl_ctl.s.hs_power_en = 1;
	425	+ uctl_ctl.s.ss_power_en = 1;
	426	+ cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
	427	+
	428	+ /* Step 7: Wait 10 controller-clock cycles to take effect. */
	429	+ udelay(10);
	430	+
	431	+ /* Step 8a: Deassert UCTL reset signal. */
	432	+ uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
	433	+ uctl_ctl.s.uctl_rst = 0;
	434	+ cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
	435	+
	436	+ /* Step 8b: Wait 10 controller-clock cycles. */
	437	+ udelay(10);
	438	+
	439	+ /* Steo 8c: Setup power-power control. */
	440	+ if (dwc3_octeon_config_power(dev, base)) {
	441	+ dev_err(dev, "Error configuring power.\n");
	442	+ return -EINVAL;
	443	+ }
	444	+
	445	+ /* Step 8d: Deassert UAHC reset signal. */
	446	+ uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
	447	+ uctl_ctl.s.uahc_rst = 0;
	448	+ cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
	449	+
	450	+ /* Step 8e: Wait 10 controller-clock cycles. */
	451	+ udelay(10);
	452	+
	453	+ /* Step 9: Enable conditional coprocessor clock of UCTL. */
	454	+ uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
	455	+ uctl_ctl.s.csclk_en = 1;
	456	+ cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
	457	+
	458	+ /Step 10: Set for host mode only. /
	459	+ uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
	460	+ uctl_ctl.s.drd_mode = 0;
	461	+ cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
	462	+
	463	+ return 0;
	464	+}
	465	+
	466	+static void __init dwc3_octeon_set_endian_mode(u64 base)
	467	+{
	468	+#define UCTL_SHIM_CFG 0xe8
	469	+ union cvm_usbdrd_uctl_shim_cfg shim_cfg;
	470	+
	471	+ shim_cfg.u64 = cvmx_read_csr(base + UCTL_SHIM_CFG);
	472	+#ifdef __BIG_ENDIAN
	473	+ shim_cfg.s.dma_endian_mode = 1;
	474	+ shim_cfg.s.csr_endian_mode = 1;
	475	+#else
	476	+ shim_cfg.s.dma_endian_mode = 0;
	477	+ shim_cfg.s.csr_endian_mode = 0;
	478	+#endif
	479	+ cvmx_write_csr(base + UCTL_SHIM_CFG, shim_cfg.u64);
	480	+}
	481	+
	482	+#define CVMX_USBDRDX_UCTL_CTL(index) \
	483	+ (CVMX_ADD_IO_SEG(0x0001180068000000ull) + \
	484	+ ((index & 1) * 0x1000000ull))
	485	+static void __init dwc3_octeon_phy_reset(u64 base)
	486	+{
	487	+ union cvm_usbdrd_uctl_ctl uctl_ctl;
	488	+ int index = (base >> 24) & 1;
	489	+
	490	+ uctl_ctl.u64 = cvmx_read_csr(CVMX_USBDRDX_UCTL_CTL(index));
	491	+ uctl_ctl.s.uphy_rst = 0;
	492	+ cvmx_write_csr(CVMX_USBDRDX_UCTL_CTL(index), uctl_ctl.u64);
	493	+}
	494	+
	495	+static int __init dwc3_octeon_device_init(void)
	496	+{
	497	+ const char compat_node_name[] = "cavium,octeon-7130-usb-uctl";
	498	+ struct platform_device *pdev;
	499	+ struct device_node *node;
	500	+ struct resource *res;
	501	+ void __iomem *base;
	502	+
	503	+ /*
	504	+ * There should only be three universal controllers, "uctl"
	505	+ * in the device tree. Two USB and a SATA, which we ignore.
	506	+ */
	507	+ node = NULL;
	508	+ do {
	509	+ node = of_find_node_by_name(node, "uctl");
	510	+ if (!node)
	511	+ return -ENODEV;
	512	+
	513	+ if (of_device_is_compatible(node, compat_node_name)) {
	514	+ pdev = of_find_device_by_node(node);
	515	+ if (!pdev)
	516	+ return -ENODEV;
	517	+
	518	+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	519	+ if (res == NULL) {
	520	+ dev_err(&pdev->dev, "No memory resources\n");
	521	+ return -ENXIO;
	522	+ }
	523	+
	524	+ /*
	525	+ * The code below maps in the registers necessary for
	526	+ * setting up the clocks and reseting PHYs. We must
	527	+ * release the resources so the dwc3 subsystem doesn't
	528	+ * know the difference.
	529	+ */
	530	+ base = devm_ioremap_resource(&pdev->dev, res);
	531	+ if (IS_ERR(base))
	532	+ return PTR_ERR(base);
	533	+
	534	+ mutex_lock(&dwc3_octeon_clocks_mutex);
	535	+ dwc3_octeon_clocks_start(&pdev->dev, (u64)base);
	536	+ dwc3_octeon_set_endian_mode((u64)base);
	537	+ dwc3_octeon_phy_reset((u64)base);
	538	+ dev_info(&pdev->dev, "clocks initialized.\n");
	539	+ mutex_unlock(&dwc3_octeon_clocks_mutex);
	540	+ devm_iounmap(&pdev->dev, base);
	541	+ devm_release_mem_region(&pdev->dev, res->start,
	542	+ resource_size(res));
	543	+ }
	544	+ } while (node != NULL);
	545	+
	546	+ return 0;
	547	+}
	548	+device_initcall(dwc3_octeon_device_init);
	549	+
	550	+MODULE_AUTHOR("David Daney <david.daney@cavium.com>");
	551	+MODULE_LICENSE("GPL");
	552	+MODULE_DESCRIPTION("USB driver for OCTEON III SoC");

arch/mips/cavium-octeon/setup.c+23−0

@@ -949,6 +949,29 @@ static __init void memory_exclude_page(u64 addr, u64 mem, u64 size) · 948 unmodified lines
949	949	}
950	950	#endif /* CONFIG_CRASH_DUMP */
951	951
	952	+void __init fw_init_cmdline(void)
	953	+{
	954	+ int i;
	955	+
	956	+ octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3;
	957	+ for (i = 0; i < octeon_boot_desc_ptr->argc; i++) {
	958	+ const char *arg =
	959	+ cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]);
	960	+ if (strlen(arcs_cmdline) + strlen(arg) + 1 <
	961	+ sizeof(arcs_cmdline) - 1) {
	962	+ strcat(arcs_cmdline, " ");
	963	+ strcat(arcs_cmdline, arg);
	964	+ }
	965	+ }
	966	+}
	967	+
	968	+void __init *plat_get_fdt(void)
	969	+{
	970	+ octeon_bootinfo =
	971	+ cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr);
	972	+ return phys_to_virt(octeon_bootinfo->fdt_addr);
	973	+}
	974	+
952	975	void __init plat_mem_setup(void)
953	976	{
954	977	uint64_t mem_alloc_size;

arch/mips/cavium-octeon/smp.c+20−4

@@ -11,7 +11,8 @@ · 10 unmodified lines
11	11	#include <linux/interrupt.h>
12	12	#include <linux/kernel_stat.h>
13	13	#include <linux/sched.h>
14		−#include <linux/module.h>
	14	+#include <linux/init.h>
	15	+#include <linux/export.h>
15	16
16	17	#include <asm/mmu_context.h>
17	18	#include <asm/time.h>
@@ -24,12 +25,17 @@ · 6 unmodified lines
24	25	volatile unsigned long octeon_processor_boot = 0xff;
25	26	volatile unsigned long octeon_processor_sp;
26	27	volatile unsigned long octeon_processor_gp;
	28	+#ifdef CONFIG_RELOCATABLE
	29	+volatile unsigned long octeon_processor_relocated_kernel_entry;
	30	+#endif /* CONFIG_RELOCATABLE */
27	31
28	32	#ifdef CONFIG_HOTPLUG_CPU
29	33	uint64_t octeon_bootloader_entry_addr;
30	34	EXPORT_SYMBOL(octeon_bootloader_entry_addr);
31	35	#endif
32	36
	37	+extern void kernel_entry(unsigned long arg1, ...);
	38	+
33	39	static void octeon_icache_flush(void)
34	40	{
35	41	asm volatile ("synci 0($0)\n");
@@ -180,6 +186,19 @@ static void __init octeon_smp_setup(void) · 144 unmodified lines
180	186	octeon_smp_hotplug_setup();
181	187	}
182	188
	189	+
	190	+#ifdef CONFIG_RELOCATABLE
	191	+int plat_post_relocation(long offset)
	192	+{
	193	+ unsigned long entry = (unsigned long)kernel_entry;
	194	+
	195	+ /* Send secondaries into relocated kernel */
	196	+ octeon_processor_relocated_kernel_entry = entry + offset;
	197	+
	198	+ return 0;
	199	+}
	200	+#endif /* CONFIG_RELOCATABLE */
	201	+
183	202	/**
184	203	* Firmware CPU startup hook
185	204	*
@@ -272,7 +291,6 @@ static int octeon_cpu_disable(void) · 86 unmodified lines
272	291
273	292	set_cpu_online(cpu, false);
274	293	calculate_cpu_foreign_map();
275		− cpumask_clear_cpu(cpu, &cpu_callin_map);
276	294	octeon_fixup_irqs();
277	295
278	296	__flush_cache_all();
@@ -333,8 +351,6 @@ void play_dead(void) · 54 unmodified lines
333	351	;
334	352	}
335	353
336		−extern void kernel_entry(unsigned long arg1, ...);
337		−
338	354	static void start_after_reset(void)
339	355	{
340	356	kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */

arch/mips/configs/cavium_octeon_defconfig+1−0

@@ -45,6 +45,7 @@ CONFIG_SYN_COOKIES=y · 44 unmodified lines
45	45	# CONFIG_INET_LRO is not set
46	46	CONFIG_IPV6=y
47	47	CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
	48	+CONFIG_DEVTMPFS=y
48	49	# CONFIG_FW_LOADER is not set
49	50	CONFIG_MTD=y
50	51	# CONFIG_MTD_OF_PARTS is not set

arch/mips/configs/ip22_defconfig+2−2

@@ -67,8 +67,8 @@ CONFIG_NETFILTER_NETLINK_QUEUE=m · 66 unmodified lines
67	67	CONFIG_NF_CONNTRACK=m
68	68	CONFIG_NF_CONNTRACK_SECMARK=y
69	69	CONFIG_NF_CONNTRACK_EVENTS=y
70		−CONFIG_NF_CT_PROTO_DCCP=m
71		−CONFIG_NF_CT_PROTO_UDPLITE=m
	70	+CONFIG_NF_CT_PROTO_DCCP=y
	71	+CONFIG_NF_CT_PROTO_UDPLITE=y
72	72	CONFIG_NF_CONNTRACK_AMANDA=m
73	73	CONFIG_NF_CONNTRACK_FTP=m
74	74	CONFIG_NF_CONNTRACK_H323=m

arch/mips/configs/ip27_defconfig+1−2

@@ -133,7 +133,7 @@ CONFIG_LIBFC=m · 132 unmodified lines
133	133	CONFIG_SCSI_QLOGIC_1280=y
134	134	CONFIG_SCSI_PMCRAID=m
135	135	CONFIG_SCSI_BFA_FC=m
136		−CONFIG_SCSI_DH=m
	136	+CONFIG_SCSI_DH=y
137	137	CONFIG_SCSI_DH_RDAC=m
138	138	CONFIG_SCSI_DH_HP_SW=m
139	139	CONFIG_SCSI_DH_EMC=m
@@ -205,7 +205,6 @@ CONFIG_MLX4_EN=m · 65 unmodified lines
205	205	# CONFIG_MLX4_DEBUG is not set
206	206	CONFIG_TEHUTI=m
207	207	CONFIG_BNX2X=m
208		−CONFIG_QLGE=m
209	208	CONFIG_SFC=m
210	209	CONFIG_BE2NET=m
211	210	CONFIG_LIBERTAS_THINFIRM=m

arch/mips/configs/lemote2f_defconfig+1−1

@@ -39,7 +39,7 @@ CONFIG_HIBERNATION=y · 38 unmodified lines
39	39	CONFIG_PM_STD_PARTITION="/dev/hda3"
40	40	CONFIG_CPU_FREQ=y
41	41	CONFIG_CPU_FREQ_DEBUG=y
42		−CONFIG_CPU_FREQ_STAT=m
	42	+CONFIG_CPU_FREQ_STAT=y
43	43	CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
44	44	CONFIG_CPU_FREQ_GOV_POWERSAVE=m
45	45	CONFIG_CPU_FREQ_GOV_USERSPACE=m

arch/mips/configs/loongson1b_defconfig+4−0

@@ -74,6 +74,10 @@ CONFIG_SERIAL_8250_CONSOLE=y · 73 unmodified lines
74	74	CONFIG_GPIOLIB=y
75	75	CONFIG_GPIO_LOONGSON1=y
76	76	# CONFIG_HWMON is not set
	77	+CONFIG_WATCHDOG=y
	78	+CONFIG_WATCHDOG_NOWAYOUT=y
	79	+CONFIG_WATCHDOG_SYSFS=y
	80	+CONFIG_LOONGSON1_WDT=y
77	81	# CONFIG_VGA_CONSOLE is not set
78	82	CONFIG_HID_GENERIC=m
79	83	CONFIG_USB_HID=m

arch/mips/configs/loongson1c_defconfig+4−0

@@ -75,6 +75,10 @@ CONFIG_SERIAL_8250_CONSOLE=y · 74 unmodified lines
75	75	CONFIG_GPIOLIB=y
76	76	CONFIG_GPIO_LOONGSON1=y
77	77	# CONFIG_HWMON is not set
	78	+CONFIG_WATCHDOG=y
	79	+CONFIG_WATCHDOG_NOWAYOUT=y
	80	+CONFIG_WATCHDOG_SYSFS=y
	81	+CONFIG_LOONGSON1_WDT=y
78	82	# CONFIG_VGA_CONSOLE is not set
79	83	CONFIG_HID_GENERIC=m
80	84	CONFIG_USB_HID=m

arch/mips/configs/malta_defconfig+2−2

@@ -59,8 +59,8 @@ CONFIG_NETFILTER=y · 58 unmodified lines
59	59	CONFIG_NF_CONNTRACK=m
60	60	CONFIG_NF_CONNTRACK_SECMARK=y
61	61	CONFIG_NF_CONNTRACK_EVENTS=y
62		−CONFIG_NF_CT_PROTO_DCCP=m
63		−CONFIG_NF_CT_PROTO_UDPLITE=m
	62	+CONFIG_NF_CT_PROTO_DCCP=y
	63	+CONFIG_NF_CT_PROTO_UDPLITE=y
64	64	CONFIG_NF_CONNTRACK_AMANDA=m
65	65	CONFIG_NF_CONNTRACK_FTP=m
66	66	CONFIG_NF_CONNTRACK_H323=m

arch/mips/configs/malta_kvm_defconfig+2−2

@@ -60,8 +60,8 @@ CONFIG_NETFILTER=y · 59 unmodified lines
60	60	CONFIG_NF_CONNTRACK=m
61	61	CONFIG_NF_CONNTRACK_SECMARK=y
62	62	CONFIG_NF_CONNTRACK_EVENTS=y
63		−CONFIG_NF_CT_PROTO_DCCP=m
64		−CONFIG_NF_CT_PROTO_UDPLITE=m
	63	+CONFIG_NF_CT_PROTO_DCCP=y
	64	+CONFIG_NF_CT_PROTO_UDPLITE=y
65	65	CONFIG_NF_CONNTRACK_AMANDA=m
66	66	CONFIG_NF_CONNTRACK_FTP=m
67	67	CONFIG_NF_CONNTRACK_H323=m

arch/mips/configs/malta_kvm_guest_defconfig+2−2

@@ -59,8 +59,8 @@ CONFIG_NETFILTER=y · 58 unmodified lines
59	59	CONFIG_NF_CONNTRACK=m
60	60	CONFIG_NF_CONNTRACK_SECMARK=y
61	61	CONFIG_NF_CONNTRACK_EVENTS=y
62		−CONFIG_NF_CT_PROTO_DCCP=m
63		−CONFIG_NF_CT_PROTO_UDPLITE=m
	62	+CONFIG_NF_CT_PROTO_DCCP=y
	63	+CONFIG_NF_CT_PROTO_UDPLITE=y
64	64	CONFIG_NF_CONNTRACK_AMANDA=m
65	65	CONFIG_NF_CONNTRACK_FTP=m
66	66	CONFIG_NF_CONNTRACK_H323=m

arch/mips/configs/maltaup_xpa_defconfig+2−2

@@ -61,8 +61,8 @@ CONFIG_NETFILTER=y · 60 unmodified lines
61	61	CONFIG_NF_CONNTRACK=m
62	62	CONFIG_NF_CONNTRACK_SECMARK=y
63	63	CONFIG_NF_CONNTRACK_EVENTS=y
64		−CONFIG_NF_CT_PROTO_DCCP=m
65		−CONFIG_NF_CT_PROTO_UDPLITE=m
	64	+CONFIG_NF_CT_PROTO_DCCP=y
	65	+CONFIG_NF_CT_PROTO_UDPLITE=y
66	66	CONFIG_NF_CONNTRACK_AMANDA=m
67	67	CONFIG_NF_CONNTRACK_FTP=m
68	68	CONFIG_NF_CONNTRACK_H323=m

arch/mips/configs/nlm_xlp_defconfig+1−1

@@ -110,7 +110,7 @@ CONFIG_NETFILTER=y · 109 unmodified lines
110	110	CONFIG_NF_CONNTRACK=m
111	111	CONFIG_NF_CONNTRACK_SECMARK=y
112	112	CONFIG_NF_CONNTRACK_EVENTS=y
113		−CONFIG_NF_CT_PROTO_UDPLITE=m
	113	+CONFIG_NF_CT_PROTO_UDPLITE=y
114	114	CONFIG_NF_CONNTRACK_AMANDA=m
115	115	CONFIG_NF_CONNTRACK_FTP=m
116	116	CONFIG_NF_CONNTRACK_H323=m

arch/mips/configs/nlm_xlr_defconfig+1−1

@@ -90,7 +90,7 @@ CONFIG_NETFILTER=y · 89 unmodified lines
90	90	CONFIG_NF_CONNTRACK=m
91	91	CONFIG_NF_CONNTRACK_SECMARK=y
92	92	CONFIG_NF_CONNTRACK_EVENTS=y
93		−CONFIG_NF_CT_PROTO_UDPLITE=m
	93	+CONFIG_NF_CT_PROTO_UDPLITE=y
94	94	CONFIG_NF_CONNTRACK_AMANDA=m
95	95	CONFIG_NF_CONNTRACK_FTP=m
96	96	CONFIG_NF_CONNTRACK_H323=m

arch/mips/configs/xilfpga_defconfig+36−1

@@ -7,6 +7,12 @@ CONFIG_EMBEDDED=y · 6 unmodified lines
7	7	CONFIG_SLAB=y
8	8	# CONFIG_BLOCK is not set
9	9	# CONFIG_SUSPEND is not set
	10	+CONFIG_NET=y
	11	+CONFIG_PACKET=y
	12	+CONFIG_UNIX=y
	13	+CONFIG_INET=y
	14	+# CONFIG_IPV6 is not set
	15	+# CONFIG_WIRELESS is not set
10	16	# CONFIG_UEVENT_HELPER is not set
11	17	CONFIG_DEVTMPFS=y
12	18	CONFIG_DEVTMPFS_MOUNT=y
@@ -14,6 +20,30 @@ CONFIG_DEVTMPFS_MOUNT=y · 1 unmodified line
14	20	# CONFIG_PREVENT_FIRMWARE_BUILD is not set
15	21	# CONFIG_FW_LOADER is not set
16	22	# CONFIG_ALLOW_DEV_COREDUMP is not set
	23	+CONFIG_NETDEVICES=y
	24	+# CONFIG_NET_CORE is not set
	25	+# CONFIG_NET_VENDOR_ARC is not set
	26	+# CONFIG_NET_CADENCE is not set
	27	+# CONFIG_NET_VENDOR_BROADCOM is not set
	28	+# CONFIG_NET_VENDOR_EZCHIP is not set
	29	+# CONFIG_NET_VENDOR_INTEL is not set
	30	+# CONFIG_NET_VENDOR_MARVELL is not set
	31	+# CONFIG_NET_VENDOR_MICREL is not set
	32	+# CONFIG_NET_VENDOR_NATSEMI is not set
	33	+# CONFIG_NET_VENDOR_NETRONOME is not set
	34	+# CONFIG_NET_VENDOR_QUALCOMM is not set
	35	+# CONFIG_NET_VENDOR_RENESAS is not set
	36	+# CONFIG_NET_VENDOR_ROCKER is not set
	37	+# CONFIG_NET_VENDOR_SAMSUNG is not set
	38	+# CONFIG_NET_VENDOR_SEEQ is not set
	39	+# CONFIG_NET_VENDOR_SMSC is not set
	40	+# CONFIG_NET_VENDOR_STMICRO is not set
	41	+# CONFIG_NET_VENDOR_SYNOPSYS is not set
	42	+# CONFIG_NET_VENDOR_VIA is not set
	43	+# CONFIG_NET_VENDOR_WIZNET is not set
	44	+CONFIG_XILINX_EMACLITE=y
	45	+CONFIG_SMSC_PHY=y
	46	+# CONFIG_WLAN is not set
17	47	# CONFIG_INPUT_MOUSEDEV is not set
18	48	# CONFIG_INPUT_KEYBOARD is not set
19	49	# CONFIG_INPUT_MOUSE is not set
@@ -25,13 +55,18 @@ CONFIG_SERIAL_8250=y · 5 unmodified lines
25	55	CONFIG_SERIAL_8250_CONSOLE=y
26	56	CONFIG_SERIAL_OF_PLATFORM=y
27	57	# CONFIG_HW_RANDOM is not set
	58	+CONFIG_I2C=y
	59	+CONFIG_I2C_CHARDEV=y
	60	+# CONFIG_I2C_HELPER_AUTO is not set
	61	+CONFIG_I2C_XILINX=y
28	62	CONFIG_GPIO_SYSFS=y
29	63	CONFIG_GPIO_XILINX=y
30		−# CONFIG_HWMON is not set
	64	+CONFIG_SENSORS_ADT7410=y
31	65	# CONFIG_USB_SUPPORT is not set
32	66	# CONFIG_MIPS_PLATFORM_DEVICES is not set
33	67	# CONFIG_IOMMU_SUPPORT is not set
34	68	# CONFIG_PROC_PAGE_MONITOR is not set
	69	+CONFIG_TMPFS=y
35	70	# CONFIG_MISC_FILESYSTEMS is not set
36	71	CONFIG_PANIC_ON_OOPS=y
37	72	# CONFIG_SCHED_DEBUG is not set

arch/mips/configs/xway_defconfig+13−8

@@ -1,12 +1,16 @@
1	1	CONFIG_LANTIQ=y
	2	+CONFIG_PCI_LANTIQ=y
2	3	CONFIG_XRX200_PHY_FW=y
3	4	CONFIG_CPU_MIPS32_R2=y
	5	+CONFIG_MIPS_MT_SMP=y
	6	+CONFIG_MIPS_VPE_LOADER=y
4	7	# CONFIG_COMPACTION is not set
5		−# CONFIG_CROSS_MEMORY_ATTACH is not set
	8	+CONFIG_NR_CPUS=2
6	9	CONFIG_HZ_100=y
7	10	# CONFIG_SECCOMP is not set
8	11	# CONFIG_LOCALVERSION_AUTO is not set
9	12	CONFIG_SYSVIPC=y
	13	+# CONFIG_CROSS_MEMORY_ATTACH is not set
10	14	CONFIG_HIGH_RES_TIMERS=y
11	15	CONFIG_BLK_DEV_INITRD=y
12	16	# CONFIG_RD_GZIP is not set
@@ -22,8 +26,8 @@ CONFIG_MODULE_UNLOAD=y · 9 unmodified lines
22	26	# CONFIG_BLK_DEV_BSG is not set
23	27	CONFIG_PARTITION_ADVANCED=y
24	28	# CONFIG_IOSCHED_CFQ is not set
	29	+CONFIG_PCI=y
25	30	# CONFIG_COREDUMP is not set
26		−# CONFIG_SUSPEND is not set
27	31	CONFIG_NET=y
28	32	CONFIG_PACKET=y
29	33	CONFIG_UNIX=y
@@ -35,12 +39,10 @@ CONFIG_IP_ROUTE_MULTIPATH=y · 5 unmodified lines
35	39	CONFIG_IP_ROUTE_VERBOSE=y
36	40	CONFIG_IP_MROUTE=y
37	41	CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
38		−CONFIG_ARPD=y
39	42	CONFIG_SYN_COOKIES=y
40	43	# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
41	44	# CONFIG_INET_XFRM_MODE_TUNNEL is not set
42	45	# CONFIG_INET_XFRM_MODE_BEET is not set
43		−# CONFIG_INET_LRO is not set
44	46	# CONFIG_INET_DIAG is not set
45	47	CONFIG_TCP_CONG_ADVANCED=y
46	48	# CONFIG_TCP_CONG_BIC is not set
@@ -62,7 +64,6 @@ CONFIG_NETFILTER_XT_MATCH_MAC=m · 15 unmodified lines
62	64	CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
63	65	CONFIG_NETFILTER_XT_MATCH_STATE=m
64	66	CONFIG_NF_CONNTRACK_IPV4=m
65		−# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
66	67	CONFIG_IP_NF_IPTABLES=m
67	68	CONFIG_IP_NF_FILTER=m
68	69	CONFIG_IP_NF_TARGET_REJECT=m
@@ -84,6 +85,8 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y · 15 unmodified lines
84	85	CONFIG_MTD_PHYSMAP=y
85	86	CONFIG_MTD_PHYSMAP_OF=y
86	87	CONFIG_MTD_LANTIQ=y
	88	+CONFIG_MTD_NAND=y
	89	+CONFIG_MTD_NAND_XWAY=y
87	90	CONFIG_EEPROM_93CX6=m
88	91	CONFIG_SCSI=y
89	92	CONFIG_BLK_DEV_SD=y
@@ -91,6 +94,7 @@ CONFIG_NETDEVICES=y · 1 unmodified line
91	94	CONFIG_LANTIQ_ETOP=y
92	95	# CONFIG_NET_VENDOR_WIZNET is not set
93	96	CONFIG_PHYLIB=y
	97	+CONFIG_INTEL_XWAY_PHY=y
94	98	CONFIG_PPP=m
95	99	CONFIG_PPP_FILTER=y
96	100	CONFIG_PPP_MULTILINK=y
@@ -111,17 +115,21 @@ CONFIG_SERIAL_8250=y · 14 unmodified lines
111	115	CONFIG_SERIAL_8250_CONSOLE=y
112	116	CONFIG_SERIAL_8250_RUNTIME_UARTS=2
113	117	CONFIG_SERIAL_OF_PLATFORM=y
	118	+CONFIG_SERIAL_LANTIQ=y
114	119	CONFIG_SPI=y
115	120	CONFIG_GPIO_MM_LANTIQ=y
116	121	CONFIG_GPIO_STP_XWAY=y
117	122	# CONFIG_HWMON is not set
118	123	CONFIG_WATCHDOG=y
	124	+CONFIG_LANTIQ_WDT=y
119	125	# CONFIG_HID is not set
120	126	# CONFIG_USB_HID is not set
121	127	CONFIG_USB=y
122	128	CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
123	129	CONFIG_USB_STORAGE=y
124	130	CONFIG_USB_STORAGE_DEBUG=y
	131	+CONFIG_USB_DWC2=y
	132	+CONFIG_USB_DWC2_PCI=y
125	133	CONFIG_NEW_LEDS=y
126	134	CONFIG_LEDS_CLASS=y
127	135	CONFIG_LEDS_TRIGGERS=y
@@ -151,9 +159,6 @@ CONFIG_MAGIC_SYSRQ=y · 23 unmodified lines
151	159	# CONFIG_SCHED_DEBUG is not set
152	160	# CONFIG_FTRACE is not set
153	161	CONFIG_CMDLINE_BOOL=y
154		−CONFIG_CRYPTO_MANAGER=m
155	162	CONFIG_CRYPTO_ARC4=m
156		−# CONFIG_CRYPTO_ANSI_CPRNG is not set
157	163	CONFIG_CRC_ITU_T=m
158	164	CONFIG_CRC32_SARWATE=y
159		−CONFIG_AVERAGE=y

arch/mips/dec/prom/identify.c+1−1

@@ -7,7 +7,7 @@ · 6 unmodified lines
7	7	#include <linux/init.h>
8	8	#include <linux/kernel.h>
9	9	#include <linux/mc146818rtc.h>
10		−#include <linux/module.h>
	10	+#include <linux/export.h>
11	11	#include <linux/string.h>
12	12	#include <linux/types.h>
13	13

arch/mips/dec/setup.c+1−1

@@ -9,12 +9,12 @@ · 8 unmodified lines
9	9	* Copyright (C) 2000, 2001, 2002, 2003, 2005 Maciej W. Rozycki
10	10	*/
11	11	#include <linux/console.h>
	12	+#include <linux/export.h>
12	13	#include <linux/init.h>
13	14	#include <linux/interrupt.h>
14	15	#include <linux/ioport.h>
15	16	#include <linux/irq.h>
16	17	#include <linux/irqnr.h>
17		−#include <linux/module.h>
18	18	#include <linux/param.h>
19	19	#include <linux/percpu-defs.h>
20	20	#include <linux/sched.h>

arch/mips/dec/wbflush.c+1−3

@@ -14,6 +14,7 @@ · 13 unmodified lines
14	14	* Copyright (C) 2002 Maciej W. Rozycki
15	15	*/
16	16
	17	+#include <linux/export.h>
17	18	#include <linux/init.h>
18	19
19	20	#include <asm/bootinfo.h>
@@ -88,7 +89,4 @@ static void wbflush_mips(void) · 68 unmodified lines
88	89	{
89	90	__fast_iob();
90	91	}
91		−
92		−#include <linux/module.h>
93		−
94	92	EXPORT_SYMBOL(__wbflush);

arch/mips/emma/markeins/setup.c+1−1

@@ -90,7 +90,7 @@ void __init plat_time_init(void) · 89 unmodified lines
90	90	static void markeins_board_init(void);
91	91	extern void markeins_irq_setup(void);
92	92
93		−static void inline __init markeins_sio_setup(void)
	93	+static inline void __init markeins_sio_setup(void)
94	94	{
95	95	}
96	96

arch/mips/generic/Makefile+1−0

@@ -13,3 +13,4 @@ obj-y += irq.o · 12 unmodified lines
13	13	obj-y += proc.o
14	14
15	15	obj-$(CONFIG_LEGACY_BOARD_SEAD3) += board-sead3.o
	16	+obj-$(CONFIG_KEXEC) += kexec.o

arch/mips/generic/init.c+13−0

@@ -88,6 +88,19 @@ void __init *plat_get_fdt(void) · 87 unmodified lines
88	88	return (void *)fdt;
89	89	}
90	90
	91	+void __init plat_fdt_relocated(void *new_location)
	92	+{
	93	+ /*
	94	+ * reset fdt as the cached value would point to the location
	95	+ * before relocations happened and update the location argument
	96	+ * if it was passed using UHI
	97	+ */
	98	+ fdt = NULL;
	99	+
	100	+ if (fw_arg0 == -2)
	101	+ fw_arg1 = (unsigned long)new_location;
	102	+}
	103	+
91	104	void __init plat_mem_setup(void)
92	105	{
93	106	if (mach && mach->fixup_fdt)

arch/mips/generic/kexec.c+44−0

@@ -0,0 +1,44 @@
	1	+/*
	2	+ * Copyright (C) 2016 Imagination Technologies
	3	+ * Author: Marcin Nowakowski <marcin.nowakowski@imgtec.com>
	4	+ *
	5	+ * This program is free software; you can redistribute it and/or modify it
	6	+ * under the terms of the GNU General Public License as published by the
	7	+ * Free Software Foundation; either version 2 of the License, or (at your
	8	+ * option) any later version.
	9	+ */
	10	+
	11	+#include <linux/kexec.h>
	12	+#include <linux/libfdt.h>
	13	+#include <linux/uaccess.h>
	14	+
	15	+static int generic_kexec_prepare(struct kimage *image)
	16	+{
	17	+ int i;
	18	+
	19	+ for (i = 0; i < image->nr_segments; i++) {
	20	+ struct fdt_header fdt;
	21	+
	22	+ if (image->segment[i].memsz <= sizeof(fdt))
	23	+ continue;
	24	+
	25	+ if (copy_from_user(&fdt, image->segment[i].buf, sizeof(fdt)))
	26	+ continue;
	27	+
	28	+ if (fdt_check_header(&fdt))
	29	+ continue;
	30	+
	31	+ kexec_args[0] = -2;
	32	+ kexec_args[1] = (unsigned long)
	33	+ phys_to_virt((unsigned long)image->segment[i].mem);
	34	+ break;
	35	+ }
	36	+ return 0;
	37	+}
	38	+
	39	+static int __init register_generic_kexec(void)
	40	+{
	41	+ _machine_kexec_prepare = generic_kexec_prepare;
	42	+ return 0;
	43	+}
	44	+arch_initcall(register_generic_kexec);

arch/mips/include/asm/Kbuild+2−0

@@ -4,6 +4,7 @@ generic-y += clkdev.h · 3 unmodified lines
4	4	generic-y += current.h
5	5	generic-y += dma-contiguous.h
6	6	generic-y += emergency-restart.h
	7	+generic-y += export.h
7	8	generic-y += irq_work.h
8	9	generic-y += local64.h
9	10	generic-y += mcs_spinlock.h
@@ -15,6 +16,7 @@ generic-y += sections.h · 5 unmodified lines
15	16	generic-y += segment.h
16	17	generic-y += serial.h
17	18	generic-y += trace_clock.h
	19	+generic-y += unaligned.h
18	20	generic-y += user.h
19	21	generic-y += word-at-a-time.h
20	22	generic-y += xor.h

arch/mips/include/asm/asm-prototypes.h+5−0

@@ -0,0 +1,5 @@
	1	+#include <asm/checksum.h>
	2	+#include <asm/page.h>
	3	+#include <asm/fpu.h>
	4	+#include <asm-generic/asm-prototypes.h>
	5	+#include <asm/uaccess.h>

arch/mips/include/asm/asm.h+6−4

@@ -54,7 +54,8 @@ · 53 unmodified lines
54	54	.align 2; \
55	55	.type symbol, @function; \
56	56	.ent symbol, 0; \
57		−symbol: .frame sp, 0, ra
	57	+symbol: .frame sp, 0, ra; \
	58	+ .insn
58	59
59	60	/*
60	61	* NESTED - declare nested routine entry point
@@ -63,8 +64,9 @@ symbol: .frame sp, 0, ra · 2 unmodified lines
63	64	.globl symbol; \
64	65	.align 2; \
65	66	.type symbol, @function; \
66		− .ent symbol, 0; \
67		−symbol: .frame sp, framesize, rpc
	67	+ .ent symbol, 0; \
	68	+symbol: .frame sp, framesize, rpc; \
	69	+ .insn
68	70
69	71	/*
70	72	* END - mark end of function
@@ -86,7 +88,7 @@ symbol: · 15 unmodified lines
86	88	#define FEXPORT(symbol) \
87	89	.globl symbol; \
88	90	.type symbol, @function; \
89		−symbol:
	91	+symbol: .insn
90	92
91	93	/*
92	94	* ABS - export absolute symbol

arch/mips/include/asm/bootinfo.h+13−0

@@ -164,6 +164,19 @@ static inline void plat_swiotlb_setup(void) {} · 163 unmodified lines
164	164	* Return: Pointer to the flattened device tree blob.
165	165	*/
166	166	extern void *plat_get_fdt(void);
	167	+
	168	+#ifdef CONFIG_RELOCATABLE
	169	+
	170	+/**
	171	+ * plat_fdt_relocated() - Update platform's information about relocated dtb
	172	+ *
	173	+ * This function provides a platform-independent API to set platform's
	174	+ * information about relocated DTB if it needs to be moved due to kernel
	175	+ * relocation occurring at boot.
	176	+ */
	177	+void plat_fdt_relocated(void *new_location);
	178	+
	179	+#endif /* CONFIG_RELOCATABLE */
167	180	#endif /* CONFIG_USE_OF */
168	181
169	182	#endif /* _ASM_BOOTINFO_H */

arch/mips/include/asm/checksum.h+2−0

@@ -186,7 +186,9 @@ static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr, · 185 unmodified lines
186	186	" daddu %0, %4 \n"
187	187	" dsll32 $1, %0, 0 \n"
188	188	" daddu %0, $1 \n"
	189	+ " sltu $1, %0, $1 \n"
189	190	" dsra32 %0, %0, 0 \n"
	191	+ " addu %0, $1 \n"
190	192	#endif
191	193	" .set pop"
192	194	: "=r" (sum)

arch/mips/include/asm/elf.h+9−0

@@ -210,6 +210,9 @@ typedef elf_greg_t elf_gregset_t[ELF_NGREG]; · 209 unmodified lines
210	210	typedef double elf_fpreg_t;
211	211	typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
212	212
	213	+void mips_dump_regs32(u32 uregs, const struct pt_regs regs);
	214	+void mips_dump_regs64(u64 uregs, const struct pt_regs regs);
	215	+
213	216	#ifdef CONFIG_32BIT
214	217	/*
215	218	* This is used to ensure we don't load something for the wrong architecture.
@@ -221,6 +224,9 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; · 5 unmodified lines
221	224	*/
222	225	#define ELF_CLASS ELFCLASS32
223	226
	227	+#define ELF_CORE_COPY_REGS(dest, regs) \
	228	+ mips_dump_regs32((u32 *)&(dest), (regs));
	229	+
224	230	#endif /* CONFIG_32BIT */
225	231
226	232	#ifdef CONFIG_64BIT
@@ -234,6 +240,9 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; · 7 unmodified lines
234	240	*/
235	241	#define ELF_CLASS ELFCLASS64
236	242
	243	+#define ELF_CORE_COPY_REGS(dest, regs) \
	244	+ mips_dump_regs64((u64 *)&(dest), (regs));
	245	+
237	246	#endif /* CONFIG_64BIT */
238	247
239	248	/*

arch/mips/include/asm/highmem.h+0−3

@@ -25,9 +25,6 @@ · 24 unmodified lines
25	25	#include <asm/cpu-features.h>
26	26	#include <asm/kmap_types.h>
27	27
28		−/* undef for production */
29		−#define HIGHMEM_DEBUG 1
30		−
31	28	/* declarations for highmem.c */
32	29	extern unsigned long highstart_pfn, highend_pfn;
33	30

arch/mips/include/asm/i8259.h+0−1

@@ -40,7 +40,6 @@ extern raw_spinlock_t i8259A_lock; · 39 unmodified lines
40	40	extern void make_8259A_irq(unsigned int irq);
41	41
42	42	extern void init_i8259_irqs(void);
43		−extern int i8259_of_init(struct device_node node, struct device_node parent);
44	43
45	44	/**
46	45	* i8159_set_poll() - Override the i8259 polling function

arch/mips/include/asm/irq.h+12−0

@@ -17,6 +17,18 @@ · 16 unmodified lines
17	17
18	18	#include <irq.h>
19	19
	20	+#define IRQ_STACK_SIZE THREAD_SIZE
	21	+
	22	+extern void *irq_stack[NR_CPUS];
	23	+
	24	+static inline bool on_irq_stack(int cpu, unsigned long sp)
	25	+{
	26	+ unsigned long low = (unsigned long)irq_stack[cpu];
	27	+ unsigned long high = low + IRQ_STACK_SIZE;
	28	+
	29	+ return (low <= sp && sp <= high);
	30	+}
	31	+
20	32	#ifdef CONFIG_I8259
21	33	static inline int irq_canonicalize(int irq)
22	34	{

arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h+9−0

@@ -80,6 +80,15 @@ enum bcm47xx_board { · 79 unmodified lines
80	80	BCM47XX_BOARD_LINKSYS_WRT610NV2,
81	81	BCM47XX_BOARD_LINKSYS_WRTSL54GS,
82	82
	83	+ BCM47XX_BOARD_LUXUL_ABR_4400_V1,
	84	+ BCM47XX_BOARD_LUXUL_XAP_310_V1,
	85	+ BCM47XX_BOARD_LUXUL_XAP_1210_V1,
	86	+ BCM47XX_BOARD_LUXUL_XAP_1230_V1,
	87	+ BCM47XX_BOARD_LUXUL_XAP_1240_V1,
	88	+ BCM47XX_BOARD_LUXUL_XAP_1500_V1,
	89	+ BCM47XX_BOARD_LUXUL_XBR_4400_V1,
	90	+ BCM47XX_BOARD_LUXUL_XVW_P30_V1,
	91	+ BCM47XX_BOARD_LUXUL_XWR_600_V1,
83	92	BCM47XX_BOARD_LUXUL_XWR_1750_V1,
84	93
85	94	BCM47XX_BOARD_MICROSOFT_MN700,

arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h+13−2

@@ -99,9 +99,20 @@ · 98 unmodified lines
99	99	# to begin
100	100	#
101	101
102		− # This is the variable where the next core to boot os stored
103		− PTR_LA t0, octeon_processor_boot
104	102	octeon_spin_wait_boot:
	103	+#ifdef CONFIG_RELOCATABLE
	104	+ PTR_LA t0, octeon_processor_relocated_kernel_entry
	105	+ LONG_L t0, (t0)
	106	+ beq zero, t0, 1f
	107	+ nop
	108	+
	109	+ jr t0
	110	+ nop
	111	+1:
	112	+#endif /* CONFIG_RELOCATABLE */
	113	+
	114	+ # This is the variable where the next core to boot is stored
	115	+ PTR_LA t0, octeon_processor_boot
105	116	# Get the core id of the next to be booted
106	117	LONG_L t1, (t0)
107	118	# Keep looping if it isn't me

arch/mips/include/asm/mach-ip27/spaces.h+4−2

@@ -12,14 +12,16 @@ · 11 unmodified lines
12	12
13	13	/*
14	14	* IP27 uses the R10000's uncached attribute feature. Attribute 3 selects
15		− * uncached memory addressing.
	15	+ * uncached memory addressing. Hide the definitions on 32-bit compilation
	16	+ * of the compat-vdso code.
16	17	*/
17		−
	18	+#ifdef CONFIG_64BIT
18	19	#define HSPEC_BASE 0x9000000000000000
19	20	#define IO_BASE 0x9200000000000000
20	21	#define MSPEC_BASE 0x9400000000000000
21	22	#define UNCAC_BASE 0x9600000000000000
22	23	#define CAC_BASE 0xa800000000000000
	24	+#endif
23	25
24	26	#define TO_MSPEC(x) (MSPEC_BASE \| ((x) & TO_PHYS_MASK))
25	27	#define TO_HSPEC(x) (HSPEC_BASE \| ((x) & TO_PHYS_MASK))

arch/mips/include/asm/mach-loongson32/loongson1.h+5−4

@@ -3,9 +3,9 @@ · 2 unmodified lines
3	3	*
4	4	* Register mappings for Loongson 1
5	5	*
6		− * This program is free software; you can redistribute it and/or modify it
7		− * under the terms of the GNU General Public License as published by the
8		− * Free Software Foundation; either version 2 of the License, or (at your
	6	+ * This program is free software; you can redistribute it and/or modify it
	7	+ * under the terms of the GNU General Public License as published by the
	8	+ * Free Software Foundation; either version 2 of the License, or (at your
9	9	* option) any later version.
10	10	*/
11	11
@@ -13,7 +13,7 @@ · 1 unmodified line
13	13	#define __ASM_MACH_LOONGSON32_LOONGSON1_H
14	14
15	15	#if defined(CONFIG_LOONGSON1_LS1B)
16		−#define DEFAULT_MEMSIZE 256 /* If no memsize provided */
	16	+#define DEFAULT_MEMSIZE 64 /* If no memsize provided */
17	17	#elif defined(CONFIG_LOONGSON1_LS1C)
18	18	#define DEFAULT_MEMSIZE 32
19	19	#endif
@@ -52,6 +52,7 @@ · 32 unmodified lines
52	52	#include <regs-clk.h>
53	53	#include <regs-mux.h>
54	54	#include <regs-pwm.h>
	55	+#include <regs-rtc.h>
55	56	#include <regs-wdt.h>
56	57
57	58	#endif /* __ASM_MACH_LOONGSON32_LOONGSON1_H */

arch/mips/include/asm/mach-loongson32/platform.h+5−4

@@ -1,9 +1,9 @@
1	1	/*
2	2	* Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3	3	*
4		− * This program is free software; you can redistribute it and/or modify it
5		− * under the terms of the GNU General Public License as published by the
6		− * Free Software Foundation; either version 2 of the License, or (at your
	4	+ * This program is free software; you can redistribute it and/or modify it
	5	+ * under the terms of the GNU General Public License as published by the
	6	+ * Free Software Foundation; either version 2 of the License, or (at your
7	7	* option) any later version.
8	8	*/
9	9
@@ -25,11 +25,12 @@ extern struct platform_device ls1x_gpio0_pdev; · 15 unmodified lines
25	25	extern struct platform_device ls1x_gpio1_pdev;
26	26	extern struct platform_device ls1x_nand_pdev;
27	27	extern struct platform_device ls1x_rtc_pdev;
	28	+extern struct platform_device ls1x_wdt_pdev;
28	29
29	30	void __init ls1x_clk_init(void);
30	31	void __init ls1x_dma_set_platdata(struct plat_ls1x_dma *pdata);
31	32	void __init ls1x_nand_set_platdata(struct plat_ls1x_nand *pdata);
32		−void __init ls1x_serial_set_uartclk(struct platform_device *pdev);
33	33	void __init ls1x_rtc_set_extclk(struct platform_device *pdev);
	34	+void __init ls1x_serial_set_uartclk(struct platform_device *pdev);
34	35
35	36	#endif /* __ASM_MACH_LOONGSON32_PLATFORM_H */

arch/mips/include/asm/mach-loongson32/regs-rtc.h+23−0

@@ -0,0 +1,23 @@
	1	+/*
	2	+ * Copyright (c) 2016 Yang Ling <gnaygnil@gmail.com>
	3	+ *
	4	+ * Loongson 1 RTC timer Register Definitions.
	5	+ *
	6	+ * This program is free software; you can redistribute it and/or modify it
	7	+ * under the terms of the GNU General Public License as published by the
	8	+ * Free Software Foundation; either version 2 of the License, or (at your
	9	+ * option) any later version.
	10	+ */
	11	+
	12	+#ifndef __ASM_MACH_LOONGSON32_REGS_RTC_H
	13	+#define __ASM_MACH_LOONGSON32_REGS_RTC_H
	14	+
	15	+#define LS1X_RTC_REG(x) \
	16	+ ((void __iomem *)KSEG1ADDR(LS1X_RTC_BASE + (x)))
	17	+
	18	+#define LS1X_RTC_CTRL LS1X_RTC_REG(0x40)
	19	+
	20	+#define RTC_EXTCLK_OK (BIT(5) \| BIT(8))
	21	+#define RTC_EXTCLK_EN BIT(8)
	22	+
	23	+#endif /* __ASM_MACH_LOONGSON32_REGS_RTC_H */

arch/mips/include/asm/mach-ralink/mt7620.h+6−1

@@ -115,9 +115,14 @@ · 114 unmodified lines
115	115	#define MT7620_GPIO_MODE_WDT_MASK 0x3
116	116	#define MT7620_GPIO_MODE_WDT_SHIFT 21
117	117
	118	+#define MT7620_GPIO_MODE_MDIO 0
	119	+#define MT7620_GPIO_MODE_MDIO_REFCLK 1
	120	+#define MT7620_GPIO_MODE_MDIO_GPIO 2
	121	+#define MT7620_GPIO_MODE_MDIO_MASK 0x3
	122	+#define MT7620_GPIO_MODE_MDIO_SHIFT 7
	123	+
118	124	#define MT7620_GPIO_MODE_I2C 0
119	125	#define MT7620_GPIO_MODE_UART1 5
120		−#define MT7620_GPIO_MODE_MDIO 8
121	126	#define MT7620_GPIO_MODE_RGMII1 9
122	127	#define MT7620_GPIO_MODE_RGMII2 10
123	128	#define MT7620_GPIO_MODE_SPI 11

arch/mips/include/asm/mips-cm.h+7−0

@@ -187,6 +187,7 @@ BUILD_CM_R_(config, MIPS_CM_GCB_OFS + 0x00) · 186 unmodified lines
187	187	BUILD_CM_RW(base, MIPS_CM_GCB_OFS + 0x08)
188	188	BUILD_CM_RW(access, MIPS_CM_GCB_OFS + 0x20)
189	189	BUILD_CM_R_(rev, MIPS_CM_GCB_OFS + 0x30)
	190	+BUILD_CM_RW(err_control, MIPS_CM_GCB_OFS + 0x38)
190	191	BUILD_CM_RW(error_mask, MIPS_CM_GCB_OFS + 0x40)
191	192	BUILD_CM_RW(error_cause, MIPS_CM_GCB_OFS + 0x48)
192	193	BUILD_CM_RW(error_addr, MIPS_CM_GCB_OFS + 0x50)
@@ -266,6 +267,12 @@ BUILD_CM_Cx_R_(tcid_8_priority, 0x80) · 73 unmodified lines
266	267	#define CM_REV_CM2_5 CM_ENCODE_REV(7, 0)
267	268	#define CM_REV_CM3 CM_ENCODE_REV(8, 0)
268	269
	270	+/* GCR_ERR_CONTROL register fields */
	271	+#define CM_GCR_ERR_CONTROL_L2_ECC_EN_SHF 1
	272	+#define CM_GCR_ERR_CONTROL_L2_ECC_EN_MSK (_ULCAST_(0x1) << 1)
	273	+#define CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT_SHF 0
	274	+#define CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT_MSK (_ULCAST_(0x1) << 0)
	275	+
269	276	/* GCR_ERROR_CAUSE register fields */
270	277	#define CM_GCR_ERROR_CAUSE_ERRTYPE_SHF 27
271	278	#define CM_GCR_ERROR_CAUSE_ERRTYPE_MSK (_ULCAST_(0x1f) << 27)

arch/mips/include/asm/mipsregs.h+33−0

@@ -685,6 +685,39 @@ · 684 unmodified lines
685	685	#define MIPS_WATCHHI_W (_ULCAST_(1) << 0)
686	686	#define MIPS_WATCHHI_IRW (_ULCAST_(0x7) << 0)
687	687
	688	+/* PerfCnt control register definitions */
	689	+#define MIPS_PERFCTRL_EXL (_ULCAST_(1) << 0)
	690	+#define MIPS_PERFCTRL_K (_ULCAST_(1) << 1)
	691	+#define MIPS_PERFCTRL_S (_ULCAST_(1) << 2)
	692	+#define MIPS_PERFCTRL_U (_ULCAST_(1) << 3)
	693	+#define MIPS_PERFCTRL_IE (_ULCAST_(1) << 4)
	694	+#define MIPS_PERFCTRL_EVENT_S 5
	695	+#define MIPS_PERFCTRL_EVENT (_ULCAST_(0x3ff) << MIPS_PERFCTRL_EVENT_S)
	696	+#define MIPS_PERFCTRL_PCTD (_ULCAST_(1) << 15)
	697	+#define MIPS_PERFCTRL_EC (_ULCAST_(0x3) << 23)
	698	+#define MIPS_PERFCTRL_EC_R (_ULCAST_(0) << 23)
	699	+#define MIPS_PERFCTRL_EC_RI (_ULCAST_(1) << 23)
	700	+#define MIPS_PERFCTRL_EC_G (_ULCAST_(2) << 23)
	701	+#define MIPS_PERFCTRL_EC_GRI (_ULCAST_(3) << 23)
	702	+#define MIPS_PERFCTRL_W (_ULCAST_(1) << 30)
	703	+#define MIPS_PERFCTRL_M (_ULCAST_(1) << 31)
	704	+
	705	+/* PerfCnt control register MT extensions used by MIPS cores */
	706	+#define MIPS_PERFCTRL_VPEID_S 16
	707	+#define MIPS_PERFCTRL_VPEID (_ULCAST_(0xf) << MIPS_PERFCTRL_VPEID_S)
	708	+#define MIPS_PERFCTRL_TCID_S 22
	709	+#define MIPS_PERFCTRL_TCID (_ULCAST_(0xff) << MIPS_PERFCTRL_TCID_S)
	710	+#define MIPS_PERFCTRL_MT_EN (_ULCAST_(0x3) << 20)
	711	+#define MIPS_PERFCTRL_MT_EN_ALL (_ULCAST_(0) << 20)
	712	+#define MIPS_PERFCTRL_MT_EN_VPE (_ULCAST_(1) << 20)
	713	+#define MIPS_PERFCTRL_MT_EN_TC (_ULCAST_(2) << 20)
	714	+
	715	+/* PerfCnt control register MT extensions used by BMIPS5000 */
	716	+#define BRCM_PERFCTRL_TC (_ULCAST_(1) << 30)
	717	+
	718	+/* PerfCnt control register MT extensions used by Netlogic XLR */
	719	+#define XLR_PERFCTRL_ALLTHREADS (_ULCAST_(1) << 13)
	720	+
688	721	/* MAAR bit definitions */
689	722	#define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
690	723	#define MIPS_MAAR_ADDR_SHIFT 12

arch/mips/include/asm/octeon/cvmx-gpio-defs.h+6−2

@@ -46,7 +46,8 @@ union cvmx_gpio_bit_cfgx { · 45 unmodified lines
46	46	uint64_t u64;
47	47	struct cvmx_gpio_bit_cfgx_s {
48	48	#ifdef __BIG_ENDIAN_BITFIELD
49		− uint64_t reserved_17_63:47;
	49	+ uint64_t reserved_21_63:42;
	50	+ uint64_t output_sel:5;
50	51	uint64_t synce_sel:2;
51	52	uint64_t clk_gen:1;
52	53	uint64_t clk_sel:2;
@@ -66,7 +67,8 @@ union cvmx_gpio_bit_cfgx { · 13 unmodified lines
66	67	uint64_t clk_sel:2;
67	68	uint64_t clk_gen:1;
68	69	uint64_t synce_sel:2;
69		− uint64_t reserved_17_63:47;
	70	+ uint64_t output_sel:5;
	71	+ uint64_t reserved_21_63:42;
70	72	#endif
71	73	} s;
72	74	struct cvmx_gpio_bit_cfgx_cn30xx {
@@ -126,6 +128,8 @@ union cvmx_gpio_bit_cfgx { · 53 unmodified lines
126	128	struct cvmx_gpio_bit_cfgx_s cn66xx;
127	129	struct cvmx_gpio_bit_cfgx_s cn68xx;
128	130	struct cvmx_gpio_bit_cfgx_s cn68xxp1;
	131	+ struct cvmx_gpio_bit_cfgx_s cn70xx;
	132	+ struct cvmx_gpio_bit_cfgx_s cn73xx;
129	133	struct cvmx_gpio_bit_cfgx_s cnf71xx;
130	134	};
131	135

arch/mips/include/asm/octeon/cvmx-helper-rgmii.h+1−2

@@ -80,8 +80,7 @@ extern cvmx_helper_link_info_t __cvmx_helper_rgmii_link_get(int ipd_port); · 79 unmodified lines
80	80	* Configure an IPD/PKO port for the specified link state. This
81	81	* function does not influence auto negotiation at the PHY level.
82	82	* The passed link state must always match the link state returned
83		− * by cvmx_helper_link_get(). It is normally best to use
84		− * cvmx_helper_link_autoconf() instead.
	83	+ * by cvmx_helper_link_get().
85	84	*
86	85	* @ipd_port: IPD/PKO port to configure
87	86	* @link_info: The new link state

arch/mips/include/asm/octeon/cvmx-helper-sgmii.h+1−2

@@ -74,8 +74,7 @@ extern cvmx_helper_link_info_t __cvmx_helper_sgmii_link_get(int ipd_port); · 73 unmodified lines
74	74	* Configure an IPD/PKO port for the specified link state. This
75	75	* function does not influence auto negotiation at the PHY level.
76	76	* The passed link state must always match the link state returned
77		− * by cvmx_helper_link_get(). It is normally best to use
78		− * cvmx_helper_link_autoconf() instead.
	77	+ * by cvmx_helper_link_get().
79	78	*
80	79	* @ipd_port: IPD/PKO port to configure
81	80	* @link_info: The new link state

arch/mips/include/asm/octeon/cvmx-helper-spi.h+1−2

@@ -71,8 +71,7 @@ extern cvmx_helper_link_info_t __cvmx_helper_spi_link_get(int ipd_port); · 70 unmodified lines
71	71	* Configure an IPD/PKO port for the specified link state. This
72	72	* function does not influence auto negotiation at the PHY level.
73	73	* The passed link state must always match the link state returned
74		− * by cvmx_helper_link_get(). It is normally best to use
75		− * cvmx_helper_link_autoconf() instead.
	74	+ * by cvmx_helper_link_get().
76	75	*
77	76	* @ipd_port: IPD/PKO port to configure
78	77	* @link_info: The new link state

arch/mips/include/asm/octeon/cvmx-helper-xaui.h+1−2

@@ -74,8 +74,7 @@ extern cvmx_helper_link_info_t __cvmx_helper_xaui_link_get(int ipd_port); · 73 unmodified lines
74	74	* Configure an IPD/PKO port for the specified link state. This
75	75	* function does not influence auto negotiation at the PHY level.
76	76	* The passed link state must always match the link state returned
77		− * by cvmx_helper_link_get(). It is normally best to use
78		− * cvmx_helper_link_autoconf() instead.
	77	+ * by cvmx_helper_link_get().
79	78	*
80	79	* @ipd_port: IPD/PKO port to configure
81	80	* @link_info: The new link state

arch/mips/include/asm/octeon/cvmx-helper.h+1−13

@@ -155,17 +155,6 @@ extern int cvmx_helper_get_number_of_interfaces(void); · 154 unmodified lines
155	155	extern cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int
156	156	interface);
157	157
158		−/**
159		− * Auto configure an IPD/PKO port link state and speed. This
160		− * function basically does the equivalent of:
161		− * cvmx_helper_link_set(ipd_port, cvmx_helper_link_get(ipd_port));
162		− *
163		− * @ipd_port: IPD/PKO port to auto configure
164		− *
165		− * Returns Link state after configure
166		− */
167		−extern cvmx_helper_link_info_t cvmx_helper_link_autoconf(int ipd_port);
168		−
169	158	/**
170	159	* Return the link state of an IPD/PKO port as returned by
171	160	* auto negotiation. The result of this function may not match
@@ -182,8 +171,7 @@ extern cvmx_helper_link_info_t cvmx_helper_link_get(int ipd_port); · 10 unmodified lines
182	171	* Configure an IPD/PKO port for the specified link state. This
183	172	* function does not influence auto negotiation at the PHY level.
184	173	* The passed link state must always match the link state returned
185		− * by cvmx_helper_link_get(). It is normally best to use
186		− * cvmx_helper_link_autoconf() instead.
	174	+ * by cvmx_helper_link_get().
187	175	*
188	176	* @ipd_port: IPD/PKO port to configure
189	177	* @link_info: The new link state

arch/mips/include/asm/pgalloc.h+1−15

@@ -43,21 +43,7 @@ static inline void pud_populate(struct mm_struct mm, pud_t pud, pmd_t *pmd) · 42 unmodified lines
43	43	* Initialize a new pgd / pmd table with invalid pointers.
44	44	*/
45	45	extern void pgd_init(unsigned long page);
46		−
47		−static inline pgd_t pgd_alloc(struct mm_struct mm)
48		−{
49		− pgd_t ret, init;
50		−
51		− ret = (pgd_t *) __get_free_pages(GFP_KERNEL, PGD_ORDER);
52		− if (ret) {
53		− init = pgd_offset(&init_mm, 0UL);
54		− pgd_init((unsigned long)ret);
55		− memcpy(ret + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
56		− (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
57		− }
58		−
59		− return ret;
60		−}
	46	+extern pgd_t pgd_alloc(struct mm_struct mm);
61	47
62	48	static inline void pgd_free(struct mm_struct mm, pgd_t pgd)
63	49	{

arch/mips/include/asm/r4kcache.h+39−22

@@ -147,49 +147,66 @@ static inline void flush_scache_line(unsigned long addr) · 146 unmodified lines
147	147	}
148	148
149	149	#define protected_cache_op(op,addr) \
	150	+({ \
	151	+ int __err = 0; \
150	152	__asm__ __volatile__( \
151	153	" .set push \n" \
152	154	" .set noreorder \n" \
153	155	" .set "MIPS_ISA_ARCH_LEVEL" \n" \
154		− "1: cache %0, (%1) \n" \
155		− "2: .set pop \n" \
	156	+ "1: cache %1, (%2) \n" \
	157	+ "2: .insn \n" \
	158	+ " .set pop \n" \
	159	+ " .section .fixup,\"ax\" \n" \
	160	+ "3: li %0, %3 \n" \
	161	+ " j 2b \n" \
	162	+ " .previous \n" \
156	163	" .section __ex_table,\"a\" \n" \
157		− " "STR(PTR)" 1b, 2b \n" \
	164	+ " "STR(PTR)" 1b, 3b \n" \
158	165	" .previous" \
159		− : \
160		− : "i" (op), "r" (addr))
	166	+ : "+r" (__err) \
	167	+ : "i" (op), "r" (addr), "i" (-EFAULT)); \
	168	+ __err; \
	169	+})
	170	+
161	171
162	172	#define protected_cachee_op(op,addr) \
	173	+({ \
	174	+ int __err = 0; \
163	175	__asm__ __volatile__( \
164	176	" .set push \n" \
165	177	" .set noreorder \n" \
166	178	" .set mips0 \n" \
167	179	" .set eva \n" \
168		− "1: cachee %0, (%1) \n" \
169		− "2: .set pop \n" \
	180	+ "1: cachee %1, (%2) \n" \
	181	+ "2: .insn \n" \
	182	+ " .set pop \n" \
	183	+ " .section .fixup,\"ax\" \n" \
	184	+ "3: li %0, %3 \n" \
	185	+ " j 2b \n" \
	186	+ " .previous \n" \
170	187	" .section __ex_table,\"a\" \n" \
171		− " "STR(PTR)" 1b, 2b \n" \
	188	+ " "STR(PTR)" 1b, 3b \n" \
172	189	" .previous" \
173		− : \
174		− : "i" (op), "r" (addr))
	190	+ : "+r" (__err) \
	191	+ : "i" (op), "r" (addr), "i" (-EFAULT)); \
	192	+ __err; \
	193	+})
175	194
176	195	/*
177	196	* The next two are for badland addresses like signal trampolines.
178	197	*/
179		−static inline void protected_flush_icache_line(unsigned long addr)
	198	+static inline int protected_flush_icache_line(unsigned long addr)
180	199	{
181	200	switch (boot_cpu_type()) {
182	201	case CPU_LOONGSON2:
183		− protected_cache_op(Hit_Invalidate_I_Loongson2, addr);
184		− break;
	202	+ return protected_cache_op(Hit_Invalidate_I_Loongson2, addr);
185	203
186	204	default:
187	205	#ifdef CONFIG_EVA
188		− protected_cachee_op(Hit_Invalidate_I, addr);
	206	+ return protected_cachee_op(Hit_Invalidate_I, addr);
189	207	#else
190		− protected_cache_op(Hit_Invalidate_I, addr);
	208	+ return protected_cache_op(Hit_Invalidate_I, addr);
191	209	#endif
192		− break;
193	210	}
194	211	}
195	212
@@ -199,21 +216,21 @@ static inline void protected_flush_icache_line(unsigned long addr) · 3 unmodified lines
199	216	* caches. We're talking about one cacheline unnecessarily getting invalidated
200	217	* here so the penalty isn't overly hard.
201	218	*/
202		−static inline void protected_writeback_dcache_line(unsigned long addr)
	219	+static inline int protected_writeback_dcache_line(unsigned long addr)
203	220	{
204	221	#ifdef CONFIG_EVA
205		− protected_cachee_op(Hit_Writeback_Inv_D, addr);
	222	+ return protected_cachee_op(Hit_Writeback_Inv_D, addr);
206	223	#else
207		− protected_cache_op(Hit_Writeback_Inv_D, addr);
	224	+ return protected_cache_op(Hit_Writeback_Inv_D, addr);
208	225	#endif
209	226	}
210	227
211		−static inline void protected_writeback_scache_line(unsigned long addr)
	228	+static inline int protected_writeback_scache_line(unsigned long addr)
212	229	{
213	230	#ifdef CONFIG_EVA
214		− protected_cachee_op(Hit_Writeback_Inv_SD, addr);
	231	+ return protected_cachee_op(Hit_Writeback_Inv_SD, addr);
215	232	#else
216		− protected_cache_op(Hit_Writeback_Inv_SD, addr);
	233	+ return protected_cache_op(Hit_Writeback_Inv_SD, addr);
217	234	#endif
218	235	}
219	236

arch/mips/include/asm/smp.h+1−9

@@ -42,11 +42,7 @@ extern int __cpu_logical_map[NR_CPUS]; · 41 unmodified lines
42	42	#define SMP_CALL_FUNCTION 0x2
43	43	/* Octeon - Tell another core to flush its icache */
44	44	#define SMP_ICACHE_FLUSH 0x4
45		−/* Used by kexec crashdump to save all cpu's state */
46		−#define SMP_DUMP 0x8
47		−#define SMP_ASK_C0COUNT 0x10
48		−
49		−extern cpumask_t cpu_callin_map;
	45	+#define SMP_ASK_C0COUNT 0x8
50	46
51	47	/* Mask of CPUs which are currently definitely operating coherently */
52	48	extern cpumask_t cpu_coherent_mask;
@@ -113,8 +109,4 @@ static inline void arch_send_call_function_ipi_mask(const struct cpumask *mask) · 60 unmodified lines
113	109	mp_ops->send_ipi_mask(mask, SMP_CALL_FUNCTION);
114	110	}
115	111
116		−#if defined(CONFIG_KEXEC)
117		−extern void (dump_ipi_function_ptr)(void );
118		−void dump_send_ipi(void (dump_ipi_callback)(void ));
119		−#endif
120	112	#endif /* __ASM_SMP_H */

arch/mips/include/asm/stackframe.h+11−8

@@ -216,12 +216,19 @@ · 215 unmodified lines
216	216	LONG_S $25, PT_R25(sp)
217	217	LONG_S $28, PT_R28(sp)
218	218	LONG_S $31, PT_R31(sp)
	219	+
	220	+ /* Set thread_info if we're coming from user mode */
	221	+ mfc0 k0, CP0_STATUS
	222	+ sll k0, 3 /* extract cu0 bit */
	223	+ bltz k0, 9f
	224	+
219	225	ori $28, sp, _THREAD_MASK
220	226	xori $28, _THREAD_MASK
221	227	#ifdef CONFIG_CPU_CAVIUM_OCTEON
222	228	.set mips64
223	229	pref 0, 0($28) /* Prefetch the current pointer */
224	230	#endif
	231	+9:
225	232	.set pop
226	233	.endm
227	234
@@ -357,9 +364,13 @@ · 129 unmodified lines
357	364
358	365	.macro RESTORE_SP_AND_RET
359	366	LONG_L sp, PT_R29(sp)
	367	+#ifdef CONFIG_CPU_MIPSR6
	368	+ eretnc
	369	+#else
360	370	.set arch=r4000
361	371	eret
362	372	.set mips0
	373	+#endif
363	374	.endm
364	375
365	376	#endif
@@ -376,14 +387,6 @@ · 10 unmodified lines
376	387	RESTORE_SP
377	388	.endm
378	389
379		− .macro RESTORE_ALL_AND_RET
380		− RESTORE_TEMP
381		− RESTORE_STATIC
382		− RESTORE_AT
383		− RESTORE_SOME
384		− RESTORE_SP_AND_RET
385		− .endm
386		−
387	390	/*
388	391	* Move to kernel mode and disable interrupts.
389	392	* Set cp0 enable bit as sign that we're running on the kernel stack

arch/mips/include/asm/switch_to.h+12−6

@@ -66,13 +66,18 @@ do { \ · 65 unmodified lines
66	66	#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
67	67	#endif
68	68
69		−#define __clear_software_ll_bit() \
70		−do { if (cpu_has_rw_llb) { \
	69	+/*
	70	+ * Clear LLBit during context switches on MIPSr6 such that eretnc can be used
	71	+ * unconditionally when returning to userland in entry.S.
	72	+ */
	73	+#define __clear_r6_hw_ll_bit() do { \
	74	+ if (cpu_has_mips_r6) \
71	75	write_c0_lladdr(0); \
72		− } else { \
73		− if (!__builtin_constant_p(cpu_has_llsc) \|\| !cpu_has_llsc)\
74		− ll_bit = 0; \
75		− } \
	76	+} while (0)
	77	+
	78	+#define __clear_software_ll_bit() do { \
	79	+ if (!__builtin_constant_p(cpu_has_llsc) \|\| !cpu_has_llsc) \
	80	+ ll_bit = 0; \
76	81	} while (0)
77	82
78	83	/*
@@ -120,6 +125,7 @@ do { \ · 41 unmodified lines
120	125	} \
121	126	clear_c0_status(ST0_CU2); \
122	127	} \
	128	+ __clear_r6_hw_ll_bit(); \
123	129	__clear_software_ll_bit(); \
124	130	if (cpu_has_userlocal) \
125	131	write_c0_userlocal(task_thread_info(next)->tp_value); \

arch/mips/include/asm/thread_info.h+0−1

@@ -27,7 +27,6 @@ struct thread_info { · 26 unmodified lines
27	27	unsigned long tp_value; /* thread pointer */
28	28	__u32 cpu; /* current CPU */
29	29	int preempt_count; /* 0 => preemptable, <0 => BUG */
30		− int r2_emul_return; /* 1 => Returning from R2 emulator */
31	30	mm_segment_t addr_limit; /*
32	31	* thread address space limit:
33	32	* 0x7fffffff for user-thead

arch/mips/include/asm/tlbex.h+26−0

@@ -0,0 +1,26 @@
	1	+#ifndef __ASM_TLBEX_H
	2	+#define __ASM_TLBEX_H
	3	+
	4	+#include <asm/uasm.h>
	5	+
	6	+/*
	7	+ * Write random or indexed TLB entry, and care about the hazards from
	8	+ * the preceding mtc0 and for the following eret.
	9	+ */
	10	+enum tlb_write_entry {
	11	+ tlb_random,
	12	+ tlb_indexed
	13	+};
	14	+
	15	+extern int pgd_reg;
	16	+
	17	+void build_get_pmde64(u32 p, struct uasm_label l, struct uasm_reloc **r,
	18	+ unsigned int tmp, unsigned int ptr);
	19	+void build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr);
	20	+void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr);
	21	+void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep);
	22	+void build_tlb_write_entry(u32 p, struct uasm_label l,
	23	+ struct uasm_reloc **r,
	24	+ enum tlb_write_entry wmode);
	25	+
	26	+#endif /* __ASM_TLBEX_H */

arch/mips/include/asm/uaccess.h+18−0

@@ -1241,6 +1241,9 @@ extern size_t __copy_in_user_eva(void __to, const void __from, size_t __n); · 1240 unmodified lines
1241	1241	__cu_len; \
1242	1242	})
1243	1243
	1244	+extern __kernel_size_t __bzero_kernel(void __user *addr, __kernel_size_t size);
	1245	+extern __kernel_size_t __bzero(void __user *addr, __kernel_size_t size);
	1246	+
1244	1247	/*
1245	1248	* __clear_user: - Zero a block of memory in user space, with less checking.
1246	1249	* @to: Destination address, in user space.
@@ -1293,6 +1296,9 @@ __clear_user(void __user *addr, __kernel_size_t size) · 46 unmodified lines
1293	1296	__cl_size; \
1294	1297	})
1295	1298
	1299	+extern long __strncpy_from_kernel_nocheck_asm(char __to, const char __user __from, long __len);
	1300	+extern long __strncpy_from_user_nocheck_asm(char __to, const char __user __from, long __len);
	1301	+
1296	1302	/*
1297	1303	* __strncpy_from_user: - Copy a NUL terminated string from userspace, with less checking.
1298	1304	* @dst: Destination address, in kernel space. This buffer must be at
@@ -1344,6 +1350,9 @@ __strncpy_from_user(char __to, const char __user __from, long __len) · 45 unmodified lines
1344	1350	return res;
1345	1351	}
1346	1352
	1353	+extern long __strncpy_from_kernel_asm(char __to, const char __user __from, long __len);
	1354	+extern long __strncpy_from_user_asm(char __to, const char __user __from, long __len);
	1355	+
1347	1356	/*
1348	1357	* strncpy_from_user: - Copy a NUL terminated string from userspace.
1349	1358	* @dst: Destination address, in kernel space. This buffer must be at
@@ -1393,6 +1402,9 @@ strncpy_from_user(char __to, const char __user __from, long __len) · 43 unmodified lines
1393	1402	return res;
1394	1403	}
1395	1404
	1405	+extern long __strlen_kernel_asm(const char __user *s);
	1406	+extern long __strlen_user_asm(const char __user *s);
	1407	+
1396	1408	/*
1397	1409	* strlen_user: - Get the size of a string in user space.
1398	1410	* @str: The string to measure.
@@ -1434,6 +1446,9 @@ static inline long strlen_user(const char __user *s) · 35 unmodified lines
1434	1446	return res;
1435	1447	}
1436	1448
	1449	+extern long __strnlen_kernel_nocheck_asm(const char __user *s, long n);
	1450	+extern long __strnlen_user_nocheck_asm(const char __user *s, long n);
	1451	+
1437	1452	/* Returns: 0 if bad, string length+1 (memory size) of string if ok */
1438	1453	static inline long __strnlen_user(const char __user *s, long n)
1439	1454	{
@@ -1463,6 +1478,9 @@ static inline long __strnlen_user(const char __user *s, long n) · 23 unmodified lines
1463	1478	return res;
1464	1479	}
1465	1480
	1481	+extern long __strnlen_kernel_asm(const char __user *s, long n);
	1482	+extern long __strnlen_user_asm(const char __user *s, long n);
	1483	+
1466	1484	/*
1467	1485	* strnlen_user: - Get the size of a string in user space.
1468	1486	* @str: The string to measure.

arch/mips/include/asm/uasm.h+5−0

@@ -9,6 +9,9 @@ · 8 unmodified lines
9	9	* Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved.
10	10	*/
11	11
	12	+#ifndef __ASM_UASM_H
	13	+#define __ASM_UASM_H
	14	+
12	15	#include <linux/types.h>
13	16
14	17	#ifdef CONFIG_EXPORT_UASM
@@ -309,3 +312,5 @@ void uasm_il_bltz(u32 p, struct uasm_reloc r, unsigned int reg, int lid); · 294 unmodified lines
309	312	void uasm_il_bne(u32 p, struct uasm_reloc r, unsigned int reg1,
310	313	unsigned int reg2, int lid);
311	314	void uasm_il_bnez(u32 p, struct uasm_reloc r, unsigned int reg, int lid);
	315	+
	316	+#endif /* __ASM_UASM_H */

arch/mips/include/asm/unaligned.h+0−28

@@ -1,28 +0,0 @@
1		−/*
2		− * This file is subject to the terms and conditions of the GNU General Public
3		− * License. See the file "COPYING" in the main directory of this archive
4		− * for more details.
5		− *
6		− * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
7		− */
8		−#ifndef _ASM_MIPS_UNALIGNED_H
9		−#define _ASM_MIPS_UNALIGNED_H
10		−
11		−#include <linux/compiler.h>
12		−#if defined(__MIPSEB__)
13		−# include <linux/unaligned/be_struct.h>
14		−# include <linux/unaligned/le_byteshift.h>
15		−# define get_unaligned __get_unaligned_be
16		−# define put_unaligned __put_unaligned_be
17		−#elif defined(__MIPSEL__)
18		−# include <linux/unaligned/le_struct.h>
19		−# include <linux/unaligned/be_byteshift.h>
20		−# define get_unaligned __get_unaligned_le
21		−# define put_unaligned __put_unaligned_le
22		−#else
23		−# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
24		−#endif
25		−
26		−# include <linux/unaligned/generic.h>
27		−
28		−#endif /* _ASM_MIPS_UNALIGNED_H */

arch/mips/jazz/jazzdma.c+1−1

@@ -9,7 +9,7 @@ · 8 unmodified lines
9	9	*/
10	10	#include <linux/kernel.h>
11	11	#include <linux/init.h>
12		−#include <linux/module.h>
	12	+#include <linux/export.h>
13	13	#include <linux/errno.h>
14	14	#include <linux/mm.h>
15	15	#include <linux/bootmem.h>

arch/mips/jz4740/gpio.c+1−1

@@ -14,7 +14,7 @@ · 13 unmodified lines
14	14	*/
15	15
16	16	#include <linux/kernel.h>
17		−#include <linux/module.h>
	17	+#include <linux/export.h>
18	18	#include <linux/init.h>
19	19
20	20	#include <linux/io.h>

arch/mips/jz4740/prom.c+0−1

@@ -13,7 +13,6 @@ · 12 unmodified lines
13	13	*
14	14	*/
15	15
16		−#include <linux/module.h>
17	16	#include <linux/kernel.h>
18	17	#include <linux/init.h>
19	18	#include <linux/string.h>

arch/mips/jz4740/timer.c+2−1

@@ -13,9 +13,10 @@ · 12 unmodified lines
13	13	*
14	14	*/
15	15
	16	+#include <linux/export.h>
16	17	#include <linux/io.h>
	18	+#include <linux/init.h>
17	19	#include <linux/kernel.h>
18		−#include <linux/module.h>
19	20
20	21	#include <asm/mach-jz4740/base.h>
21	22	#include <asm/mach-jz4740/timer.h>

arch/mips/kernel/Makefile+2−2

@@ -7,7 +7,7 @@ extra-y := head.o vmlinux.lds · 6 unmodified lines
7	7	obj-y += cpu-probe.o branch.o elf.o entry.o genex.o idle.o irq.o \
8	8	process.o prom.o ptrace.o reset.o setup.o signal.o \
9	9	syscall.o time.o topology.o traps.o unaligned.o watch.o \
10		− vdso.o
	10	+ vdso.o cacheinfo.o
11	11
12	12	ifdef CONFIG_FUNCTION_TRACER
13	13	CFLAGS_REMOVE_ftrace.o = -pg
@@ -30,7 +30,7 @@ obj-$(CONFIG_SYNC_R4K) += sync-r4k.o · 16 unmodified lines
30	30
31	31	obj-$(CONFIG_DEBUG_FS) += segment.o
32	32	obj-$(CONFIG_STACKTRACE) += stacktrace.o
33		−obj-$(CONFIG_MODULES) += mips_ksyms.o module.o
	33	+obj-$(CONFIG_MODULES) += module.o
34	34	obj-$(CONFIG_MODULES_USE_ELF_RELA) += module-rela.o
35	35
36	36	obj-$(CONFIG_FTRACE_SYSCALLS) += ftrace.o

arch/mips/kernel/asm-offsets.c+1−1

@@ -97,11 +97,11 @@ void output_thread_info_defines(void) · 96 unmodified lines
97	97	OFFSET(TI_TP_VALUE, thread_info, tp_value);
98	98	OFFSET(TI_CPU, thread_info, cpu);
99	99	OFFSET(TI_PRE_COUNT, thread_info, preempt_count);
100		− OFFSET(TI_R2_EMUL_RET, thread_info, r2_emul_return);
101	100	OFFSET(TI_ADDR_LIMIT, thread_info, addr_limit);
102	101	OFFSET(TI_REGS, thread_info, regs);
103	102	DEFINE(_THREAD_SIZE, THREAD_SIZE);
104	103	DEFINE(_THREAD_MASK, THREAD_MASK);
	104	+ DEFINE(_IRQ_STACK_SIZE, IRQ_STACK_SIZE);
105	105	BLANK();
106	106	}
107	107

arch/mips/kernel/cacheinfo.c+87−0

@@ -0,0 +1,87 @@
	1	+/*
	2	+ * MIPS cacheinfo support
	3	+ *
	4	+ * This program is free software; you can redistribute it and/or modify
	5	+ * it under the terms of the GNU General Public License version 2 as
	6	+ * published by the Free Software Foundation.
	7	+ *
	8	+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
	9	+ * kind, whether express or implied; without even the implied warranty
	10	+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	+ * GNU General Public License for more details.
	12	+ *
	13	+ * You should have received a copy of the GNU General Public License
	14	+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
	15	+ */
	16	+#include <linux/cacheinfo.h>
	17	+
	18	+/* Populates leaf and increments to next leaf */
	19	+#define populate_cache(cache, leaf, c_level, c_type) \
	20	+do { \
	21	+ leaf->type = c_type; \
	22	+ leaf->level = c_level; \
	23	+ leaf->coherency_line_size = c->cache.linesz; \
	24	+ leaf->number_of_sets = c->cache.sets; \
	25	+ leaf->ways_of_associativity = c->cache.ways; \
	26	+ leaf->size = c->cache.linesz * c->cache.sets * \
	27	+ c->cache.ways; \
	28	+ leaf++; \
	29	+} while (0)
	30	+
	31	+static int __init_cache_level(unsigned int cpu)
	32	+{
	33	+ struct cpuinfo_mips *c = &current_cpu_data;
	34	+ struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
	35	+ int levels = 0, leaves = 0;
	36	+
	37	+ /*
	38	+ * If Dcache is not set, we assume the cache structures
	39	+ * are not properly initialized.
	40	+ */
	41	+ if (c->dcache.waysize)
	42	+ levels += 1;
	43	+ else
	44	+ return -ENOENT;
	45	+
	46	+
	47	+ leaves += (c->icache.waysize) ? 2 : 1;
	48	+
	49	+ if (c->scache.waysize) {
	50	+ levels++;
	51	+ leaves++;
	52	+ }
	53	+
	54	+ if (c->tcache.waysize) {
	55	+ levels++;
	56	+ leaves++;
	57	+ }
	58	+
	59	+ this_cpu_ci->num_levels = levels;
	60	+ this_cpu_ci->num_leaves = leaves;
	61	+ return 0;
	62	+}
	63	+
	64	+static int __populate_cache_leaves(unsigned int cpu)
	65	+{
	66	+ struct cpuinfo_mips *c = &current_cpu_data;
	67	+ struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
	68	+ struct cacheinfo *this_leaf = this_cpu_ci->info_list;
	69	+
	70	+ if (c->icache.waysize) {
	71	+ populate_cache(dcache, this_leaf, 1, CACHE_TYPE_DATA);
	72	+ populate_cache(icache, this_leaf, 1, CACHE_TYPE_INST);
	73	+ } else {
	74	+ populate_cache(dcache, this_leaf, 1, CACHE_TYPE_UNIFIED);
	75	+ }
	76	+
	77	+ if (c->scache.waysize)
	78	+ populate_cache(scache, this_leaf, 2, CACHE_TYPE_UNIFIED);
	79	+
	80	+ if (c->tcache.waysize)
	81	+ populate_cache(tcache, this_leaf, 3, CACHE_TYPE_UNIFIED);
	82	+
	83	+ return 0;
	84	+}
	85	+
	86	+DEFINE_SMP_CALL_CACHE_FUNCTION(init_cache_level)
	87	+DEFINE_SMP_CALL_CACHE_FUNCTION(populate_cache_leaves)

arch/mips/kernel/cpu-bugs64.c+12−12

@@ -148,11 +148,11 @@ static inline void check_mult_sh(void) · 147 unmodified lines
148	148	bug = 1;
149	149
150	150	if (bug == 0) {
151		− printk("no.\n");
	151	+ pr_cont("no.\n");
152	152	return;
153	153	}
154	154
155		− printk("yes, workaround... ");
	155	+ pr_cont("yes, workaround... ");
156	156
157	157	fix = 1;
158	158	for (i = 0; i < 8; i++)
@@ -160,11 +160,11 @@ static inline void check_mult_sh(void) · 1 unmodified line
160	160	fix = 0;
161	161
162	162	if (fix == 1) {
163		− printk("yes.\n");
	163	+ pr_cont("yes.\n");
164	164	return;
165	165	}
166	166
167		− printk("no.\n");
	167	+ pr_cont("no.\n");
168	168	panic(bug64hit, !R4000_WAR ? r4kwar : nowar);
169	169	}
170	170
@@ -218,11 +218,11 @@ static inline void check_daddi(void) · 47 unmodified lines
218	218	local_irq_restore(flags);
219	219
220	220	if (daddi_ov) {
221		− printk("no.\n");
	221	+ pr_cont("no.\n");
222	222	return;
223	223	}
224	224
225		− printk("yes, workaround... ");
	225	+ pr_cont("yes, workaround... ");
226	226
227	227	local_irq_save(flags);
228	228	handler = set_except_vector(EXCCODE_OV, handle_daddi_ov);
@@ -236,11 +236,11 @@ static inline void check_daddi(void) · 7 unmodified lines
236	236	local_irq_restore(flags);
237	237
238	238	if (daddi_ov) {
239		− printk("yes.\n");
	239	+ pr_cont("yes.\n");
240	240	return;
241	241	}
242	242
243		− printk("no.\n");
	243	+ pr_cont("no.\n");
244	244	panic(bug64hit, !DADDI_WAR ? daddiwar : nowar);
245	245	}
246	246
@@ -288,11 +288,11 @@ static inline void check_daddiu(void) · 41 unmodified lines
288	288	daddiu_bug = v != w;
289	289
290	290	if (!daddiu_bug) {
291		− printk("no.\n");
	291	+ pr_cont("no.\n");
292	292	return;
293	293	}
294	294
295		− printk("yes, workaround... ");
	295	+ pr_cont("yes, workaround... ");
296	296
297	297	asm volatile(
298	298	"addiu %2, $0, %3\n\t"
@@ -304,11 +304,11 @@ static inline void check_daddiu(void) · 5 unmodified lines
304	304	: "I" (0xffffffffffffdb9aUL), "I" (0x1234));
305	305
306	306	if (v == w) {
307		− printk("yes.\n");
	307	+ pr_cont("yes.\n");
308	308	return;
309	309	}
310	310
311		− printk("no.\n");
	311	+ pr_cont("no.\n");
312	312	panic(bug64hit, !DADDI_WAR ? daddiwar : nowar);
313	313	}
314	314

arch/mips/kernel/crash.c+1−1

@@ -56,7 +56,7 @@ static void crash_kexec_prepare_cpus(void) · 55 unmodified lines
56	56
57	57	ncpus = num_online_cpus() - 1;/* Excluding the panic cpu */
58	58
59		− dump_send_ipi(crash_shutdown_secondary);
	59	+ smp_call_function(crash_shutdown_secondary, NULL, 0);
60	60	smp_wmb();
61	61
62	62	/*

arch/mips/kernel/entry.S+0−18

@@ -47,11 +47,6 @@ resume_userspace: · 46 unmodified lines
47	47	local_irq_disable # make sure we dont miss an
48	48	# interrupt setting need_resched
49	49	# between sampling and return
50		−#ifdef CONFIG_MIPSR2_TO_R6_EMULATOR
51		− lw k0, TI_R2_EMUL_RET($28)
52		− bnez k0, restore_all_from_r2_emul
53		−#endif
54		−
55	50	LONG_L a2, TI_FLAGS($28) # current->work
56	51	andi t0, a2, _TIF_WORK_MASK # (ignoring syscall_trace)
57	52	bnez t0, work_pending
@@ -120,19 +115,6 @@ restore_partial: # restore partial frame · 62 unmodified lines
120	115	RESTORE_SP_AND_RET
121	116	.set at
122	117
123		−#ifdef CONFIG_MIPSR2_TO_R6_EMULATOR
124		−restore_all_from_r2_emul: # restore full frame
125		− .set noat
126		− sw zero, TI_R2_EMUL_RET($28) # reset it
127		− RESTORE_TEMP
128		− RESTORE_AT
129		− RESTORE_STATIC
130		− RESTORE_SOME
131		− LONG_L sp, PT_R29(sp)
132		− eretnc
133		− .set at
134		−#endif
135		−
136	118	work_pending:
137	119	andi t0, a2, _TIF_NEED_RESCHED # a2 is preloaded with TI_FLAGS
138	120	beqz t0, work_notifysig

arch/mips/kernel/genex.S+76−5

@@ -187,9 +187,44 @@ NESTED(handle_int, PT_SIZE, sp) · 186 unmodified lines
187	187
188	188	LONG_L s0, TI_REGS($28)
189	189	LONG_S sp, TI_REGS($28)
190		− PTR_LA ra, ret_from_irq
191		− PTR_LA v0, plat_irq_dispatch
192		− jr v0
	190	+
	191	+ /*
	192	+ * SAVE_ALL ensures we are using a valid kernel stack for the thread.
	193	+ * Check if we are already using the IRQ stack.
	194	+ */
	195	+ move s1, sp # Preserve the sp
	196	+
	197	+ /* Get IRQ stack for this CPU */
	198	+ ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG
	199	+#if defined(CONFIG_32BIT) \|\| defined(KBUILD_64BIT_SYM32)
	200	+ lui k1, %hi(irq_stack)
	201	+#else
	202	+ lui k1, %highest(irq_stack)
	203	+ daddiu k1, %higher(irq_stack)
	204	+ dsll k1, 16
	205	+ daddiu k1, %hi(irq_stack)
	206	+ dsll k1, 16
	207	+#endif
	208	+ LONG_SRL k0, SMP_CPUID_PTRSHIFT
	209	+ LONG_ADDU k1, k0
	210	+ LONG_L t0, %lo(irq_stack)(k1)
	211	+
	212	+ # Check if already on IRQ stack
	213	+ PTR_LI t1, ~(_THREAD_SIZE-1)
	214	+ and t1, t1, sp
	215	+ beq t0, t1, 2f
	216	+
	217	+ /* Switch to IRQ stack */
	218	+ li t1, _IRQ_STACK_SIZE
	219	+ PTR_ADD sp, t0, t1
	220	+
	221	+2:
	222	+ jal plat_irq_dispatch
	223	+
	224	+ /* Restore sp */
	225	+ move sp, s1
	226	+
	227	+ j ret_from_irq
193	228	#ifdef CONFIG_CPU_MICROMIPS
194	229	nop
195	230	#endif
@@ -262,8 +297,44 @@ NESTED(except_vec_vi_handler, 0, sp) · 66 unmodified lines
262	297
263	298	LONG_L s0, TI_REGS($28)
264	299	LONG_S sp, TI_REGS($28)
265		− PTR_LA ra, ret_from_irq
266		− jr v0
	300	+
	301	+ /*
	302	+ * SAVE_ALL ensures we are using a valid kernel stack for the thread.
	303	+ * Check if we are already using the IRQ stack.
	304	+ */
	305	+ move s1, sp # Preserve the sp
	306	+
	307	+ /* Get IRQ stack for this CPU */
	308	+ ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG
	309	+#if defined(CONFIG_32BIT) \|\| defined(KBUILD_64BIT_SYM32)
	310	+ lui k1, %hi(irq_stack)
	311	+#else
	312	+ lui k1, %highest(irq_stack)
	313	+ daddiu k1, %higher(irq_stack)
	314	+ dsll k1, 16
	315	+ daddiu k1, %hi(irq_stack)
	316	+ dsll k1, 16
	317	+#endif
	318	+ LONG_SRL k0, SMP_CPUID_PTRSHIFT
	319	+ LONG_ADDU k1, k0
	320	+ LONG_L t0, %lo(irq_stack)(k1)
	321	+
	322	+ # Check if already on IRQ stack
	323	+ PTR_LI t1, ~(_THREAD_SIZE-1)
	324	+ and t1, t1, sp
	325	+ beq t0, t1, 2f
	326	+
	327	+ /* Switch to IRQ stack */
	328	+ li t1, _IRQ_STACK_SIZE
	329	+ PTR_ADD sp, t0, t1
	330	+
	331	+2:
	332	+ jalr v0
	333	+
	334	+ /* Restore sp */
	335	+ move sp, s1
	336	+
	337	+ j ret_from_irq
267	338	END(except_vec_vi_handler)
268	339
269	340	/*

arch/mips/kernel/irq.c+11−0

@@ -25,6 +25,8 @@ · 24 unmodified lines
25	25	#include <linux/atomic.h>
26	26	#include <linux/uaccess.h>
27	27
	28	+void *irq_stack[NR_CPUS];
	29	+
28	30	/*
29	31	* 'what should we do if we get a hw irq event on an illegal vector'.
30	32	* each architecture has to answer this themselves.
@@ -58,6 +60,15 @@ void __init init_IRQ(void) · 27 unmodified lines
58	60	clear_c0_status(ST0_IM);
59	61
60	62	arch_init_irq();
	63	+
	64	+ for_each_possible_cpu(i) {
	65	+ int irq_pages = IRQ_STACK_SIZE / PAGE_SIZE;
	66	+ void s = (void )__get_free_pages(GFP_KERNEL, irq_pages);
	67	+
	68	+ irq_stack[i] = s;
	69	+ pr_debug("CPU%d IRQ stack at 0x%p - 0x%p\n", i,
	70	+ irq_stack[i], irq_stack[i] + IRQ_STACK_SIZE);
	71	+ }
61	72	}
62	73
63	74	#ifdef CONFIG_DEBUG_STACKOVERFLOW

arch/mips/kernel/linux32.c+3−8

@@ -64,15 +64,10 @@ SYSCALL_DEFINE6(32_mmap2, unsigned long, addr, unsigned long, len, · 63 unmodified lines
64	64	unsigned long, prot, unsigned long, flags, unsigned long, fd,
65	65	unsigned long, pgoff)
66	66	{
67		− unsigned long error;
68		−
69		− error = -EINVAL;
70	67	if (pgoff & (~PAGE_MASK >> 12))
71		− goto out;
72		− error = sys_mmap_pgoff(addr, len, prot, flags, fd,
73		− pgoff >> (PAGE_SHIFT-12));
74		−out:
75		− return error;
	68	+ return -EINVAL;
	69	+ return sys_mmap_pgoff(addr, len, prot, flags, fd,
	70	+ pgoff >> (PAGE_SHIFT-12));
76	71	}
77	72
78	73	#define RLIM_INFINITY32 0x7fffffff

arch/mips/kernel/machine_kexec.c+22−0

@@ -28,9 +28,31 @@ atomic_t kexec_ready_to_reboot = ATOMIC_INIT(0); · 27 unmodified lines
28	28	void (*_crash_smp_send_stop)(void) = NULL;
29	29	#endif
30	30
	31	+static void kexec_image_info(const struct kimage *kimage)
	32	+{
	33	+ unsigned long i;
	34	+
	35	+ pr_debug("kexec kimage info:\n");
	36	+ pr_debug(" type: %d\n", kimage->type);
	37	+ pr_debug(" start: %lx\n", kimage->start);
	38	+ pr_debug(" head: %lx\n", kimage->head);
	39	+ pr_debug(" nr_segments: %lu\n", kimage->nr_segments);
	40	+
	41	+ for (i = 0; i < kimage->nr_segments; i++) {
	42	+ pr_debug(" segment[%lu]: %016lx - %016lx, 0x%lx bytes, %lu pages\n",
	43	+ i,
	44	+ kimage->segment[i].mem,
	45	+ kimage->segment[i].mem + kimage->segment[i].memsz,
	46	+ (unsigned long)kimage->segment[i].memsz,
	47	+ (unsigned long)kimage->segment[i].memsz / PAGE_SIZE);
	48	+ }
	49	+}
	50	+
31	51	int
32	52	machine_kexec_prepare(struct kimage *kimage)
33	53	{
	54	+ kexec_image_info(kimage);
	55	+
34	56	if (_machine_kexec_prepare)
35	57	return _machine_kexec_prepare(kimage);
36	58	return 0;

arch/mips/kernel/mcount.S+3−0

@@ -10,6 +10,7 @@ · 9 unmodified lines
10	10	* Author: Wu Zhangjin <wuzhangjin@gmail.com>
11	11	*/
12	12
	13	+#include <asm/export.h>
13	14	#include <asm/regdef.h>
14	15	#include <asm/stackframe.h>
15	16	#include <asm/ftrace.h>
@@ -66,6 +67,7 @@ · 50 unmodified lines
66	67	NESTED(ftrace_caller, PT_SIZE, ra)
67	68	.globl _mcount
68	69	_mcount:
	70	+EXPORT_SYMBOL(_mcount)
69	71	b ftrace_stub
70	72	#ifdef CONFIG_32BIT
71	73	addiu sp,sp,8
@@ -114,6 +116,7 @@ ftrace_stub: · 42 unmodified lines
114	116	#else /* ! CONFIG_DYNAMIC_FTRACE */
115	117
116	118	NESTED(_mcount, PT_SIZE, ra)
	119	+EXPORT_SYMBOL(_mcount)
117	120	PTR_LA t1, ftrace_stub
118	121	PTR_L t2, ftrace_trace_function /* Prepare t2 for (1) */
119	122	bne t1, t2, static_trace

arch/mips/kernel/mips-mt-fpaff.c+3−2

@@ -99,9 +99,10 @@ asmlinkage long mipsmt_sys_sched_setaffinity(pid_t pid, unsigned int len, · 98 unmodified lines
99	99	retval = -ENOMEM;
100	100	goto out_free_new_mask;
101	101	}
102		− retval = -EPERM;
103		− if (!check_same_owner(p) && !capable(CAP_SYS_NICE))
	102	+ if (!check_same_owner(p) && !capable(CAP_SYS_NICE)) {
	103	+ retval = -EPERM;
104	104	goto out_unlock;
	105	+ }
105	106
106	107	retval = security_task_setscheduler(p);
107	108	if (retval)

arch/mips/kernel/mips-r2-to-r6-emul.c+6−6

@@ -433,8 +433,8 @@ static int multu_func(struct pt_regs *regs, u32 ir) · 432 unmodified lines
433	433	rs = regs->regs[MIPSInst_RS(ir)];
434	434	res = (u64)rt * (u64)rs;
435	435	rt = res;
436		− regs->lo = (s64)rt;
437		− regs->hi = (s64)(res >> 32);
	436	+ regs->lo = (s64)(s32)rt;
	437	+ regs->hi = (s64)(s32)(res >> 32);
438	438
439	439	MIPS_R2_STATS(muls);
440	440
@@ -670,9 +670,9 @@ static int maddu_func(struct pt_regs *regs, u32 ir) · 229 unmodified lines
670	670	res += ((((s64)rt) << 32) \| (u32)rs);
671	671
672	672	rt = res;
673		− regs->lo = (s64)rt;
	673	+ regs->lo = (s64)(s32)rt;
674	674	rs = res >> 32;
675		− regs->hi = (s64)rs;
	675	+ regs->hi = (s64)(s32)rs;
676	676
677	677	MIPS_R2_STATS(dsps);
678	678
@@ -728,9 +728,9 @@ static int msubu_func(struct pt_regs *regs, u32 ir) · 49 unmodified lines
728	728	res = ((((s64)rt) << 32) \| (u32)rs) - res;
729	729
730	730	rt = res;
731		− regs->lo = (s64)rt;
	731	+ regs->lo = (s64)(s32)rt;
732	732	rs = res >> 32;
733		− regs->hi = (s64)rs;
	733	+ regs->hi = (s64)(s32)rs;
734	734
735	735	MIPS_R2_STATS(dsps);
736	736

arch/mips/kernel/mips_ksyms.c+0−94

@@ -1,94 +0,0 @@
1		−/*
2		− * Export MIPS-specific functions needed for loadable modules.
3		− *
4		− * This file is subject to the terms and conditions of the GNU General Public
5		− * License. See the file "COPYING" in the main directory of this archive
6		− * for more details.
7		− *
8		− * Copyright (C) 1996, 97, 98, 99, 2000, 01, 03, 04, 05, 12 by Ralf Baechle
9		− * Copyright (C) 1999, 2000, 01 Silicon Graphics, Inc.
10		− */
11		−#include <linux/interrupt.h>
12		−#include <linux/export.h>
13		−#include <asm/checksum.h>
14		−#include <linux/mm.h>
15		−#include <linux/uaccess.h>
16		−#include <asm/ftrace.h>
17		−#include <asm/fpu.h>
18		−#include <asm/msa.h>
19		−
20		−extern void __bzero_kernel(void __s, size_t __count);
21		−extern void __bzero(void __s, size_t __count);
22		−extern long __strncpy_from_kernel_nocheck_asm(char *__to,
23		− const char *__from, long __len);
24		−extern long __strncpy_from_kernel_asm(char __to, const char __from,
25		− long __len);
26		−extern long __strncpy_from_user_nocheck_asm(char *__to,
27		− const char *__from, long __len);
28		−extern long __strncpy_from_user_asm(char __to, const char __from,
29		− long __len);
30		−extern long __strlen_kernel_asm(const char *s);
31		−extern long __strlen_user_asm(const char *s);
32		−extern long __strnlen_kernel_nocheck_asm(const char *s);
33		−extern long __strnlen_kernel_asm(const char *s);
34		−extern long __strnlen_user_nocheck_asm(const char *s);
35		−extern long __strnlen_user_asm(const char *s);
36		−
37		−/*
38		− * Core architecture code
39		− */
40		−EXPORT_SYMBOL_GPL(_save_fp);
41		−#ifdef CONFIG_CPU_HAS_MSA
42		−EXPORT_SYMBOL_GPL(_save_msa);
43		−#endif
44		−
45		−/*
46		− * String functions
47		− */
48		−EXPORT_SYMBOL(memset);
49		−EXPORT_SYMBOL(memcpy);
50		−EXPORT_SYMBOL(memmove);
51		−
52		−/*
53		− * Functions that operate on entire pages. Mostly used by memory management.
54		− */
55		−EXPORT_SYMBOL(clear_page);
56		−EXPORT_SYMBOL(copy_page);
57		−
58		−/*
59		− * Userspace access stuff.
60		− */
61		−EXPORT_SYMBOL(__copy_user);
62		−EXPORT_SYMBOL(__copy_user_inatomic);
63		−#ifdef CONFIG_EVA
64		−EXPORT_SYMBOL(__copy_from_user_eva);
65		−EXPORT_SYMBOL(__copy_in_user_eva);
66		−EXPORT_SYMBOL(__copy_to_user_eva);
67		−EXPORT_SYMBOL(__copy_user_inatomic_eva);
68		−EXPORT_SYMBOL(__bzero_kernel);
69		−#endif
70		−EXPORT_SYMBOL(__bzero);
71		−EXPORT_SYMBOL(__strncpy_from_kernel_nocheck_asm);
72		−EXPORT_SYMBOL(__strncpy_from_kernel_asm);
73		−EXPORT_SYMBOL(__strncpy_from_user_nocheck_asm);
74		−EXPORT_SYMBOL(__strncpy_from_user_asm);
75		−EXPORT_SYMBOL(__strlen_kernel_asm);
76		−EXPORT_SYMBOL(__strlen_user_asm);
77		−EXPORT_SYMBOL(__strnlen_kernel_nocheck_asm);
78		−EXPORT_SYMBOL(__strnlen_kernel_asm);
79		−EXPORT_SYMBOL(__strnlen_user_nocheck_asm);
80		−EXPORT_SYMBOL(__strnlen_user_asm);
81		−
82		−#ifndef CONFIG_CPU_MIPSR6
83		−EXPORT_SYMBOL(csum_partial);
84		−EXPORT_SYMBOL(csum_partial_copy_nocheck);
85		−EXPORT_SYMBOL(__csum_partial_copy_kernel);
86		−EXPORT_SYMBOL(__csum_partial_copy_to_user);
87		−EXPORT_SYMBOL(__csum_partial_copy_from_user);
88		−#endif
89		−
90		−EXPORT_SYMBOL(invalid_pte_table);
91		−#ifdef CONFIG_FUNCTION_TRACER
92		−/* _mcount is defined in arch/mips/kernel/mcount.S */
93		−EXPORT_SYMBOL(_mcount);
94		−#endif

arch/mips/kernel/perf_event_mipsxx.c+23−32

@@ -101,40 +101,31 @@ struct mips_pmu { · 100 unmodified lines
101	101
102	102	static struct mips_pmu mipspmu;
103	103
104		−#define M_PERFCTL_EXL (1 << 0)
105		−#define M_PERFCTL_KERNEL (1 << 1)
106		−#define M_PERFCTL_SUPERVISOR (1 << 2)
107		−#define M_PERFCTL_USER (1 << 3)
108		−#define M_PERFCTL_INTERRUPT_ENABLE (1 << 4)
109		−#define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5)
110		−#define M_PERFCTL_VPEID(vpe) ((vpe) << 16)
	104	+#define M_PERFCTL_EVENT(event) (((event) << MIPS_PERFCTRL_EVENT_S) & \
	105	+ MIPS_PERFCTRL_EVENT)
	106	+#define M_PERFCTL_VPEID(vpe) ((vpe) << MIPS_PERFCTRL_VPEID_S)
111	107
112	108	#ifdef CONFIG_CPU_BMIPS5000
113	109	#define M_PERFCTL_MT_EN(filter) 0
114	110	#else /* !CONFIG_CPU_BMIPS5000 */
115		−#define M_PERFCTL_MT_EN(filter) ((filter) << 20)
	111	+#define M_PERFCTL_MT_EN(filter) (filter)
116	112	#endif /* CONFIG_CPU_BMIPS5000 */
117	113
118		−#define M_TC_EN_ALL M_PERFCTL_MT_EN(0)
119		−#define M_TC_EN_VPE M_PERFCTL_MT_EN(1)
120		−#define M_TC_EN_TC M_PERFCTL_MT_EN(2)
121		−#define M_PERFCTL_TCID(tcid) ((tcid) << 22)
122		−#define M_PERFCTL_WIDE (1 << 30)
123		−#define M_PERFCTL_MORE (1 << 31)
124		−#define M_PERFCTL_TC (1 << 30)
	114	+#define M_TC_EN_ALL M_PERFCTL_MT_EN(MIPS_PERFCTRL_MT_EN_ALL)
	115	+#define M_TC_EN_VPE M_PERFCTL_MT_EN(MIPS_PERFCTRL_MT_EN_VPE)
	116	+#define M_TC_EN_TC M_PERFCTL_MT_EN(MIPS_PERFCTRL_MT_EN_TC)
125	117
126		−#define M_PERFCTL_COUNT_EVENT_WHENEVER (M_PERFCTL_EXL \| \
127		− M_PERFCTL_KERNEL \| \
128		− M_PERFCTL_USER \| \
129		− M_PERFCTL_SUPERVISOR \| \
130		− M_PERFCTL_INTERRUPT_ENABLE)
	118	+#define M_PERFCTL_COUNT_EVENT_WHENEVER (MIPS_PERFCTRL_EXL \| \
	119	+ MIPS_PERFCTRL_K \| \
	120	+ MIPS_PERFCTRL_U \| \
	121	+ MIPS_PERFCTRL_S \| \
	122	+ MIPS_PERFCTRL_IE)
131	123
132	124	#ifdef CONFIG_MIPS_MT_SMP
133	125	#define M_PERFCTL_CONFIG_MASK 0x3fff801f
134	126	#else
135	127	#define M_PERFCTL_CONFIG_MASK 0x1f
136	128	#endif
137		−#define M_PERFCTL_EVENT_MASK 0xfe0
138	129
139	130
140	131	#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
@@ -345,11 +336,11 @@ static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx) · 204 unmodified lines
345	336	cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) \|
346	337	(evt->config_base & M_PERFCTL_CONFIG_MASK) \|
347	338	/* Make sure interrupt enabled. */
348		− M_PERFCTL_INTERRUPT_ENABLE;
	339	+ MIPS_PERFCTRL_IE;
349	340	if (IS_ENABLED(CONFIG_CPU_BMIPS5000))
350	341	/* enable the counter for the calling thread */
351	342	cpuc->saved_ctrl[idx] \|=
352		− (1 << (12 + vpe_id())) \| M_PERFCTL_TC;
	343	+ (1 << (12 + vpe_id())) \| BRCM_PERFCTRL_TC;
353	344
354	345	/*
355	346	* We do not actually let the counter run. Leave it until start().
@@ -754,11 +745,11 @@ static int __n_counters(void) · 398 unmodified lines
754	745	{
755	746	if (!cpu_has_perf)
756	747	return 0;
757		− if (!(read_c0_perfctrl0() & M_PERFCTL_MORE))
	748	+ if (!(read_c0_perfctrl0() & MIPS_PERFCTRL_M))
758	749	return 1;
759		− if (!(read_c0_perfctrl1() & M_PERFCTL_MORE))
	750	+ if (!(read_c0_perfctrl1() & MIPS_PERFCTRL_M))
760	751	return 2;
761		− if (!(read_c0_perfctrl2() & M_PERFCTL_MORE))
	752	+ if (!(read_c0_perfctrl2() & MIPS_PERFCTRL_M))
762	753	return 3;
763	754
764	755	return 4;
@@ -1339,7 +1330,7 @@ static int __hw_perf_event_init(struct perf_event *event) · 574 unmodified lines
1339	1330	* We allow max flexibility on how each individual counter shared
1340	1331	* by the single CPU operates (the mode exclusion and the range).
1341	1332	*/
1342		− hwc->config_base = M_PERFCTL_INTERRUPT_ENABLE;
	1333	+ hwc->config_base = MIPS_PERFCTRL_IE;
1343	1334
1344	1335	/* Calculate range bits and validate it. */
1345	1336	if (num_possible_cpus() > 1)
@@ -1350,14 +1341,14 @@ static int __hw_perf_event_init(struct perf_event *event) · 4 unmodified lines
1350	1341	mutex_unlock(&raw_event_mutex);
1351	1342
1352	1343	if (!attr->exclude_user)
1353		− hwc->config_base \|= M_PERFCTL_USER;
	1344	+ hwc->config_base \|= MIPS_PERFCTRL_U;
1354	1345	if (!attr->exclude_kernel) {
1355		− hwc->config_base \|= M_PERFCTL_KERNEL;
	1346	+ hwc->config_base \|= MIPS_PERFCTRL_K;
1356	1347	/* MIPS kernel mode: KSU == 00b \|\| EXL == 1 \|\| ERL == 1 */
1357		− hwc->config_base \|= M_PERFCTL_EXL;
	1348	+ hwc->config_base \|= MIPS_PERFCTRL_EXL;
1358	1349	}
1359	1350	if (!attr->exclude_hv)
1360		− hwc->config_base \|= M_PERFCTL_SUPERVISOR;
	1351	+ hwc->config_base \|= MIPS_PERFCTRL_S;
1361	1352
1362	1353	hwc->config_base &= M_PERFCTL_CONFIG_MASK;
1363	1354	/*
@@ -1830,7 +1821,7 @@ init_hw_perf_events(void) · 466 unmodified lines
1830	1821	mipspmu.num_counters = counters;
1831	1822	mipspmu.irq = irq;
1832	1823
1833		− if (read_c0_perfctrl0() & M_PERFCTL_WIDE) {
	1824	+ if (read_c0_perfctrl0() & MIPS_PERFCTRL_W) {
1834	1825	mipspmu.max_period = (1ULL << 63) - 1;
1835	1826	mipspmu.valid_count = (1ULL << 63) - 1;
1836	1827	mipspmu.overflow = 1ULL << 63;

arch/mips/kernel/process.c+157−57

@@ -33,6 +33,7 @@ · 32 unmodified lines
33	33	#include <asm/dsemul.h>
34	34	#include <asm/dsp.h>
35	35	#include <asm/fpu.h>
	36	+#include <asm/irq.h>
36	37	#include <asm/msa.h>
37	38	#include <asm/pgtable.h>
38	39	#include <asm/mipsregs.h>
@@ -49,9 +50,7 @@ · 10 unmodified lines
49	50	#ifdef CONFIG_HOTPLUG_CPU
50	51	void arch_cpu_idle_dead(void)
51	52	{
52		− /* What the heck is this check doing ? */
53		− if (!cpumask_test_cpu(smp_processor_id(), &cpu_callin_map))
54		− play_dead();
	53	+ play_dead();
55	54	}
56	55	#endif
57	56
@@ -195,11 +194,9 @@ struct mips_frame_info { · 137 unmodified lines
195	194	#define J_TARGET(pc,target) \
196	195	(((unsigned long)(pc) & 0xf0000000) \| ((target) << 2))
197	196
198		−static inline int is_ra_save_ins(union mips_instruction *ip)
	197	+static inline int is_ra_save_ins(union mips_instruction ip, int poff)
199	198	{
200	199	#ifdef CONFIG_CPU_MICROMIPS
201		− union mips_instruction mmi;
202		−
203	200	/*
204	201	* swsp ra,offset
205	202	* swm16 reglist,offset(sp)
@@ -209,29 +206,71 @@ static inline int is_ra_save_ins(union mips_instruction *ip) · 3 unmodified lines
209	206	*
210	207	* microMIPS is way more fun...
211	208	*/
212		− if (mm_insn_16bit(ip->halfword[0])) {
213		− mmi.word = (ip->halfword[0] << 16);
214		− return (mmi.mm16_r5_format.opcode == mm_swsp16_op &&
215		− mmi.mm16_r5_format.rt == 31) \|\|
216		− (mmi.mm16_m_format.opcode == mm_pool16c_op &&
217		− mmi.mm16_m_format.func == mm_swm16_op);
	209	+ if (mm_insn_16bit(ip->halfword[1])) {
	210	+ switch (ip->mm16_r5_format.opcode) {
	211	+ case mm_swsp16_op:
	212	+ if (ip->mm16_r5_format.rt != 31)
	213	+ return 0;
	214	+
	215	+ *poff = ip->mm16_r5_format.simmediate;
	216	+ poff = (poff << 2) / sizeof(ulong);
	217	+ return 1;
	218	+
	219	+ case mm_pool16c_op:
	220	+ switch (ip->mm16_m_format.func) {
	221	+ case mm_swm16_op:
	222	+ *poff = ip->mm16_m_format.imm;
	223	+ *poff += 1 + ip->mm16_m_format.rlist;
	224	+ poff = (poff << 2) / sizeof(ulong);
	225	+ return 1;
	226	+
	227	+ default:
	228	+ return 0;
	229	+ }
	230	+
	231	+ default:
	232	+ return 0;
	233	+ }
218	234	}
219		− else {
220		− mmi.halfword[0] = ip->halfword[1];
221		− mmi.halfword[1] = ip->halfword[0];
222		− return (mmi.mm_m_format.opcode == mm_pool32b_op &&
223		− mmi.mm_m_format.rd > 9 &&
224		− mmi.mm_m_format.base == 29 &&
225		− mmi.mm_m_format.func == mm_swm32_func) \|\|
226		− (mmi.i_format.opcode == mm_sw32_op &&
227		− mmi.i_format.rs == 29 &&
228		− mmi.i_format.rt == 31);
	235	+
	236	+ switch (ip->i_format.opcode) {
	237	+ case mm_sw32_op:
	238	+ if (ip->i_format.rs != 29)
	239	+ return 0;
	240	+ if (ip->i_format.rt != 31)
	241	+ return 0;
	242	+
	243	+ *poff = ip->i_format.simmediate / sizeof(ulong);
	244	+ return 1;
	245	+
	246	+ case mm_pool32b_op:
	247	+ switch (ip->mm_m_format.func) {
	248	+ case mm_swm32_func:
	249	+ if (ip->mm_m_format.rd < 0x10)
	250	+ return 0;
	251	+ if (ip->mm_m_format.base != 29)
	252	+ return 0;
	253	+
	254	+ *poff = ip->mm_m_format.simmediate;
	255	+ poff += (ip->mm_m_format.rd & 0xf) sizeof(u32);
	256	+ *poff /= sizeof(ulong);
	257	+ return 1;
	258	+ default:
	259	+ return 0;
	260	+ }
	261	+
	262	+ default:
	263	+ return 0;
229	264	}
230	265	#else
231	266	/* sw / sd $ra, offset($sp) */
232		− return (ip->i_format.opcode == sw_op \|\| ip->i_format.opcode == sd_op) &&
233		− ip->i_format.rs == 29 &&
234		− ip->i_format.rt == 31;
	267	+ if ((ip->i_format.opcode == sw_op \|\| ip->i_format.opcode == sd_op) &&
	268	+ ip->i_format.rs == 29 && ip->i_format.rt == 31) {
	269	+ *poff = ip->i_format.simmediate / sizeof(ulong);
	270	+ return 1;
	271	+ }
	272	+
	273	+ return 0;
235	274	#endif
236	275	}
237	276
@@ -246,13 +285,16 @@ static inline int is_jump_ins(union mips_instruction *ip) · 8 unmodified lines
246	285	*
247	286	* microMIPS is kind of more fun...
248	287	*/
249		− union mips_instruction mmi;
250		−
251		− mmi.word = (ip->halfword[0] << 16);
	288	+ if (mm_insn_16bit(ip->halfword[1])) {
	289	+ if ((ip->mm16_r5_format.opcode == mm_pool16c_op &&
	290	+ (ip->mm16_r5_format.rt & mm_jr16_op) == mm_jr16_op))
	291	+ return 1;
	292	+ return 0;
	293	+ }
252	294
253		− if ((mmi.mm16_r5_format.opcode == mm_pool16c_op &&
254		− (mmi.mm16_r5_format.rt & mm_jr16_op) == mm_jr16_op) \|\|
255		− ip->j_format.opcode == mm_jal32_op)
	295	+ if (ip->j_format.opcode == mm_j32_op)
	296	+ return 1;
	297	+ if (ip->j_format.opcode == mm_jal32_op)
256	298	return 1;
257	299	if (ip->r_format.opcode != mm_pool32a_op \|\|
258	300	ip->r_format.func != mm_pool32axf_op)
@@ -280,15 +322,13 @@ static inline int is_sp_move_ins(union mips_instruction *ip) · 21 unmodified lines
280	322	*
281	323	* microMIPS is not more fun...
282	324	*/
283		− if (mm_insn_16bit(ip->halfword[0])) {
284		− union mips_instruction mmi;
285		−
286		− mmi.word = (ip->halfword[0] << 16);
287		− return (mmi.mm16_r3_format.opcode == mm_pool16d_op &&
288		− mmi.mm16_r3_format.simmediate && mm_addiusp_func) \|\|
289		− (mmi.mm16_r5_format.opcode == mm_pool16d_op &&
290		− mmi.mm16_r5_format.rt == 29);
	325	+ if (mm_insn_16bit(ip->halfword[1])) {
	326	+ return (ip->mm16_r3_format.opcode == mm_pool16d_op &&
	327	+ ip->mm16_r3_format.simmediate && mm_addiusp_func) \|\|
	328	+ (ip->mm16_r5_format.opcode == mm_pool16d_op &&
	329	+ ip->mm16_r5_format.rt == 29);
291	330	}
	331	+
292	332	return ip->mm_i_format.opcode == mm_addiu32_op &&
293	333	ip->mm_i_format.rt == 29 && ip->mm_i_format.rs == 29;
294	334	#else
@@ -303,30 +343,36 @@ static inline int is_sp_move_ins(union mips_instruction *ip) · 8 unmodified lines
303	343
304	344	static int get_frame_info(struct mips_frame_info *info)
305	345	{
306		−#ifdef CONFIG_CPU_MICROMIPS
307		− union mips_instruction ip = (void ) (((char *) info->func) - 1);
308		−#else
309		− union mips_instruction *ip = info->func;
310		−#endif
311		− unsigned max_insns = info->func_size / sizeof(union mips_instruction);
312		− unsigned i;
	346	+ bool is_mmips = IS_ENABLED(CONFIG_CPU_MICROMIPS);
	347	+ union mips_instruction insn, ip, ip_end;
	348	+ const unsigned int max_insns = 128;
	349	+ unsigned int i;
313	350
314	351	info->pc_offset = -1;
315	352	info->frame_size = 0;
316	353
	354	+ ip = (void *)msk_isa16_mode((ulong)info->func);
317	355	if (!ip)
318	356	goto err;
319	357
320		− if (max_insns == 0)
321		− max_insns = 128U; /* unknown function size */
322		− max_insns = min(128U, max_insns);
	358	+ ip_end = (void *)ip + info->func_size;
323	359
324		− for (i = 0; i < max_insns; i++, ip++) {
	360	+ for (i = 0; i < max_insns && ip < ip_end; i++, ip++) {
	361	+ if (is_mmips && mm_insn_16bit(ip->halfword[0])) {
	362	+ insn.halfword[0] = 0;
	363	+ insn.halfword[1] = ip->halfword[0];
	364	+ } else if (is_mmips) {
	365	+ insn.halfword[0] = ip->halfword[1];
	366	+ insn.halfword[1] = ip->halfword[0];
	367	+ } else {
	368	+ insn.word = ip->word;
	369	+ }
325	370
326		− if (is_jump_ins(ip))
	371	+ if (is_jump_ins(&insn))
327	372	break;
	373	+
328	374	if (!info->frame_size) {
329		− if (is_sp_move_ins(ip))
	375	+ if (is_sp_move_ins(&insn))
330	376	{
331	377	#ifdef CONFIG_CPU_MICROMIPS
332	378	if (mm_insn_16bit(ip->halfword[0]))
@@ -349,11 +395,9 @@ static int get_frame_info(struct mips_frame_info *info) · 16 unmodified lines
349	395	}
350	396	continue;
351	397	}
352		− if (info->pc_offset == -1 && is_ra_save_ins(ip)) {
353		− info->pc_offset =
354		− ip->i_format.simmediate / sizeof(long);
	398	+ if (info->pc_offset == -1 &&
	399	+ is_ra_save_ins(&insn, &info->pc_offset))
355	400	break;
356		− }
357	401	}
358	402	if (info->frame_size && info->pc_offset >= 0) /* nested */
359	403	return 0;
@@ -511,7 +555,19 @@ EXPORT_SYMBOL(unwind_stack_by_address); · 151 unmodified lines
511	555	unsigned long unwind_stack(struct task_struct task, unsigned long sp,
512	556	unsigned long pc, unsigned long *ra)
513	557	{
514		− unsigned long stack_page = (unsigned long)task_stack_page(task);
	558	+ unsigned long stack_page = 0;
	559	+ int cpu;
	560	+
	561	+ for_each_possible_cpu(cpu) {
	562	+ if (on_irq_stack(cpu, *sp)) {
	563	+ stack_page = (unsigned long)irq_stack[cpu];
	564	+ break;
	565	+ }
	566	+ }
	567	+
	568	+ if (!stack_page)
	569	+ stack_page = (unsigned long)task_stack_page(task);
	570	+
515	571	return unwind_stack_by_address(stack_page, sp, pc, ra);
516	572	}
517	573	#endif
@@ -673,3 +729,47 @@ int mips_set_process_fp_mode(struct task_struct *task, unsigned int value) · 155 unmodified lines
673	729
674	730	return 0;
675	731	}
	732	+
	733	+#if defined(CONFIG_32BIT) \|\| defined(CONFIG_MIPS32_O32)
	734	+void mips_dump_regs32(u32 uregs, const struct pt_regs regs)
	735	+{
	736	+ unsigned int i;
	737	+
	738	+ for (i = MIPS32_EF_R1; i <= MIPS32_EF_R31; i++) {
	739	+ /* k0/k1 are copied as zero. */
	740	+ if (i == MIPS32_EF_R26 \|\| i == MIPS32_EF_R27)
	741	+ uregs[i] = 0;
	742	+ else
	743	+ uregs[i] = regs->regs[i - MIPS32_EF_R0];
	744	+ }
	745	+
	746	+ uregs[MIPS32_EF_LO] = regs->lo;
	747	+ uregs[MIPS32_EF_HI] = regs->hi;
	748	+ uregs[MIPS32_EF_CP0_EPC] = regs->cp0_epc;
	749	+ uregs[MIPS32_EF_CP0_BADVADDR] = regs->cp0_badvaddr;
	750	+ uregs[MIPS32_EF_CP0_STATUS] = regs->cp0_status;
	751	+ uregs[MIPS32_EF_CP0_CAUSE] = regs->cp0_cause;
	752	+}
	753	+#endif /* CONFIG_32BIT \|\| CONFIG_MIPS32_O32 */
	754	+
	755	+#ifdef CONFIG_64BIT
	756	+void mips_dump_regs64(u64 uregs, const struct pt_regs regs)
	757	+{
	758	+ unsigned int i;
	759	+
	760	+ for (i = MIPS64_EF_R1; i <= MIPS64_EF_R31; i++) {
	761	+ /* k0/k1 are copied as zero. */
	762	+ if (i == MIPS64_EF_R26 \|\| i == MIPS64_EF_R27)
	763	+ uregs[i] = 0;
	764	+ else
	765	+ uregs[i] = regs->regs[i - MIPS64_EF_R0];
	766	+ }
	767	+
	768	+ uregs[MIPS64_EF_LO] = regs->lo;
	769	+ uregs[MIPS64_EF_HI] = regs->hi;
	770	+ uregs[MIPS64_EF_CP0_EPC] = regs->cp0_epc;
	771	+ uregs[MIPS64_EF_CP0_BADVADDR] = regs->cp0_badvaddr;
	772	+ uregs[MIPS64_EF_CP0_STATUS] = regs->cp0_status;
	773	+ uregs[MIPS64_EF_CP0_CAUSE] = regs->cp0_cause;
	774	+}
	775	+#endif /* CONFIG_64BIT */

arch/mips/kernel/prom.c+7−0

@@ -49,6 +49,13 @@ void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) · 48 unmodified lines
49	49	return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS));
50	50	}
51	51
	52	+int __init early_init_dt_reserve_memory_arch(phys_addr_t base,
	53	+ phys_addr_t size, bool nomap)
	54	+{
	55	+ add_memory_region(base, size, BOOT_MEM_RESERVED);
	56	+ return 0;
	57	+}
	58	+
52	59	void __init __dt_setup_arch(void *bph)
53	60	{
54	61	if (!early_init_dt_scan(bph))

arch/mips/kernel/ptrace.c+2−32

@@ -294,23 +294,8 @@ static int gpr32_get(struct task_struct *target, · 293 unmodified lines
294	294	{
295	295	struct pt_regs *regs = task_pt_regs(target);
296	296	u32 uregs[ELF_NGREG] = {};
297		− unsigned i;
298		−
299		− for (i = MIPS32_EF_R1; i <= MIPS32_EF_R31; i++) {
300		− /* k0/k1 are copied as zero. */
301		− if (i == MIPS32_EF_R26 \|\| i == MIPS32_EF_R27)
302		− continue;
303		−
304		− uregs[i] = regs->regs[i - MIPS32_EF_R0];
305		− }
306		−
307		− uregs[MIPS32_EF_LO] = regs->lo;
308		− uregs[MIPS32_EF_HI] = regs->hi;
309		− uregs[MIPS32_EF_CP0_EPC] = regs->cp0_epc;
310		− uregs[MIPS32_EF_CP0_BADVADDR] = regs->cp0_badvaddr;
311		− uregs[MIPS32_EF_CP0_STATUS] = regs->cp0_status;
312		− uregs[MIPS32_EF_CP0_CAUSE] = regs->cp0_cause;
313	297
	298	+ mips_dump_regs32(uregs, regs);
314	299	return user_regset_copyout(&pos, &count, &kbuf, &ubuf, uregs, 0,
315	300	sizeof(uregs));
316	301	}
@@ -373,23 +358,8 @@ static int gpr64_get(struct task_struct *target, · 56 unmodified lines
373	358	{
374	359	struct pt_regs *regs = task_pt_regs(target);
375	360	u64 uregs[ELF_NGREG] = {};
376		− unsigned i;
377		−
378		− for (i = MIPS64_EF_R1; i <= MIPS64_EF_R31; i++) {
379		− /* k0/k1 are copied as zero. */
380		− if (i == MIPS64_EF_R26 \|\| i == MIPS64_EF_R27)
381		− continue;
382		−
383		− uregs[i] = regs->regs[i - MIPS64_EF_R0];
384		− }
385		−
386		− uregs[MIPS64_EF_LO] = regs->lo;
387		− uregs[MIPS64_EF_HI] = regs->hi;
388		− uregs[MIPS64_EF_CP0_EPC] = regs->cp0_epc;
389		− uregs[MIPS64_EF_CP0_BADVADDR] = regs->cp0_badvaddr;
390		− uregs[MIPS64_EF_CP0_STATUS] = regs->cp0_status;
391		− uregs[MIPS64_EF_CP0_CAUSE] = regs->cp0_cause;
392	361
	362	+ mips_dump_regs64(uregs, regs);
393	363	return user_regset_copyout(&pos, &count, &kbuf, &ubuf, uregs, 0,
394	364	sizeof(uregs));
395	365	}

arch/mips/kernel/r2300_switch.S+2−0

@@ -12,6 +12,7 @@ · 11 unmodified lines
12	12	*/
13	13	#include <asm/asm.h>
14	14	#include <asm/cachectl.h>
	15	+#include <asm/export.h>
15	16	#include <asm/fpregdef.h>
16	17	#include <asm/mipsregs.h>
17	18	#include <asm/asm-offsets.h>
@@ -72,6 +73,7 @@ LEAF(resume) · 54 unmodified lines
72	73	* Save a thread's fp context.
73	74	*/
74	75	LEAF(_save_fp)
	76	+EXPORT_SYMBOL(_save_fp)
75	77	fpu_save_single a0, t1 # clobbers t1
76	78	jr ra
77	79	END(_save_fp)

arch/mips/kernel/r4k_switch.S+3−0

@@ -12,6 +12,7 @@ · 11 unmodified lines
12	12	*/
13	13	#include <asm/asm.h>
14	14	#include <asm/cachectl.h>
	15	+#include <asm/export.h>
15	16	#include <asm/fpregdef.h>
16	17	#include <asm/mipsregs.h>
17	18	#include <asm/asm-offsets.h>
@@ -75,6 +76,7 @@ · 57 unmodified lines
75	76	* Save a thread's fp context.
76	77	*/
77	78	LEAF(_save_fp)
	79	+EXPORT_SYMBOL(_save_fp)
78	80	#if defined(CONFIG_64BIT) \|\| defined(CONFIG_CPU_MIPS32_R2) \|\| \
79	81	defined(CONFIG_CPU_MIPS32_R6)
80	82	mfc0 t0, CP0_STATUS
@@ -101,6 +103,7 @@ LEAF(_restore_fp) · 20 unmodified lines
101	103	* Save a thread's MSA vector context.
102	104	*/
103	105	LEAF(_save_msa)
	106	+EXPORT_SYMBOL(_save_msa)
104	107	msa_save_all a0
105	108	jr ra
106	109	END(_save_msa)

arch/mips/kernel/relocate.c+55−1

@@ -31,6 +31,18 @@ extern u32 _relocation_end[]; /* End relocation table */ · 30 unmodified lines
31	31	extern long __start___ex_table; /* Start exception table */
32	32	extern long __stop___ex_table; /* End exception table */
33	33
	34	+extern void __weak plat_fdt_relocated(void *new_location);
	35	+
	36	+/*
	37	+ * This function may be defined for a platform to perform any post-relocation
	38	+ * fixup necessary.
	39	+ * Return non-zero to abort relocation
	40	+ */
	41	+int __weak plat_post_relocation(long offset)
	42	+{
	43	+ return 0;
	44	+}
	45	+
34	46	static inline u32 __init get_synci_step(void)
35	47	{
36	48	u32 res;
@@ -291,12 +303,14 @@ void *__init relocate_kernel(void) · 254 unmodified lines
291	303	int res = 1;
292	304	/* Default to original kernel entry point */
293	305	void *kernel_entry = start_kernel;
	306	+ void *fdt = NULL;
294	307
295	308	/* Get the command line */
296	309	fw_init_cmdline();
297	310	#if defined(CONFIG_USE_OF)
298	311	/* Deal with the device tree */
299		− early_init_dt_scan(plat_get_fdt());
	312	+ fdt = plat_get_fdt();
	313	+ early_init_dt_scan(fdt);
300	314	if (boot_command_line[0]) {
301	315	/* Boot command line was passed in device tree */
302	316	strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
@@ -316,6 +330,29 @@ void *__init relocate_kernel(void) · 13 unmodified lines
316	330	arcs_cmdline[0] = '\0';
317	331
318	332	if (offset) {
	333	+ void (fdt_relocated_)(void ) = NULL;
	334	+#if defined(CONFIG_USE_OF)
	335	+ unsigned long fdt_phys = virt_to_phys(fdt);
	336	+
	337	+ /*
	338	+ * If built-in dtb is used then it will have been relocated
	339	+ * during kernel _text relocation. If appended DTB is used
	340	+ * then it will not be relocated, but it should remain
	341	+ * intact in the original location. If dtb is loaded by
	342	+ * the bootloader then it may need to be moved if it crosses
	343	+ * the target memory area
	344	+ */
	345	+
	346	+ if (fdt_phys >= virt_to_phys(RELOCATED(&_text)) &&
	347	+ fdt_phys <= virt_to_phys(RELOCATED(&_end))) {
	348	+ void *fdt_relocated =
	349	+ RELOCATED(ALIGN((long)&_end, PAGE_SIZE));
	350	+ memcpy(fdt_relocated, fdt, fdt_totalsize(fdt));
	351	+ fdt = fdt_relocated;
	352	+ fdt_relocated_ = RELOCATED(&plat_fdt_relocated);
	353	+ }
	354	+#endif /* CONFIG_USE_OF */
	355	+
319	356	/* Copy the kernel to it's new location */
320	357	memcpy(loc_new, &_text, kernel_length);
321	358
@@ -338,6 +375,23 @@ void *__init relocate_kernel(void) · 16 unmodified lines
338	375	*/
339	376	memcpy(RELOCATED(&__bss_start), &__bss_start, bss_length);
340	377
	378	+ /*
	379	+ * If fdt was stored outside of the kernel image and
	380	+ * had to be moved then update platform's state data
	381	+ * with the new fdt location
	382	+ */
	383	+ if (fdt_relocated_)
	384	+ fdt_relocated_(fdt);
	385	+
	386	+ /*
	387	+ * Last chance for the platform to abort relocation.
	388	+ * This may also be used by the platform to perform any
	389	+ * initialisation required now that the new kernel is
	390	+ * resident in memory and ready to be executed.
	391	+ */
	392	+ if (plat_post_relocation(offset))
	393	+ goto out;
	394	+
341	395	/* The current thread is now within the relocated image */
342	396	__current_thread_info = RELOCATED(&init_thread_union);
343	397

arch/mips/kernel/setup.c+91−3

@@ -27,6 +27,7 @@ · 26 unmodified lines
27	27	#include <linux/device.h>
28	28	#include <linux/dma-contiguous.h>
29	29	#include <linux/decompress/generic.h>
	30	+#include <linux/of_fdt.h>
30	31
31	32	#include <asm/addrspace.h>
32	33	#include <asm/bootinfo.h>
@@ -153,6 +154,35 @@ void __init detect_memory_region(phys_addr_t start, phys_addr_t sz_min, phys_add · 120 unmodified lines
153	154	add_memory_region(start, size, BOOT_MEM_RAM);
154	155	}
155	156
	157	+bool __init memory_region_available(phys_addr_t start, phys_addr_t size)
	158	+{
	159	+ int i;
	160	+ bool in_ram = false, free = true;
	161	+
	162	+ for (i = 0; i < boot_mem_map.nr_map; i++) {
	163	+ phys_addr_t start_, end_;
	164	+
	165	+ start_ = boot_mem_map.map[i].addr;
	166	+ end_ = boot_mem_map.map[i].addr + boot_mem_map.map[i].size;
	167	+
	168	+ switch (boot_mem_map.map[i].type) {
	169	+ case BOOT_MEM_RAM:
	170	+ if (start >= start_ && start + size <= end_)
	171	+ in_ram = true;
	172	+ break;
	173	+ case BOOT_MEM_RESERVED:
	174	+ if ((start >= start_ && start < end_) \|\|
	175	+ (start < start_ && start + size >= start_))
	176	+ free = false;
	177	+ break;
	178	+ default:
	179	+ continue;
	180	+ }
	181	+ }
	182	+
	183	+ return in_ram && free;
	184	+}
	185	+
156	186	static void __init print_memory_map(void)
157	187	{
158	188	int i;
@@ -332,11 +362,19 @@ static void __init bootmem_init(void) · 173 unmodified lines
332	362
333	363	#else /* !CONFIG_SGI_IP27 */
334	364
	365	+static unsigned long __init bootmap_bytes(unsigned long pages)
	366	+{
	367	+ unsigned long bytes = DIV_ROUND_UP(pages, 8);
	368	+
	369	+ return ALIGN(bytes, sizeof(long));
	370	+}
	371	+
335	372	static void __init bootmem_init(void)
336	373	{
337	374	unsigned long reserved_end;
338	375	unsigned long mapstart = ~0UL;
339	376	unsigned long bootmap_size;
	377	+ bool bootmap_valid = false;
340	378	int i;
341	379
342	380	/*
@@ -430,11 +468,42 @@ static void __init bootmem_init(void) · 87 unmodified lines
430	468	#endif
431	469
432	470	/*
433		− * Initialize the boot-time allocator with low memory only.
	471	+ * check that mapstart doesn't overlap with any of
	472	+ * memory regions that have been reserved through eg. DTB
434	473	*/
435		− bootmap_size = init_bootmem_node(NODE_DATA(0), mapstart,
436		− min_low_pfn, max_low_pfn);
	474	+ bootmap_size = bootmap_bytes(max_low_pfn - min_low_pfn);
437	475
	476	+ bootmap_valid = memory_region_available(PFN_PHYS(mapstart),
	477	+ bootmap_size);
	478	+ for (i = 0; i < boot_mem_map.nr_map && !bootmap_valid; i++) {
	479	+ unsigned long mapstart_addr;
	480	+
	481	+ switch (boot_mem_map.map[i].type) {
	482	+ case BOOT_MEM_RESERVED:
	483	+ mapstart_addr = PFN_ALIGN(boot_mem_map.map[i].addr +
	484	+ boot_mem_map.map[i].size);
	485	+ if (PHYS_PFN(mapstart_addr) < mapstart)
	486	+ break;
	487	+
	488	+ bootmap_valid = memory_region_available(mapstart_addr,
	489	+ bootmap_size);
	490	+ if (bootmap_valid)
	491	+ mapstart = PHYS_PFN(mapstart_addr);
	492	+ break;
	493	+ default:
	494	+ break;
	495	+ }
	496	+ }
	497	+
	498	+ if (!bootmap_valid)
	499	+ panic("No memory area to place a bootmap bitmap");
	500	+
	501	+ /*
	502	+ * Initialize the boot-time allocator with low memory only.
	503	+ */
	504	+ if (bootmap_size != init_bootmem_node(NODE_DATA(0), mapstart,
	505	+ min_low_pfn, max_low_pfn))
	506	+ panic("Unexpected memory size required for bootmap");
438	507
439	508	for (i = 0; i < boot_mem_map.nr_map; i++) {
440	509	unsigned long start, end;
@@ -483,6 +552,10 @@ static void __init bootmem_init(void) · 42 unmodified lines
483	552	continue;
484	553	default:
485	554	/* Not usable memory */
	555	+ if (start > min_low_pfn && end < max_low_pfn)
	556	+ reserve_bootmem(boot_mem_map.map[i].addr,
	557	+ boot_mem_map.map[i].size,
	558	+ BOOTMEM_DEFAULT);
486	559	continue;
487	560	}
488	561
@@ -589,6 +662,10 @@ static int __init early_parse_mem(char *p) · 100 unmodified lines
589	662	start = memparse(p + 1, &p);
590	663
591	664	add_memory_region(start, size, BOOT_MEM_RAM);
	665	+
	666	+ if (start && start > PHYS_OFFSET)
	667	+ add_memory_region(PHYS_OFFSET, start - PHYS_OFFSET,
	668	+ BOOT_MEM_RESERVED);
592	669	return 0;
593	670	}
594	671	early_param("mem", early_parse_mem);
@@ -664,6 +741,11 @@ static void __init mips_parse_crashkernel(void) · 69 unmodified lines
664	741	if (ret != 0 \|\| crash_size <= 0)
665	742	return;
666	743
	744	+ if (!memory_region_available(crash_base, crash_size)) {
	745	+ pr_warn("Invalid memory region reserved for crash kernel\n");
	746	+ return;
	747	+ }
	748	+
667	749	crashk_res.start = crash_base;
668	750	crashk_res.end = crash_base + crash_size - 1;
669	751	}
@@ -672,6 +754,9 @@ static void __init request_crashkernel(struct resource *res) · 2 unmodified lines
672	754	{
673	755	int ret;
674	756
	757	+ if (crashk_res.start == crashk_res.end)
	758	+ return;
	759	+
675	760	ret = request_resource(res, &crashk_res);
676	761	if (!ret)
677	762	pr_info("Reserving %ldMB of memory at %ldMB for crashkernel\n",
@@ -757,6 +842,9 @@ static void __init arch_mem_init(char **cmdline_p) · 79 unmodified lines
757	842	print_memory_map();
758	843	}
759	844
	845	+ early_init_fdt_reserve_self();
	846	+ early_init_fdt_scan_reserved_mem();
	847	+
760	848	bootmem_init();
761	849	#ifdef CONFIG_PROC_VMCORE
762	850	if (setup_elfcorehdr && setup_elfcorehdr_size) {

arch/mips/kernel/smp-bmips.c+1−1

@@ -364,7 +364,7 @@ static int bmips_cpu_disable(void) · 363 unmodified lines
364	364
365	365	set_cpu_online(cpu, false);
366	366	calculate_cpu_foreign_map();
367		− cpumask_clear_cpu(cpu, &cpu_callin_map);
	367	+ irq_cpu_offline();
368	368	clear_c0_status(IE_IRQ5);
369	369
370	370	local_flush_tlb_all();

arch/mips/kernel/smp-cps.c+5−2

@@ -326,7 +326,11 @@ static void cps_boot_secondary(int cpu, struct task_struct *idle) · 325 unmodified lines
326	326	if (cpu_online(remote))
327	327	break;
328	328	}
329		− BUG_ON(remote >= NR_CPUS);
	329	+ if (remote >= NR_CPUS) {
	330	+ pr_crit("No online CPU in core %u to start CPU%d\n",
	331	+ core, cpu);
	332	+ goto out;
	333	+ }
330	334
331	335	err = smp_call_function_single(remote, remote_vpe_boot,
332	336	NULL, 1);
@@ -399,7 +403,6 @@ static int cps_cpu_disable(void) · 66 unmodified lines
399	403	smp_mb__after_atomic();
400	404	set_cpu_online(cpu, false);
401	405	calculate_cpu_foreign_map();
402		− cpumask_clear_cpu(cpu, &cpu_callin_map);
403	406
404	407	return 0;
405	408	}

arch/mips/kernel/smp.c+9−25

@@ -48,8 +48,6 @@ · 47 unmodified lines
48	48	#include <asm/setup.h>
49	49	#include <asm/maar.h>
50	50
51		−cpumask_t cpu_callin_map; /* Bitmask of started secondaries */
52		−
53	51	int __cpu_number_map[NR_CPUS]; /* Map physical to logical */
54	52	EXPORT_SYMBOL(__cpu_number_map);
55	53
@@ -68,6 +66,8 @@ EXPORT_SYMBOL(cpu_sibling_map); · 12 unmodified lines
68	66	cpumask_t cpu_core_map[NR_CPUS] __read_mostly;
69	67	EXPORT_SYMBOL(cpu_core_map);
70	68
	69	+static DECLARE_COMPLETION(cpu_running);
	70	+
71	71	/*
72	72	* A logcal cpu mask containing only one VPE per core to
73	73	* reduce the number of IPIs on large MT systems.
@@ -369,7 +369,7 @@ asmlinkage void start_secondary(void) · 295 unmodified lines
369	369	cpumask_set_cpu(cpu, &cpu_coherent_mask);
370	370	notify_cpu_starting(cpu);
371	371
372		− cpumask_set_cpu(cpu, &cpu_callin_map);
	372	+ complete(&cpu_running);
373	373	synchronise_count_slave(cpu);
374	374
375	375	set_cpu_online(cpu, true);
@@ -430,7 +430,6 @@ void smp_prepare_boot_cpu(void) · 54 unmodified lines
430	430	{
431	431	set_cpu_possible(0, true);
432	432	set_cpu_online(0, true);
433		− cpumask_set_cpu(0, &cpu_callin_map);
434	433	}
435	434
436	435	int __cpu_up(unsigned int cpu, struct task_struct *tidle)
@@ -438,11 +437,13 @@ int __cpu_up(unsigned int cpu, struct task_struct *tidle) · 1 unmodified line
438	437	mp_ops->boot_secondary(cpu, tidle);
439	438
440	439	/*
441		− * Trust is futile. We should really have timeouts ...
	440	+ * We must check for timeout here, as the CPU will not be marked
	441	+ * online until the counters are synchronised.
442	442	*/
443		− while (!cpumask_test_cpu(cpu, &cpu_callin_map)) {
444		− udelay(100);
445		− schedule();
	443	+ if (!wait_for_completion_timeout(&cpu_running,
	444	+ msecs_to_jiffies(1000))) {
	445	+ pr_crit("CPU%u: failed to start\n", cpu);
	446	+ return -EIO;
446	447	}
447	448
448	449	synchronise_count_master(cpu);
@@ -637,23 +638,6 @@ void flush_tlb_one(unsigned long vaddr) · 188 unmodified lines
637	638	EXPORT_SYMBOL(flush_tlb_page);
638	639	EXPORT_SYMBOL(flush_tlb_one);
639	640
640		−#if defined(CONFIG_KEXEC)
641		−void (dump_ipi_function_ptr)(void ) = NULL;
642		−void dump_send_ipi(void (dump_ipi_callback)(void ))
643		−{
644		− int i;
645		− int cpu = smp_processor_id();
646		−
647		− dump_ipi_function_ptr = dump_ipi_callback;
648		− smp_mb();
649		− for_each_online_cpu(i)
650		− if (i != cpu)
651		− mp_ops->send_ipi_single(i, SMP_DUMP);
652		−
653		−}
654		−EXPORT_SYMBOL(dump_send_ipi);
655		−#endif
656		−
657	641	#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
658	642
659	643	static DEFINE_PER_CPU(atomic_t, tick_broadcast_count);

arch/mips/kernel/sync-r4k.c+2−2

@@ -29,7 +29,7 @@ void synchronise_count_master(int cpu) · 28 unmodified lines
29	29	int i;
30	30	unsigned long flags;
31	31
32		− printk(KERN_INFO "Synchronize counters for CPU %u: ", cpu);
	32	+ pr_info("Synchronize counters for CPU %u: ", cpu);
33	33
34	34	local_irq_save(flags);
35	35
@@ -83,7 +83,7 @@ void synchronise_count_master(int cpu) · 47 unmodified lines
83	83	* count registers were almost certainly out of sync
84	84	* so no point in alarming people
85	85	*/
86		− printk("done.\n");
	86	+ pr_cont("done.\n");
87	87	}
88	88
89	89	void synchronise_count_slave(int cpu)

arch/mips/kernel/syscall.c+2−10

@@ -36,7 +36,6 @@ · 35 unmodified lines
36	36	#include <asm/sim.h>
37	37	#include <asm/shmparam.h>
38	38	#include <asm/sysmips.h>
39		−#include <linux/uaccess.h>
40	39	#include <asm/switch_to.h>
41	40
42	41	/*
@@ -60,16 +59,9 @@ SYSCALL_DEFINE6(mips_mmap, unsigned long, addr, unsigned long, len, · 17 unmodified lines
60	59	unsigned long, prot, unsigned long, flags, unsigned long,
61	60	fd, off_t, offset)
62	61	{
63		− unsigned long result;
64		−
65		− result = -EINVAL;
66	62	if (offset & ~PAGE_MASK)
67		− goto out;
68		−
69		− result = sys_mmap_pgoff(addr, len, prot, flags, fd, offset >> PAGE_SHIFT);
70		−
71		−out:
72		− return result;
	63	+ return -EINVAL;
	64	+ return sys_mmap_pgoff(addr, len, prot, flags, fd, offset >> PAGE_SHIFT);
73	65	}
74	66
75	67	SYSCALL_DEFINE6(mips_mmap2, unsigned long, addr, unsigned long, len,

arch/mips/kernel/traps.c+60−5

@@ -51,6 +51,7 @@ · 50 unmodified lines
51	51	#include <asm/idle.h>
52	52	#include <asm/mips-cm.h>
53	53	#include <asm/mips-r2-to-r6-emul.h>
	54	+#include <asm/mips-cm.h>
54	55	#include <asm/mipsregs.h>
55	56	#include <asm/mipsmtregs.h>
56	57	#include <asm/module.h>
@@ -1107,7 +1108,6 @@ asmlinkage void do_ri(struct pt_regs *regs) · 1050 unmodified lines
1107	1108	switch (status) {
1108	1109	case 0:
1109	1110	case SIGEMT:
1110		− task_thread_info(current)->r2_emul_return = 1;
1111	1111	return;
1112	1112	case SIGILL:
1113	1113	goto no_r2_instr;
@@ -1115,7 +1115,6 @@ asmlinkage void do_ri(struct pt_regs *regs) · 1 unmodified line
1115	1115	process_fpemu_return(status,
1116	1116	&current->thread.cp0_baduaddr,
1117	1117	fcr31);
1118		− task_thread_info(current)->r2_emul_return = 1;
1119	1118	return;
1120	1119	}
1121	1120	}
@@ -1644,6 +1643,65 @@ __setup("nol2par", nol2parity); · 522 unmodified lines
1644	1643	*/
1645	1644	static inline void parity_protection_init(void)
1646	1645	{
	1646	+#define ERRCTL_PE 0x80000000
	1647	+#define ERRCTL_L2P 0x00800000
	1648	+
	1649	+ if (mips_cm_revision() >= CM_REV_CM3) {
	1650	+ ulong gcr_ectl, cp0_ectl;
	1651	+
	1652	+ /*
	1653	+ * With CM3 systems we need to ensure that the L1 & L2
	1654	+ * parity enables are set to the same value, since this
	1655	+ * is presumed by the hardware engineers.
	1656	+ *
	1657	+ * If the user disabled either of L1 or L2 ECC checking,
	1658	+ * disable both.
	1659	+ */
	1660	+ l1parity &= l2parity;
	1661	+ l2parity &= l1parity;
	1662	+
	1663	+ /* Probe L1 ECC support */
	1664	+ cp0_ectl = read_c0_ecc();
	1665	+ write_c0_ecc(cp0_ectl \| ERRCTL_PE);
	1666	+ back_to_back_c0_hazard();
	1667	+ cp0_ectl = read_c0_ecc();
	1668	+
	1669	+ /* Probe L2 ECC support */
	1670	+ gcr_ectl = read_gcr_err_control();
	1671	+
	1672	+ if (!(gcr_ectl & CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT_MSK) \|\|
	1673	+ !(cp0_ectl & ERRCTL_PE)) {
	1674	+ /*
	1675	+ * One of L1 or L2 ECC checking isn't supported,
	1676	+ * so we cannot enable either.
	1677	+ */
	1678	+ l1parity = l2parity = 0;
	1679	+ }
	1680	+
	1681	+ /* Configure L1 ECC checking */
	1682	+ if (l1parity)
	1683	+ cp0_ectl \|= ERRCTL_PE;
	1684	+ else
	1685	+ cp0_ectl &= ~ERRCTL_PE;
	1686	+ write_c0_ecc(cp0_ectl);
	1687	+ back_to_back_c0_hazard();
	1688	+ WARN_ON(!!(read_c0_ecc() & ERRCTL_PE) != l1parity);
	1689	+
	1690	+ /* Configure L2 ECC checking */
	1691	+ if (l2parity)
	1692	+ gcr_ectl \|= CM_GCR_ERR_CONTROL_L2_ECC_EN_MSK;
	1693	+ else
	1694	+ gcr_ectl &= ~CM_GCR_ERR_CONTROL_L2_ECC_EN_MSK;
	1695	+ write_gcr_err_control(gcr_ectl);
	1696	+ gcr_ectl = read_gcr_err_control();
	1697	+ gcr_ectl &= CM_GCR_ERR_CONTROL_L2_ECC_EN_MSK;
	1698	+ WARN_ON(!!gcr_ectl != l2parity);
	1699	+
	1700	+ pr_info("Cache parity protection %sabled\n",
	1701	+ l1parity ? "en" : "dis");
	1702	+ return;
	1703	+ }
	1704	+
1647	1705	switch (current_cpu_type()) {
1648	1706	case CPU_24K:
1649	1707	case CPU_34K:
@@ -1654,11 +1712,8 @@ static inline void parity_protection_init(void) · 4 unmodified lines
1654	1712	case CPU_PROAPTIV:
1655	1713	case CPU_P5600:
1656	1714	case CPU_QEMU_GENERIC:
1657		− case CPU_I6400:
1658	1715	case CPU_P6600:
1659	1716	{
1660		−#define ERRCTL_PE 0x80000000
1661		−#define ERRCTL_L2P 0x00800000
1662	1717	unsigned long errctl;
1663	1718	unsigned int l1parity_present, l2parity_present;
1664	1719

arch/mips/kernel/uprobes.c+1−1

@@ -226,7 +226,7 @@ int __weak set_swbp(struct arch_uprobe auprobe, struct mm_struct mm, · 225 unmodified lines
226	226	return uprobe_write_opcode(mm, vaddr, UPROBE_SWBP_INSN);
227	227	}
228	228
229		−void __weak arch_uprobe_copy_ixol(struct page *page, unsigned long vaddr,
	229	+void arch_uprobe_copy_ixol(struct page *page, unsigned long vaddr,
230	230	void *src, unsigned long len)
231	231	{
232	232	unsigned long kaddr, kstart;

arch/mips/kernel/vmlinux.lds.S+1−1

@@ -182,7 +182,7 @@ SECTIONS · 181 unmodified lines
182	182	* Force .bss to 64K alignment so that .bss..swapper_pg_dir
183	183	* gets that alignment. .sbss should be empty, so there will be
184	184	* no holes after __init_end. */
185		− BSS_SECTION(0, 0x10000, 0)
	185	+ BSS_SECTION(0, 0x10000, 8)
186	186
187	187	_end = . ;
188	188

arch/mips/lantiq/irq.c+17−21

@@ -269,6 +269,11 @@ static void ltq_hw5_irqdispatch(void) · 268 unmodified lines
269	269	DEFINE_HWx_IRQDISPATCH(5)
270	270	#endif
271	271
	272	+static void ltq_hw_irq_handler(struct irq_desc *desc)
	273	+{
	274	+ ltq_hw_irqdispatch(irq_desc_get_irq(desc) - 2);
	275	+}
	276	+
272	277	#ifdef CONFIG_MIPS_MT_SMP
273	278	void __init arch_init_ipiirq(int irq, struct irqaction *action)
274	279	{
@@ -313,23 +318,19 @@ static struct irqaction irq_call = { · 38 unmodified lines
313	318	asmlinkage void plat_irq_dispatch(void)
314	319	{
315	320	unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
316		− unsigned int i;
317		−
318		− if ((MIPS_CPU_TIMER_IRQ == 7) && (pending & CAUSEF_IP7)) {
319		− do_IRQ(MIPS_CPU_TIMER_IRQ);
320		− goto out;
321		− } else {
322		− for (i = 0; i < MAX_IM; i++) {
323		− if (pending & (CAUSEF_IP2 << i)) {
324		− ltq_hw_irqdispatch(i);
325		− goto out;
326		− }
327		− }
	321	+ int irq;
	322	+
	323	+ if (!pending) {
	324	+ spurious_interrupt();
	325	+ return;
328	326	}
329		− pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
330	327
331		−out:
332		− return;
	328	+ pending >>= CAUSEB_IP;
	329	+ while (pending) {
	330	+ irq = fls(pending) - 1;
	331	+ do_IRQ(MIPS_CPU_IRQ_BASE + irq);
	332	+ pending &= ~BIT(irq);
	333	+ }
333	334	}
334	335
335	336	static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
@@ -354,11 +355,6 @@ static const struct irq_domain_ops irq_domain_ops = { · 18 unmodified lines
354	355	.map = icu_map,
355	356	};
356	357
357		−static struct irqaction cascade = {
358		− .handler = no_action,
359		− .name = "cascade",
360		−};
361		−
362	358	int __init icu_of_init(struct device_node node, struct device_node parent)
363	359	{
364	360	struct device_node *eiu_node;
@@ -390,7 +386,7 @@ int __init icu_of_init(struct device_node node, struct device_node parent) · 25 unmodified lines
390	386	mips_cpu_irq_init();
391	387
392	388	for (i = 0; i < MAX_IM; i++)
393		− setup_irq(i + 2, &cascade);
	389	+ irq_set_chained_handler(i + 2, ltq_hw_irq_handler);
394	390
395	391	if (cpu_has_vint) {
396	392	pr_info("Setting up vectored interrupts\n");

arch/mips/lantiq/prom.c+6−0

@@ -25,6 +25,12 @@ · 24 unmodified lines
25	25	DEFINE_SPINLOCK(ebu_lock);
26	26	EXPORT_SYMBOL_GPL(ebu_lock);
27	27
	28	+/*
	29	+ * This is needed by the VPE loader code, just set it to 0 and assume
	30	+ * that the firmware hardcodes this value to something useful.
	31	+ */
	32	+unsigned long physical_memsize = 0L;
	33	+
28	34	/*
29	35	* this struct is filled by the soc specific detection code and holds
30	36	* information about the specific soc type, revision and name

arch/mips/lantiq/xway/dma.c+21−20

@@ -19,7 +19,8 @@ · 18 unmodified lines
19	19	#include <linux/platform_device.h>
20	20	#include <linux/io.h>
21	21	#include <linux/dma-mapping.h>
22		−#include <linux/module.h>
	22	+#include <linux/export.h>
	23	+#include <linux/spinlock.h>
23	24	#include <linux/clk.h>
24	25	#include <linux/err.h>
25	26
@@ -59,16 +60,17 @@ · 33 unmodified lines
59	60	ltq_dma_membase + (z))
60	61
61	62	static void __iomem *ltq_dma_membase;
	63	+static DEFINE_SPINLOCK(ltq_dma_lock);
62	64
63	65	void
64	66	ltq_dma_enable_irq(struct ltq_dma_channel *ch)
65	67	{
66	68	unsigned long flags;
67	69
68		− local_irq_save(flags);
	70	+ spin_lock_irqsave(&ltq_dma_lock, flags);
69	71	ltq_dma_w32(ch->nr, LTQ_DMA_CS);
70	72	ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
71		− local_irq_restore(flags);
	73	+ spin_unlock_irqrestore(&ltq_dma_lock, flags);
72	74	}
73	75	EXPORT_SYMBOL_GPL(ltq_dma_enable_irq);
74	76
@@ -77,10 +79,10 @@ ltq_dma_disable_irq(struct ltq_dma_channel *ch) · 2 unmodified lines
77	79	{
78	80	unsigned long flags;
79	81
80		− local_irq_save(flags);
	82	+ spin_lock_irqsave(&ltq_dma_lock, flags);
81	83	ltq_dma_w32(ch->nr, LTQ_DMA_CS);
82	84	ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN);
83		− local_irq_restore(flags);
	85	+ spin_unlock_irqrestore(&ltq_dma_lock, flags);
84	86	}
85	87	EXPORT_SYMBOL_GPL(ltq_dma_disable_irq);
86	88
@@ -89,10 +91,10 @@ ltq_dma_ack_irq(struct ltq_dma_channel *ch) · 2 unmodified lines
89	91	{
90	92	unsigned long flags;
91	93
92		− local_irq_save(flags);
	94	+ spin_lock_irqsave(&ltq_dma_lock, flags);
93	95	ltq_dma_w32(ch->nr, LTQ_DMA_CS);
94	96	ltq_dma_w32(DMA_IRQ_ACK, LTQ_DMA_CIS);
95		− local_irq_restore(flags);
	97	+ spin_unlock_irqrestore(&ltq_dma_lock, flags);
96	98	}
97	99	EXPORT_SYMBOL_GPL(ltq_dma_ack_irq);
98	100
@@ -101,11 +103,11 @@ ltq_dma_open(struct ltq_dma_channel *ch) · 2 unmodified lines
101	103	{
102	104	unsigned long flag;
103	105
104		− local_irq_save(flag);
	106	+ spin_lock_irqsave(&ltq_dma_lock, flag);
105	107	ltq_dma_w32(ch->nr, LTQ_DMA_CS);
106	108	ltq_dma_w32_mask(0, DMA_CHAN_ON, LTQ_DMA_CCTRL);
107		− ltq_dma_enable_irq(ch);
108		− local_irq_restore(flag);
	109	+ ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
	110	+ spin_unlock_irqrestore(&ltq_dma_lock, flag);
109	111	}
110	112	EXPORT_SYMBOL_GPL(ltq_dma_open);
111	113
@@ -114,11 +116,11 @@ ltq_dma_close(struct ltq_dma_channel *ch) · 2 unmodified lines
114	116	{
115	117	unsigned long flag;
116	118
117		− local_irq_save(flag);
	119	+ spin_lock_irqsave(&ltq_dma_lock, flag);
118	120	ltq_dma_w32(ch->nr, LTQ_DMA_CS);
119	121	ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
120		− ltq_dma_disable_irq(ch);
121		− local_irq_restore(flag);
	122	+ ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN);
	123	+ spin_unlock_irqrestore(&ltq_dma_lock, flag);
122	124	}
123	125	EXPORT_SYMBOL_GPL(ltq_dma_close);
124	126
@@ -133,7 +135,7 @@ ltq_dma_alloc(struct ltq_dma_channel *ch) · 8 unmodified lines
133	135	&ch->phys, GFP_ATOMIC);
134	136	memset(ch->desc_base, 0, LTQ_DESC_NUM * LTQ_DESC_SIZE);
135	137
136		− local_irq_save(flags);
	138	+ spin_lock_irqsave(&ltq_dma_lock, flags);
137	139	ltq_dma_w32(ch->nr, LTQ_DMA_CS);
138	140	ltq_dma_w32(ch->phys, LTQ_DMA_CDBA);
139	141	ltq_dma_w32(LTQ_DESC_NUM, LTQ_DMA_CDLEN);
@@ -142,7 +144,7 @@ ltq_dma_alloc(struct ltq_dma_channel *ch) · 2 unmodified lines
142	144	ltq_dma_w32_mask(0, DMA_CHAN_RST, LTQ_DMA_CCTRL);
143	145	while (ltq_dma_r32(LTQ_DMA_CCTRL) & DMA_CHAN_RST)
144	146	;
145		− local_irq_restore(flags);
	147	+ spin_unlock_irqrestore(&ltq_dma_lock, flags);
146	148	}
147	149
148	150	void
@@ -152,11 +154,11 @@ ltq_dma_alloc_tx(struct ltq_dma_channel *ch) · 3 unmodified lines
152	154
153	155	ltq_dma_alloc(ch);
154	156
155		− local_irq_save(flags);
	157	+ spin_lock_irqsave(&ltq_dma_lock, flags);
156	158	ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE);
157	159	ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
158	160	ltq_dma_w32(DMA_WEIGHT \| DMA_TX, LTQ_DMA_CCTRL);
159		− local_irq_restore(flags);
	161	+ spin_unlock_irqrestore(&ltq_dma_lock, flags);
160	162	}
161	163	EXPORT_SYMBOL_GPL(ltq_dma_alloc_tx);
162	164
@@ -167,11 +169,11 @@ ltq_dma_alloc_rx(struct ltq_dma_channel *ch) · 4 unmodified lines
167	169
168	170	ltq_dma_alloc(ch);
169	171
170		− local_irq_save(flags);
	172	+ spin_lock_irqsave(&ltq_dma_lock, flags);
171	173	ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE);
172	174	ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
173	175	ltq_dma_w32(DMA_WEIGHT, LTQ_DMA_CCTRL);
174		− local_irq_restore(flags);
	176	+ spin_unlock_irqrestore(&ltq_dma_lock, flags);
175	177	}
176	178	EXPORT_SYMBOL_GPL(ltq_dma_alloc_rx);
177	179
@@ -255,7 +257,6 @@ static const struct of_device_id dma_match[] = { · 77 unmodified lines
255	257	{ .compatible = "lantiq,dma-xway" },
256	258	{},
257	259	};
258		−MODULE_DEVICE_TABLE(of, dma_match);
259	260
260	261	static struct platform_driver dma_driver = {
261	262	.probe = ltq_dma_init,

arch/mips/lantiq/xway/gptu.c+1−2

@@ -9,7 +9,7 @@ · 8 unmodified lines
9	9
10	10	#include <linux/interrupt.h>
11	11	#include <linux/ioport.h>
12		−#include <linux/module.h>
	12	+#include <linux/init.h>
13	13	#include <linux/of_platform.h>
14	14	#include <linux/of_irq.h>
15	15
@@ -187,7 +187,6 @@ static const struct of_device_id gptu_match[] = { · 171 unmodified lines
187	187	{ .compatible = "lantiq,gptu-xway" },
188	188	{},
189	189	};
190		−MODULE_DEVICE_TABLE(of, dma_match);
191	190
192	191	static struct platform_driver dma_driver = {
193	192	.probe = gptu_probe,

arch/mips/lantiq/xway/sysctrl.c+6−6

@@ -469,8 +469,8 @@ void __init ltq_soc_init(void) · 468 unmodified lines
469	469	panic("Failed to load xbar nodes from devicetree");
470	470	if (of_address_to_resource(np_pmu, 0, &res_xbar))
471	471	panic("Failed to get xbar resources");
472		− if (request_mem_region(res_xbar.start, resource_size(&res_xbar),
473		− res_xbar.name) < 0)
	472	+ if (!request_mem_region(res_xbar.start, resource_size(&res_xbar),
	473	+ res_xbar.name))
474	474	panic("Failed to get xbar resources");
475	475
476	476	ltq_xbar_membase = ioremap_nocache(res_xbar.start,
@@ -545,7 +545,7 @@ void __init ltq_soc_init(void) · 68 unmodified lines
545	545	clkdev_add_pmu("1a800000.pcie", "msi", 1, 1, PMU1_PCIE2_MSI);
546	546	clkdev_add_pmu("1a800000.pcie", "pdi", 1, 1, PMU1_PCIE2_PDI);
547	547	clkdev_add_pmu("1a800000.pcie", "ctl", 1, 1, PMU1_PCIE2_CTL);
548		− clkdev_add_pmu("1e108000.eth", NULL, 1, 0, PMU_SWITCH \| PMU_PPE_DP);
	548	+ clkdev_add_pmu("1e108000.eth", NULL, 0, 0, PMU_SWITCH \| PMU_PPE_DP);
549	549	clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
550	550	clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
551	551	} else if (of_machine_is_compatible("lantiq,ar10")) {
@@ -553,7 +553,7 @@ void __init ltq_soc_init(void) · 1 unmodified line
553	553	ltq_ar10_fpi_hz(), ltq_ar10_pp32_hz());
554	554	clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
555	555	clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);
556		− clkdev_add_pmu("1e108000.eth", NULL, 1, 0, PMU_SWITCH \|
	556	+ clkdev_add_pmu("1e108000.eth", NULL, 0, 0, PMU_SWITCH \|
557	557	PMU_PPE_DP \| PMU_PPE_TC);
558	558	clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
559	559	clkdev_add_pmu("1f203000.rcu", "gphy", 1, 0, PMU_GPHY);
@@ -575,11 +575,11 @@ void __init ltq_soc_init(void) · 15 unmodified lines
575	575	clkdev_add_pmu(NULL, "ahb", 1, 0, PMU_AHBM \| PMU_AHBS);
576	576
577	577	clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
578		− clkdev_add_pmu("1e108000.eth", NULL, 1, 0,
	578	+ clkdev_add_pmu("1e108000.eth", NULL, 0, 0,
579	579	PMU_SWITCH \| PMU_PPE_DPLUS \| PMU_PPE_DPLUM \|
580	580	PMU_PPE_EMA \| PMU_PPE_TC \| PMU_PPE_SLL01 \|
581	581	PMU_PPE_QSB \| PMU_PPE_TOP);
582		− clkdev_add_pmu("1f203000.rcu", "gphy", 1, 0, PMU_GPHY);
	582	+ clkdev_add_pmu("1f203000.rcu", "gphy", 0, 0, PMU_GPHY);
583	583	clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
584	584	clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
585	585	clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);

arch/mips/lasat/at93c.c+0−1

@@ -7,7 +7,6 @@ · 6 unmodified lines
7	7	#include <linux/kernel.h>
8	8	#include <linux/delay.h>
9	9	#include <asm/lasat/lasat.h>
10		−#include <linux/module.h>
11	10
12	11	#include "at93c.h"
13	12

arch/mips/lasat/sysctl.c+0−1

@@ -20,7 +20,6 @@ · 19 unmodified lines
20	20	#include <linux/types.h>
21	21	#include <asm/lasat/lasat.h>
22	22
23		−#include <linux/module.h>
24	23	#include <linux/sysctl.h>
25	24	#include <linux/stddef.h>
26	25	#include <linux/init.h>

arch/mips/lib/csum_partial.S+6−0

@@ -13,6 +13,7 @@ · 12 unmodified lines
13	13	#include <linux/errno.h>
14	14	#include <asm/asm.h>
15	15	#include <asm/asm-offsets.h>
	16	+#include <asm/export.h>
16	17	#include <asm/regdef.h>
17	18
18	19	#ifdef CONFIG_64BIT
@@ -103,6 +104,7 @@ · 84 unmodified lines
103	104	.set noreorder
104	105	.align 5
105	106	LEAF(csum_partial)
	107	+EXPORT_SYMBOL(csum_partial)
106	108	move sum, zero
107	109	move t7, zero
108	110
@@ -460,6 +462,7 @@ LEAF(csum_partial) · 351 unmodified lines
460	462	#endif
461	463	.if \__nocheck == 1
462	464	FEXPORT(csum_partial_copy_nocheck)
	465	+ EXPORT_SYMBOL(csum_partial_copy_nocheck)
463	466	.endif
464	467	move sum, zero
465	468	move odd, zero
@@ -823,9 +826,12 @@ LEAF(csum_partial) · 357 unmodified lines
823	826	.endm
824	827
825	828	LEAF(__csum_partial_copy_kernel)
	829	+EXPORT_SYMBOL(__csum_partial_copy_kernel)
826	830	#ifndef CONFIG_EVA
827	831	FEXPORT(__csum_partial_copy_to_user)
	832	+EXPORT_SYMBOL(__csum_partial_copy_to_user)
828	833	FEXPORT(__csum_partial_copy_from_user)
	834	+EXPORT_SYMBOL(__csum_partial_copy_from_user)
829	835	#endif
830	836	__BUILD_CSUM_PARTIAL_COPY_USER LEGACY_MODE USEROP USEROP 1
831	837	END(__csum_partial_copy_kernel)

arch/mips/lib/memcpy.S+9−0

@@ -31,6 +31,7 @@ · 30 unmodified lines
31	31
32	32	#include <asm/asm.h>
33	33	#include <asm/asm-offsets.h>
	34	+#include <asm/export.h>
34	35	#include <asm/regdef.h>
35	36
36	37	#define dst a0
@@ -622,6 +623,7 @@ SEXC(1) · 585 unmodified lines
622	623
623	624	.align 5
624	625	LEAF(memmove)
	626	+EXPORT_SYMBOL(memmove)
625	627	ADD t0, a0, a2
626	628	ADD t1, a1, a2
627	629	sltu t0, a1, t0 # dst + len <= src -> memcpy
@@ -674,6 +676,7 @@ LEAF(__rmemcpy) /* a0=dst a1=src a2=len */ · 46 unmodified lines
674	676	* t6 is used as a flag to note inatomic mode.
675	677	*/
676	678	LEAF(__copy_user_inatomic)
	679	+EXPORT_SYMBOL(__copy_user_inatomic)
677	680	b __copy_user_common
678	681	li t6, 1
679	682	END(__copy_user_inatomic)
@@ -686,9 +689,11 @@ LEAF(__copy_user_inatomic) · 6 unmodified lines
686	689	*/
687	690	.align 5
688	691	LEAF(memcpy) /* a0=dst a1=src a2=len */
	692	+EXPORT_SYMBOL(memcpy)
689	693	move v0, dst /* return value */
690	694	.L__memcpy:
691	695	FEXPORT(__copy_user)
	696	+EXPORT_SYMBOL(__copy_user)
692	697	li t6, 0 /* not inatomic */
693	698	__copy_user_common:
694	699	/* Legacy Mode, user <-> user */
@@ -704,6 +709,7 @@ __copy_user_common: · 9 unmodified lines
704	709	*/
705	710
706	711	LEAF(__copy_user_inatomic_eva)
	712	+EXPORT_SYMBOL(__copy_user_inatomic_eva)
707	713	b __copy_from_user_common
708	714	li t6, 1
709	715	END(__copy_user_inatomic_eva)
@@ -713,6 +719,7 @@ LEAF(__copy_user_inatomic_eva) · 3 unmodified lines
713	719	*/
714	720
715	721	LEAF(__copy_from_user_eva)
	722	+EXPORT_SYMBOL(__copy_from_user_eva)
716	723	li t6, 0 /* not inatomic */
717	724	__copy_from_user_common:
718	725	__BUILD_COPY_USER EVA_MODE USEROP KERNELOP
@@ -725,6 +732,7 @@ END(__copy_from_user_eva) · 6 unmodified lines
725	732	*/
726	733
727	734	LEAF(__copy_to_user_eva)
	735	+EXPORT_SYMBOL(__copy_to_user_eva)
728	736	__BUILD_COPY_USER EVA_MODE KERNELOP USEROP
729	737	END(__copy_to_user_eva)
730	738
@@ -733,6 +741,7 @@ END(__copy_to_user_eva) · 2 unmodified lines
733	741	*/
734	742
735	743	LEAF(__copy_in_user_eva)
	744	+EXPORT_SYMBOL(__copy_in_user_eva)
736	745	__BUILD_COPY_USER EVA_MODE USEROP USEROP
737	746	END(__copy_in_user_eva)
738	747

arch/mips/lib/memset.S+5−0

@@ -10,6 +10,7 @@ · 9 unmodified lines
10	10	*/
11	11	#include <asm/asm.h>
12	12	#include <asm/asm-offsets.h>
	13	+#include <asm/export.h>
13	14	#include <asm/regdef.h>
14	15
15	16	#if LONGSIZE == 4
@@ -270,6 +271,7 @@ · 254 unmodified lines
270	271	*/
271	272
272	273	LEAF(memset)
	274	+EXPORT_SYMBOL(memset)
273	275	beqz a1, 1f
274	276	move v0, a0 /* result */
275	277
@@ -285,13 +287,16 @@ LEAF(memset) · 9 unmodified lines
285	287	1:
286	288	#ifndef CONFIG_EVA
287	289	FEXPORT(__bzero)
	290	+EXPORT_SYMBOL(__bzero)
288	291	#else
289	292	FEXPORT(__bzero_kernel)
	293	+EXPORT_SYMBOL(__bzero_kernel)
290	294	#endif
291	295	__BUILD_BZERO LEGACY_MODE
292	296
293	297	#ifdef CONFIG_EVA
294	298	LEAF(__bzero)
	299	+EXPORT_SYMBOL(__bzero)
295	300	__BUILD_BZERO EVA_MODE
296	301	END(__bzero)
297	302	#endif

arch/mips/lib/strlen_user.S+4−0

@@ -9,6 +9,7 @@ · 8 unmodified lines
9	9	*/
10	10	#include <asm/asm.h>
11	11	#include <asm/asm-offsets.h>
	12	+#include <asm/export.h>
12	13	#include <asm/regdef.h>
13	14
14	15	#define EX(insn,reg,addr,handler) \
@@ -48,9 +49,11 @@ LEAF(__strlen_\func\()_asm) · 33 unmodified lines
48	49	/* Set aliases */
49	50	.global __strlen_user_asm
50	51	.set __strlen_user_asm, __strlen_kernel_asm
	52	+EXPORT_SYMBOL(__strlen_user_asm)
51	53	#endif
52	54
53	55	__BUILD_STRLEN_ASM kernel
	56	+EXPORT_SYMBOL(__strlen_kernel_asm)
54	57
55	58	#ifdef CONFIG_EVA
56	59
@@ -58,4 +61,5 @@ __BUILD_STRLEN_ASM kernel · 1 unmodified line
58	61	.set eva
59	62	__BUILD_STRLEN_ASM user
60	63	.set pop
	64	+EXPORT_SYMBOL(__strlen_user_asm)
61	65	#endif

arch/mips/lib/strncpy_user.S+7−0

@@ -9,6 +9,7 @@ · 8 unmodified lines
9	9	#include <linux/errno.h>
10	10	#include <asm/asm.h>
11	11	#include <asm/asm-offsets.h>
	12	+#include <asm/export.h>
12	13	#include <asm/regdef.h>
13	14
14	15	#define EX(insn,reg,addr,handler) \
@@ -72,13 +73,19 @@ FEXPORT(__strncpy_from_\func\()_nocheck_asm) · 57 unmodified lines
72	73	.global __strncpy_from_user_nocheck_asm
73	74	.set __strncpy_from_user_asm, __strncpy_from_kernel_asm
74	75	.set __strncpy_from_user_nocheck_asm, __strncpy_from_kernel_nocheck_asm
	76	+EXPORT_SYMBOL(__strncpy_from_user_asm)
	77	+EXPORT_SYMBOL(__strncpy_from_user_nocheck_asm)
75	78	#endif
76	79
77	80	__BUILD_STRNCPY_ASM kernel
	81	+EXPORT_SYMBOL(__strncpy_from_kernel_asm)
	82	+EXPORT_SYMBOL(__strncpy_from_kernel_nocheck_asm)
78	83
79	84	#ifdef CONFIG_EVA
80	85	.set push
81	86	.set eva
82	87	__BUILD_STRNCPY_ASM user
83	88	.set pop
	89	+EXPORT_SYMBOL(__strncpy_from_user_asm)
	90	+EXPORT_SYMBOL(__strncpy_from_user_nocheck_asm)
84	91	#endif

arch/mips/lib/strnlen_user.S+7−0

@@ -8,6 +8,7 @@ · 7 unmodified lines
8	8	*/
9	9	#include <asm/asm.h>
10	10	#include <asm/asm-offsets.h>
	11	+#include <asm/export.h>
11	12	#include <asm/regdef.h>
12	13
13	14	#define EX(insn,reg,addr,handler) \
@@ -70,9 +71,13 @@ FEXPORT(__strnlen_\func\()_nocheck_asm) · 56 unmodified lines
70	71	.global __strnlen_user_nocheck_asm
71	72	.set __strnlen_user_asm, __strnlen_kernel_asm
72	73	.set __strnlen_user_nocheck_asm, __strnlen_kernel_nocheck_asm
	74	+EXPORT_SYMBOL(__strnlen_user_asm)
	75	+EXPORT_SYMBOL(__strnlen_user_nocheck_asm)
73	76	#endif
74	77
75	78	__BUILD_STRNLEN_ASM kernel
	79	+EXPORT_SYMBOL(__strnlen_kernel_asm)
	80	+EXPORT_SYMBOL(__strnlen_kernel_nocheck_asm)
76	81
77	82	#ifdef CONFIG_EVA
78	83
@@ -80,4 +85,6 @@ __BUILD_STRNLEN_ASM kernel · 1 unmodified line
80	85	.set eva
81	86	__BUILD_STRNLEN_ASM user
82	87	.set pop
	88	+EXPORT_SYMBOL(__strnlen_user_asm)
	89	+EXPORT_SYMBOL(__strnlen_user_nocheck_asm)
83	90	#endif

arch/mips/loongson32/common/platform.c+28−17

@@ -1,9 +1,9 @@
1	1	/*
2	2	* Copyright (c) 2011-2016 Zhang, Keguang <keguang.zhang@gmail.com>
3	3	*
4		− * This program is free software; you can redistribute it and/or modify it
5		− * under the terms of the GNU General Public License as published by the
6		− * Free Software Foundation; either version 2 of the License, or (at your
	4	+ * This program is free software; you can redistribute it and/or modify it
	5	+ * under the terms of the GNU General Public License as published by the
	6	+ * Free Software Foundation; either version 2 of the License, or (at your
7	7	* option) any later version.
8	8	*/
9	9
@@ -23,10 +23,6 @@ · 13 unmodified lines
23	23	#include <dma.h>
24	24	#include <nand.h>
25	25
26		−#define LS1X_RTC_CTRL ((void __iomem *)KSEG1ADDR(LS1X_RTC_BASE + 0x40))
27		−#define RTC_EXTCLK_OK (BIT(5) \| BIT(8))
28		−#define RTC_EXTCLK_EN BIT(8)
29		−
30	26	/* 8250/16550 compatible UART */
31	27	#define LS1X_UART(_id) \
32	28	{ \
@@ -70,19 +66,10 @@ void __init ls1x_serial_set_uartclk(struct platform_device *pdev) · 37 unmodified lines
70	66	p->uartclk = clk_get_rate(clk);
71	67	}
72	68
73		−void __init ls1x_rtc_set_extclk(struct platform_device *pdev)
74		−{
75		− u32 val;
76		−
77		− val = __raw_readl(LS1X_RTC_CTRL);
78		− if (!(val & RTC_EXTCLK_OK))
79		− __raw_writel(val \| RTC_EXTCLK_EN, LS1X_RTC_CTRL);
80		−}
81		−
82	69	/* CPUFreq */
83	70	static struct plat_ls1x_cpufreq ls1x_cpufreq_pdata = {
84	71	.clk_name = "cpu_clk",
85		− .osc_clk_name = "osc_33m_clk",
	72	+ .osc_clk_name = "osc_clk",
86	73	.max_freq = 266 * 1000,
87	74	.min_freq = 33 * 1000,
88	75	};
@@ -357,7 +344,31 @@ struct platform_device ls1x_ehci_pdev = { · 268 unmodified lines
357	344	};
358	345
359	346	/* Real Time Clock */
	347	+void __init ls1x_rtc_set_extclk(struct platform_device *pdev)
	348	+{
	349	+ u32 val = __raw_readl(LS1X_RTC_CTRL);
	350	+
	351	+ if (!(val & RTC_EXTCLK_OK))
	352	+ __raw_writel(val \| RTC_EXTCLK_EN, LS1X_RTC_CTRL);
	353	+}
	354	+
360	355	struct platform_device ls1x_rtc_pdev = {
361	356	.name = "ls1x-rtc",
362	357	.id = -1,
363	358	};
	359	+
	360	+/* Watchdog */
	361	+static struct resource ls1x_wdt_resources[] = {
	362	+ {
	363	+ .start = LS1X_WDT_BASE,
	364	+ .end = LS1X_WDT_BASE + SZ_16 - 1,
	365	+ .flags = IORESOURCE_MEM,
	366	+ },
	367	+};
	368	+
	369	+struct platform_device ls1x_wdt_pdev = {
	370	+ .name = "ls1x-wdt",
	371	+ .id = -1,
	372	+ .num_resources = ARRAY_SIZE(ls1x_wdt_resources),
	373	+ .resource = ls1x_wdt_resources,
	374	+};

arch/mips/loongson32/ls1b/board.c+4−3

@@ -1,9 +1,9 @@
1	1	/*
2	2	* Copyright (c) 2011-2016 Zhang, Keguang <keguang.zhang@gmail.com>
3	3	*
4		− * This program is free software; you can redistribute it and/or modify it
5		− * under the terms of the GNU General Public License as published by the
6		− * Free Software Foundation; either version 2 of the License, or (at your
	4	+ * This program is free software; you can redistribute it and/or modify it
	5	+ * under the terms of the GNU General Public License as published by the
	6	+ * Free Software Foundation; either version 2 of the License, or (at your
7	7	* option) any later version.
8	8	*/
9	9
@@ -72,6 +72,7 @@ static struct platform_device *ls1b_platform_devices[] __initdata = { · 62 unmodified lines
72	72	&ls1x_gpio1_pdev,
73	73	&ls1x_nand_pdev,
74	74	&ls1x_rtc_pdev,
	75	+ &ls1x_wdt_pdev,
75	76	};
76	77
77	78	static int __init ls1b_platform_init(void)

arch/mips/loongson32/ls1c/board.c+4−3

@@ -1,9 +1,9 @@
1	1	/*
2	2	* Copyright (c) 2016 Yang Ling <gnaygnil@gmail.com>
3	3	*
4		− * This program is free software; you can redistribute it and/or modify it
5		− * under the terms of the GNU General Public License as published by the
6		− * Free Software Foundation; either version 2 of the License, or (at your
	4	+ * This program is free software; you can redistribute it and/or modify it
	5	+ * under the terms of the GNU General Public License as published by the
	6	+ * Free Software Foundation; either version 2 of the License, or (at your
7	7	* option) any later version.
8	8	*/
9	9
@@ -13,6 +13,7 @@ static struct platform_device *ls1c_platform_devices[] __initdata = { · 3 unmodified lines
13	13	&ls1x_uart_pdev,
14	14	&ls1x_eth0_pdev,
15	15	&ls1x_rtc_pdev,
	16	+ &ls1x_wdt_pdev,
16	17	};
17	18
18	19	static int __init ls1c_platform_init(void)

arch/mips/loongson64/common/cs5536/cs5536_mfgpt.c+1−1

@@ -17,7 +17,7 @@ · 16 unmodified lines
17	17
18	18	#include <linux/io.h>
19	19	#include <linux/init.h>
20		−#include <linux/module.h>
	20	+#include <linux/export.h>
21	21	#include <linux/jiffies.h>
22	22	#include <linux/spinlock.h>
23	23	#include <linux/interrupt.h>

arch/mips/loongson64/common/dma-swiotlb.c+6−14

@@ -17,22 +17,14 @@ static void loongson_dma_alloc_coherent(struct device dev, size_t size, · 16 unmodified lines
17	17	/* ignore region specifiers */
18	18	gfp &= ~(__GFP_DMA \| __GFP_DMA32 \| __GFP_HIGHMEM);
19	19
20		−#ifdef CONFIG_ISA
21		− if (dev == NULL)
	20	+ if ((IS_ENABLED(CONFIG_ISA) && dev == NULL) \|\|
	21	+ (IS_ENABLED(CONFIG_ZONE_DMA) &&
	22	+ dev->coherent_dma_mask < DMA_BIT_MASK(32)))
22	23	gfp \|= __GFP_DMA;
23		− else
24		−#endif
25		−#ifdef CONFIG_ZONE_DMA
26		− if (dev->coherent_dma_mask < DMA_BIT_MASK(32))
27		− gfp \|= __GFP_DMA;
28		− else
29		−#endif
30		−#ifdef CONFIG_ZONE_DMA32
31		− if (dev->coherent_dma_mask < DMA_BIT_MASK(40))
	24	+ else if (IS_ENABLED(CONFIG_ZONE_DMA32) &&
	25	+ dev->coherent_dma_mask < DMA_BIT_MASK(40))
32	26	gfp \|= __GFP_DMA32;
33		− else
34		−#endif
35		− ;
	27	+
36	28	gfp \|= __GFP_NORETRY;
37	29
38	30	ret = swiotlb_alloc_coherent(dev, size, dma_handle, gfp);

arch/mips/loongson64/common/env.c+1−1

@@ -17,7 +17,7 @@ · 16 unmodified lines
17	17	* Free Software Foundation; either version 2 of the License, or (at your
18	18	* option) any later version.
19	19	*/
20		−#include <linux/module.h>
	20	+#include <linux/export.h>
21	21	#include <asm/bootinfo.h>
22	22	#include <loongson.h>
23	23	#include <boot_param.h>

arch/mips/loongson64/common/setup.c+2−1

@@ -7,7 +7,8 @@ · 6 unmodified lines
7	7	* Free Software Foundation; either version 2 of the License, or (at your
8	8	* option) any later version.
9	9	*/
10		−#include <linux/module.h>
	10	+#include <linux/export.h>
	11	+#include <linux/init.h>
11	12
12	13	#include <asm/wbflush.h>
13	14	#include <asm/bootinfo.h>

arch/mips/loongson64/common/uart_base.c+1−1

@@ -8,7 +8,7 @@ · 7 unmodified lines
8	8	* option) any later version.
9	9	*/
10	10
11		−#include <linux/module.h>
	11	+#include <linux/export.h>
12	12	#include <asm/bootinfo.h>
13	13
14	14	#include <loongson.h>

arch/mips/loongson64/lemote-2f/ec_kb3310b.c+2−1

@@ -10,7 +10,8 @@ · 9 unmodified lines
10	10	* (at your option) any later version.
11	11	*/
12	12
13		−#include <linux/module.h>
	13	+#include <linux/io.h>
	14	+#include <linux/export.h>
14	15	#include <linux/spinlock.h>
15	16	#include <linux/delay.h>
16	17

arch/mips/loongson64/lemote-2f/irq.c+2−1

@@ -8,8 +8,9 @@ · 7 unmodified lines
8	8	* option) any later version.
9	9	*/
10	10
	11	+#include <linux/export.h>
	12	+#include <linux/init.h>
11	13	#include <linux/interrupt.h>
12		−#include <linux/module.h>
13	14
14	15	#include <asm/irq_cpu.h>
15	16	#include <asm/i8259.h>

arch/mips/loongson64/lemote-2f/pm.c+1−1

@@ -14,7 +14,7 @@ · 13 unmodified lines
14	14	#include <linux/interrupt.h>
15	15	#include <linux/pm.h>
16	16	#include <linux/i8042.h>
17		−#include <linux/module.h>
	17	+#include <linux/export.h>
18	18
19	19	#include <asm/i8259.h>
20	20	#include <asm/mipsregs.h>

arch/mips/loongson64/loongson-3/irq.c+1−1

@@ -1,7 +1,7 @@
1	1	#include <loongson.h>
2	2	#include <irq.h>
3	3	#include <linux/interrupt.h>
4		−#include <linux/module.h>
	4	+#include <linux/init.h>
5	5
6	6	#include <asm/irq_cpu.h>
7	7	#include <asm/i8259.h>

arch/mips/loongson64/loongson-3/numa.c+1−1

@@ -14,7 +14,7 @@ · 13 unmodified lines
14	14	#include <linux/kernel.h>
15	15	#include <linux/mm.h>
16	16	#include <linux/mmzone.h>
17		−#include <linux/module.h>
	17	+#include <linux/export.h>
18	18	#include <linux/nodemask.h>
19	19	#include <linux/swap.h>
20	20	#include <linux/memblock.h>

arch/mips/loongson64/loongson-3/smp.c+0−1

@@ -418,7 +418,6 @@ static int loongson3_cpu_disable(void) · 417 unmodified lines
418	418
419	419	set_cpu_online(cpu, false);
420	420	calculate_cpu_foreign_map();
421		− cpumask_clear_cpu(cpu, &cpu_callin_map);
422	421	local_irq_save(flags);
423	422	fixup_irqs();
424	423	local_irq_restore(flags);

arch/mips/mm/Makefile+1−1

@@ -4,7 +4,7 @@ · 3 unmodified lines
4	4
5	5	obj-y += cache.o dma-default.o extable.o fault.o \
6	6	gup.o init.o mmap.o page.o page-funcs.o \
7		− tlbex.o tlbex-fault.o tlb-funcs.o
	7	+ pgtable.o tlbex.o tlbex-fault.o tlb-funcs.o
8	8
9	9	ifdef CONFIG_CPU_MICROMIPS
10	10	obj-y += uasm-micromips.o

arch/mips/mm/c-r4k.c+5−1

@@ -1452,6 +1452,7 @@ static void probe_pcache(void) · 1451 unmodified lines
1452	1452	switch (current_cpu_type()) {
1453	1453	case CPU_20KC:
1454	1454	case CPU_25KF:
	1455	+ case CPU_I6400:
1455	1456	case CPU_SB1:
1456	1457	case CPU_SB1A:
1457	1458	case CPU_XLR:
@@ -1478,7 +1479,6 @@ static void probe_pcache(void) · 20 unmodified lines
1478	1479	case CPU_PROAPTIV:
1479	1480	case CPU_M5150:
1480	1481	case CPU_QEMU_GENERIC:
1481		− case CPU_I6400:
1482	1482	case CPU_P6600:
1483	1483	case CPU_M6250:
1484	1484	if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
@@ -1497,6 +1497,10 @@ static void probe_pcache(void) · 12 unmodified lines
1497	1497	c->dcache.flags \|= MIPS_CACHE_ALIASES;
1498	1498	}
1499	1499
	1500	+ /* Physically indexed caches don't suffer from virtual aliasing */
	1501	+ if (c->dcache.flags & MIPS_CACHE_PINDEX)
	1502	+ c->dcache.flags &= ~MIPS_CACHE_ALIASES;
	1503	+
1500	1504	switch (current_cpu_type()) {
1501	1505	case CPU_20KC:
1502	1506	/*

arch/mips/mm/init.c+3−0

@@ -30,6 +30,7 @@ · 29 unmodified lines
30	30	#include <linux/hardirq.h>
31	31	#include <linux/gfp.h>
32	32	#include <linux/kcore.h>
	33	+#include <linux/export.h>
33	34
34	35	#include <asm/asm-offsets.h>
35	36	#include <asm/bootinfo.h>
@@ -538,5 +539,7 @@ unsigned long pgd_current[NR_CPUS]; · 502 unmodified lines
538	539	pgd_t swapper_pg_dir[_PTRS_PER_PGD] __section(.bss..swapper_pg_dir);
539	540	#ifndef __PAGETABLE_PMD_FOLDED
540	541	pmd_t invalid_pmd_table[PTRS_PER_PMD] __page_aligned_bss;
	542	+EXPORT_SYMBOL_GPL(invalid_pmd_table);
541	543	#endif
542	544	pte_t invalid_pte_table[PTRS_PER_PTE] __page_aligned_bss;
	545	+EXPORT_SYMBOL(invalid_pte_table);

arch/mips/mm/mmap.c+5−5

@@ -146,14 +146,14 @@ unsigned long arch_mmap_rnd(void) · 145 unmodified lines
146	146	{
147	147	unsigned long rnd;
148	148
149		− rnd = get_random_long();
150		− rnd <<= PAGE_SHIFT;
	149	+#ifdef CONFIG_COMPAT
151	150	if (TASK_IS_32BIT_ADDR)
152		− rnd &= 0xfffffful;
	151	+ rnd = get_random_long() & ((1UL << mmap_rnd_compat_bits) - 1);
153	152	else
154		− rnd &= 0xffffffful;
	153	+#endif /* CONFIG_COMPAT */
	154	+ rnd = get_random_long() & ((1UL << mmap_rnd_bits) - 1);
155	155
156		− return rnd;
	156	+ return rnd << PAGE_SHIFT;
157	157	}
158	158
159	159	void arch_pick_mmap_layout(struct mm_struct *mm)

arch/mips/mm/page-funcs.S+3−0

@@ -9,6 +9,7 @@ · 8 unmodified lines
9	9	* Copyright (C) 2012 Ralf Baechle <ralf@linux-mips.org>
10	10	*/
11	11	#include <asm/asm.h>
	12	+#include <asm/export.h>
12	13	#include <asm/regdef.h>
13	14
14	15	#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
@@ -29,6 +30,7 @@ · 14 unmodified lines
29	30	*/
30	31	EXPORT(__clear_page_start)
31	32	LEAF(cpu_clear_page_function_name)
	33	+EXPORT_SYMBOL(cpu_clear_page_function_name)
32	34	1: j 1b /* Dummy, will be replaced. */
33	35	.space 288
34	36	END(cpu_clear_page_function_name)
@@ -44,6 +46,7 @@ EXPORT(__clear_page_end) · 9 unmodified lines
44	46	*/
45	47	EXPORT(__copy_page_start)
46	48	LEAF(cpu_copy_page_function_name)
	49	+EXPORT_SYMBOL(cpu_copy_page_function_name)
47	50	1: j 1b /* Dummy, will be replaced. */
48	51	.space 1344
49	52	END(cpu_copy_page_function_name)

arch/mips/mm/page.c+2−0

@@ -661,6 +661,7 @@ void clear_page(void *page) · 660 unmodified lines
661	661	;
662	662	__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
663	663	}
	664	+EXPORT_SYMBOL(clear_page);
664	665
665	666	void copy_page(void to, void from)
666	667	{
@@ -687,5 +688,6 @@ void copy_page(void to, void from) · 20 unmodified lines
687	688	;
688	689	__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
689	690	}
	691	+EXPORT_SYMBOL(copy_page);
690	692
691	693	#endif /* CONFIG_SIBYTE_DMA_PAGEOPS */

arch/mips/mm/pgtable-64.c+2−0

@@ -6,6 +6,7 @@ · 5 unmodified lines
6	6	* Copyright (C) 1999, 2000 by Silicon Graphics
7	7	* Copyright (C) 2003 by Ralf Baechle
8	8	*/
	9	+#include <linux/export.h>
9	10	#include <linux/init.h>
10	11	#include <linux/mm.h>
11	12	#include <asm/fixmap.h>
@@ -60,6 +61,7 @@ void pmd_init(unsigned long addr, unsigned long pagetable) · 48 unmodified lines
60	61	p[-1] = pagetable;
61	62	} while (p != end);
62	63	}
	64	+EXPORT_SYMBOL_GPL(pmd_init);
63	65	#endif
64	66
65	67	pmd_t mk_pmd(struct page *page, pgprot_t prot)

arch/mips/mm/pgtable.c+25−0

@@ -0,0 +1,25 @@
	1	+/*
	2	+ * This file is subject to the terms and conditions of the GNU General Public
	3	+ * License. See the file "COPYING" in the main directory of this archive
	4	+ * for more details.
	5	+ */
	6	+#include <linux/export.h>
	7	+#include <linux/mm.h>
	8	+#include <linux/string.h>
	9	+#include <asm/pgalloc.h>
	10	+
	11	+pgd_t pgd_alloc(struct mm_struct mm)
	12	+{
	13	+ pgd_t ret, init;
	14	+
	15	+ ret = (pgd_t *) __get_free_pages(GFP_KERNEL, PGD_ORDER);
	16	+ if (ret) {
	17	+ init = pgd_offset(&init_mm, 0UL);
	18	+ pgd_init((unsigned long)ret);
	19	+ memcpy(ret + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
	20	+ (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
	21	+ }
	22	+
	23	+ return ret;
	24	+}
	25	+EXPORT_SYMBOL_GPL(pgd_alloc);

arch/mips/mm/sc-ip22.c+34−20

@@ -31,26 +31,40 @@ static inline void indy_sc_wipe(unsigned long first, unsigned long last) · 30 unmodified lines
31	31	unsigned long tmp;
32	32
33	33	__asm__ __volatile__(
34		− ".set\tpush\t\t\t# indy_sc_wipe\n\t"
35		− ".set\tnoreorder\n\t"
36		− ".set\tmips3\n\t"
37		− ".set\tnoat\n\t"
38		− "mfc0\t%2, $12\n\t"
39		− "li\t$1, 0x80\t\t\t# Go 64 bit\n\t"
40		− "mtc0\t$1, $12\n\t"
41		−
42		− "dli\t$1, 0x9000000080000000\n\t"
43		− "or\t%0, $1\t\t\t# first line to flush\n\t"
44		− "or\t%1, $1\t\t\t# last line to flush\n\t"
45		− ".set\tat\n\t"
46		−
47		− "1:\tsw\t$0, 0(%0)\n\t"
48		− "bne\t%0, %1, 1b\n\t"
49		− " daddu\t%0, 32\n\t"
50		−
51		− "mtc0\t%2, $12\t\t\t# Back to 32 bit\n\t"
52		− "nop; nop; nop; nop;\n\t"
53		− ".set\tpop"
	34	+ " .set push # indy_sc_wipe \n"
	35	+ " .set noreorder \n"
	36	+ " .set mips3 \n"
	37	+ " .set noat \n"
	38	+ " mfc0 %2, $12 \n"
	39	+ " li $1, 0x80 # Go 64 bit \n"
	40	+ " mtc0 $1, $12 \n"
	41	+ " \n"
	42	+ " # \n"
	43	+ " # Open code a dli $1, 0x9000000080000000 \n"
	44	+ " # \n"
	45	+ " # Required because binutils 2.25 will happily accept \n"
	46	+ " # 64 bit instructions in .set mips3 mode but puke on \n"
	47	+ " # 64 bit constants when generating 32 bit ELF \n"
	48	+ " # \n"
	49	+ " lui $1,0x9000 \n"
	50	+ " dsll $1,$1,0x10 \n"
	51	+ " ori $1,$1,0x8000 \n"
	52	+ " dsll $1,$1,0x10 \n"
	53	+ " \n"
	54	+ " or %0, $1 # first line to flush \n"
	55	+ " or %1, $1 # last line to flush \n"
	56	+ " .set at \n"
	57	+ " \n"
	58	+ "1: sw $0, 0(%0) \n"
	59	+ " bne %0, %1, 1b \n"
	60	+ " daddu %0, 32 \n"
	61	+ " \n"
	62	+ " mtc0 %2, $12 # Back to 32 bit \n"
	63	+ " nop # pipeline hazard \n"
	64	+ " nop \n"
	65	+ " nop \n"
	66	+ " nop \n"
	67	+ " .set pop \n"
54	68	: "=r" (first), "=r" (last), "=&r" (tmp)
55	69	: "0" (first), "1" (last));
56	70	}

arch/mips/mm/sc-mips.c+1−0

@@ -181,6 +181,7 @@ static int __init mips_sc_probe_cm3(void) · 180 unmodified lines
181	181
182	182	if (c->scache.linesz) {
183	183	c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
	184	+ c->options \|= MIPS_CPU_INCLUSIVE_CACHES;
184	185	return 1;
185	186	}
186	187

arch/mips/mm/tlbex.c+23−21

@@ -22,6 +22,7 @@ · 21 unmodified lines
22	22	*/
23	23
24	24	#include <linux/bug.h>
	25	+#include <linux/export.h>
25	26	#include <linux/kernel.h>
26	27	#include <linux/types.h>
27	28	#include <linux/smp.h>
@@ -34,6 +35,7 @@ · 6 unmodified lines
34	35	#include <asm/war.h>
35	36	#include <asm/uasm.h>
36	37	#include <asm/setup.h>
	38	+#include <asm/tlbex.h>
37	39
38	40	static int mips_xpa_disabled;
39	41
@@ -344,7 +346,8 @@ static int allocate_kscratch(void) · 304 unmodified lines
344	346	}
345	347
346	348	static int scratch_reg;
347		−static int pgd_reg;
	349	+int pgd_reg;
	350	+EXPORT_SYMBOL_GPL(pgd_reg);
348	351	enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch};
349	352
350	353	static struct work_registers build_get_work_registers(u32 **p)
@@ -496,15 +499,9 @@ static void __maybe_unused build_tlb_probe_entry(u32 **p) · 145 unmodified lines
496	499	}
497	500	}
498	501
499		−/*
500		− * Write random or indexed TLB entry, and care about the hazards from
501		− * the preceding mtc0 and for the following eret.
502		− */
503		−enum tlb_write_entry { tlb_random, tlb_indexed };
504		−
505		−static void build_tlb_write_entry(u32 p, struct uasm_label l,
506		− struct uasm_reloc **r,
507		− enum tlb_write_entry wmode)
	502	+void build_tlb_write_entry(u32 p, struct uasm_label l,
	503	+ struct uasm_reloc **r,
	504	+ enum tlb_write_entry wmode)
508	505	{
509	506	void(tlbw)(u32 *) = NULL;
510	507
@@ -627,6 +624,7 @@ static void build_tlb_write_entry(u32 p, struct uasm_label l, · 116 unmodified lines
627	624	break;
628	625	}
629	626	}
	627	+EXPORT_SYMBOL_GPL(build_tlb_write_entry);
630	628
631	629	static __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
632	630	unsigned int reg)
@@ -781,9 +779,8 @@ static void build_huge_handler_tail(u32 p, struct uasm_reloc r, · 148 unmodified lines
781	779	* TMP and PTR are scratch.
782	780	* TMP will be clobbered, PTR will hold the pmd entry.
783	781	*/
784		−static void
785		−build_get_pmde64(u32 p, struct uasm_label l, struct uasm_reloc **r,
786		− unsigned int tmp, unsigned int ptr)
	782	+void build_get_pmde64(u32 p, struct uasm_label l, struct uasm_reloc **r,
	783	+ unsigned int tmp, unsigned int ptr)
787	784	{
788	785	#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
789	786	long pgdc = (long)pgd_current;
@@ -859,6 +856,7 @@ build_get_pmde64(u32 p, struct uasm_label l, struct uasm_reloc **r, · 69 unmodified lines
859	856	uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
860	857	#endif
861	858	}
	859	+EXPORT_SYMBOL_GPL(build_get_pmde64);
862	860
863	861	/*
864	862	* BVADDR is the faulting address, PTR is scratch.
@@ -934,8 +932,7 @@ build_get_pgd_vmalloc64(u32 p, struct uasm_label l, struct uasm_reloc **r, · 69 unmodified lines
934	932	* TMP and PTR are scratch.
935	933	* TMP will be clobbered, PTR will hold the pgd entry.
936	934	*/
937		−static void __maybe_unused
938		−build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
	935	+void build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
939	936	{
940	937	if (pgd_reg != -1) {
941	938	/* pgd is in pgd_reg */
@@ -960,6 +957,7 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) · 18 unmodified lines
960	957	uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);
961	958	uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
962	959	}
	960	+EXPORT_SYMBOL_GPL(build_get_pgde32);
963	961
964	962	#endif /* !CONFIG_64BIT */
965	963
@@ -989,7 +987,7 @@ static void build_adjust_context(u32 **p, unsigned int ctx) · 23 unmodified lines
989	987	uasm_i_andi(p, ctx, ctx, mask);
990	988	}
991	989
992		−static void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
	990	+void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
993	991	{
994	992	/*
995	993	* Bug workaround for the Nevada. It seems as if under certain
@@ -1013,8 +1011,9 @@ static void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) · 17 unmodified lines
1013	1011	build_adjust_context(p, tmp);
1014	1012	UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */
1015	1013	}
	1014	+EXPORT_SYMBOL_GPL(build_get_ptep);
1016	1015
1017		−static void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep)
	1016	+void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep)
1018	1017	{
1019	1018	int pte_off_even = 0;
1020	1019	int pte_off_odd = sizeof(pte_t);
@@ -1063,6 +1062,7 @@ static void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep) · 42 unmodified lines
1063	1062	UASM_i_MTC0(p, 0, C0_ENTRYLO1);
1064	1063	UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
1065	1064	}
	1065	+EXPORT_SYMBOL_GPL(build_update_entries);
1066	1066
1067	1067	struct mips_huge_tlb_info {
1068	1068	int huge_pte;
@@ -1536,7 +1536,9 @@ static void build_loongson3_tlb_refill_handler(void) · 467 unmodified lines
1536	1536	extern u32 handle_tlbl[], handle_tlbl_end[];
1537	1537	extern u32 handle_tlbs[], handle_tlbs_end[];
1538	1538	extern u32 handle_tlbm[], handle_tlbm_end[];
1539		−extern u32 tlbmiss_handler_setup_pgd_start[], tlbmiss_handler_setup_pgd[];
	1539	+extern u32 tlbmiss_handler_setup_pgd_start[];
	1540	+extern u32 tlbmiss_handler_setup_pgd[];
	1541	+EXPORT_SYMBOL_GPL(tlbmiss_handler_setup_pgd);
1540	1542	extern u32 tlbmiss_handler_setup_pgd_end[];
1541	1543
1542	1544	static void build_setup_pgd(void)
@@ -2041,7 +2043,7 @@ build_r4000_tlbchange_handler_tail(u32 p, struct uasm_label l, · 498 unmodified lines
2041	2043
2042	2044	static void build_r4000_tlb_load_handler(void)
2043	2045	{
2044		− u32 *p = handle_tlbl;
	2046	+ u32 p = (u32 )msk_isa16_mode((ulong)handle_tlbl);
2045	2047	const int handle_tlbl_size = handle_tlbl_end - handle_tlbl;
2046	2048	struct uasm_label *l = labels;
2047	2049	struct uasm_reloc *r = relocs;
@@ -2224,7 +2226,7 @@ static void build_r4000_tlb_load_handler(void) · 176 unmodified lines
2224	2226
2225	2227	static void build_r4000_tlb_store_handler(void)
2226	2228	{
2227		− u32 *p = handle_tlbs;
	2229	+ u32 p = (u32 )msk_isa16_mode((ulong)handle_tlbs);
2228	2230	const int handle_tlbs_size = handle_tlbs_end - handle_tlbs;
2229	2231	struct uasm_label *l = labels;
2230	2232	struct uasm_reloc *r = relocs;
@@ -2279,7 +2281,7 @@ static void build_r4000_tlb_store_handler(void) · 48 unmodified lines
2279	2281
2280	2282	static void build_r4000_tlb_modify_handler(void)
2281	2283	{
2282		− u32 *p = handle_tlbm;
	2284	+ u32 p = (u32 )msk_isa16_mode((ulong)handle_tlbm);
2283	2285	const int handle_tlbm_size = handle_tlbm_end - handle_tlbm;
2284	2286	struct uasm_label *l = labels;
2285	2287	struct uasm_reloc *r = relocs;

arch/mips/mti-malta/malta-platform.c+0−1

@@ -23,7 +23,6 @@ · 22 unmodified lines
23	23	*/
24	24	#include <linux/init.h>
25	25	#include <linux/serial_8250.h>
26		−#include <linux/module.h>
27	26	#include <linux/irq.h>
28	27	#include <linux/platform_device.h>
29	28	#include <asm/mips-boards/maltaint.h>

arch/mips/netlogic/common/irq.c+2−2

@@ -275,7 +275,7 @@ asmlinkage void plat_irq_dispatch(void) · 274 unmodified lines
275	275	do_IRQ(nlm_irq_to_xirq(node, i));
276	276	}
277	277
278		−#ifdef CONFIG_OF
	278	+#ifdef CONFIG_CPU_XLP
279	279	static const struct irq_domain_ops xlp_pic_irq_domain_ops = {
280	280	.xlate = irq_domain_xlate_onetwocell,
281	281	};
@@ -348,7 +348,7 @@ void __init arch_init_irq(void) · 66 unmodified lines
348	348	#if defined(CONFIG_CPU_XLR)
349	349	nlm_setup_fmn_irq();
350	350	#endif
351		−#if defined(CONFIG_OF)
	351	+#ifdef CONFIG_CPU_XLP
352	352	of_irq_init(xlp_pic_irq_ids);
353	353	#endif
354	354	}

arch/mips/netlogic/common/smpboot.S+2−2

@@ -59,8 +59,8 @@ NESTED(xlp_boot_core0_siblings, PT_SIZE, sp) · 58 unmodified lines
59	59	sync
60	60	/* find the location to which nlm_boot_siblings was relocated */
61	61	li t0, CKSEG1ADDR(RESET_VEC_PHYS)
62		− dla t1, nlm_reset_entry
63		− dla t2, nlm_boot_siblings
	62	+ PTR_LA t1, nlm_reset_entry
	63	+ PTR_LA t2, nlm_boot_siblings
64	64	dsubu t2, t1
65	65	daddu t2, t0
66	66	/* call it */

arch/mips/netlogic/xlp/wakeup.c+1−1

@@ -197,7 +197,7 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask) · 196 unmodified lines
197	197	}
198	198	}
199	199
200		−void xlp_wakeup_secondary_cpus()
	200	+void xlp_wakeup_secondary_cpus(void)
201	201	{
202	202	/*
203	203	* In case of u-boot, the secondaries are in reset

arch/mips/oprofile/op_model_mipsxx.c+13−27

@@ -15,26 +15,12 @@ · 14 unmodified lines
15	15
16	16	#include "op_impl.h"
17	17
18		−#define M_PERFCTL_EXL (1UL << 0)
19		−#define M_PERFCTL_KERNEL (1UL << 1)
20		−#define M_PERFCTL_SUPERVISOR (1UL << 2)
21		−#define M_PERFCTL_USER (1UL << 3)
22		−#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4)
23		−#define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5)
24		−#define M_PERFCTL_VPEID(vpe) ((vpe) << 16)
25		−#define M_PERFCTL_MT_EN(filter) ((filter) << 20)
26		−#define M_TC_EN_ALL M_PERFCTL_MT_EN(0)
27		−#define M_TC_EN_VPE M_PERFCTL_MT_EN(1)
28		−#define M_TC_EN_TC M_PERFCTL_MT_EN(2)
29		−#define M_PERFCTL_TCID(tcid) ((tcid) << 22)
30		−#define M_PERFCTL_WIDE (1UL << 30)
31		−#define M_PERFCTL_MORE (1UL << 31)
	18	+#define M_PERFCTL_EVENT(event) (((event) << MIPS_PERFCTRL_EVENT_S) & \
	19	+ MIPS_PERFCTRL_EVENT)
	20	+#define M_PERFCTL_VPEID(vpe) ((vpe) << MIPS_PERFCTRL_VPEID_S)
32	21
33	22	#define M_COUNTER_OVERFLOW (1UL << 31)
34	23
35		−/* Netlogic XLR specific, count events in all threads in a core */
36		−#define M_PERFCTL_COUNT_ALL_THREADS (1UL << 13)
37		−
38	24	static int (*save_perf_irq)(void);
39	25	static int perfcount_irq;
40	26
@@ -51,7 +37,7 @@ static int perfcount_irq; · 10 unmodified lines
51	37
52	38	#ifdef CONFIG_MIPS_MT_SMP
53	39	static int cpu_has_mipsmt_pertccounters;
54		−#define WHAT (M_TC_EN_VPE \| \
	40	+#define WHAT (MIPS_PERFCTRL_MT_EN_VPE \| \
55	41	M_PERFCTL_VPEID(cpu_data[smp_processor_id()].vpe_id))
56	42	#define vpe_id() (cpu_has_mipsmt_pertccounters ? \
57	43	0 : cpu_data[smp_processor_id()].vpe_id)
@@ -161,15 +147,15 @@ static void mipsxx_reg_setup(struct op_counter_config *ctr) · 103 unmodified lines
161	147	continue;
162	148
163	149	reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) \|
164		− M_PERFCTL_INTERRUPT_ENABLE;
	150	+ MIPS_PERFCTRL_IE;
165	151	if (ctr[i].kernel)
166		− reg.control[i] \|= M_PERFCTL_KERNEL;
	152	+ reg.control[i] \|= MIPS_PERFCTRL_K;
167	153	if (ctr[i].user)
168		− reg.control[i] \|= M_PERFCTL_USER;
	154	+ reg.control[i] \|= MIPS_PERFCTRL_U;
169	155	if (ctr[i].exl)
170		− reg.control[i] \|= M_PERFCTL_EXL;
	156	+ reg.control[i] \|= MIPS_PERFCTRL_EXL;
171	157	if (boot_cpu_type() == CPU_XLR)
172		− reg.control[i] \|= M_PERFCTL_COUNT_ALL_THREADS;
	158	+ reg.control[i] \|= XLR_PERFCTRL_ALLTHREADS;
173	159	reg.counter[i] = 0x80000000 - ctr[i].count;
174	160	}
175	161	}
@@ -254,7 +240,7 @@ static int mipsxx_perfcount_handler(void) · 78 unmodified lines
254	240	case n + 1: \
255	241	control = r_c0_perfctrl ## n(); \
256	242	counter = r_c0_perfcntr ## n(); \
257		− if ((control & M_PERFCTL_INTERRUPT_ENABLE) && \
	243	+ if ((control & MIPS_PERFCTRL_IE) && \
258	244	(counter & M_COUNTER_OVERFLOW)) { \
259	245	oprofile_add_sample(get_irq_regs(), n); \
260	246	w_c0_perfcntr ## n(reg.counter[n]); \
@@ -273,11 +259,11 @@ static inline int __n_counters(void) · 12 unmodified lines
273	259	{
274	260	if (!cpu_has_perf)
275	261	return 0;
276		− if (!(read_c0_perfctrl0() & M_PERFCTL_MORE))
	262	+ if (!(read_c0_perfctrl0() & MIPS_PERFCTRL_M))
277	263	return 1;
278		− if (!(read_c0_perfctrl1() & M_PERFCTL_MORE))
	264	+ if (!(read_c0_perfctrl1() & MIPS_PERFCTRL_M))
279	265	return 2;
280		− if (!(read_c0_perfctrl2() & M_PERFCTL_MORE))
	266	+ if (!(read_c0_perfctrl2() & MIPS_PERFCTRL_M))
281	267	return 3;
282	268
283	269	return 4;

arch/mips/pci/pci-tx4927.c+11−11

@@ -21,9 +21,9 @@ int __init tx4927_report_pciclk(void) · 20 unmodified lines
21	21	{
22	22	int pciclk = 0;
23	23
24		− printk(KERN_INFO "PCIC --%s PCICLK:",
25		− (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66) ?
26		− " PCI66" : "");
	24	+ pr_info("PCIC --%s PCICLK:",
	25	+ (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66) ?
	26	+ " PCI66" : "");
27	27	if (__raw_readq(&tx4927_ccfgptr->pcfg) & TX4927_PCFG_PCICLKEN_ALL) {
28	28	u64 ccfg = __raw_readq(&tx4927_ccfgptr->ccfg);
29	29	switch ((unsigned long)ccfg &
@@ -37,14 +37,14 @@ int __init tx4927_report_pciclk(void) · 7 unmodified lines
37	37	case TX4927_CCFG_PCIDIVMODE_6:
38	38	pciclk = txx9_cpu_clock / 6; break;
39	39	}
40		− printk("Internal(%u.%uMHz)",
41		− (pciclk + 50000) / 1000000,
42		− ((pciclk + 50000) / 100000) % 10);
	40	+ pr_cont("Internal(%u.%uMHz)",
	41	+ (pciclk + 50000) / 1000000,
	42	+ ((pciclk + 50000) / 100000) % 10);
43	43	} else {
44		− printk("External");
	44	+ pr_cont("External");
45	45	pciclk = -1;
46	46	}
47		− printk("\n");
	47	+ pr_cont("\n");
48	48	return pciclk;
49	49	}
50	50
@@ -74,8 +74,8 @@ int __init tx4927_pciclk66_setup(void) · 23 unmodified lines
74	74	}
75	75	tx4927_ccfg_change(TX4927_CCFG_PCIDIVMODE_MASK,
76	76	pcidivmode);
77		− printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n",
78		− (unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg));
	77	+ pr_debug("PCICLK: ccfg:%08lx\n",
	78	+ (unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg));
79	79	} else
80	80	pciclk = -1;
81	81	return pciclk;
@@ -87,5 +87,5 @@ void __init tx4927_setup_pcierr_irq(void) · 5 unmodified lines
87	87	tx4927_pcierr_interrupt,
88	88	0, "PCI error",
89	89	(void *)TX4927_PCIC_REG))
90		− printk(KERN_WARNING "Failed to request irq for PCIERR\n");
	90	+ pr_warn("Failed to request irq for PCIERR\n");
91	91	}

arch/mips/pci/pci-tx4938.c+15−15

@@ -21,9 +21,9 @@ int __init tx4938_report_pciclk(void) · 20 unmodified lines
21	21	{
22	22	int pciclk = 0;
23	23
24		− printk(KERN_INFO "PCIC --%s PCICLK:",
25		− (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66) ?
26		− " PCI66" : "");
	24	+ pr_info("PCIC --%s PCICLK:",
	25	+ (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66) ?
	26	+ " PCI66" : "");
27	27	if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_PCICLKEN_ALL) {
28	28	u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg);
29	29	switch ((unsigned long)ccfg &
@@ -45,14 +45,14 @@ int __init tx4938_report_pciclk(void) · 15 unmodified lines
45	45	case TX4938_CCFG_PCIDIVMODE_11:
46	46	pciclk = txx9_cpu_clock / 11; break;
47	47	}
48		− printk("Internal(%u.%uMHz)",
49		− (pciclk + 50000) / 1000000,
50		− ((pciclk + 50000) / 100000) % 10);
	48	+ pr_cont("Internal(%u.%uMHz)",
	49	+ (pciclk + 50000) / 1000000,
	50	+ ((pciclk + 50000) / 100000) % 10);
51	51	} else {
52		− printk("External");
	52	+ pr_cont("External");
53	53	pciclk = -1;
54	54	}
55		− printk("\n");
	55	+ pr_cont("\n");
56	56	return pciclk;
57	57	}
58	58
@@ -62,10 +62,10 @@ void __init tx4938_report_pci1clk(void) · 3 unmodified lines
62	62	unsigned int pciclk =
63	63	txx9_gbus_clock / ((ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2);
64	64
65		− printk(KERN_INFO "PCIC1 -- %sPCICLK:%u.%uMHz\n",
66		− (ccfg & TX4938_CCFG_PCI1_66) ? "PCI66 " : "",
67		− (pciclk + 50000) / 1000000,
68		− ((pciclk + 50000) / 100000) % 10);
	65	+ pr_info("PCIC1 -- %sPCICLK:%u.%uMHz\n",
	66	+ (ccfg & TX4938_CCFG_PCI1_66) ? "PCI66 " : "",
	67	+ (pciclk + 50000) / 1000000,
	68	+ ((pciclk + 50000) / 100000) % 10);
69	69	}
70	70
71	71	int __init tx4938_pciclk66_setup(void)
@@ -105,8 +105,8 @@ int __init tx4938_pciclk66_setup(void) · 33 unmodified lines
105	105	}
106	106	tx4938_ccfg_change(TX4938_CCFG_PCIDIVMODE_MASK,
107	107	pcidivmode);
108		− printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n",
109		− (unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg));
	108	+ pr_debug("PCICLK: ccfg:%08lx\n",
	109	+ (unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg));
110	110	} else
111	111	pciclk = -1;
112	112	return pciclk;
@@ -138,5 +138,5 @@ void __init tx4938_setup_pcierr_irq(void) · 25 unmodified lines
138	138	tx4927_pcierr_interrupt,
139	139	0, "PCI error",
140	140	(void *)TX4927_PCIC_REG))
141		− printk(KERN_WARNING "Failed to request irq for PCIERR\n");
	141	+ pr_warn("Failed to request irq for PCIERR\n");
142	142	}

arch/mips/pci/pci-tx4939.c+5−5

@@ -28,14 +28,14 @@ int __init tx4939_report_pciclk(void) · 27 unmodified lines
28	28	pciclk = txx9_master_clock * 20 / 6;
29	29	if (!(__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCI66))
30	30	pciclk /= 2;
31		− printk(KERN_CONT "Internal(%u.%uMHz)",
32		− (pciclk + 50000) / 1000000,
33		− ((pciclk + 50000) / 100000) % 10);
	31	+ pr_cont("Internal(%u.%uMHz)",
	32	+ (pciclk + 50000) / 1000000,
	33	+ ((pciclk + 50000) / 100000) % 10);
34	34	} else {
35		− printk(KERN_CONT "External");
	35	+ pr_cont("External");
36	36	pciclk = -1;
37	37	}
38		− printk(KERN_CONT "\n");
	38	+ pr_cont("\n");
39	39	return pciclk;
40	40	}
41	41

arch/mips/pic32/pic32mzda/Makefile+2−3

@@ -2,8 +2,7 @@ · 1 unmodified line
2	2	# Joshua Henderson, <joshua.henderson@microchip.com>
3	3	# Copyright (C) 2015 Microchip Technology, Inc. All rights reserved.
4	4	#
5		−obj-y := init.o time.o config.o
	5	+obj-y := config.o early_clk.o init.o time.o
6	6
7	7	obj-$(CONFIG_EARLY_PRINTK) += early_console.o \
8		− early_pin.o \
9		− early_clk.o
	8	+ early_pin.o

arch/mips/pmcs-msp71xx/msp_prom.c+1−1

@@ -34,7 +34,7 @@ · 33 unmodified lines
34	34	* 675 Mass Ave, Cambridge, MA 02139, USA.
35	35	*/
36	36
37		−#include <linux/module.h>
	37	+#include <linux/export.h>
38	38	#include <linux/kernel.h>
39	39	#include <linux/init.h>
40	40	#include <linux/string.h>

arch/mips/pmcs-msp71xx/msp_time.c+0−1

@@ -26,7 +26,6 @@ · 25 unmodified lines
26	26	#include <linux/kernel_stat.h>
27	27	#include <linux/sched.h>
28	28	#include <linux/spinlock.h>
29		−#include <linux/module.h>
30	29	#include <linux/ptrace.h>
31	30
32	31	#include <asm/cevt-r4k.h>

arch/mips/ralink/Kconfig+1−0

@@ -46,6 +46,7 @@ choice · 45 unmodified lines
46	46	select SYS_SUPPORTS_MULTITHREADING
47	47	select SYS_SUPPORTS_SMP
48	48	select SYS_SUPPORTS_MIPS_CPS
	49	+ select SYS_SUPPORTS_HIGHMEM
49	50	select MIPS_GIC
50	51	select COMMON_CLK
51	52	select CLKSRC_MIPS_GIC

arch/mips/ralink/clk.c+8−1

@@ -8,7 +8,8 @@ · 7 unmodified lines
8	8	*/
9	9
10	10	#include <linux/kernel.h>
11		−#include <linux/module.h>
	11	+#include <linux/init.h>
	12	+#include <linux/export.h>
12	13	#include <linux/clkdev.h>
13	14	#include <linux/clk.h>
14	15
@@ -62,6 +63,12 @@ int clk_set_rate(struct clk *clk, unsigned long rate) · 47 unmodified lines
62	63	}
63	64	EXPORT_SYMBOL_GPL(clk_set_rate);
64	65
	66	+long clk_round_rate(struct clk *clk, unsigned long rate)
	67	+{
	68	+ return -1;
	69	+}
	70	+EXPORT_SYMBOL_GPL(clk_round_rate);
	71	+
65	72	void __init plat_time_init(void)
66	73	{
67	74	struct clk *clk;

arch/mips/ralink/irq.c+2−2

@@ -163,8 +163,8 @@ static int __init intc_of_init(struct device_node *node, · 162 unmodified lines
163	163	if (of_address_to_resource(node, 0, &res))
164	164	panic("Failed to get intc memory range");
165	165
166		− if (request_mem_region(res.start, resource_size(&res),
167		− res.name) < 0)
	166	+ if (!request_mem_region(res.start, resource_size(&res),
	167	+ res.name))
168	168	pr_err("Failed to request intc memory");
169	169
170	170	rt_intc_membase = ioremap_nocache(res.start,

arch/mips/ralink/mt7620.c+20−12

@@ -12,7 +12,6 @@ · 11 unmodified lines
12	12
13	13	#include <linux/kernel.h>
14	14	#include <linux/init.h>
15		−#include <linux/module.h>
16	15
17	16	#include <asm/mipsregs.h>
18	17	#include <asm/mach-ralink/ralink_regs.h>
@@ -55,7 +54,10 @@ static int dram_type; · 36 unmodified lines
55	54	static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };
56	55	static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
57	56	static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
58		−static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) };
	57	+static struct rt2880_pmx_func mdio_grp[] = {
	58	+ FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2),
	59	+ FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2),
	60	+};
59	61	static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
60	62	static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
61	63	static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
@@ -92,7 +94,8 @@ static struct rt2880_pmx_group mt7620a_pinmux_data[] = { · 30 unmodified lines
92	94	GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
93	95	GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
94	96	MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
95		− GRP("mdio", mdio_grp, 1, MT7620_GPIO_MODE_MDIO),
	97	+ GRP_G("mdio", mdio_grp, MT7620_GPIO_MODE_MDIO_MASK,
	98	+ MT7620_GPIO_MODE_MDIO_GPIO, MT7620_GPIO_MODE_MDIO_SHIFT),
96	99	GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
97	100	GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
98	101	GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK,
@@ -176,7 +179,7 @@ static struct rt2880_pmx_func spi_cs1_grp_mt7628[] = { · 77 unmodified lines
176	179
177	180	static struct rt2880_pmx_func spis_grp_mt7628[] = {
178	181	FUNC("pwm_uart2", 3, 14, 4),
179		− FUNC("util", 2, 14, 4),
	182	+ FUNC("utif", 2, 14, 4),
180	183	FUNC("gpio", 1, 14, 4),
181	184	FUNC("spis", 0, 14, 4),
182	185	};
@@ -190,28 +193,28 @@ static struct rt2880_pmx_func gpio_grp_mt7628[] = { · 7 unmodified lines
190	193
191	194	static struct rt2880_pmx_func p4led_kn_grp_mt7628[] = {
192	195	FUNC("jtag", 3, 30, 1),
193		− FUNC("util", 2, 30, 1),
	196	+ FUNC("utif", 2, 30, 1),
194	197	FUNC("gpio", 1, 30, 1),
195	198	FUNC("p4led_kn", 0, 30, 1),
196	199	};
197	200
198	201	static struct rt2880_pmx_func p3led_kn_grp_mt7628[] = {
199	202	FUNC("jtag", 3, 31, 1),
200		− FUNC("util", 2, 31, 1),
	203	+ FUNC("utif", 2, 31, 1),
201	204	FUNC("gpio", 1, 31, 1),
202	205	FUNC("p3led_kn", 0, 31, 1),
203	206	};
204	207
205	208	static struct rt2880_pmx_func p2led_kn_grp_mt7628[] = {
206	209	FUNC("jtag", 3, 32, 1),
207		− FUNC("util", 2, 32, 1),
	210	+ FUNC("utif", 2, 32, 1),
208	211	FUNC("gpio", 1, 32, 1),
209	212	FUNC("p2led_kn", 0, 32, 1),
210	213	};
211	214
212	215	static struct rt2880_pmx_func p1led_kn_grp_mt7628[] = {
213	216	FUNC("jtag", 3, 33, 1),
214		− FUNC("util", 2, 33, 1),
	217	+ FUNC("utif", 2, 33, 1),
215	218	FUNC("gpio", 1, 33, 1),
216	219	FUNC("p1led_kn", 0, 33, 1),
217	220	};
@@ -232,28 +235,28 @@ static struct rt2880_pmx_func wled_kn_grp_mt7628[] = { · 14 unmodified lines
232	235
233	236	static struct rt2880_pmx_func p4led_an_grp_mt7628[] = {
234	237	FUNC("jtag", 3, 39, 1),
235		− FUNC("util", 2, 39, 1),
	238	+ FUNC("utif", 2, 39, 1),
236	239	FUNC("gpio", 1, 39, 1),
237	240	FUNC("p4led_an", 0, 39, 1),
238	241	};
239	242
240	243	static struct rt2880_pmx_func p3led_an_grp_mt7628[] = {
241	244	FUNC("jtag", 3, 40, 1),
242		− FUNC("util", 2, 40, 1),
	245	+ FUNC("utif", 2, 40, 1),
243	246	FUNC("gpio", 1, 40, 1),
244	247	FUNC("p3led_an", 0, 40, 1),
245	248	};
246	249
247	250	static struct rt2880_pmx_func p2led_an_grp_mt7628[] = {
248	251	FUNC("jtag", 3, 41, 1),
249		− FUNC("util", 2, 41, 1),
	252	+ FUNC("utif", 2, 41, 1),
250	253	FUNC("gpio", 1, 41, 1),
251	254	FUNC("p2led_an", 0, 41, 1),
252	255	};
253	256
254	257	static struct rt2880_pmx_func p1led_an_grp_mt7628[] = {
255	258	FUNC("jtag", 3, 42, 1),
256		− FUNC("util", 2, 42, 1),
	259	+ FUNC("utif", 2, 42, 1),
257	260	FUNC("gpio", 1, 42, 1),
258	261	FUNC("p1led_an", 0, 42, 1),
259	262	};
@@ -509,6 +512,7 @@ void __init ralink_clk_init(void) · 249 unmodified lines
509	512	unsigned long sys_rate;
510	513	unsigned long dram_rate;
511	514	unsigned long periph_rate;
	515	+ unsigned long pcmi2s_rate;
512	516
513	517	xtal_rate = mt7620_get_xtal_rate();
514	518
@@ -523,6 +527,7 @@ void __init ralink_clk_init(void) · 8 unmodified lines
523	527	cpu_rate = MHZ(575);
524	528	dram_rate = sys_rate = cpu_rate / 3;
525	529	periph_rate = MHZ(40);
	530	+ pcmi2s_rate = MHZ(480);
526	531
527	532	ralink_clk_add("10000d00.uartlite", periph_rate);
528	533	ralink_clk_add("10000e00.uartlite", periph_rate);
@@ -534,6 +539,7 @@ void __init ralink_clk_init(void) · 5 unmodified lines
534	539	dram_rate = mt7620_get_dram_rate(pll_rate);
535	540	sys_rate = mt7620_get_sys_rate(cpu_rate);
536	541	periph_rate = mt7620_get_periph_rate(xtal_rate);
	542	+ pcmi2s_rate = periph_rate;
537	543
538	544	pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
539	545	RINT(xtal_rate), RFRAC(xtal_rate),
@@ -555,6 +561,8 @@ void __init ralink_clk_init(void) · 15 unmodified lines
555	561	ralink_clk_add("cpu", cpu_rate);
556	562	ralink_clk_add("10000100.timer", periph_rate);
557	563	ralink_clk_add("10000120.watchdog", periph_rate);
	564	+ ralink_clk_add("10000900.i2c", periph_rate);
	565	+ ralink_clk_add("10000a00.i2s", pcmi2s_rate);
558	566	ralink_clk_add("10000b00.spi", sys_rate);
559	567	ralink_clk_add("10000b40.spi", sys_rate);
560	568	ralink_clk_add("10000c00.uartlite", periph_rate);

arch/mips/ralink/mt7621.c+1−2

@@ -9,7 +9,6 @@ · 8 unmodified lines
9	9
10	10	#include <linux/kernel.h>
11	11	#include <linux/init.h>
12		−#include <linux/module.h>
13	12
14	13	#include <asm/mipsregs.h>
15	14	#include <asm/smp-ops.h>
@@ -181,7 +180,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info) · 165 unmodified lines
181	180	} else {
182	181	panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
183	182	}
184		−
	183	+ ralink_soc = MT762X_SOC_MT7621AT;
185	184	rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
186	185
187	186	snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,

arch/mips/ralink/of.c+12−4

@@ -40,9 +40,9 @@ __iomem void plat_of_remap_node(const char node) · 39 unmodified lines
40	40	if (of_address_to_resource(np, 0, &res))
41	41	panic("Failed to get resource for %s", node);
42	42
43		− if ((request_mem_region(res.start,
	43	+ if (!request_mem_region(res.start,
44	44	resource_size(&res),
45		− res.name) < 0))
	45	+ res.name))
46	46	panic("Failed to request resources for %s", node);
47	47
48	48	return ioremap_nocache(res.start, resource_size(&res));
@@ -66,13 +66,21 @@ static int __init early_init_dt_find_memory(unsigned long node, · 17 unmodified lines
66	66
67	67	void __init plat_mem_setup(void)
68	68	{
	69	+ void *dtb = NULL;
	70	+
69	71	set_io_port_base(KSEG1);
70	72
71	73	/*
72	74	* Load the builtin devicetree. This causes the chosen node to be
73		− * parsed resulting in our memory appearing
	75	+ * parsed resulting in our memory appearing. fw_passed_dtb is used
	76	+ * by CONFIG_MIPS_APPENDED_RAW_DTB as well.
74	77	*/
75		− __dt_setup_arch(__dtb_start);
	78	+ if (fw_passed_dtb)
	79	+ dtb = (void *)fw_passed_dtb;
	80	+ else if (__dtb_start != __dtb_end)
	81	+ dtb = (void *)__dtb_start;
	82	+
	83	+ __dt_setup_arch(dtb);
76	84
77	85	of_scan_flat_dt(early_init_dt_find_memory, NULL);
78	86	if (memory_dtb)

arch/mips/ralink/prom.c+4−5

@@ -30,8 +30,10 @@ const char *get_system_type(void) · 29 unmodified lines
30	30	return soc_info.sys_type;
31	31	}
32	32
33		−static __init void prom_init_cmdline(int argc, char **argv)
	33	+static __init void prom_init_cmdline(void)
34	34	{
	35	+ int argc;
	36	+ char **argv;
35	37	int i;
36	38
37	39	pr_debug("prom: fw_arg0=%08x fw_arg1=%08x fw_arg2=%08x fw_arg3=%08x\n",
@@ -60,14 +62,11 @@ static __init void prom_init_cmdline(int argc, char **argv) · 22 unmodified lines
60	62
61	63	void __init prom_init(void)
62	64	{
63		− int argc;
64		− char **argv;
65		−
66	65	prom_soc_init(&soc_info);
67	66
68	67	pr_info("SoC Type: %s\n", get_system_type());
69	68
70		− prom_init_cmdline(argc, argv);
	69	+ prom_init_cmdline();
71	70	}
72	71
73	72	void __init prom_free_prom_memory(void)

arch/mips/ralink/rt288x.c+1−11

@@ -12,7 +12,6 @@ · 11 unmodified lines
12	12
13	13	#include <linux/kernel.h>
14	14	#include <linux/init.h>
15		−#include <linux/module.h>
16	15
17	16	#include <asm/mipsregs.h>
18	17	#include <asm/mach-ralink/ralink_regs.h>
@@ -40,16 +39,6 @@ static struct rt2880_pmx_group rt2880_pinmux_data_act[] = { · 21 unmodified lines
40	39	{ 0 }
41	40	};
42	41
43		−static void rt288x_wdt_reset(void)
44		−{
45		− u32 t;
46		−
47		− /* enable WDT reset output on pin SRAM_CS_N */
48		− t = rt_sysc_r32(SYSC_REG_CLKCFG);
49		− t \|= CLKCFG_SRAM_CS_N_WDT;
50		− rt_sysc_w32(t, SYSC_REG_CLKCFG);
51		−}
52		−
53	42	void __init ralink_clk_init(void)
54	43	{
55	44	unsigned long cpu_rate, wmac_rate = 40000000;
@@ -75,6 +64,7 @@ void __init ralink_clk_init(void) · 19 unmodified lines
75	64	ralink_clk_add("300100.timer", cpu_rate / 2);
76	65	ralink_clk_add("300120.watchdog", cpu_rate / 2);
77	66	ralink_clk_add("300500.uart", cpu_rate / 2);
	67	+ ralink_clk_add("300900.i2c", cpu_rate / 2);
78	68	ralink_clk_add("300c00.uartlite", cpu_rate / 2);
79	69	ralink_clk_add("400000.ethernet", cpu_rate / 2);
80	70	ralink_clk_add("480000.wmac", wmac_rate);

arch/mips/ralink/rt305x.c+4−12

@@ -12,8 +12,9 @@ · 11 unmodified lines
12	12
13	13	#include <linux/kernel.h>
14	14	#include <linux/init.h>
15		−#include <linux/module.h>
	15	+#include <linux/bug.h>
16	16
	17	+#include <asm/io.h>
17	18	#include <asm/mipsregs.h>
18	19	#include <asm/mach-ralink/ralink_regs.h>
19	20	#include <asm/mach-ralink/rt305x.h>
@@ -89,17 +90,6 @@ static struct rt2880_pmx_group rt5350_pinmux_data[] = { · 69 unmodified lines
89	90	{ 0 }
90	91	};
91	92
92		−static void rt305x_wdt_reset(void)
93		−{
94		− u32 t;
95		−
96		− /* enable WDT reset output on pin SRAM_CS_N */
97		− t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
98		− t \|= RT305X_SYSCFG_SRAM_CS0_MODE_WDT <<
99		− RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT;
100		− rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
101		−}
102		−
103	93	static unsigned long rt5350_get_mem_size(void)
104	94	{
105	95	void __iomem sysc = (void __iomem ) KSEG1ADDR(RT305X_SYSC_BASE);
@@ -200,6 +190,8 @@ void __init ralink_clk_init(void) · 94 unmodified lines
200	190
201	191	ralink_clk_add("cpu", cpu_rate);
202	192	ralink_clk_add("sys", sys_rate);
	193	+ ralink_clk_add("10000900.i2c", uart_rate);
	194	+ ralink_clk_add("10000a00.i2s", uart_rate);
203	195	ralink_clk_add("10000b00.spi", sys_rate);
204	196	ralink_clk_add("10000b40.spi", sys_rate);
205	197	ralink_clk_add("10000100.timer", wdt_rate);

arch/mips/ralink/rt3883.c+3−12

@@ -12,7 +12,6 @@ · 11 unmodified lines
12	12
13	13	#include <linux/kernel.h>
14	14	#include <linux/init.h>
15		−#include <linux/module.h>
16	15
17	16	#include <asm/mipsregs.h>
18	17	#include <asm/mach-ralink/ralink_regs.h>
@@ -63,16 +62,6 @@ static struct rt2880_pmx_group rt3883_pinmux_data[] = { · 44 unmodified lines
63	62	{ 0 }
64	63	};
65	64
66		−static void rt3883_wdt_reset(void)
67		−{
68		− u32 t;
69		−
70		− /* enable WDT reset output on GPIO 2 */
71		− t = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
72		− t \|= RT3883_SYSCFG1_GPIO2_AS_WDT_OUT;
73		− rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
74		−}
75		−
76	65	void __init ralink_clk_init(void)
77	66	{
78	67	unsigned long cpu_rate, sys_rate;
@@ -108,6 +97,8 @@ void __init ralink_clk_init(void) · 29 unmodified lines
108	97	ralink_clk_add("10000100.timer", sys_rate);
109	98	ralink_clk_add("10000120.watchdog", sys_rate);
110	99	ralink_clk_add("10000500.uart", 40000000);
	100	+ ralink_clk_add("10000900.i2c", 40000000);
	101	+ ralink_clk_add("10000a00.i2s", 40000000);
111	102	ralink_clk_add("10000b00.spi", sys_rate);
112	103	ralink_clk_add("10000b40.spi", sys_rate);
113	104	ralink_clk_add("10000c00.uartlite", 40000000);
@@ -155,5 +146,5 @@ void prom_soc_init(struct ralink_soc_info *soc_info) · 41 unmodified lines
155	146
156	147	rt2880_pinmux_data = rt3883_pinmux_data;
157	148
158		− ralink_soc == RT3883_SOC;
	149	+ ralink_soc = RT3883_SOC;
159	150	}

arch/mips/ralink/timer.c+0−14

@@ -71,11 +71,6 @@ static int rt_timer_request(struct rt_timer *rt) · 70 unmodified lines
71	71	return err;
72	72	}
73	73
74		−static void rt_timer_free(struct rt_timer *rt)
75		−{
76		− free_irq(rt->irq, rt);
77		−}
78		−
79	74	static int rt_timer_config(struct rt_timer *rt, unsigned long divisor)
80	75	{
81	76	if (rt->timer_freq < divisor)
@@ -101,15 +96,6 @@ static int rt_timer_enable(struct rt_timer *rt) · 19 unmodified lines
101	96	return 0;
102	97	}
103	98
104		−static void rt_timer_disable(struct rt_timer *rt)
105		−{
106		− u32 t;
107		−
108		− t = rt_timer_r32(rt, TIMER_REG_TMR0CTL);
109		− t &= ~TMR0CTL_ENABLE;
110		− rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
111		−}
112		−
113	99	static int rt_timer_probe(struct platform_device *pdev)
114	100	{
115	101	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

arch/mips/rb532/irq.c+0−1

@@ -29,7 +29,6 @@ · 28 unmodified lines
29	29	#include <linux/init.h>
30	30	#include <linux/io.h>
31	31	#include <linux/kernel_stat.h>
32		−#include <linux/module.h>
33	32	#include <linux/signal.h>
34	33	#include <linux/sched.h>
35	34	#include <linux/types.h>

arch/mips/rb532/prom.c+1−1

@@ -26,7 +26,7 @@ · 25 unmodified lines
26	26
27	27	#include <linux/init.h>
28	28	#include <linux/mm.h>
29		−#include <linux/module.h>
	29	+#include <linux/export.h>
30	30	#include <linux/string.h>
31	31	#include <linux/console.h>
32	32	#include <linux/bootmem.h>

arch/mips/sgi-ip22/Platform+1−1

@@ -25,7 +25,7 @@ endif · 24 unmodified lines
25	25	# Simplified: what IP22 does at 128MB+ in ksegN, IP28 does at 512MB+ in xkphys
26	26	#
27	27	ifdef CONFIG_SGI_IP28
28		− ifeq ($(call cc-option-yn,-mr10k-cache-barrier=store), n)
	28	+ ifeq ($(call cc-option-yn,-march=r10000 -mr10k-cache-barrier=store), n)
29	29	$(error gcc doesn't support needed option -mr10k-cache-barrier=store)
30	30	endif
31	31	endif

arch/mips/sgi-ip22/ip22-hpc.c+1−1

@@ -5,8 +5,8 @@ · 4 unmodified lines
5	5	* Copyright (C) 1998 Ralf Baechle
6	6	*/
7	7
	8	+#include <linux/export.h>
8	9	#include <linux/init.h>
9		−#include <linux/module.h>
10	10	#include <linux/types.h>
11	11
12	12	#include <asm/io.h>

arch/mips/sgi-ip22/ip22-mc.c+2−1

@@ -8,8 +8,9 @@ · 7 unmodified lines
8	8	*/
9	9
10	10	#include <linux/init.h>
11		−#include <linux/module.h>
	11	+#include <linux/export.h>
12	12	#include <linux/kernel.h>
	13	+#include <linux/spinlock.h>
13	14
14	15	#include <asm/io.h>
15	16	#include <asm/bootinfo.h>

arch/mips/sgi-ip22/ip22-nvram.c+1−1

@@ -3,7 +3,7 @@ · 2 unmodified lines
3	3	*
4	4	* Copyright (C) 2003 Ladislav Michl (ladis@linux-mips.org)
5	5	*/
6		−#include <linux/module.h>
	6	+#include <linux/export.h>
7	7
8	8	#include <asm/sgi/hpc3.h>
9	9	#include <asm/sgi/ip22.h>

arch/mips/sgi-ip22/ip22-reset.c+0−1

@@ -8,7 +8,6 @@ · 7 unmodified lines
8	8	#include <linux/linkage.h>
9	9	#include <linux/init.h>
10	10	#include <linux/rtc/ds1286.h>
11		−#include <linux/module.h>
12	11	#include <linux/interrupt.h>
13	12	#include <linux/kernel.h>
14	13	#include <linux/sched.h>

arch/mips/sgi-ip22/ip22-setup.c+0−1

@@ -8,7 +8,6 @@ · 7 unmodified lines
8	8	#include <linux/kernel.h>
9	9	#include <linux/kdev_t.h>
10	10	#include <linux/types.h>
11		−#include <linux/module.h>
12	11	#include <linux/console.h>
13	12	#include <linux/sched.h>
14	13	#include <linux/tty.h>

arch/mips/sgi-ip27/ip27-berr.c+0−2

@@ -9,11 +9,9 @@ · 8 unmodified lines
9	9	*/
10	10	#include <linux/init.h>
11	11	#include <linux/kernel.h>
12		−#include <linux/module.h>
13	12	#include <linux/signal.h> /* for SIGBUS */
14	13	#include <linux/sched.h> /* schow_regs(), force_sig() */
15	14
16		−#include <asm/module.h>
17	15	#include <asm/sn/addrs.h>
18	16	#include <asm/sn/arch.h>
19	17	#include <asm/sn/sn0/hub.h>

arch/mips/sgi-ip27/ip27-init.c+1−1

@@ -11,7 +11,7 @@ · 10 unmodified lines
11	11	#include <linux/sched.h>
12	12	#include <linux/smp.h>
13	13	#include <linux/mm.h>
14		−#include <linux/module.h>
	14	+#include <linux/export.h>
15	15	#include <linux/cpumask.h>
16	16	#include <asm/cpu.h>
17	17	#include <asm/io.h>

arch/mips/sgi-ip27/ip27-klnuma.c+1−1

@@ -82,7 +82,7 @@ static __init void copy_kernel(nasid_t dest_nasid) · 81 unmodified lines
82	82	memcpy((void )dest_kern_start, (void )source_start, kern_size);
83	83	}
84	84
85		−void __init replicate_kernel_text()
	85	+void __init replicate_kernel_text(void)
86	86	{
87	87	cnodeid_t cnode;
88	88	nasid_t client_nasid;

arch/mips/sgi-ip27/ip27-memory.c+1−1

@@ -15,7 +15,7 @@ · 14 unmodified lines
15	15	#include <linux/memblock.h>
16	16	#include <linux/mm.h>
17	17	#include <linux/mmzone.h>
18		−#include <linux/module.h>
	18	+#include <linux/export.h>
19	19	#include <linux/nodemask.h>
20	20	#include <linux/swap.h>
21	21	#include <linux/bootmem.h>

arch/mips/sgi-ip32/crime.c+1−1

@@ -10,7 +10,7 @@ · 9 unmodified lines
10	10	#include <linux/init.h>
11	11	#include <linux/kernel.h>
12	12	#include <linux/interrupt.h>
13		−#include <linux/module.h>
	13	+#include <linux/export.h>
14	14	#include <asm/bootinfo.h>
15	15	#include <asm/io.h>
16	16	#include <asm/mipsregs.h>

arch/mips/sgi-ip32/ip32-irq.c+2−2

@@ -28,12 +28,12 @@ · 27 unmodified lines
28	28	#include <asm/ip32/ip32_ints.h>
29	29
30	30	/* issue a PIO read to make sure no PIO writes are pending */
31		−static void inline flush_crime_bus(void)
	31	+static inline void flush_crime_bus(void)
32	32	{
33	33	crime->control;
34	34	}
35	35
36		−static void inline flush_mace_bus(void)
	36	+static inline void flush_mace_bus(void)
37	37	{
38	38	mace->perif.ctrl.misc;
39	39	}

arch/mips/sibyte/bcm1480/setup.c+1−1

@@ -17,7 +17,7 @@ · 16 unmodified lines
17	17	*/
18	18	#include <linux/init.h>
19	19	#include <linux/kernel.h>
20		−#include <linux/module.h>
	20	+#include <linux/export.h>
21	21	#include <linux/reboot.h>
22	22	#include <linux/string.h>
23	23

arch/mips/sibyte/sb1250/setup.c+1−1

@@ -15,8 +15,8 @@ · 14 unmodified lines
15	15	* along with this program; if not, write to the Free Software
16	16	* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17	17	*/
	18	+#include <linux/export.h>
18	19	#include <linux/init.h>
19		−#include <linux/module.h>
20	20	#include <linux/kernel.h>
21	21	#include <linux/reboot.h>
22	22	#include <linux/string.h>

arch/mips/txx9/generic/7segled.c+2−2

@@ -55,8 +55,8 @@ static ssize_t raw_store(struct device *dev, · 54 unmodified lines
55	55	return size;
56	56	}
57	57
58		−static DEVICE_ATTR(ascii, 0200, NULL, ascii_store);
59		−static DEVICE_ATTR(raw, 0200, NULL, raw_store);
	58	+static DEVICE_ATTR_WO(ascii);
	59	+static DEVICE_ATTR_WO(raw);
60	60
61	61	static ssize_t map_seg7_show(struct device *dev,
62	62	struct device_attribute *attr,

arch/mips/txx9/generic/pci.c+13−15

@@ -55,7 +55,7 @@ int __init txx9_pci66_check(struct pci_controller *hose, int top_bus, · 54 unmodified lines
55	55	/* It seems SLC90E66 needs some time after PCI reset... */
56	56	mdelay(80);
57	57
58		− printk(KERN_INFO "PCI: Checking 66MHz capabilities...\n");
	58	+ pr_info("PCI: Checking 66MHz capabilities...\n");
59	59
60	60	for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
61	61	if (PCI_FUNC(pci_devfn))
@@ -74,9 +74,8 @@ int __init txx9_pci66_check(struct pci_controller *hose, int top_bus, · 12 unmodified lines
74	74	early_read_config_word(hose, top_bus, current_bus,
75	75	pci_devfn, PCI_STATUS, &stat);
76	76	if (!(stat & PCI_STATUS_66MHZ)) {
77		− printk(KERN_DEBUG
78		− "PCI: %02x:%02x not 66MHz capable.\n",
79		− current_bus, pci_devfn);
	77	+ pr_debug("PCI: %02x:%02x not 66MHz capable.\n",
	78	+ current_bus, pci_devfn);
80	79	cap66 = 0;
81	80	break;
82	81	}
@@ -209,8 +208,8 @@ txx9_alloc_pci_controller(struct pci_controller *pcic, · 126 unmodified lines
209	208
210	209	pcic->mem_offset = 0; /* busaddr == physaddr */
211	210
212		− printk(KERN_INFO "PCI: IO %pR MEM %pR\n",
213		− &pcic->mem_resource[1], &pcic->mem_resource[0]);
	211	+ pr_info("PCI: IO %pR MEM %pR\n", &pcic->mem_resource[1],
	212	+ &pcic->mem_resource[0]);
214	213
215	214	/* register_pci_controller() will request MEM resource */
216	215	release_resource(&pcic->mem_resource[0]);
@@ -219,7 +218,7 @@ txx9_alloc_pci_controller(struct pci_controller *pcic, · 2 unmodified lines
219	218	release_resource(&pcic->mem_resource[0]);
220	219	free_and_exit:
221	220	kfree(new);
222		− printk(KERN_ERR "PCI: Failed to allocate resources.\n");
	221	+ pr_err("PCI: Failed to allocate resources.\n");
223	222	return NULL;
224	223	}
225	224
@@ -260,7 +259,7 @@ static int txx9_i8259_irq_setup(int irq) · 34 unmodified lines
260	259	err = request_irq(irq, &i8259_interrupt, IRQF_SHARED,
261	260	"cascade(i8259)", (void *)(long)irq);
262	261	if (!err)
263		− printk(KERN_INFO "PCI-ISA bridge PIC (irq %d)\n", irq);
	262	+ pr_info("PCI-ISA bridge PIC (irq %d)\n", irq);
264	263	return err;
265	264	}
266	265
@@ -308,13 +307,13 @@ static void quirk_slc90e66_ide(struct pci_dev *dev) · 41 unmodified lines
308	307	/* SMSC SLC90E66 IDE uses irq 14, 15 (default) */
309	308	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 14);
310	309	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &dat);
311		− printk(KERN_INFO "PCI: %s: IRQ %02x", pci_name(dev), dat);
	310	+ pr_info("PCI: %s: IRQ %02x", pci_name(dev), dat);
312	311	/* enable SMSC SLC90E66 IDE */
313	312	for (i = 0; i < ARRAY_SIZE(regs); i++) {
314	313	pci_read_config_byte(dev, regs[i], &dat);
315	314	pci_write_config_byte(dev, regs[i], dat \| 0x80);
316	315	pci_read_config_byte(dev, regs[i], &dat);
317		− printk(KERN_CONT " IDETIM%d %02x", i, dat);
	316	+ pr_cont(" IDETIM%d %02x", i, dat);
318	317	}
319	318	pci_read_config_byte(dev, 0x5c, &dat);
320	319	/*
@@ -329,8 +328,7 @@ static void quirk_slc90e66_ide(struct pci_dev *dev) · 8 unmodified lines
329	328	dat \|= 0x01;
330	329	pci_write_config_byte(dev, 0x5c, dat);
331	330	pci_read_config_byte(dev, 0x5c, &dat);
332		− printk(KERN_CONT " REG5C %02x", dat);
333		− printk(KERN_CONT "\n");
	331	+ pr_cont(" REG5C %02x\n", dat);
334	332	}
335	333	#endif /* CONFIG_TOSHIBA_FPCIB0 */
336	334
@@ -352,7 +350,7 @@ static void final_fixup(struct pci_dev *dev) · 15 unmodified lines
352	350	(bist & PCI_BIST_CAPABLE)) {
353	351	unsigned long timeout;
354	352	pci_set_power_state(dev, PCI_D0);
355		− printk(KERN_INFO "PCI: %s BIST...", pci_name(dev));
	353	+ pr_info("PCI: %s BIST...", pci_name(dev));
356	354	pci_write_config_byte(dev, PCI_BIST, PCI_BIST_START);
357	355	timeout = jiffies + HZ * 2; /* timeout after 2 sec */
358	356	do {
@@ -361,9 +359,9 @@ static void final_fixup(struct pci_dev *dev) · 2 unmodified lines
361	359	break;
362	360	} while (bist & PCI_BIST_START);
363	361	if (bist & (PCI_BIST_CODE_MASK \| PCI_BIST_START))
364		− printk(KERN_CONT "failed. (0x%x)\n", bist);
	362	+ pr_cont("failed. (0x%x)\n", bist);
365	363	else
366		− printk(KERN_CONT "OK.\n");
	364	+ pr_cont("OK.\n");
367	365	}
368	366	}
369	367

arch/mips/txx9/generic/setup.c+1−1

@@ -14,7 +14,7 @@ · 13 unmodified lines
14	14	#include <linux/types.h>
15	15	#include <linux/interrupt.h>
16	16	#include <linux/string.h>
17		−#include <linux/module.h>
	17	+#include <linux/export.h>
18	18	#include <linux/clk-provider.h>
19	19	#include <linux/clkdev.h>
20	20	#include <linux/err.h>

arch/mips/txx9/generic/setup_tx3927.c+3−3

@@ -67,9 +67,9 @@ void __init tx3927_setup(void) · 66 unmodified lines
67	67	/* do reset on watchdog */
68	68	tx3927_ccfgptr->ccfg \|= TX3927_CCFG_WR;
69	69
70		− printk(KERN_INFO "TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
71		− tx3927_ccfgptr->crir,
72		− tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
	70	+ pr_info("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
	71	+ tx3927_ccfgptr->crir, tx3927_ccfgptr->ccfg,
	72	+ tx3927_ccfgptr->pcfg);
73	73
74	74	/* TMR */
75	75	for (i = 0; i < TX3927_NR_TMR; i++)

arch/mips/txx9/generic/setup_tx4927.c+9−11

@@ -183,15 +183,14 @@ void __init tx4927_setup(void) · 182 unmodified lines
183	183	if (!(____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB))
184	184	txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_PCICLKEN_ALL);
185	185
186		− printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
187		− txx9_pcode_str,
188		− (cpuclk + 500000) / 1000000,
189		− (txx9_master_clock + 500000) / 1000000,
190		− (__u32)____raw_readq(&tx4927_ccfgptr->crir),
191		− (unsigned long long)____raw_readq(&tx4927_ccfgptr->ccfg),
192		− (unsigned long long)____raw_readq(&tx4927_ccfgptr->pcfg));
	186	+ pr_info("%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
	187	+ txx9_pcode_str, (cpuclk + 500000) / 1000000,
	188	+ (txx9_master_clock + 500000) / 1000000,
	189	+ (__u32)____raw_readq(&tx4927_ccfgptr->crir),
	190	+ ____raw_readq(&tx4927_ccfgptr->ccfg),
	191	+ ____raw_readq(&tx4927_ccfgptr->pcfg));
193	192
194		− printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
	193	+ pr_info("%s SDRAMC --", txx9_pcode_str);
195	194	for (i = 0; i < 4; i++) {
196	195	__u64 cr = TX4927_SDRAMC_CR(i);
197	196	unsigned long base, size;
@@ -199,15 +198,14 @@ void __init tx4927_setup(void) · 1 unmodified line
199	198	continue; /* disabled */
200	199	base = (unsigned long)(cr >> 49) << 21;
201	200	size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21;
202		− printk(" CR%d:%016llx", i, (unsigned long long)cr);
	201	+ pr_cont(" CR%d:%016llx", i, cr);
203	202	tx4927_sdram_resource[i].name = "SDRAM";
204	203	tx4927_sdram_resource[i].start = base;
205	204	tx4927_sdram_resource[i].end = base + size - 1;
206	205	tx4927_sdram_resource[i].flags = IORESOURCE_MEM;
207	206	request_resource(&iomem_resource, &tx4927_sdram_resource[i]);
208	207	}
209		− printk(" TR:%09llx\n",
210		− (unsigned long long)____raw_readq(&tx4927_sdramcptr->tr));
	208	+ pr_cont(" TR:%09llx\n", ____raw_readq(&tx4927_sdramcptr->tr));
211	209
212	210	/* TMR */
213	211	/* disable all timers */

arch/mips/txx9/generic/setup_tx4938.c+13−15

@@ -196,15 +196,14 @@ void __init tx4938_setup(void) · 195 unmodified lines
196	196	if (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB))
197	197	txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_PCICLKEN_ALL);
198	198
199		− printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
200		− txx9_pcode_str,
201		− (cpuclk + 500000) / 1000000,
202		− (txx9_master_clock + 500000) / 1000000,
203		− (__u32)____raw_readq(&tx4938_ccfgptr->crir),
204		− (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg),
205		− (unsigned long long)____raw_readq(&tx4938_ccfgptr->pcfg));
206		−
207		− printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
	199	+ pr_info("%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
	200	+ txx9_pcode_str, (cpuclk + 500000) / 1000000,
	201	+ (txx9_master_clock + 500000) / 1000000,
	202	+ (__u32)____raw_readq(&tx4938_ccfgptr->crir),
	203	+ ____raw_readq(&tx4938_ccfgptr->ccfg),
	204	+ ____raw_readq(&tx4938_ccfgptr->pcfg));
	205	+
	206	+ pr_info("%s SDRAMC --", txx9_pcode_str);
208	207	for (i = 0; i < 4; i++) {
209	208	__u64 cr = TX4938_SDRAMC_CR(i);
210	209	unsigned long base, size;
@@ -212,15 +211,14 @@ void __init tx4938_setup(void) · 1 unmodified line
212	211	continue; /* disabled */
213	212	base = (unsigned long)(cr >> 49) << 21;
214	213	size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21;
215		− printk(" CR%d:%016llx", i, (unsigned long long)cr);
	214	+ pr_cont(" CR%d:%016llx", i, cr);
216	215	tx4938_sdram_resource[i].name = "SDRAM";
217	216	tx4938_sdram_resource[i].start = base;
218	217	tx4938_sdram_resource[i].end = base + size - 1;
219	218	tx4938_sdram_resource[i].flags = IORESOURCE_MEM;
220	219	request_resource(&iomem_resource, &tx4938_sdram_resource[i]);
221	220	}
222		− printk(" TR:%09llx\n",
223		− (unsigned long long)____raw_readq(&tx4938_sdramcptr->tr));
	221	+ pr_cont(" TR:%09llx\n", ____raw_readq(&tx4938_sdramcptr->tr));
224	222
225	223	/* SRAM */
226	224	if (txx9_pcode == 0x4938 && ____raw_readq(&tx4938_sramcptr->cr) & 1) {
@@ -254,20 +252,20 @@ void __init tx4938_setup(void) · 27 unmodified lines
254	252	txx9_clear64(&tx4938_ccfgptr->clkctr,
255	253	TX4938_CLKCTR_PCIC1RST);
256	254	} else {
257		− printk(KERN_INFO "%s: stop PCIC1\n", txx9_pcode_str);
	255	+ pr_info("%s: stop PCIC1\n", txx9_pcode_str);
258	256	/* stop PCIC1 */
259	257	txx9_set64(&tx4938_ccfgptr->clkctr,
260	258	TX4938_CLKCTR_PCIC1CKD);
261	259	}
262	260	if (!(pcfg & TX4938_PCFG_ETH0_SEL)) {
263		− printk(KERN_INFO "%s: stop ETH0\n", txx9_pcode_str);
	261	+ pr_info("%s: stop ETH0\n", txx9_pcode_str);
264	262	txx9_set64(&tx4938_ccfgptr->clkctr,
265	263	TX4938_CLKCTR_ETH0RST);
266	264	txx9_set64(&tx4938_ccfgptr->clkctr,
267	265	TX4938_CLKCTR_ETH0CKD);
268	266	}
269	267	if (!(pcfg & TX4938_PCFG_ETH1_SEL)) {
270		− printk(KERN_INFO "%s: stop ETH1\n", txx9_pcode_str);
	268	+ pr_info("%s: stop ETH1\n", txx9_pcode_str);
271	269	txx9_set64(&tx4938_ccfgptr->clkctr,
272	270	TX4938_CLKCTR_ETH1RST);
273	271	txx9_set64(&tx4938_ccfgptr->clkctr,

arch/mips/txx9/generic/setup_tx4939.c+4−4

@@ -221,8 +221,8 @@ void __init tx4939_setup(void) · 220 unmodified lines
221	221	(txx9_master_clock + 500000) / 1000000,
222	222	(txx9_gbus_clock + 500000) / 1000000,
223	223	(__u32)____raw_readq(&tx4939_ccfgptr->crir),
224		− (unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg),
225		− (unsigned long long)____raw_readq(&tx4939_ccfgptr->pcfg));
	224	+ ____raw_readq(&tx4939_ccfgptr->ccfg),
	225	+ ____raw_readq(&tx4939_ccfgptr->pcfg));
226	226
227	227	pr_info("%s DDRC -- EN:%08x", txx9_pcode_str,
228	228	(__u32)____raw_readq(&tx4939_ddrcptr->winen));
@@ -230,7 +230,7 @@ void __init tx4939_setup(void) · 1 unmodified line
230	230	__u64 win = ____raw_readq(&tx4939_ddrcptr->win[i]);
231	231	if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
232	232	continue; /* disabled */
233		− printk(KERN_CONT " #%d:%016llx", i, (unsigned long long)win);
	233	+ pr_cont(" #%d:%016llx", i, win);
234	234	tx4939_sdram_resource[i].name = "DDR SDRAM";
235	235	tx4939_sdram_resource[i].start =
236	236	(unsigned long)(win >> 48) << 20;
@@ -240,7 +240,7 @@ void __init tx4939_setup(void) · 3 unmodified lines
240	240	tx4939_sdram_resource[i].flags = IORESOURCE_MEM;
241	241	request_resource(&iomem_resource, &tx4939_sdram_resource[i]);
242	242	}
243		− printk(KERN_CONT "\n");
	243	+ pr_cont("\n");
244	244
245	245	/* SRAM */
246	246	if (____raw_readq(&tx4939_sramcptr->cr) & 1) {

arch/mips/txx9/generic/smsc_fdc37m81x.c+7−10

@@ -105,9 +105,8 @@ unsigned long __init smsc_fdc37m81x_init(unsigned long port) · 104 unmodified lines
105	105	u8 chip_id;
106	106
107	107	if (g_smsc_fdc37m81x_base)
108		− printk(KERN_WARNING "%s: stepping on old base=0x%0*lx\n",
109		− __func__,
110		− field, g_smsc_fdc37m81x_base);
	108	+ pr_warn("%s: stepping on old base=0x%0*lx\n", __func__, field,
	109	+ g_smsc_fdc37m81x_base);
111	110
112	111	g_smsc_fdc37m81x_base = port;
113	112
@@ -117,8 +116,7 @@ unsigned long __init smsc_fdc37m81x_init(unsigned long port) · 3 unmodified lines
117	116	if (chip_id == SMSC_FDC37M81X_CHIP_ID)
118	117	smsc_fdc37m81x_config_end();
119	118	else {
120		− printk(KERN_WARNING "%s: unknown chip id 0x%02x\n", __func__,
121		− chip_id);
	119	+ pr_warn("%s: unknown chip id 0x%02x\n", __func__, chip_id);
122	120	g_smsc_fdc37m81x_base = 0;
123	121	}
124	122
@@ -128,9 +126,8 @@ unsigned long __init smsc_fdc37m81x_init(unsigned long port) · 3 unmodified lines
128	126	#ifdef DEBUG
129	127	static void smsc_fdc37m81x_config_dump_one(const char *key, u8 dev, u8 reg)
130	128	{
131		− printk(KERN_INFO "%s: dev=0x%02x reg=0x%02x val=0x%02x\n",
132		− key, dev, reg,
133		− smsc_fdc37m81x_rd(reg));
	129	+ pr_info("%s: dev=0x%02x reg=0x%02x val=0x%02x\n", key, dev, reg,
	130	+ smsc_fdc37m81x_rd(reg));
134	131	}
135	132
136	133	void smsc_fdc37m81x_config_dump(void)
@@ -142,7 +139,7 @@ void smsc_fdc37m81x_config_dump(void) · 5 unmodified lines
142	139
143	140	orig = smsc_fdc37m81x_rd(SMSC_FDC37M81X_DNUM);
144	141
145		− printk(KERN_INFO "%s: common\n", fname);
	142	+ pr_info("%s: common\n", fname);
146	143	smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE,
147	144	SMSC_FDC37M81X_DNUM);
148	145	smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE,
@@ -154,7 +151,7 @@ void smsc_fdc37m81x_config_dump(void) · 5 unmodified lines
154	151	smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE,
155	152	SMSC_FDC37M81X_PMGT);
156	153
157		− printk(KERN_INFO "%s: keyboard\n", fname);
	154	+ pr_info("%s: keyboard\n", fname);
158	155	smsc_dc37m81x_wr(SMSC_FDC37M81X_DNUM, SMSC_FDC37M81X_KBD);
159	156	smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD,
160	157	SMSC_FDC37M81X_ACTIVE);

arch/mips/txx9/jmr3927/prom.c+1−1

@@ -45,7 +45,7 @@ void __init jmr3927_prom_init(void) · 44 unmodified lines
45	45	{
46	46	/* CCFG */
47	47	if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0)
48		− printk(KERN_ERR "TX3927 TLB off\n");
	48	+ pr_err("TX3927 TLB off\n");
49	49
50	50	add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM);
51	51	txx9_sio_putchar_init(TX3927_SIO_REG(1));

arch/mips/txx9/jmr3927/setup.c+5−6

@@ -150,12 +150,11 @@ static void __init jmr3927_board_init(void) · 149 unmodified lines
150	150
151	151	jmr3927_led_set(0);
152	152
153		− printk(KERN_INFO
154		− "JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
155		− jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
156		− jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
157		− jmr3927_dipsw1(), jmr3927_dipsw2(),
158		− jmr3927_dipsw3(), jmr3927_dipsw4());
	153	+ pr_info("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
	154	+ jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
	155	+ jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
	156	+ jmr3927_dipsw1(), jmr3927_dipsw2(),
	157	+ jmr3927_dipsw3(), jmr3927_dipsw4());
159	158	}
160	159
161	160	/* This trick makes rtc-ds1742 driver usable as is. */

arch/mips/txx9/rbtx4938/setup.c+7−7

@@ -123,15 +123,15 @@ static int __init rbtx4938_ethaddr_init(void) · 122 unmodified lines
123	123
124	124	/* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
125	125	if (spi_eeprom_read(SPI_BUSNO, SEEPROM1_CS, 0, dat, sizeof(dat))) {
126		− printk(KERN_ERR "seeprom: read error.\n");
	126	+ pr_err("seeprom: read error.\n");
127	127	return -ENODEV;
128	128	} else {
129	129	if (strcmp(dat, "MAC") != 0)
130		− printk(KERN_WARNING "seeprom: bad signature.\n");
	130	+ pr_warn("seeprom: bad signature.\n");
131	131	for (i = 0, sum = 0; i < sizeof(dat); i++)
132	132	sum += dat[i];
133	133	if (sum)
134		− printk(KERN_WARNING "seeprom: bad checksum.\n");
	134	+ pr_warn("seeprom: bad checksum.\n");
135	135	}
136	136	tx4938_ethaddr_init(&dat[4], &dat[4 + 6]);
137	137	#endif /* CONFIG_PCI */
@@ -214,14 +214,14 @@ static void __init rbtx4938_mem_setup(void) · 76 unmodified lines
214	214	rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
215	215	rbtx4938_fpga_resource.flags = IORESOURCE_MEM \| IORESOURCE_BUSY;
216	216	if (request_resource(&txx9_ce_res[2], &rbtx4938_fpga_resource))
217		− printk(KERN_ERR "request resource for fpga failed\n");
	217	+ pr_err("request resource for fpga failed\n");
218	218
219	219	_machine_restart = rbtx4938_machine_restart;
220	220
221	221	writeb(0xff, rbtx4938_led_addr);
222		− printk(KERN_INFO "RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
223		− readb(rbtx4938_fpga_rev_addr),
224		− readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr));
	222	+ pr_info("RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
	223	+ readb(rbtx4938_fpga_rev_addr),
	224	+ readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr));
225	225	}
226	226
227	227	static void __init rbtx4938_ne_init(void)

arch/mips/vdso/Makefile+6−2

@@ -11,6 +11,7 @@ cflags-vdso := $(ccflags-vdso) \ · 10 unmodified lines
11	11	$(filter -W%,$(filter-out -Wa$(comma)%,$(KBUILD_CFLAGS))) \
12	12	-O2 -g -fPIC -fno-strict-aliasing -fno-common -fno-builtin -G 0 \
13	13	-DDISABLE_BRANCH_PROFILING \
	14	+ $(call cc-option, -fno-asynchronous-unwind-tables) \
14	15	$(call cc-option, -fno-stack-protector)
15	16	aflags-vdso := $(ccflags-vdso) \
16	17	-D__ASSEMBLY__ -Wa,-gdwarf-2
@@ -50,6 +51,9 @@ quiet_cmd_vdsold = VDSO $@ · 33 unmodified lines
50	51	cmd_vdsold = $(CC) $(c_flags) $(VDSO_LDFLAGS) \
51	52	-Wl,-T $(filter %.lds,$^) $(filter %.o,$^) -o $@
52	53
	54	+quiet_cmd_vdsoas_o_S = AS $@
	55	+ cmd_vdsoas_o_S = $(CC) $(a_flags) -c -o $@ $<
	56	+
53	57	# Strip rule for the raw .so files
54	58	$(obj)/%.so.raw: OBJCOPYFLAGS := -S
55	59	$(obj)/%.so.raw: $(obj)/%.so.dbg.raw FORCE
@@ -110,7 +114,7 @@ $(obj-vdso-o32): KBUILD_CFLAGS := $(cflags-vdso) -mabi=32 · 54 unmodified lines
110	114	$(obj-vdso-o32): KBUILD_AFLAGS := $(aflags-vdso) -mabi=32
111	115
112	116	$(obj)/%-o32.o: $(src)/%.S FORCE
113		− $(call if_changed_dep,as_o_S)
	117	+ $(call if_changed_dep,vdsoas_o_S)
114	118
115	119	$(obj)/%-o32.o: $(src)/%.c FORCE
116	120	$(call cmd,force_checksrc)
@@ -150,7 +154,7 @@ $(obj-vdso-n32): KBUILD_CFLAGS := $(cflags-vdso) -mabi=n32 · 33 unmodified lines
150	154	$(obj-vdso-n32): KBUILD_AFLAGS := $(aflags-vdso) -mabi=n32
151	155
152	156	$(obj)/%-n32.o: $(src)/%.S FORCE
153		− $(call if_changed_dep,as_o_S)
	157	+ $(call if_changed_dep,vdsoas_o_S)
154	158
155	159	$(obj)/%-n32.o: $(src)/%.c FORCE
156	160	$(call cmd,force_checksrc)

arch/mips/vr41xx/common/bcu.c+2−1

@@ -28,11 +28,12 @@ · 27 unmodified lines
28	28	* Yoichi Yuasa <yuasa@linux-mips.org>
29	29	* - Added support for NEC VR4133.
30	30	*/
	31	+#include <linux/export.h>
31	32	#include <linux/kernel.h>
32		−#include <linux/module.h>
33	33	#include <linux/smp.h>
34	34	#include <linux/types.h>
35	35
	36	+#include <asm/cpu-type.h>
36	37	#include <asm/cpu.h>
37	38	#include <asm/io.h>
38	39

arch/mips/vr41xx/common/cmu.c+1−1

@@ -28,9 +28,9 @@ · 27 unmodified lines
28	28	* Yoichi Yuasa <yuasa@linux-mips.org>
29	29	* - Added support for NEC VR4133.
30	30	*/
	31	+#include <linux/export.h>
31	32	#include <linux/init.h>
32	33	#include <linux/ioport.h>
33		−#include <linux/module.h>
34	34	#include <linux/smp.h>
35	35	#include <linux/spinlock.h>
36	36	#include <linux/types.h>

arch/mips/vr41xx/common/icu.c+1−1

@@ -29,10 +29,10 @@ · 28 unmodified lines
29	29	* - Coped with INTASSIGN of NEC VR4133.
30	30	*/
31	31	#include <linux/errno.h>
	32	+#include <linux/export.h>
32	33	#include <linux/init.h>
33	34	#include <linux/ioport.h>
34	35	#include <linux/irq.h>
35		−#include <linux/module.h>
36	36	#include <linux/smp.h>
37	37	#include <linux/types.h>
38	38

arch/mips/vr41xx/common/irq.c+1−1

@@ -17,8 +17,8 @@ · 16 unmodified lines
17	17	* along with this program; if not, write to the Free Software
18	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19	19	*/
	20	+#include <linux/export.h>
20	21	#include <linux/interrupt.h>
21		−#include <linux/module.h>
22	22	#include <linux/irq.h>
23	23
24	24	#include <asm/irq_cpu.h>

arch/mips/xilfpga/intc.c+2−5

@@ -11,15 +11,12 @@ · 10 unmodified lines
11	11
12	12	#include <linux/of.h>
13	13	#include <linux/of_irq.h>
	14	+#include <linux/irqchip.h>
14	15
15	16	#include <asm/irq_cpu.h>
16	17
17		−static struct of_device_id of_irq_ids[] __initdata = {
18		− { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init },
19		− {},
20		−};
21	18
22	19	void __init arch_init_irq(void)
23	20	{
24		− of_irq_init(of_irq_ids);
	21	+ irqchip_init();
25	22	}

drivers/of/base.c+1−1

@@ -2112,7 +2112,7 @@ void of_alias_scan(void * (*dt_alloc)(u64 size, u64 align)) · 2111 unmodified lines
2112	2112	continue;
2113	2113
2114	2114	/* Allocate an alias_prop with enough space for the stem */
2115		− ap = dt_alloc(sizeof(*ap) + len + 1, 4);
	2115	+ ap = dt_alloc(sizeof(ap) + len + 1, __alignof__(ap));
2116	2116	if (!ap)
2117	2117	continue;
2118	2118	memset(ap, 0, sizeof(*ap) + len + 1);

drivers/of/fdt.c+6−3

@@ -738,9 +738,12 @@ int __init of_scan_flat_dt(int (*it)(unsigned long node, · 737 unmodified lines
738	738	const char *pathp;
739	739	int offset, rc = 0, depth = -1;
740	740
741		− for (offset = fdt_next_node(blob, -1, &depth);
742		− offset >= 0 && depth >= 0 && !rc;
743		− offset = fdt_next_node(blob, offset, &depth)) {
	741	+ if (!blob)
	742	+ return 0;
	743	+
	744	+ for (offset = fdt_next_node(blob, -1, &depth);
	745	+ offset >= 0 && depth >= 0 && !rc;
	746	+ offset = fdt_next_node(blob, offset, &depth)) {
744	747
745	748	pathp = fdt_get_name(blob, offset, NULL);
746	749	if (*pathp == '/')

scripts/Kbuild.include+1−1

@@ -284,7 +284,7 @@ ksym_dep_filter = \ · 283 unmodified lines
284	284	$(CPP) $(call flags_nodeps,c_flags) -D__KSYM_DEPS__ $< ;; \
285	285	as_*_S\|cpp_s_S) \
286	286	$(CPP) $(call flags_nodeps,a_flags) -D__KSYM_DEPS__ $< ;; \
287		− boot\|build\|cpp_lds_S\|dtc\|host\|vdso*) : ;; \
	287	+ boot\|build\|cpp_its_S\|cpp_lds_S\|dtc\|host\|vdso*) : ;; \
288	288	*) echo "Don't know how to preprocess $(1)" >&2; false ;; \
289	289	esac \| tr ";" "\n" \| sed -rn 's/^.=== __KSYM_(.) ===.*$$/KSYM_\1/p'
290	290