Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mturquette/linux

Pull clock subsystem fixes from Mike Turquette: "A mix of small fixes affecting mostly ARM platforms as well as a discrete clock expander chip. Most fixes are corrections to lousy clock data of one form or another." * tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mturquette/linux: clk: mxs: Include clk mxs header file clk: vt8500: Fix unbalanced spinlock in vt8500_dclk_set_rate() clk: si5351: Set initial clkout rate when defined in platform data. clk: si5351: Fix clkout rate computation. clk: samsung: Add CLK_IGNORE_UNUSED flag for the sysreg clocks clk: ux500: clk-sysctrl: handle clocks with no parents clk: ux500: Provide device enumeration number suffix for SMSC911x

Linus Torvalds committed 13 years ago

Commit 0f7dafd2 parents c361cb5 d68c3806 files · +25 −6Browse files

Unified · Split

6 files

drivers/clk/clk-si5351.c +11 −1
drivers/clk/clk-vt8500.c +1 −1
drivers/clk/mxs/clk-imx28.c +1 −0
drivers/clk/samsung/clk-exynos4.c +4 −2
drivers/clk/ux500/clk-sysctrl.c +7 −1
drivers/clk/ux500/u8500_clk.c +1 −1

drivers/clk/clk-si5351.c+11−1

 	unsigned char reg;
 	unsigned char rdiv;
-	if (hwdata->num > 5)
+	if (hwdata->num <= 5)
 		reg = si5351_msynth_params_address(hwdata->num) + 2;
 	else
 		reg = SI5351_CLK6_7_OUTPUT_DIVIDER;
 			return -EINVAL;
 		}
 		drvdata->onecell.clks[n] = clk;
+		/* set initial clkout rate */
+		if (pdata->clkout[n].rate != 0) {
+			int ret;
+			ret = clk_set_rate(clk, pdata->clkout[n].rate);
+			if (ret != 0) {
+				dev_err(&client->dev, "Cannot set rate : %d\n",
+					ret);
+			}
+		}
 	}
 	ret = of_clk_add_provider(client->dev.of_node, of_clk_src_onecell_get,

drivers/clk/clk-vt8500.c+1−1

@@ -183,7 +183,7 @@ static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate, · 182 unmodified lines
183	writel(divisor, cdev->div_reg);	183	writel(divisor, cdev->div_reg);
184	vt8500_pmc_wait_busy();	184	vt8500_pmc_wait_busy();
185		185
186	spin_lock_irqsave(cdev->lock, flags);	186	spin_unlock_irqrestore(cdev->lock, flags);
187		187
188	return 0;	188	return 0;
189	}	189	}

drivers/clk/mxs/clk-imx28.c+1−0

@@ -10,6 +10,7 @@ · 9 unmodified lines
10	*/	10	*/
11		11
12	#include <linux/clk.h>	12	#include <linux/clk.h>
		13	#include <linux/clk/mxs.h>
13	#include <linux/clkdev.h>	14	#include <linux/clkdev.h>
14	#include <linux/err.h>	15	#include <linux/err.h>
15	#include <linux/init.h>	16	#include <linux/init.h>

drivers/clk/samsung/clk-exynos4.c+4−2

 	GATE(smmu_pcie, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0),
 	GATE(modemif, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0),
 	GATE(chipid, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
-	GATE(sysreg, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
+	GATE(sysreg, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0,
+			CLK_IGNORE_UNUSED, 0),
 	GATE(hdmi_cec, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0, 0),
 	GATE(smmu_rotator, "smmu_rotator", "aclk200",
 			E4210_GATE_IP_IMAGE, 4, 0, 0),
 	GATE(smmu_mdma, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 0),
 	GATE(mipi_hsi, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
 	GATE(chipid, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0),
-	GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, 0, 0),
+	GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1,
+			CLK_IGNORE_UNUSED, 0),
 	GATE(hdmi_cec, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, 0),
 	GATE(sclk_mdnie0, "sclk_mdnie0", "div_mdnie0",
 			SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0),

drivers/clk/ux500/clk-sysctrl.c+7−1

 		return ERR_PTR(-ENOMEM);
 	}
-	for (i = 0; i < num_parents; i++) {
+	/* set main clock registers */
+	clk->reg_sel[0] = reg_sel[0];
+	clk->reg_bits[0] = reg_bits[0];
+	clk->reg_mask[0] = reg_mask[0];
+	/* handle clocks with more than one parent */
+	for (i = 1; i < num_parents; i++) {
 		clk->reg_sel[i] = reg_sel[i];
 		clk->reg_bits[i] = reg_bits[i];
 		clk->reg_mask[i] = reg_mask[i];

drivers/clk/ux500/u8500_clk.c+1−1

@@ -325,7 +325,7 @@ void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, · 324 unmodified lines
325	clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base,	325	clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base,
326	BIT(0), 0);	326	BIT(0), 0);
327	clk_register_clkdev(clk, "fsmc", NULL);	327	clk_register_clkdev(clk, "fsmc", NULL);
328	clk_register_clkdev(clk, NULL, "smsc911x");	328	clk_register_clkdev(clk, NULL, "smsc911x.0");
329		329
330	clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base,	330	clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base,
331	BIT(1), 0);	331	BIT(1), 0);