Add L1 substate capability structure register definitions for use in subsequent patches. See the PCIe r3.1 spec, sec 7.33. [bhelgaas: add PCIe spec reference] Signed-off-by: Rajat Jain <rajatja@google.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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| @@ -682,6 +682,7 @@ · 681 unmodified lines | ||
| 682 | 682 | #define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */ |
| 683 | 683 | #define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ |
| 684 | 684 | #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */ |
| 685 | +#define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ | |
| 685 | 686 | #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ |
| 686 | 687 | #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM |
| 687 | 688 | |
| @@ -985,4 +986,19 @@ · 297 unmodified lines | ||
| 985 | 986 | #define PCI_PTM_CTRL_ENABLE 0x00000001 /* PTM enable */ |
| 986 | 987 | #define PCI_PTM_CTRL_ROOT 0x00000002 /* Root select */ |
| 987 | 988 | |
| 989 | +/* L1 PM Substates */ | |
| 990 | +#define PCI_L1SS_CAP 4 /* capability register */ | |
| 991 | +#define PCI_L1SS_CAP_PCIPM_L1_2 1 /* PCI PM L1.2 Support */ | |
| 992 | +#define PCI_L1SS_CAP_PCIPM_L1_1 2 /* PCI PM L1.1 Support */ | |
| 993 | +#define PCI_L1SS_CAP_ASPM_L1_2 4 /* ASPM L1.2 Support */ | |
| 994 | +#define PCI_L1SS_CAP_ASPM_L1_1 8 /* ASPM L1.1 Support */ | |
| 995 | +#define PCI_L1SS_CAP_L1_PM_SS 16 /* L1 PM Substates Support */ | |
| 996 | +#define PCI_L1SS_CTL1 8 /* Control Register 1 */ | |
| 997 | +#define PCI_L1SS_CTL1_PCIPM_L1_2 1 /* PCI PM L1.2 Enable */ | |
| 998 | +#define PCI_L1SS_CTL1_PCIPM_L1_1 2 /* PCI PM L1.1 Support */ | |
| 999 | +#define PCI_L1SS_CTL1_ASPM_L1_2 4 /* ASPM L1.2 Support */ | |
| 1000 | +#define PCI_L1SS_CTL1_ASPM_L1_1 8 /* ASPM L1.1 Support */ | |
| 1001 | +#define PCI_L1SS_CTL1_L1SS_MASK 0x0000000F | |
| 1002 | +#define PCI_L1SS_CTL2 0xC /* Control Register 2 */ | |
| 1003 | + | |
| 988 | 1004 | #endif /* LINUX_PCI_REGS_H */ |