lael-labs/linux

.mailmap+2−0

 Ben Gardner <bgardner@wabtec.com>
 Ben M Cahill <ben.m.cahill@intel.com>
 Björn Steinbrink <B.Steinbrink@gmx.de>
+Björn Töpel <bjorn@kernel.org> <bjorn.topel@gmail.com>
+Björn Töpel <bjorn@kernel.org> <bjorn.topel@intel.com>
 Boris Brezillon <bbrezillon@kernel.org> <b.brezillon.dev@gmail.com>
 Boris Brezillon <bbrezillon@kernel.org> <b.brezillon@overkiz.com>
 Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@bootlin.com>

Documentation/admin-guide/kernel-parameters.txt+4−0

 			This option is obsoleted by the "nopv" option, which
 			has equivalent effect for XEN platform.
+	xen_no_vector_callback
+			[KNL,X86,XEN] Disable the vector callback for Xen
+			event channel interrupts.
 	xen_scrub_pages=	[XEN]
 			Boolean option to control scrubbing pages before giving them back
 			to Xen, for use by other domains. Can be also changed at runtime

Documentation/firmware-guide/acpi/apei/einj.rst+2−2

@@ -50,8 +50,8 @@ The following files belong to it: · 49 unmodified lines
50	0x00000010 Memory Uncorrectable non-fatal	50	0x00000010 Memory Uncorrectable non-fatal
51	0x00000020 Memory Uncorrectable fatal	51	0x00000020 Memory Uncorrectable fatal
52	0x00000040 PCI Express Correctable	52	0x00000040 PCI Express Correctable
53	0x00000080 PCI Express Uncorrectable fatal	53	0x00000080 PCI Express Uncorrectable non-fatal
54	0x00000100 PCI Express Uncorrectable non-fatal	54	0x00000100 PCI Express Uncorrectable fatal
55	0x00000200 Platform Correctable	55	0x00000200 Platform Correctable
56	0x00000400 Platform Uncorrectable non-fatal	56	0x00000400 Platform Uncorrectable non-fatal
57	0x00000800 Platform Uncorrectable fatal	57	0x00000800 Platform Uncorrectable fatal

Documentation/networking/tls-offload.rst+3−0

@@ -534,3 +534,6 @@ offload. Hence, TLS TX device feature flag requires TX csum offload being set. · 533 unmodified lines
534	Disabling the latter implies clearing the former. Disabling TX checksum offload	534	Disabling the latter implies clearing the former. Disabling TX checksum offload
535	should not affect old connections, and drivers should make sure checksum	535	should not affect old connections, and drivers should make sure checksum
536	calculation does not break for them.	536	calculation does not break for them.
		537	Similarly, device-offloaded TLS decryption implies doing RXCSUM. If the user
		538	does not want to enable RX csum offload, TLS RX device feature is disabled
		539	as well.

MAINTAINERS+5−4

 M:	Felix Kuehling <Felix.Kuehling@amd.com>
 L:	amd-gfx@lists.freedesktop.org
 S:	Supported
-T:	git git://people.freedesktop.org/~agd5f/linux
+T:	git https://gitlab.freedesktop.org/agd5f/linux.git
 F:	drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd*.[ch]
 F:	drivers/gpu/drm/amd/amdkfd/
 F:	drivers/gpu/drm/amd/include/cik_structs.h
 X:	arch/riscv/net/bpf_jit_comp64.c
 BPF JIT for RISC-V (64-bit)
-M:	Björn Töpel <bjorn.topel@gmail.com>
+M:	Björn Töpel <bjorn@kernel.org>
 L:	netdev@vger.kernel.org
 L:	bpf@vger.kernel.org
 S:	Maintained
 M:	Christian König <christian.koenig@amd.com>
 L:	amd-gfx@lists.freedesktop.org
 S:	Supported
-T:	git git://people.freedesktop.org/~agd5f/linux
+T:	git https://gitlab.freedesktop.org/agd5f/linux.git
 F:	drivers/gpu/drm/amd/
 F:	drivers/gpu/drm/radeon/
 F:	include/uapi/drm/amdgpu_drm.h
 M:	David Rientjes <rientjes@google.com>
 M:	Joonsoo Kim <iamjoonsoo.kim@lge.com>
 M:	Andrew Morton <akpm@linux-foundation.org>
+M:	Vlastimil Babka <vbabka@suse.cz>
 L:	linux-mm@kvack.org
 S:	Maintained
 F:	include/linux/sl?b*.h
 K:	(?:\b|_)xdp(?:\b|_)
 XDP SOCKETS (AF_XDP)
-M:	Björn Töpel <bjorn.topel@intel.com>
+M:	Björn Töpel <bjorn@kernel.org>
 M:	Magnus Karlsson <magnus.karlsson@intel.com>
 R:	Jonathan Lemon <jonathan.lemon@gmail.com>
 L:	netdev@vger.kernel.org

Makefile+1−1

@@ -2,7 +2,7 @@ · 1 unmodified line
2	VERSION = 5	2	VERSION = 5
3	PATCHLEVEL = 11	3	PATCHLEVEL = 11
4	SUBLEVEL = 0	4	SUBLEVEL = 0
5	EXTRAVERSION = -rc3	5	EXTRAVERSION = -rc4
6	NAME = Kleptomaniac Octopus	6	NAME = Kleptomaniac Octopus
7		7
8	# DOCUMENTATION	8	# DOCUMENTATION

arch/arm/xen/enlighten.c+1−1

@@ -371,7 +371,7 @@ static int __init xen_guest_init(void) · 370 unmodified lines
371	}	371	}
372	gnttab_init();	372	gnttab_init();
373	if (!xen_initial_domain())	373	if (!xen_initial_domain())
374	xenbus_probe(NULL);	374	xenbus_probe();
375		375
376	/*	376	/*
377	* Making sure board specific code will not set up ops for	377	* Making sure board specific code will not set up ops for

arch/arm64/Kconfig+0−2

 	select HAVE_NMI
 	select HAVE_PATA_PLATFORM
 	select HAVE_PERF_EVENTS
-	select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI && HW_PERF_EVENTS
-	select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && HAVE_PERF_EVENTS_NMI
 	select HAVE_PERF_REGS
 	select HAVE_PERF_USER_STACK_DUMP
 	select HAVE_REGS_AND_STACK_ACCESS_API

arch/arm64/include/asm/atomic.h+5−5

@@ -17,7 +17,7 @@ · 16 unmodified lines
17	#include <asm/lse.h>	17	#include <asm/lse.h>
18		18
19	#define ATOMIC_OP(op) \	19	#define ATOMIC_OP(op) \
20	static inline void arch_##op(int i, atomic_t *v) \	20	static __always_inline void arch_##op(int i, atomic_t *v) \
21	{ \	21	{ \
22	__lse_ll_sc_body(op, i, v); \	22	__lse_ll_sc_body(op, i, v); \
23	}	23	}
@@ -32,7 +32,7 @@ ATOMIC_OP(atomic_sub) · 8 unmodified lines
32	#undef ATOMIC_OP	32	#undef ATOMIC_OP
33		33
34	#define ATOMIC_FETCH_OP(name, op) \	34	#define ATOMIC_FETCH_OP(name, op) \
35	static inline int arch_##op##name(int i, atomic_t *v) \	35	static __always_inline int arch_##op##name(int i, atomic_t *v) \
36	{ \	36	{ \
37	return __lse_ll_sc_body(op##name, i, v); \	37	return __lse_ll_sc_body(op##name, i, v); \
38	}	38	}
@@ -56,7 +56,7 @@ ATOMIC_FETCH_OPS(atomic_sub_return) · 17 unmodified lines
56	#undef ATOMIC_FETCH_OPS	56	#undef ATOMIC_FETCH_OPS
57		57
58	#define ATOMIC64_OP(op) \	58	#define ATOMIC64_OP(op) \
59	static inline void arch_##op(long i, atomic64_t *v) \	59	static __always_inline void arch_##op(long i, atomic64_t *v) \
60	{ \	60	{ \
61	__lse_ll_sc_body(op, i, v); \	61	__lse_ll_sc_body(op, i, v); \
62	}	62	}
@@ -71,7 +71,7 @@ ATOMIC64_OP(atomic64_sub) · 8 unmodified lines
71	#undef ATOMIC64_OP	71	#undef ATOMIC64_OP
72		72
73	#define ATOMIC64_FETCH_OP(name, op) \	73	#define ATOMIC64_FETCH_OP(name, op) \
74	static inline long arch_##op##name(long i, atomic64_t *v) \	74	static __always_inline long arch_##op##name(long i, atomic64_t *v) \
75	{ \	75	{ \
76	return __lse_ll_sc_body(op##name, i, v); \	76	return __lse_ll_sc_body(op##name, i, v); \
77	}	77	}
@@ -94,7 +94,7 @@ ATOMIC64_FETCH_OPS(atomic64_sub_return) · 16 unmodified lines
94	#undef ATOMIC64_FETCH_OP	94	#undef ATOMIC64_FETCH_OP
95	#undef ATOMIC64_FETCH_OPS	95	#undef ATOMIC64_FETCH_OPS
96		96
97	static inline long arch_atomic64_dec_if_positive(atomic64_t *v)	97	static __always_inline long arch_atomic64_dec_if_positive(atomic64_t *v)
98	{	98	{
99	return __lse_ll_sc_body(atomic64_dec_if_positive, v);	99	return __lse_ll_sc_body(atomic64_dec_if_positive, v);
100	}	100	}

arch/arm64/include/asm/processor.h+1−2

@@ -94,8 +94,7 @@ · 93 unmodified lines
94	#endif /* CONFIG_ARM64_FORCE_52BIT */	94	#endif /* CONFIG_ARM64_FORCE_52BIT */
95		95
96	extern phys_addr_t arm64_dma_phys_limit;	96	extern phys_addr_t arm64_dma_phys_limit;
97	extern phys_addr_t arm64_dma32_phys_limit;	97	#define ARCH_LOW_ADDRESS_LIMIT (arm64_dma_phys_limit - 1)
98	#define ARCH_LOW_ADDRESS_LIMIT ((arm64_dma_phys_limit ? : arm64_dma32_phys_limit) - 1)
99		98
100	struct debug_info {	99	struct debug_info {
101	#ifdef CONFIG_HAVE_HW_BREAKPOINT	100	#ifdef CONFIG_HAVE_HW_BREAKPOINT

arch/arm64/kernel/asm-offsets.c+1−1

@@ -75,7 +75,7 @@ int main(void) · 74 unmodified lines
75	DEFINE(S_SDEI_TTBR1, offsetof(struct pt_regs, sdei_ttbr1));	75	DEFINE(S_SDEI_TTBR1, offsetof(struct pt_regs, sdei_ttbr1));
76	DEFINE(S_PMR_SAVE, offsetof(struct pt_regs, pmr_save));	76	DEFINE(S_PMR_SAVE, offsetof(struct pt_regs, pmr_save));
77	DEFINE(S_STACKFRAME, offsetof(struct pt_regs, stackframe));	77	DEFINE(S_STACKFRAME, offsetof(struct pt_regs, stackframe));
78	DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs));	78	DEFINE(PT_REGS_SIZE, sizeof(struct pt_regs));
79	BLANK();	79	BLANK();
80	#ifdef CONFIG_COMPAT	80	#ifdef CONFIG_COMPAT
81	DEFINE(COMPAT_SIGFRAME_REGS_OFFSET, offsetof(struct compat_sigframe, uc.uc_mcontext.arm_r0));	81	DEFINE(COMPAT_SIGFRAME_REGS_OFFSET, offsetof(struct compat_sigframe, uc.uc_mcontext.arm_r0));

arch/arm64/kernel/entry-ftrace.S+6−6

@@ -35,7 +35,7 @@ · 34 unmodified lines
35	*/	35	*/
36	.macro ftrace_regs_entry, allregs=0	36	.macro ftrace_regs_entry, allregs=0
37	/* Make room for pt_regs, plus a callee frame */	37	/* Make room for pt_regs, plus a callee frame */
38	sub sp, sp, #(S_FRAME_SIZE + 16)	38	sub sp, sp, #(PT_REGS_SIZE + 16)
39		39
40	/* Save function arguments (and x9 for simplicity) */	40	/* Save function arguments (and x9 for simplicity) */
41	stp x0, x1, [sp, #S_X0]	41	stp x0, x1, [sp, #S_X0]
@@ -61,15 +61,15 @@ · 19 unmodified lines
61	.endif	61	.endif
62		62
63	/* Save the callsite's SP and LR */	63	/* Save the callsite's SP and LR */
64	add x10, sp, #(S_FRAME_SIZE + 16)	64	add x10, sp, #(PT_REGS_SIZE + 16)
65	stp x9, x10, [sp, #S_LR]	65	stp x9, x10, [sp, #S_LR]
66		66
67	/* Save the PC after the ftrace callsite */	67	/* Save the PC after the ftrace callsite */
68	str x30, [sp, #S_PC]	68	str x30, [sp, #S_PC]
69		69
70	/* Create a frame record for the callsite above pt_regs */	70	/* Create a frame record for the callsite above pt_regs */
71	stp x29, x9, [sp, #S_FRAME_SIZE]	71	stp x29, x9, [sp, #PT_REGS_SIZE]
72	add x29, sp, #S_FRAME_SIZE	72	add x29, sp, #PT_REGS_SIZE
73		73
74	/* Create our frame record within pt_regs. */	74	/* Create our frame record within pt_regs. */
75	stp x29, x30, [sp, #S_STACKFRAME]	75	stp x29, x30, [sp, #S_STACKFRAME]
@@ -120,7 +120,7 @@ ftrace_common_return: · 44 unmodified lines
120	ldr x9, [sp, #S_PC]	120	ldr x9, [sp, #S_PC]
121		121
122	/* Restore the callsite's SP */	122	/* Restore the callsite's SP */
123	add sp, sp, #S_FRAME_SIZE + 16	123	add sp, sp, #PT_REGS_SIZE + 16
124		124
125	ret x9	125	ret x9
126	SYM_CODE_END(ftrace_common)	126	SYM_CODE_END(ftrace_common)
@@ -130,7 +130,7 @@ SYM_CODE_START(ftrace_graph_caller) · 3 unmodified lines
130	ldr x0, [sp, #S_PC]	130	ldr x0, [sp, #S_PC]
131	sub x0, x0, #AARCH64_INSN_SIZE // ip (callsite's BL insn)	131	sub x0, x0, #AARCH64_INSN_SIZE // ip (callsite's BL insn)
132	add x1, sp, #S_LR // parent_ip (callsite's LR)	132	add x1, sp, #S_LR // parent_ip (callsite's LR)
133	ldr x2, [sp, #S_FRAME_SIZE] // parent fp (callsite's FP)	133	ldr x2, [sp, #PT_REGS_SIZE] // parent fp (callsite's FP)
134	bl prepare_ftrace_return	134	bl prepare_ftrace_return
135	b ftrace_common_return	135	b ftrace_common_return
136	SYM_CODE_END(ftrace_graph_caller)	136	SYM_CODE_END(ftrace_graph_caller)

arch/arm64/kernel/entry.S+7−7

@@ -75,7 +75,7 @@ alternative_else_nop_endif · 74 unmodified lines
75	.endif	75	.endif
76	#endif	76	#endif
77		77
78	sub sp, sp, #S_FRAME_SIZE	78	sub sp, sp, #PT_REGS_SIZE
79	#ifdef CONFIG_VMAP_STACK	79	#ifdef CONFIG_VMAP_STACK
80	/*	80	/*
81	* Test whether the SP has overflowed, without corrupting a GPR.	81	* Test whether the SP has overflowed, without corrupting a GPR.
@@ -96,7 +96,7 @@ alternative_else_nop_endif · 14 unmodified lines
96	* userspace, and can clobber EL0 registers to free up GPRs.	96	* userspace, and can clobber EL0 registers to free up GPRs.
97	*/	97	*/
98		98
99	/* Stash the original SP (minus S_FRAME_SIZE) in tpidr_el0. */	99	/* Stash the original SP (minus PT_REGS_SIZE) in tpidr_el0. */
100	msr tpidr_el0, x0	100	msr tpidr_el0, x0
101		101
102	/* Recover the original x0 value and stash it in tpidrro_el0 */	102	/* Recover the original x0 value and stash it in tpidrro_el0 */
@@ -253,7 +253,7 @@ alternative_else_nop_endif · 150 unmodified lines
253		253
254	scs_load tsk, x20	254	scs_load tsk, x20
255	.else	255	.else
256	add x21, sp, #S_FRAME_SIZE	256	add x21, sp, #PT_REGS_SIZE
257	get_current_task tsk	257	get_current_task tsk
258	.endif /* \el == 0 */	258	.endif /* \el == 0 */
259	mrs x22, elr_el1	259	mrs x22, elr_el1
@@ -377,7 +377,7 @@ alternative_else_nop_endif · 117 unmodified lines
377	ldp x26, x27, [sp, #16 * 13]	377	ldp x26, x27, [sp, #16 * 13]
378	ldp x28, x29, [sp, #16 * 14]	378	ldp x28, x29, [sp, #16 * 14]
379	ldr lr, [sp, #S_LR]	379	ldr lr, [sp, #S_LR]
380	add sp, sp, #S_FRAME_SIZE // restore sp	380	add sp, sp, #PT_REGS_SIZE // restore sp
381		381
382	.if \el == 0	382	.if \el == 0
383	alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0	383	alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0
@@ -580,12 +580,12 @@ __bad_stack: · 196 unmodified lines
580		580
581	/*	581	/*
582	* Store the original GPRs to the new stack. The orginal SP (minus	582	* Store the original GPRs to the new stack. The orginal SP (minus
583	* S_FRAME_SIZE) was stashed in tpidr_el0 by kernel_ventry.	583	* PT_REGS_SIZE) was stashed in tpidr_el0 by kernel_ventry.
584	*/	584	*/
585	sub sp, sp, #S_FRAME_SIZE	585	sub sp, sp, #PT_REGS_SIZE
586	kernel_entry 1	586	kernel_entry 1
587	mrs x0, tpidr_el0	587	mrs x0, tpidr_el0
588	add x0, x0, #S_FRAME_SIZE	588	add x0, x0, #PT_REGS_SIZE
589	str x0, [sp, #S_SP]	589	str x0, [sp, #S_SP]
590		590
591	/* Stash the regs for handle_bad_stack */	591	/* Stash the regs for handle_bad_stack */

arch/arm64/kernel/perf_event.c+2−39

@@ -23,8 +23,6 @@ · 22 unmodified lines
23	#include <linux/platform_device.h>	23	#include <linux/platform_device.h>
24	#include <linux/sched_clock.h>	24	#include <linux/sched_clock.h>
25	#include <linux/smp.h>	25	#include <linux/smp.h>
26	#include <linux/nmi.h>
27	#include <linux/cpufreq.h>
28		26
29	/* ARMv8 Cortex-A53 specific event types. */	27	/* ARMv8 Cortex-A53 specific event types. */
30	#define ARMV8_A53_PERFCTR_PREF_LINEFILL 0xC2	28	#define ARMV8_A53_PERFCTR_PREF_LINEFILL 0xC2
@@ -1250,21 +1248,10 @@ static struct platform_driver armv8_pmu_driver = { · 1219 unmodified lines
1250		1248
1251	static int __init armv8_pmu_driver_init(void)	1249	static int __init armv8_pmu_driver_init(void)
1252	{	1250	{
1253	int ret;
1254
1255	if (acpi_disabled)	1251	if (acpi_disabled)
1256	ret = platform_driver_register(&armv8_pmu_driver);	1252	return platform_driver_register(&armv8_pmu_driver);
1257	else	1253	else
1258	ret = arm_pmu_acpi_probe(armv8_pmuv3_init);	1254	return arm_pmu_acpi_probe(armv8_pmuv3_init);
1259
1260	/*
1261	* Try to re-initialize lockup detector after PMU init in
1262	* case PMU events are triggered via NMIs.
1263	*/
1264	if (ret == 0 && arm_pmu_irq_is_nmi())
1265	lockup_detector_init();
1266
1267	return ret;
1268	}	1255	}
1269	device_initcall(armv8_pmu_driver_init)	1256	device_initcall(armv8_pmu_driver_init)
1270		1257
@@ -1322,27 +1309,3 @@ void arch_perf_update_userpage(struct perf_event *event, · 51 unmodified lines
1322	userpg->cap_user_time_zero = 1;	1309	userpg->cap_user_time_zero = 1;
1323	userpg->cap_user_time_short = 1;	1310	userpg->cap_user_time_short = 1;
1324	}	1311	}
1325
1326	#ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
1327	/*
1328	* Safe maximum CPU frequency in case a particular platform doesn't implement
1329	* cpufreq driver. Although, architecture doesn't put any restrictions on
1330	* maximum frequency but 5 GHz seems to be safe maximum given the available
1331	* Arm CPUs in the market which are clocked much less than 5 GHz. On the other
1332	* hand, we can't make it much higher as it would lead to a large hard-lockup
1333	* detection timeout on parts which are running slower (eg. 1GHz on
1334	* Developerbox) and doesn't possess a cpufreq driver.
1335	*/
1336	#define SAFE_MAX_CPU_FREQ 5000000000UL // 5 GHz
1337	u64 hw_nmi_get_sample_period(int watchdog_thresh)
1338	{
1339	unsigned int cpu = smp_processor_id();
1340	unsigned long max_cpu_freq;
1341
1342	max_cpu_freq = cpufreq_get_hw_max_freq(cpu) * 1000UL;
1343	if (!max_cpu_freq)
1344	max_cpu_freq = SAFE_MAX_CPU_FREQ;
1345
1346	return (u64)max_cpu_freq * watchdog_thresh;
1347	}
1348	#endif

arch/arm64/kernel/probes/kprobes_trampoline.S+3−3

@@ -25,7 +25,7 @@ · 24 unmodified lines
25	stp x24, x25, [sp, #S_X24]	25	stp x24, x25, [sp, #S_X24]
26	stp x26, x27, [sp, #S_X26]	26	stp x26, x27, [sp, #S_X26]
27	stp x28, x29, [sp, #S_X28]	27	stp x28, x29, [sp, #S_X28]
28	add x0, sp, #S_FRAME_SIZE	28	add x0, sp, #PT_REGS_SIZE
29	stp lr, x0, [sp, #S_LR]	29	stp lr, x0, [sp, #S_LR]
30	/*	30	/*
31	* Construct a useful saved PSTATE	31	* Construct a useful saved PSTATE
@@ -62,7 +62,7 @@ · 30 unmodified lines
62	.endm	62	.endm
63		63
64	SYM_CODE_START(kretprobe_trampoline)	64	SYM_CODE_START(kretprobe_trampoline)
65	sub sp, sp, #S_FRAME_SIZE	65	sub sp, sp, #PT_REGS_SIZE
66		66
67	save_all_base_regs	67	save_all_base_regs
68		68
@@ -76,7 +76,7 @@ SYM_CODE_START(kretprobe_trampoline) · 7 unmodified lines
76		76
77	restore_all_base_regs	77	restore_all_base_regs
78		78
79	add sp, sp, #S_FRAME_SIZE	79	add sp, sp, #PT_REGS_SIZE
80	ret	80	ret
81		81
82	SYM_CODE_END(kretprobe_trampoline)	82	SYM_CODE_END(kretprobe_trampoline)

arch/arm64/kernel/signal.c+0−7

@@ -914,13 +914,6 @@ static void do_signal(struct pt_regs *regs) · 913 unmodified lines
914	asmlinkage void do_notify_resume(struct pt_regs *regs,	914	asmlinkage void do_notify_resume(struct pt_regs *regs,
915	unsigned long thread_flags)	915	unsigned long thread_flags)
916	{	916	{
917	/*
918	* The assembly code enters us with IRQs off, but it hasn't
919	* informed the tracing code of that for efficiency reasons.
920	* Update the trace code with the current status.
921	*/
922	trace_hardirqs_off();
923
924	do {	917	do {
925	if (thread_flags & _TIF_NEED_RESCHED) {	918	if (thread_flags & _TIF_NEED_RESCHED) {
926	/* Unmask Debug and SError for the next task */	919	/* Unmask Debug and SError for the next task */

arch/arm64/kernel/syscall.c+2−8

 #include <asm/daifflags.h>
 #include <asm/debug-monitors.h>
+#include <asm/exception.h>
 #include <asm/fpsimd.h>
 #include <asm/syscall.h>
 #include <asm/thread_info.h>
 	if (!has_syscall_work(flags) && !IS_ENABLED(CONFIG_DEBUG_RSEQ)) {
 		local_daif_mask();
 		flags = current_thread_info()->flags;
-		if (!has_syscall_work(flags) && !(flags & _TIF_SINGLESTEP)) {
+		if (!has_syscall_work(flags) && !(flags & _TIF_SINGLESTEP))
-			/*
-			 * We're off to userspace, where interrupts are
-			 * always enabled after we restore the flags from
-			 * the SPSR.
-			 */
-			trace_hardirqs_on();
 			return;
-		}
 		local_daif_restore(DAIF_PROCCTX);
 	}

arch/arm64/mm/init.c+18−15

 EXPORT_SYMBOL(memstart_addr);
 /*
- * We create both ZONE_DMA and ZONE_DMA32. ZONE_DMA covers the first 1G of
+ * If the corresponding config options are enabled, we create both ZONE_DMA
- * memory as some devices, namely the Raspberry Pi 4, have peripherals with
+ * and ZONE_DMA32. By default ZONE_DMA covers the 32-bit addressable memory
- * this limited view of the memory. ZONE_DMA32 will cover the rest of the 32
+ * unless restricted on specific platforms (e.g. 30-bit on Raspberry Pi 4).
- * bit addressable memory area.
+ * In such case, ZONE_DMA32 covers the rest of the 32-bit addressable memory,
+ * otherwise it is empty.
  */
 phys_addr_t arm64_dma_phys_limit __ro_after_init;
-phys_addr_t arm64_dma32_phys_limit __ro_after_init;
 #ifdef CONFIG_KEXEC_CORE
 /*
 	if (crash_base == 0) {
 		/* Current arm64 boot protocol requires 2MB alignment */
-		crash_base = memblock_find_in_range(0, arm64_dma32_phys_limit,
+		crash_base = memblock_find_in_range(0, arm64_dma_phys_limit,
 				crash_size, SZ_2M);
 		if (crash_base == 0) {
 			pr_warn("cannot allocate crashkernel (size:0x%llx)\n",
 	unsigned long max_zone_pfns[MAX_NR_ZONES]  = {0};
 	unsigned int __maybe_unused acpi_zone_dma_bits;
 	unsigned int __maybe_unused dt_zone_dma_bits;
+	phys_addr_t __maybe_unused dma32_phys_limit = max_zone_phys(32);
 #ifdef CONFIG_ZONE_DMA
 	acpi_zone_dma_bits = fls64(acpi_iort_dma_get_max_cpu_address());
 	max_zone_pfns[ZONE_DMA] = PFN_DOWN(arm64_dma_phys_limit);
 #endif
 #ifdef CONFIG_ZONE_DMA32
-	max_zone_pfns[ZONE_DMA32] = PFN_DOWN(arm64_dma32_phys_limit);
+	max_zone_pfns[ZONE_DMA32] = PFN_DOWN(dma32_phys_limit);
+	if (!arm64_dma_phys_limit)
+		arm64_dma_phys_limit = dma32_phys_limit;
 #endif
+	if (!arm64_dma_phys_limit)
+		arm64_dma_phys_limit = PHYS_MASK + 1;
 	max_zone_pfns[ZONE_NORMAL] = max;
 	free_area_init(max_zone_pfns);
 	early_init_fdt_scan_reserved_mem();
-	if (IS_ENABLED(CONFIG_ZONE_DMA32))
-		arm64_dma32_phys_limit = max_zone_phys(32);
-	else
-		arm64_dma32_phys_limit = PHYS_MASK + 1;
 	reserve_elfcorehdr();
 	high_memory = __va(memblock_end_of_DRAM() - 1) + 1;
-	dma_contiguous_reserve(arm64_dma32_phys_limit);
 }
 void __init bootmem_init(void)
 	sparse_init();
 	zone_sizes_init(min, max);
+	/*
+	 * Reserve the CMA area after arm64_dma_phys_limit was initialised.
+	 */
+	dma_contiguous_reserve(arm64_dma_phys_limit);
 	/*
 	 * request_standard_resources() depends on crashkernel's memory being
 	 * reserved, so do it here.
 void __init mem_init(void)
 {
 	if (swiotlb_force == SWIOTLB_FORCE ||
-	    max_pfn > PFN_DOWN(arm64_dma_phys_limit ? : arm64_dma32_phys_limit))
+	    max_pfn > PFN_DOWN(arm64_dma_phys_limit))
 		swiotlb_init(1);
 	else
 		swiotlb_force = SWIOTLB_NO_FORCE;

arch/ia64/include/asm/sparsemem.h+1−0

@@ -3,6 +3,7 @@ · 2 unmodified lines
3	#define _ASM_IA64_SPARSEMEM_H	3	#define _ASM_IA64_SPARSEMEM_H
4		4
5	#ifdef CONFIG_SPARSEMEM	5	#ifdef CONFIG_SPARSEMEM
		6	#include <asm/page.h>
6	/*	7	/*
7	* SECTION_SIZE_BITS 2^N: how big each section will be	8	* SECTION_SIZE_BITS 2^N: how big each section will be
8	* MAX_PHYSMEM_BITS 2^N: how much memory we can have in that space	9	* MAX_PHYSMEM_BITS 2^N: how much memory we can have in that space

arch/mips/boot/compressed/decompress.c+2−1

 #include <linux/libfdt.h>
 #include <asm/addrspace.h>
+#include <asm/unaligned.h>
 /*
  * These two variables specify the free mem region
 		dtb_size = fdt_totalsize((void *)&__appended_dtb);
 		/* last four bytes is always image size in little endian */
-		image_size = le32_to_cpup((void *)&__image_end - 4);
+		image_size = get_unaligned_le32((void *)&__image_end - 4);
 		/* copy dtb to where the booted kernel will expect it */
 		memcpy((void *)VMLINUX_LOAD_ADDRESS_ULL + image_size,

arch/mips/cavium-octeon/octeon-irq.c+1−1

@@ -1444,7 +1444,7 @@ static void octeon_irq_setup_secondary_ciu2(void) · 1443 unmodified lines
1444	static int __init octeon_irq_init_ciu(	1444	static int __init octeon_irq_init_ciu(
1445	struct device_node ciu_node, struct device_node parent)	1445	struct device_node ciu_node, struct device_node parent)
1446	{	1446	{
1447	unsigned int i, r;	1447	int i, r;
1448	struct irq_chip *chip;	1448	struct irq_chip *chip;
1449	struct irq_chip *chip_edge;	1449	struct irq_chip *chip_edge;
1450	struct irq_chip *chip_mbox;	1450	struct irq_chip *chip_mbox;

arch/mips/kernel/binfmt_elfn32.c+7−0

@@ -103,4 +103,11 @@ jiffies_to_old_timeval32(unsigned long jiffies, struct old_timeval32 *value) · 102 unmodified lines
103	#undef ns_to_kernel_old_timeval	103	#undef ns_to_kernel_old_timeval
104	#define ns_to_kernel_old_timeval ns_to_old_timeval32	104	#define ns_to_kernel_old_timeval ns_to_old_timeval32
105		105
		106	/*
		107	* Some data types as stored in coredump.
		108	*/
		109	#define user_long_t compat_long_t
		110	#define user_siginfo_t compat_siginfo_t
		111	#define copy_siginfo_to_external copy_siginfo_to_external32
		112
106	#include "../../../fs/binfmt_elf.c"	113	#include "../../../fs/binfmt_elf.c"

arch/mips/kernel/binfmt_elfo32.c+7−0

@@ -106,4 +106,11 @@ jiffies_to_old_timeval32(unsigned long jiffies, struct old_timeval32 *value) · 105 unmodified lines
106	#undef ns_to_kernel_old_timeval	106	#undef ns_to_kernel_old_timeval
107	#define ns_to_kernel_old_timeval ns_to_old_timeval32	107	#define ns_to_kernel_old_timeval ns_to_old_timeval32
108		108
		109	/*
		110	* Some data types as stored in coredump.
		111	*/
		112	#define user_long_t compat_long_t
		113	#define user_siginfo_t compat_siginfo_t
		114	#define copy_siginfo_to_external copy_siginfo_to_external32
		115
109	#include "../../../fs/binfmt_elf.c"	116	#include "../../../fs/binfmt_elf.c"

arch/mips/kernel/relocate.c+8−2

 static inline __init unsigned long rotate_xor(unsigned long hash,
 					      const void *area, size_t size)
 {
-	size_t i;
+	const typeof(hash) *ptr = PTR_ALIGN(area, sizeof(hash));
-	unsigned long *ptr = (unsigned long *)area;
+	size_t diff, i;
+	diff = (void *)ptr - area;
+	if (unlikely(size < diff + sizeof(hash)))
+		return hash;
+	size = ALIGN_DOWN(size - diff, sizeof(hash));
 	for (i = 0; i < size / sizeof(hash); i++) {
 		/* Rotate by odd number of bits and XOR. */

arch/powerpc/include/asm/vdso/gettimeofday.h+15−1

 	return do_syscall_2(__NR_gettimeofday, (unsigned long)_tv, (unsigned long)_tz);
 }
+#ifdef __powerpc64__
 static __always_inline
 int clock_gettime_fallback(clockid_t _clkid, struct __kernel_timespec *_ts)
 {
 	return do_syscall_2(__NR_clock_getres, _clkid, (unsigned long)_ts);
 }
-#ifdef CONFIG_VDSO32
+#else
 #define BUILD_VDSO32		1
+static __always_inline
+int clock_gettime_fallback(clockid_t _clkid, struct __kernel_timespec *_ts)
+{
+	return do_syscall_2(__NR_clock_gettime64, _clkid, (unsigned long)_ts);
+}
+static __always_inline
+int clock_getres_fallback(clockid_t _clkid, struct __kernel_timespec *_ts)
+{
+	return do_syscall_2(__NR_clock_getres_time64, _clkid, (unsigned long)_ts);
+}
 static __always_inline
 int clock_gettime32_fallback(clockid_t _clkid, struct old_timespec32 *_ts)
 {

arch/powerpc/kernel/vmlinux.lds.S+8−0

 	.init.text : AT(ADDR(.init.text) - LOAD_OFFSET) {
 		_sinittext = .;
 		INIT_TEXT
+		/*
+		 *.init.text might be RO so we must ensure this section ends on
+		 * a page boundary.
+		 */
+		. = ALIGN(PAGE_SIZE);
 		_einittext = .;
 #ifdef CONFIG_PPC64
 		*(.tramp.ftrace.init);
 		EXIT_TEXT
 	}
+	. = ALIGN(PAGE_SIZE);
 	INIT_DATA_SECTION(16)
 	. = ALIGN(8);

arch/riscv/Kconfig+4−2

 config PAGE_OFFSET
 	hex
-	default 0xC0000000 if 32BIT && MAXPHYSMEM_2GB
+	default 0xC0000000 if 32BIT && MAXPHYSMEM_1GB
 	default 0x80000000 if 64BIT && !MMU
 	default 0xffffffff80000000 if 64BIT && MAXPHYSMEM_2GB
 	default 0xffffffe000000000 if 64BIT && MAXPHYSMEM_128GB
 choice
 	prompt "Maximum Physical Memory"
-	default MAXPHYSMEM_2GB if 32BIT
+	default MAXPHYSMEM_1GB if 32BIT
 	default MAXPHYSMEM_2GB if 64BIT && CMODEL_MEDLOW
 	default MAXPHYSMEM_128GB if 64BIT && CMODEL_MEDANY
+	config MAXPHYSMEM_1GB
+		bool "1GiB"
 	config MAXPHYSMEM_2GB
 		bool "2GiB"
 	config MAXPHYSMEM_128GB

arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts+2−0

 	phy-mode = "gmii";
 	phy-handle = <&phy0>;
 	phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-id0007.0771";
 		reg = <0>;
+		reset-gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 	};
 };

arch/riscv/configs/defconfig+2−0

 CONFIG_HW_RANDOM_VIRTIO=y
 CONFIG_SPI=y
 CONFIG_SPI_SIFIVE=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SIFIVE=y
 # CONFIG_PTP_1588_CLOCK is not set
 CONFIG_POWER_RESET=y
 CONFIG_DRM=y

arch/riscv/include/asm/pgtable.h+0−1

@@ -99,7 +99,6 @@ · 98 unmodified lines
99	\| _PAGE_DIRTY)	99	\| _PAGE_DIRTY)
100		100
101	#define PAGE_KERNEL __pgprot(_PAGE_KERNEL)	101	#define PAGE_KERNEL __pgprot(_PAGE_KERNEL)
102	#define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL \| _PAGE_EXEC)
103	#define PAGE_KERNEL_READ __pgprot(_PAGE_KERNEL & ~_PAGE_WRITE)	102	#define PAGE_KERNEL_READ __pgprot(_PAGE_KERNEL & ~_PAGE_WRITE)
104	#define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL \| _PAGE_EXEC)	103	#define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL \| _PAGE_EXEC)
105	#define PAGE_KERNEL_READ_EXEC __pgprot((_PAGE_KERNEL & ~_PAGE_WRITE) \	104	#define PAGE_KERNEL_READ_EXEC __pgprot((_PAGE_KERNEL & ~_PAGE_WRITE) \

arch/riscv/include/asm/vdso.h+1−1

@@ -10,7 +10,7 @@ · 9 unmodified lines
10		10
11	#include <linux/types.h>	11	#include <linux/types.h>
12		12
13	#ifndef GENERIC_TIME_VSYSCALL	13	#ifndef CONFIG_GENERIC_TIME_VSYSCALL
14	struct vdso_data {	14	struct vdso_data {
15	};	15	};
16	#endif	16	#endif

arch/riscv/kernel/cacheinfo.c+10−1

@@ -26,7 +26,16 @@ cache_get_priv_group(struct cacheinfo *this_leaf) · 25 unmodified lines
26		26
27	static struct cacheinfo *get_cacheinfo(u32 level, enum cache_type type)	27	static struct cacheinfo *get_cacheinfo(u32 level, enum cache_type type)
28	{	28	{
29	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(smp_processor_id());	29	/*
		30	* Using raw_smp_processor_id() elides a preemptability check, but this
		31	* is really indicative of a larger problem: the cacheinfo UABI assumes
		32	* that cores have a homonogenous view of the cache hierarchy. That
		33	* happens to be the case for the current set of RISC-V systems, but
		34	* likely won't be true in general. Since there's no way to provide
		35	* correct information for these systems via the current UABI we're
		36	* just eliding the check for now.
		37	*/
		38	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(raw_smp_processor_id());
30	struct cacheinfo *this_leaf;	39	struct cacheinfo *this_leaf;
31	int index;	40	int index;
32		41

arch/riscv/kernel/entry.S+13−11

 	REG_L a1, (a1)
 	jr a1
 1:
-#ifdef CONFIG_TRACE_IRQFLAGS
-	call trace_hardirqs_on
-#endif
 	/*
 	 * Exceptions run with interrupts enabled or disabled depending on the
 	 * state of SR_PIE in m/sstatus.
 	 */
 	andi t0, s1, SR_PIE
 	beqz t0, 1f
+#ifdef CONFIG_TRACE_IRQFLAGS
+	call trace_hardirqs_on
+#endif
 	csrs CSR_STATUS, SR_IE
 1:
 	tail do_trap_unknown
 handle_syscall:
+#ifdef CONFIG_RISCV_M_MODE
+	/*
+	 * When running is M-Mode (no MMU config), MPIE does not get set.
+	 * As a result, we need to force enable interrupts here because
+	 * handle_exception did not do set SR_IE as it always sees SR_PIE
+	 * being cleared.
+	 */
+	csrs CSR_STATUS, SR_IE
+#endif
 #if defined(CONFIG_TRACE_IRQFLAGS) || defined(CONFIG_CONTEXT_TRACKING)
 	/* Recover a0 - a7 for system calls */
 	REG_L a0, PT_A0(sp)
 	 * Syscall number held in a7.
 	 * If syscall number is above allowed value, redirect to ni_syscall.
 	 */
-	bge a7, t0, 1f
+	bgeu a7, t0, 1f
-	/*
-	 * Check if syscall is rejected by tracer, i.e., a7 == -1.
-	 * If yes, we pretend it was executed.
-	 */
-	li t1, -1
-	beq a7, t1, ret_from_syscall_rejected
-	blt a7, t1, 1f
 	/* Call syscall */
 	la s0, sys_call_table
 	slli t0, a7, RISCV_LGPTR

arch/riscv/kernel/setup.c+13−11

 {
 	struct memblock_region *region = NULL;
 	struct resource *res = NULL;
-	int ret = 0;
+	struct resource *mem_res = NULL;
+	size_t mem_res_sz = 0;
+	int ret = 0, i = 0;
 	code_res.start = __pa_symbol(_text);
 	code_res.end = __pa_symbol(_etext) - 1;
 	bss_res.end = __pa_symbol(__bss_stop) - 1;
 	bss_res.flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY;
+	mem_res_sz = (memblock.memory.cnt + memblock.reserved.cnt) * sizeof(*mem_res);
+	mem_res = memblock_alloc(mem_res_sz, SMP_CACHE_BYTES);
+	if (!mem_res)
+		panic("%s: Failed to allocate %zu bytes\n", __func__, mem_res_sz);
 	/*
 	 * Start by adding the reserved regions, if they overlap
 	 * with /memory regions, insert_resource later on will take
 	 * care of it.
 	 */
 	for_each_reserved_mem_region(region) {
-		res = memblock_alloc(sizeof(struct resource), SMP_CACHE_BYTES);
+		res = &mem_res[i++];
-		if (!res)
-			panic("%s: Failed to allocate %zu bytes\n", __func__,
-			      sizeof(struct resource));
 		res->name = "Reserved";
 		res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
 		 * Ignore any other reserved regions within
 		 * system memory.
 		 */
-		if (memblock_is_memory(res->start))
+		if (memblock_is_memory(res->start)) {
+			memblock_free((phys_addr_t) res, sizeof(struct resource));
 			continue;
+		}
 		ret = add_resource(&iomem_resource, res);
 		if (ret < 0)
 	/* Add /memory regions to the resource tree */
 	for_each_mem_region(region) {
-		res = memblock_alloc(sizeof(struct resource), SMP_CACHE_BYTES);
+		res = &mem_res[i++];
-		if (!res)
-			panic("%s: Failed to allocate %zu bytes\n", __func__,
-			      sizeof(struct resource));
 		if (unlikely(memblock_is_nomap(region))) {
 			res->name = "Reserved";
 	return;
  error:
-	memblock_free((phys_addr_t) res, sizeof(struct resource));
 	/* Better an empty resource tree than an inconsistent one */
 	release_child_resources(&iomem_resource);
+	memblock_free((phys_addr_t) mem_res, mem_res_sz);
 }

arch/riscv/kernel/stacktrace.c+2−3

 #include <asm/stacktrace.h>
-register unsigned long sp_in_global __asm__("sp");
+register const unsigned long sp_in_global __asm__("sp");
 #ifdef CONFIG_FRAME_POINTER
 		sp = user_stack_pointer(regs);
 		pc = instruction_pointer(regs);
 	} else if (task == NULL || task == current) {
-		const register unsigned long current_sp = sp_in_global;
 		fp = (unsigned long)__builtin_frame_address(0);
-		sp = current_sp;
+		sp = sp_in_global;
 		pc = (unsigned long)walk_stackframe;
 	} else {
 		/* task blocked in __switch_to */

arch/riscv/kernel/time.c+3−0

  * Copyright (C) 2017 SiFive
  */
+#include <linux/of_clk.h>
 #include <linux/clocksource.h>
 #include <linux/delay.h>
 #include <asm/sbi.h>
 	riscv_timebase = prop;
 	lpj_fine = riscv_timebase / HZ;
+	of_clk_init(NULL);
 	timer_probe();
 }

arch/riscv/kernel/vdso.c+1−1

@@ -12,7 +12,7 @@ · 11 unmodified lines
12	#include <linux/binfmts.h>	12	#include <linux/binfmts.h>
13	#include <linux/err.h>	13	#include <linux/err.h>
14	#include <asm/page.h>	14	#include <asm/page.h>
15	#ifdef GENERIC_TIME_VSYSCALL	15	#ifdef CONFIG_GENERIC_TIME_VSYSCALL
16	#include <vdso/datapage.h>	16	#include <vdso/datapage.h>
17	#else	17	#else
18	#include <asm/vdso.h>	18	#include <asm/vdso.h>

arch/riscv/mm/init.c+14−2

 void __init setup_bootmem(void)
 {
 	phys_addr_t mem_start = 0;
-	phys_addr_t start, end = 0;
+	phys_addr_t start, dram_end, end = 0;
 	phys_addr_t vmlinux_end = __pa_symbol(&_end);
 	phys_addr_t vmlinux_start = __pa_symbol(&_start);
+	phys_addr_t max_mapped_addr = __pa(~(ulong)0);
 	u64 i;
 	/* Find the memory region containing the kernel */
 	/* Reserve from the start of the kernel to the end of the kernel */
 	memblock_reserve(vmlinux_start, vmlinux_end - vmlinux_start);
-	max_pfn = PFN_DOWN(memblock_end_of_DRAM());
+	dram_end = memblock_end_of_DRAM();
+	/*
+	 * memblock allocator is not aware of the fact that last 4K bytes of
+	 * the addressable memory can not be mapped because of IS_ERR_VALUE
+	 * macro. Make sure that last 4k bytes are not usable by memblock
+	 * if end of dram is equal to maximum addressable memory.
+	 */
+	if (max_mapped_addr == (dram_end - 1))
+		memblock_set_current_limit(max_mapped_addr - 4096);
+	max_pfn = PFN_DOWN(dram_end);
 	max_low_pfn = max_pfn;
 	dma32_phys_limit = min(4UL * SZ_1G, (unsigned long)PFN_PHYS(max_low_pfn));
 	set_max_mapnr(max_low_pfn);

arch/riscv/mm/kasan_init.c+2−2

@@ -93,8 +93,8 @@ void __init kasan_init(void) · 92 unmodified lines
93	VMALLOC_END));	93	VMALLOC_END));
94		94
95	for_each_mem_range(i, &_start, &_end) {	95	for_each_mem_range(i, &_start, &_end) {
96	void start = (void )_start;	96	void start = (void )__va(_start);
97	void end = (void )_end;	97	void end = (void )__va(_end);
98		98
99	if (start >= end)	99	if (start >= end)
100	break;	100	break;

arch/x86/hyperv/hv_init.c+26−3

@@ -315,6 +315,25 @@ static struct syscore_ops hv_syscore_ops = { · 314 unmodified lines
315	.resume = hv_resume,	315	.resume = hv_resume,
316	};	316	};
317		317
		318	static void (* __initdata old_setup_percpu_clockev)(void);
		319
		320	static void __init hv_stimer_setup_percpu_clockev(void)
		321	{
		322	/*
		323	* Ignore any errors in setting up stimer clockevents
		324	* as we can run with the LAPIC timer as a fallback.
		325	*/
		326	(void)hv_stimer_alloc();
		327
		328	/*
		329	* Still register the LAPIC timer, because the direct-mode STIMER is
		330	* not supported by old versions of Hyper-V. This also allows users
		331	* to switch to LAPIC timer via /sys, if they want to.
		332	*/
		333	if (old_setup_percpu_clockev)
		334	old_setup_percpu_clockev();
		335	}
		336
318	/*	337	/*
319	* This function is to be invoked early in the boot sequence after the	338	* This function is to be invoked early in the boot sequence after the
320	* hypervisor has been detected.	339	* hypervisor has been detected.
@@ -393,10 +412,14 @@ void __init hyperv_init(void) · 72 unmodified lines
393	wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);	412	wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);
394		413
395	/*	414	/*
396	* Ignore any errors in setting up stimer clockevents	415	* hyperv_init() is called before LAPIC is initialized: see
397	* as we can run with the LAPIC timer as a fallback.	416	* apic_intr_mode_init() -> x86_platform.apic_post_init() and
		417	* apic_bsp_setup() -> setup_local_APIC(). The direct-mode STIMER
		418	* depends on LAPIC, so hv_stimer_alloc() should be called from
		419	* x86_init.timers.setup_percpu_clockev.
398	*/	420	*/
399	(void)hv_stimer_alloc();	421	old_setup_percpu_clockev = x86_init.timers.setup_percpu_clockev;
		422	x86_init.timers.setup_percpu_clockev = hv_stimer_setup_percpu_clockev;
400		423
401	hv_apic_init();	424	hv_apic_init();
402		425

arch/x86/xen/enlighten_hvm.c+12−3

 	else
 		per_cpu(xen_vcpu_id, cpu) = cpu;
 	rc = xen_vcpu_setup(cpu);
-	if (rc)
+	if (rc || !xen_have_vector_callback)
 		return rc;
-	if (xen_have_vector_callback && xen_feature(XENFEAT_hvm_safe_pvclock))
+	if (xen_feature(XENFEAT_hvm_safe_pvclock))
 		xen_setup_timer(cpu);
 	rc = xen_smp_intr_init(cpu);
        return 0;
 }
+static bool no_vector_callback __initdata;
 static void __init xen_hvm_guest_init(void)
 {
 	if (xen_pv_domain())
 	xen_panic_handler_init();
-	if (xen_feature(XENFEAT_hvm_callback_vector))
+	if (!no_vector_callback && xen_feature(XENFEAT_hvm_callback_vector))
 		xen_have_vector_callback = 1;
 	xen_hvm_smp_init();
 }
 early_param("xen_nopv", xen_parse_nopv);
+static __init int xen_parse_no_vector_callback(char *arg)
+{
+	no_vector_callback = true;
+	return 0;
+}
+early_param("xen_no_vector_callback", xen_parse_no_vector_callback);
 bool __init xen_hvm_need_lapic(void)
 {
 	if (xen_pv_domain())

arch/x86/xen/smp_hvm.c+19−10

 	int cpu;
 	native_smp_prepare_cpus(max_cpus);
-	WARN_ON(xen_smp_intr_init(0));
-	xen_init_lock_cpu(0);
+	if (xen_have_vector_callback) {
+		WARN_ON(xen_smp_intr_init(0));
+		xen_init_lock_cpu(0);
+	}
 	for_each_possible_cpu(cpu) {
 		if (cpu == 0)
 static void xen_hvm_cpu_die(unsigned int cpu)
 {
 	if (common_cpu_die(cpu) == 0) {
-		xen_smp_intr_free(cpu);
+		if (xen_have_vector_callback) {
-		xen_uninit_lock_cpu(cpu);
+			xen_smp_intr_free(cpu);
-		xen_teardown_timer(cpu);
+			xen_uninit_lock_cpu(cpu);
+			xen_teardown_timer(cpu);
+		}
 	}
 }
 #else
 void __init xen_hvm_smp_init(void)
 {
-	if (!xen_have_vector_callback)
+	smp_ops.smp_prepare_boot_cpu = xen_hvm_smp_prepare_boot_cpu;
+	smp_ops.smp_prepare_cpus = xen_hvm_smp_prepare_cpus;
+	smp_ops.smp_cpus_done = xen_smp_cpus_done;
+	smp_ops.cpu_die = xen_hvm_cpu_die;
+	if (!xen_have_vector_callback) {
+#ifdef CONFIG_PARAVIRT_SPINLOCKS
+		nopvspin = true;
+#endif
 		return;
+	}
-	smp_ops.smp_prepare_cpus = xen_hvm_smp_prepare_cpus;
 	smp_ops.smp_send_reschedule = xen_smp_send_reschedule;
-	smp_ops.cpu_die = xen_hvm_cpu_die;
 	smp_ops.send_call_func_ipi = xen_smp_send_call_function_ipi;
 	smp_ops.send_call_func_single_ipi = xen_smp_send_call_function_single_ipi;
-	smp_ops.smp_prepare_boot_cpu = xen_hvm_smp_prepare_boot_cpu;
-	smp_ops.smp_cpus_done = xen_smp_cpus_done;
 }

crypto/asymmetric_keys/public_key.c+2−1

@@ -356,7 +356,8 @@ int public_key_verify_signature(const struct public_key *pkey, · 355 unmodified lines
356	if (ret)	356	if (ret)
357	goto error_free_key;	357	goto error_free_key;
358		358
359	if (strcmp(sig->pkey_algo, "sm2") == 0 && sig->data_size) {	359	if (sig->pkey_algo && strcmp(sig->pkey_algo, "sm2") == 0 &&
		360	sig->data_size) {
360	ret = cert_sig_digest_update(sig, tfm);	361	ret = cert_sig_digest_update(sig, tfm);
361	if (ret)	362	if (ret)
362	goto error_free_key;	363	goto error_free_key;

crypto/xor.c+2−0

@@ -107,6 +107,8 @@ do_xor_speed(struct xor_block_template tmpl, void b1, void *b2) · 106 unmodified lines
107	preempt_enable();	107	preempt_enable();
108		108
109	// bytes/ns == GB/s, multiply by 1000 to get MB/s [not MiB/s]	109	// bytes/ns == GB/s, multiply by 1000 to get MB/s [not MiB/s]
		110	if (!min)
		111	min = 1;
110	speed = (1000 * REPS * BENCH_SIZE) / (unsigned int)ktime_to_ns(min);	112	speed = (1000 * REPS * BENCH_SIZE) / (unsigned int)ktime_to_ns(min);
111	tmpl->speed = speed;	113	tmpl->speed = speed;
112		114

drivers/acpi/internal.h+1−1

@@ -97,7 +97,7 @@ void acpi_scan_table_handler(u32 event, void table, void context); · 96 unmodified lines
97	extern struct list_head acpi_bus_id_list;	97	extern struct list_head acpi_bus_id_list;
98		98
99	struct acpi_device_bus_id {	99	struct acpi_device_bus_id {
100	char bus_id[15];	100	const char *bus_id;
101	unsigned int instance_no;	101	unsigned int instance_no;
102	struct list_head node;	102	struct list_head node;
103	};	103	};

drivers/acpi/scan.c+14−1

 				acpi_device_bus_id->instance_no--;
 			else {
 				list_del(&acpi_device_bus_id->node);
+				kfree_const(acpi_device_bus_id->bus_id);
 				kfree(acpi_device_bus_id);
 			}
 			break;
 	}
 	if (!found) {
 		acpi_device_bus_id = new_bus_id;
-		strcpy(acpi_device_bus_id->bus_id, acpi_device_hid(device));
+		acpi_device_bus_id->bus_id =
+			kstrdup_const(acpi_device_hid(device), GFP_KERNEL);
+		if (!acpi_device_bus_id->bus_id) {
+			pr_err(PREFIX "Memory allocation error for bus id\n");
+			result = -ENOMEM;
+			goto err_free_new_bus_id;
+		}
 		acpi_device_bus_id->instance_no = 0;
 		list_add_tail(&acpi_device_bus_id->node, &acpi_bus_id_list);
 	}
 	if (device->parent)
 		list_del(&device->node);
 	list_del(&device->wakeup_list);
+ err_free_new_bus_id:
+	if (!found)
+		kfree(new_bus_id);
 	mutex_unlock(&acpi_device_lock);
  err_detach:

drivers/crypto/Kconfig+1−0

@@ -366,6 +366,7 @@ if CRYPTO_DEV_OMAP · 365 unmodified lines
366	config CRYPTO_DEV_OMAP_SHAM	366	config CRYPTO_DEV_OMAP_SHAM
367	tristate "Support for OMAP MD5/SHA1/SHA2 hw accelerator"	367	tristate "Support for OMAP MD5/SHA1/SHA2 hw accelerator"
368	depends on ARCH_OMAP2PLUS	368	depends on ARCH_OMAP2PLUS
		369	select CRYPTO_ENGINE
369	select CRYPTO_SHA1	370	select CRYPTO_SHA1
370	select CRYPTO_MD5	371	select CRYPTO_MD5
371	select CRYPTO_SHA256	372	select CRYPTO_SHA256

drivers/dma-buf/heaps/cma_heap.c+3−0

 		buffer->vaddr = NULL;
 	}
+	/* free page list */
+	kfree(buffer->pages);
+	/* release memory */
 	cma_release(cma_heap->cma, buffer->cma_pages, buffer->pagecount);
 	kfree(buffer);
 }

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c+36−17

 union igp_info {
 	struct atom_integrated_system_info_v1_11 v11;
 	struct atom_integrated_system_info_v1_12 v12;
+	struct atom_integrated_system_info_v2_1 v21;
 };
 union umc_info {
 		if (adev->flags & AMD_IS_APU) {
 			igp_info = (union igp_info *)
 				(mode_info->atom_context->bios + data_offset);
-			switch (crev) {
+			switch (frev) {
-			case 11:
+			case 1:
-				mem_channel_number = igp_info->v11.umachannelnumber;
+				switch (crev) {
-				/* channel width is 64 */
+				case 11:
-				if (vram_width)
+				case 12:
-					*vram_width = mem_channel_number * 64;
+					mem_channel_number = igp_info->v11.umachannelnumber;
-				mem_type = igp_info->v11.memorytype;
+					if (!mem_channel_number)
-				if (vram_type)
+						mem_channel_number = 1;
-					*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
+					/* channel width is 64 */
+					if (vram_width)
+						*vram_width = mem_channel_number * 64;
+					mem_type = igp_info->v11.memorytype;
+					if (vram_type)
+						*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
+					break;
+				default:
+					return -EINVAL;
+				}
 				break;
-			case 12:
+			case 2:
-				mem_channel_number = igp_info->v12.umachannelnumber;
+				switch (crev) {
-				/* channel width is 64 */
+				case 1:
-				if (vram_width)
+				case 2:
-					*vram_width = mem_channel_number * 64;
+					mem_channel_number = igp_info->v21.umachannelnumber;
-				mem_type = igp_info->v12.memorytype;
+					if (!mem_channel_number)
-				if (vram_type)
+						mem_channel_number = 1;
-					*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
+					/* channel width is 64 */
+					if (vram_width)
+						*vram_width = mem_channel_number * 64;
+					mem_type = igp_info->v21.memorytype;
+					if (vram_type)
+						*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
+					break;
+				default:
+					return -EINVAL;
+				}
 				break;
 			default:
 				return -EINVAL;

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c+1−1

@@ -3034,7 +3034,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) · 3033 unmodified lines
3034	#endif	3034	#endif
3035	default:	3035	default:
3036	if (amdgpu_dc > 0)	3036	if (amdgpu_dc > 0)
3037	DRM_INFO("Display Core has been requested via kernel parameter "	3037	DRM_INFO_ONCE("Display Core has been requested via kernel parameter "
3038	"but isn't supported by ASIC, ignoring\n");	3038	"but isn't supported by ASIC, ignoring\n");
3039	return false;	3039	return false;
3040	}	3040	}

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c+2−0

@@ -1085,6 +1085,8 @@ static const struct pci_device_id pciidlist[] = { · 1084 unmodified lines
1085		1085
1086	/* Renoir */	1086	/* Renoir */
1087	{0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR\|AMD_IS_APU},	1087	{0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR\|AMD_IS_APU},
		1088	{0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR\|AMD_IS_APU},
		1089	{0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR\|AMD_IS_APU},
1088		1090
1089	/* Navi12 */	1091	/* Navi12 */
1090	{0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},	1092	{0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c+46−2

@@ -99,6 +99,10 @@ · 98 unmodified lines
99	#define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580	99	#define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580
100	#define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0	100	#define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0
101		101
		102	#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025
		103	#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1
		104	#define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026
		105	#define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1
102	#define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441	106	#define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441
103	#define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1	107	#define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1
104	#define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261	108	#define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261
@@ -160,6 +164,9 @@ · 55 unmodified lines
160	#define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db	164	#define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db
161	#define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0	165	#define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
162		166
		167	#define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030
		168	#define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0
		169
163	MODULE_FIRMWARE("amdgpu/navi10_ce.bin");	170	MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
164	MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");	171	MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
165	MODULE_FIRMWARE("amdgpu/navi10_me.bin");	172	MODULE_FIRMWARE("amdgpu/navi10_me.bin");
@@ -3324,6 +3331,7 @@ static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); · 3158 unmodified lines
3324	static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);	3331	static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3325	static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);	3332	static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3326	static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);	3333	static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
		3334	static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3327		3335
3328	static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)	3336	static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3329	{	3337	{
@@ -7192,6 +7200,9 @@ static int gfx_v10_0_hw_init(void *handle) · 3862 unmodified lines
7192	if (adev->asic_type == CHIP_SIENNA_CICHLID)	7200	if (adev->asic_type == CHIP_SIENNA_CICHLID)
7193	gfx_v10_3_program_pbb_mode(adev);	7201	gfx_v10_3_program_pbb_mode(adev);
7194		7202
		7203	if (adev->asic_type >= CHIP_SIENNA_CICHLID)
		7204	gfx_v10_3_set_power_brake_sequence(adev);
		7205
7195	return r;	7206	return r;
7196	}	7207	}
7197		7208
@@ -7377,8 +7388,16 @@ static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) · 179 unmodified lines
7377		7388
7378	amdgpu_gfx_off_ctrl(adev, false);	7389	amdgpu_gfx_off_ctrl(adev, false);
7379	mutex_lock(&adev->gfx.gpu_clock_mutex);	7390	mutex_lock(&adev->gfx.gpu_clock_mutex);
7380	clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) \|	7391	switch (adev->asic_type) {
7381	((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);	7392	case CHIP_VANGOGH:
		7393	clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) \|
		7394	((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL);
		7395	break;
		7396	default:
		7397	clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) \|
		7398	((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
		7399	break;
		7400	}
7382	mutex_unlock(&adev->gfx.gpu_clock_mutex);	7401	mutex_unlock(&adev->gfx.gpu_clock_mutex);
7383	amdgpu_gfx_off_ctrl(adev, true);	7402	amdgpu_gfx_off_ctrl(adev, true);
7384	return clock;	7403	return clock;
@@ -9169,6 +9188,31 @@ static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) · 1784 unmodified lines
9169	}	9188	}
9170	}	9189	}
9171		9190
		9191	static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
		9192	{
		9193	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
		9194	(0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) \|
		9195	(0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) \|
		9196	(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
		9197
		9198	WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
		9199	WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
		9200	(0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) \|
		9201	(0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) \|
		9202	(0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) \|
		9203	(0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
		9204
		9205	WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
		9206	(0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) \|
		9207	(0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) \|
		9208	(0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
		9209
		9210	WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
		9211
		9212	WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
		9213	(0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
		9214	}
		9215
9172	const struct amdgpu_ip_block_version gfx_v10_0_ip_block =	9216	const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
9173	{	9217	{
9174	.type = AMD_IP_BLOCK_TYPE_GFX,	9218	.type = AMD_IP_BLOCK_TYPE_GFX,

drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h+1−1

@@ -47,7 +47,7 @@ enum psp_gfx_crtl_cmd_id · 46 unmodified lines
47	GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */	47	GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */
48	GFX_CTRL_CMD_ID_MODE1_RST = 0x00070000, /* trigger the Mode 1 reset */	48	GFX_CTRL_CMD_ID_MODE1_RST = 0x00070000, /* trigger the Mode 1 reset */
49	GFX_CTRL_CMD_ID_GBR_IH_SET = 0x00080000, /* set Gbr IH_RB_CNTL registers */	49	GFX_CTRL_CMD_ID_GBR_IH_SET = 0x00080000, /* set Gbr IH_RB_CNTL registers */
50	GFX_CTRL_CMD_ID_CONSUME_CMD = 0x000A0000, /* send interrupt to psp for updating write pointer of vf */	50	GFX_CTRL_CMD_ID_CONSUME_CMD = 0x00090000, /* send interrupt to psp for updating write pointer of vf */
51	GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING = 0x000C0000, /* destroy GPCOM ring */	51	GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING = 0x000C0000, /* destroy GPCOM ring */
52		52
53	GFX_CTRL_CMD_ID_MAX = 0x000F0000, /* max command ID */	53	GFX_CTRL_CMD_ID_MAX = 0x000F0000, /* max command ID */

drivers/gpu/drm/amd/amdgpu/soc15.c+2−1

 		break;
 	case CHIP_RENOIR:
 		adev->asic_funcs = &soc15_asic_funcs;
-		if (adev->pdev->device == 0x1636)
+		if ((adev->pdev->device == 0x1636) ||
+		    (adev->pdev->device == 0x164c))
 			adev->apu_flags |= AMD_APU_IS_RENOIR;
 		else
 			adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE;

drivers/gpu/drm/amd/amdkfd/kfd_crat.c+7−4

 				(struct crat_subtype_iolink *)sub_type_hdr);
 		if (ret < 0)
 			return ret;
-		crat_table->length += (sub_type_hdr->length * entries);
-		crat_table->total_entries += entries;
-		sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
+		if (entries) {
-				sub_type_hdr->length * entries);
+			crat_table->length += (sub_type_hdr->length * entries);
+			crat_table->total_entries += entries;
+			sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
+					sub_type_hdr->length * entries);
+		}
 #else
 		pr_info("IO link not available for non x86 platforms\n");
 #endif

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+9−133

@@ -939,41 +939,6 @@ static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_ · 938 unmodified lines
939	}	939	}
940	#endif	940	#endif
941		941
942	#ifdef CONFIG_DEBUG_FS
943	static int create_crtc_crc_properties(struct amdgpu_display_manager *dm)
944	{
945	dm->crc_win_x_start_property =
946	drm_property_create_range(adev_to_drm(dm->adev),
947	DRM_MODE_PROP_ATOMIC,
948	"AMD_CRC_WIN_X_START", 0, U16_MAX);
949	if (!dm->crc_win_x_start_property)
950	return -ENOMEM;
951
952	dm->crc_win_y_start_property =
953	drm_property_create_range(adev_to_drm(dm->adev),
954	DRM_MODE_PROP_ATOMIC,
955	"AMD_CRC_WIN_Y_START", 0, U16_MAX);
956	if (!dm->crc_win_y_start_property)
957	return -ENOMEM;
958
959	dm->crc_win_x_end_property =
960	drm_property_create_range(adev_to_drm(dm->adev),
961	DRM_MODE_PROP_ATOMIC,
962	"AMD_CRC_WIN_X_END", 0, U16_MAX);
963	if (!dm->crc_win_x_end_property)
964	return -ENOMEM;
965
966	dm->crc_win_y_end_property =
967	drm_property_create_range(adev_to_drm(dm->adev),
968	DRM_MODE_PROP_ATOMIC,
969	"AMD_CRC_WIN_Y_END", 0, U16_MAX);
970	if (!dm->crc_win_y_end_property)
971	return -ENOMEM;
972
973	return 0;
974	}
975	#endif
976
977	static int amdgpu_dm_init(struct amdgpu_device *adev)	942	static int amdgpu_dm_init(struct amdgpu_device *adev)
978	{	943	{
979	struct dc_init_data init_data;	944	struct dc_init_data init_data;
@@ -1120,10 +1085,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) · 140 unmodified lines
1120		1085
1121	dc_init_callbacks(adev->dm.dc, &init_params);	1086	dc_init_callbacks(adev->dm.dc, &init_params);
1122	}	1087	}
1123	#endif
1124	#ifdef CONFIG_DEBUG_FS
1125	if (create_crtc_crc_properties(&adev->dm))
1126	DRM_ERROR("amdgpu: failed to create crc property.\n");
1127	#endif	1088	#endif
1128	if (amdgpu_dm_initialize_drm_device(adev)) {	1089	if (amdgpu_dm_initialize_drm_device(adev)) {
1129	DRM_ERROR(	1090	DRM_ERROR(
@@ -5333,64 +5294,12 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc) · 4203 unmodified lines
5333	state->crc_src = cur->crc_src;	5294	state->crc_src = cur->crc_src;
5334	state->cm_has_degamma = cur->cm_has_degamma;	5295	state->cm_has_degamma = cur->cm_has_degamma;
5335	state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;	5296	state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
5336	#ifdef CONFIG_DEBUG_FS	5297
5337	state->crc_window = cur->crc_window;
5338	#endif
5339	/* TODO Duplicate dc_stream after objects are stream object is flattened */	5298	/* TODO Duplicate dc_stream after objects are stream object is flattened */
5340		5299
5341	return &state->base;	5300	return &state->base;
5342	}	5301	}
5343		5302
5344	#ifdef CONFIG_DEBUG_FS
5345	static int amdgpu_dm_crtc_atomic_set_property(struct drm_crtc *crtc,
5346	struct drm_crtc_state *crtc_state,
5347	struct drm_property *property,
5348	uint64_t val)
5349	{
5350	struct drm_device *dev = crtc->dev;
5351	struct amdgpu_device *adev = drm_to_adev(dev);
5352	struct dm_crtc_state *dm_new_state =
5353	to_dm_crtc_state(crtc_state);
5354
5355	if (property == adev->dm.crc_win_x_start_property)
5356	dm_new_state->crc_window.x_start = val;
5357	else if (property == adev->dm.crc_win_y_start_property)
5358	dm_new_state->crc_window.y_start = val;
5359	else if (property == adev->dm.crc_win_x_end_property)
5360	dm_new_state->crc_window.x_end = val;
5361	else if (property == adev->dm.crc_win_y_end_property)
5362	dm_new_state->crc_window.y_end = val;
5363	else
5364	return -EINVAL;
5365
5366	return 0;
5367	}
5368
5369	static int amdgpu_dm_crtc_atomic_get_property(struct drm_crtc *crtc,
5370	const struct drm_crtc_state *state,
5371	struct drm_property *property,
5372	uint64_t *val)
5373	{
5374	struct drm_device *dev = crtc->dev;
5375	struct amdgpu_device *adev = drm_to_adev(dev);
5376	struct dm_crtc_state *dm_state =
5377	to_dm_crtc_state(state);
5378
5379	if (property == adev->dm.crc_win_x_start_property)
5380	*val = dm_state->crc_window.x_start;
5381	else if (property == adev->dm.crc_win_y_start_property)
5382	*val = dm_state->crc_window.y_start;
5383	else if (property == adev->dm.crc_win_x_end_property)
5384	*val = dm_state->crc_window.x_end;
5385	else if (property == adev->dm.crc_win_y_end_property)
5386	*val = dm_state->crc_window.y_end;
5387	else
5388	return -EINVAL;
5389
5390	return 0;
5391	}
5392	#endif
5393
5394	static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)	5303	static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
5395	{	5304	{
5396	enum dc_irq_source irq_source;	5305	enum dc_irq_source irq_source;
@@ -5457,10 +5366,6 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { · 60 unmodified lines
5457	.enable_vblank = dm_enable_vblank,	5366	.enable_vblank = dm_enable_vblank,
5458	.disable_vblank = dm_disable_vblank,	5367	.disable_vblank = dm_disable_vblank,
5459	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,	5368	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
5460	#ifdef CONFIG_DEBUG_FS
5461	.atomic_set_property = amdgpu_dm_crtc_atomic_set_property,
5462	.atomic_get_property = amdgpu_dm_crtc_atomic_get_property,
5463	#endif
5464	};	5369	};
5465		5370
5466	static enum drm_connector_status	5371	static enum drm_connector_status
@@ -6662,25 +6567,6 @@ static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, · 1195 unmodified lines
6662	return 0;	6567	return 0;
6663	}	6568	}
6664		6569
6665	#ifdef CONFIG_DEBUG_FS
6666	static void attach_crtc_crc_properties(struct amdgpu_display_manager *dm,
6667	struct amdgpu_crtc *acrtc)
6668	{
6669	drm_object_attach_property(&acrtc->base.base,
6670	dm->crc_win_x_start_property,
6671	0);
6672	drm_object_attach_property(&acrtc->base.base,
6673	dm->crc_win_y_start_property,
6674	0);
6675	drm_object_attach_property(&acrtc->base.base,
6676	dm->crc_win_x_end_property,
6677	0);
6678	drm_object_attach_property(&acrtc->base.base,
6679	dm->crc_win_y_end_property,
6680	0);
6681	}
6682	#endif
6683
6684	static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,	6570	static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
6685	struct drm_plane *plane,	6571	struct drm_plane *plane,
6686	uint32_t crtc_index)	6572	uint32_t crtc_index)
@@ -6728,9 +6614,7 @@ static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, · 41 unmodified lines
6728	drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,	6614	drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
6729	true, MAX_COLOR_LUT_ENTRIES);	6615	true, MAX_COLOR_LUT_ENTRIES);
6730	drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);	6616	drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
6731	#ifdef CONFIG_DEBUG_FS	6617
6732	attach_crtc_crc_properties(dm, acrtc);
6733	#endif
6734	return 0;	6618	return 0;
6735		6619
6736	fail:	6620	fail:
@@ -8367,7 +8251,6 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) · 1630 unmodified lines
8367	*/	8251	*/
8368	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {	8252	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8369	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);	8253	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8370	bool configure_crc = false;
8371		8254
8372	dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);	8255	dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8373		8256
@@ -8377,27 +8260,20 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) · 3 unmodified lines
8377	dc_stream_retain(dm_new_crtc_state->stream);	8260	dc_stream_retain(dm_new_crtc_state->stream);
8378	acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;	8261	acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8379	manage_dm_interrupts(adev, acrtc, true);	8262	manage_dm_interrupts(adev, acrtc, true);
8380	}	8263
8381	if (IS_ENABLED(CONFIG_DEBUG_FS) && new_crtc_state->active &&	8264	#ifdef CONFIG_DEBUG_FS
8382	amdgpu_dm_is_valid_crc_source(dm_new_crtc_state->crc_src)) {
8383	/**	8265	/**
8384	* Frontend may have changed so reapply the CRC capture	8266	* Frontend may have changed so reapply the CRC capture
8385	* settings for the stream.	8267	* settings for the stream.
8386	*/	8268	*/
8387	dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);	8269	dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8388	dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8389		8270
8390	if (amdgpu_dm_crc_window_is_default(dm_new_crtc_state)) {	8271	if (amdgpu_dm_is_valid_crc_source(dm_new_crtc_state->crc_src)) {
8391	if (!old_crtc_state->active \|\| drm_atomic_crtc_needs_modeset(new_crtc_state))
8392	configure_crc = true;
8393	} else {
8394	if (amdgpu_dm_crc_window_changed(dm_new_crtc_state, dm_old_crtc_state))
8395	configure_crc = true;
8396	}
8397
8398	if (configure_crc)
8399	amdgpu_dm_crtc_configure_crc_source(	8272	amdgpu_dm_crtc_configure_crc_source(
8400	crtc, dm_new_crtc_state, dm_new_crtc_state->crc_src);	8273	crtc, dm_new_crtc_state,
		8274	dm_new_crtc_state->crc_src);
		8275	}
		8276	#endif
8401	}	8277	}
8402	}	8278	}
8403		8279

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h+0−38

@@ -336,32 +336,6 @@ struct amdgpu_display_manager { · 335 unmodified lines
336	*/	336	*/
337	const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;	337	const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
338		338
339	#ifdef CONFIG_DEBUG_FS
340	/**
341	* @crc_win_x_start_property:
342	*
343	* X start of the crc calculation window
344	*/
345	struct drm_property *crc_win_x_start_property;
346	/**
347	* @crc_win_y_start_property:
348	*
349	* Y start of the crc calculation window
350	*/
351	struct drm_property *crc_win_y_start_property;
352	/**
353	* @crc_win_x_end_property:
354	*
355	* X end of the crc calculation window
356	*/
357	struct drm_property *crc_win_x_end_property;
358	/**
359	* @crc_win_y_end_property:
360	*
361	* Y end of the crc calculation window
362	*/
363	struct drm_property *crc_win_y_end_property;
364	#endif
365	/**	339	/**
366	* @mst_encoders:	340	* @mst_encoders:
367	*	341	*
@@ -448,15 +422,6 @@ struct dm_plane_state { · 80 unmodified lines
448	struct dc_plane_state *dc_state;	422	struct dc_plane_state *dc_state;
449	};	423	};
450		424
451	#ifdef CONFIG_DEBUG_FS
452	struct crc_rec {
453	uint16_t x_start;
454	uint16_t y_start;
455	uint16_t x_end;
456	uint16_t y_end;
457	};
458	#endif
459
460	struct dm_crtc_state {	425	struct dm_crtc_state {
461	struct drm_crtc_state base;	426	struct drm_crtc_state base;
462	struct dc_stream_state *stream;	427	struct dc_stream_state *stream;
@@ -479,9 +444,6 @@ struct dm_crtc_state { · 16 unmodified lines
479	struct dc_info_packet vrr_infopacket;	444	struct dc_info_packet vrr_infopacket;
480		445
481	int abm_level;	446	int abm_level;
482	#ifdef CONFIG_DEBUG_FS
483	struct crc_rec crc_window;
484	#endif
485	};	447	};
486		448
487	#define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)	449	#define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c+1−53

@@ -81,41 +81,6 @@ const char const amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc, · 80 unmodified lines
81	return pipe_crc_sources;	81	return pipe_crc_sources;
82	}	82	}
83		83
84	static void amdgpu_dm_set_crc_window_default(struct dm_crtc_state *dm_crtc_state)
85	{
86	dm_crtc_state->crc_window.x_start = 0;
87	dm_crtc_state->crc_window.y_start = 0;
88	dm_crtc_state->crc_window.x_end = 0;
89	dm_crtc_state->crc_window.y_end = 0;
90	}
91
92	bool amdgpu_dm_crc_window_is_default(struct dm_crtc_state *dm_crtc_state)
93	{
94	bool ret = true;
95
96	if ((dm_crtc_state->crc_window.x_start != 0) \|\|
97	(dm_crtc_state->crc_window.y_start != 0) \|\|
98	(dm_crtc_state->crc_window.x_end != 0) \|\|
99	(dm_crtc_state->crc_window.y_end != 0))
100	ret = false;
101
102	return ret;
103	}
104
105	bool amdgpu_dm_crc_window_changed(struct dm_crtc_state *dm_new_crtc_state,
106	struct dm_crtc_state *dm_old_crtc_state)
107	{
108	bool ret = false;
109
110	if ((dm_new_crtc_state->crc_window.x_start != dm_old_crtc_state->crc_window.x_start) \|\|
111	(dm_new_crtc_state->crc_window.y_start != dm_old_crtc_state->crc_window.y_start) \|\|
112	(dm_new_crtc_state->crc_window.x_end != dm_old_crtc_state->crc_window.x_end) \|\|
113	(dm_new_crtc_state->crc_window.y_end != dm_old_crtc_state->crc_window.y_end))
114	ret = true;
115
116	return ret;
117	}
118
119	int	84	int
120	amdgpu_dm_crtc_verify_crc_source(struct drm_crtc crtc, const char src_name,	85	amdgpu_dm_crtc_verify_crc_source(struct drm_crtc crtc, const char src_name,
121	size_t *values_cnt)	86	size_t *values_cnt)
@@ -140,7 +105,6 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, · 18 unmodified lines
140	struct dc_stream_state *stream_state = dm_crtc_state->stream;	105	struct dc_stream_state *stream_state = dm_crtc_state->stream;
141	bool enable = amdgpu_dm_is_valid_crc_source(source);	106	bool enable = amdgpu_dm_is_valid_crc_source(source);
142	int ret = 0;	107	int ret = 0;
143	struct crc_params *crc_window = NULL, tmp_window;
144		108
145	/* Configuration will be deferred to stream enable. */	109	/* Configuration will be deferred to stream enable. */
146	if (!stream_state)	110	if (!stream_state)
@@ -150,24 +114,8 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, · 3 unmodified lines
150		114
151	/* Enable CRTC CRC generation if necessary. */	115	/* Enable CRTC CRC generation if necessary. */
152	if (dm_is_crc_source_crtc(source) \|\| source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE) {	116	if (dm_is_crc_source_crtc(source) \|\| source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE) {
153	if (!enable)
154	amdgpu_dm_set_crc_window_default(dm_crtc_state);
155
156	if (!amdgpu_dm_crc_window_is_default(dm_crtc_state)) {
157	crc_window = &tmp_window;
158
159	tmp_window.windowa_x_start = dm_crtc_state->crc_window.x_start;
160	tmp_window.windowa_y_start = dm_crtc_state->crc_window.y_start;
161	tmp_window.windowa_x_end = dm_crtc_state->crc_window.x_end;
162	tmp_window.windowa_y_end = dm_crtc_state->crc_window.y_end;
163	tmp_window.windowb_x_start = dm_crtc_state->crc_window.x_start;
164	tmp_window.windowb_y_start = dm_crtc_state->crc_window.y_start;
165	tmp_window.windowb_x_end = dm_crtc_state->crc_window.x_end;
166	tmp_window.windowb_y_end = dm_crtc_state->crc_window.y_end;
167	}
168
169	if (!dc_stream_configure_crc(stream_state->ctx->dc,	117	if (!dc_stream_configure_crc(stream_state->ctx->dc,
170	stream_state, crc_window, enable, enable)) {	118	stream_state, NULL, enable, enable)) {
171	ret = -EINVAL;	119	ret = -EINVAL;
172	goto unlock;	120	goto unlock;
173	}	121	}

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h+1−4

 }
 /* amdgpu_dm_crc.c */
-bool amdgpu_dm_crc_window_is_default(struct dm_crtc_state *dm_crtc_state);
+#ifdef CONFIG_DEBUG_FS
-bool amdgpu_dm_crc_window_changed(struct dm_crtc_state *dm_new_crtc_state,
-					struct dm_crtc_state *dm_old_crtc_state);
 int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
 					struct dm_crtc_state *dm_crtc_state,
 					enum amdgpu_dm_pipe_crc_source source);
-#ifdef CONFIG_DEBUG_FS
 int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name);
 int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc,
 				     const char *src_name,

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c+7−1

 	unsigned int cust_pattern_size)
 {
 	struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
-	struct pipe_ctx *pipe_ctx = &pipes[0];
+	struct pipe_ctx *pipe_ctx = NULL;
 	unsigned int lane;
 	unsigned int i;
 	unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
 	memset(&training_pattern, 0, sizeof(training_pattern));
 	for (i = 0; i < MAX_PIPES; i++) {
+		if (pipes[i].stream == NULL)
+			continue;
 		if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
 			pipe_ctx = &pipes[i];
 			break;
 		}
 	}
+	if (pipe_ctx == NULL)
+		return false;
 	/* Reset CRTC Test Pattern if it is currently running and request is VideoMode */
 	if (link->test_pattern_enabled && test_pattern ==
 			DP_TEST_PATTERN_VIDEO_MODE) {

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c+1−1

@@ -470,7 +470,7 @@ void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock) · 469 unmodified lines
470	unsigned int mpc1_get_mpc_out_mux(struct mpc *mpc, int opp_id)	470	unsigned int mpc1_get_mpc_out_mux(struct mpc *mpc, int opp_id)
471	{	471	{
472	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);	472	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
473	uint32_t val = 0;	473	uint32_t val = 0xf;
474		474
475	if (opp_id < MAX_OPP && REG(MUX[opp_id]))	475	if (opp_id < MAX_OPP && REG(MUX[opp_id]))
476	REG_GET(MUX[opp_id], MPC_OUT_MUX, &val);	476	REG_GET(MUX[opp_id], MPC_OUT_MUX, &val);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c+2−2

@@ -608,8 +608,8 @@ static const struct dc_debug_options debug_defaults_drv = { · 607 unmodified lines
608	.disable_pplib_clock_request = false,	608	.disable_pplib_clock_request = false,
609	.disable_pplib_wm_range = false,	609	.disable_pplib_wm_range = false,
610	.pplib_wm_report_mode = WM_REPORT_DEFAULT,	610	.pplib_wm_report_mode = WM_REPORT_DEFAULT,
611	.pipe_split_policy = MPC_SPLIT_DYNAMIC,	611	.pipe_split_policy = MPC_SPLIT_AVOID,
612	.force_single_disp_pipe_split = true,	612	.force_single_disp_pipe_split = false,
613	.disable_dcc = DCC_ENABLE,	613	.disable_dcc = DCC_ENABLE,
614	.voltage_align_fclk = true,	614	.voltage_align_fclk = true,
615	.disable_stereo_support = true,	615	.disable_stereo_support = true,

drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c+1−0

@@ -1731,6 +1731,7 @@ static struct resource_funcs dcn301_res_pool_funcs = { · 1730 unmodified lines
1731	.populate_dml_pipes = dcn30_populate_dml_pipes_from_context,	1731	.populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
1732	.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,	1732	.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1733	.add_stream_to_ctx = dcn30_add_stream_to_ctx,	1733	.add_stream_to_ctx = dcn30_add_stream_to_ctx,
		1734	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1734	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,	1735	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1735	.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,	1736	.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1736	.set_mcif_arb_params = dcn30_set_mcif_arb_params,	1737	.set_mcif_arb_params = dcn30_set_mcif_arb_params,

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c+6−5

 	}
 	if (mode_lib->vba.DRAMClockChangeSupportsVActive &&
-			mode_lib->vba.MinActiveDRAMClockChangeMargin > 60 &&
+			mode_lib->vba.MinActiveDRAMClockChangeMargin > 60) {
-			mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 0) {
 		mode_lib->vba.DRAMClockChangeWatermark += 25;
 		for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-			if (mode_lib->vba.DRAMClockChangeWatermark >
+			if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 0) {
-			dml_max(mode_lib->vba.StutterEnterPlusExitWatermark, mode_lib->vba.UrgentWatermark))
+				if (mode_lib->vba.DRAMClockChangeWatermark >
-				mode_lib->vba.MinTTUVBlank[k] += 25;
+				dml_max(mode_lib->vba.StutterEnterPlusExitWatermark, mode_lib->vba.UrgentWatermark))
+					mode_lib->vba.MinTTUVBlank[k] += 25;
+			}
 		}
 		mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;

drivers/gpu/drm/drm_plane.c+8−1

 	if (ret)
 		goto out;
-	if (old_fb->format != fb->format) {
+	/*
+	 * Only check the FOURCC format code, excluding modifiers. This is
+	 * enough for all legacy drivers. Atomic drivers have their own
+	 * checks in their ->atomic_check implementation, which will
+	 * return -EINVAL if any hw or driver constraint is violated due
+	 * to modifier changes.
+	 */
+	if (old_fb->format->format != fb->format->format) {
 		DRM_DEBUG_KMS("Page flip is not allowed to change frame buffer format.\n");
 		ret = -EINVAL;
 		goto out;

drivers/gpu/drm/i915/Makefile+1−0

@@ -38,6 +38,7 @@ i915-y += i915_drv.o \ · 37 unmodified lines
38	i915_config.o \	38	i915_config.o \
39	i915_irq.o \	39	i915_irq.o \
40	i915_getparam.o \	40	i915_getparam.o \
		41	i915_mitigations.o \
41	i915_params.o \	42	i915_params.o \
42	i915_pci.o \	43	i915_pci.o \
43	i915_scatterlist.o \	44	i915_scatterlist.o \

drivers/gpu/drm/i915/display/icl_dsi.c+0−4

@@ -1616,10 +1616,6 @@ static void gen11_dsi_get_power_domains(struct intel_encoder *encoder, · 1615 unmodified lines
1616		1616
1617	get_dsi_io_power_domains(i915,	1617	get_dsi_io_power_domains(i915,
1618	enc_to_intel_dsi(encoder));	1618	enc_to_intel_dsi(encoder));
1619
1620	if (crtc_state->dsc.compression_enable)
1621	intel_display_power_get(i915,
1622	intel_dsc_power_domain(crtc_state));
1623	}	1619	}
1624		1620
1625	static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,	1621	static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,

drivers/gpu/drm/i915/display/intel_panel.c+5−4

 		val = pch_get_backlight(connector);
 	else
 		val = lpt_get_backlight(connector);
-	val = intel_panel_compute_brightness(connector, val);
-	panel->backlight.level = clamp(val, panel->backlight.min,
-				       panel->backlight.max);
 	if (cpu_mode) {
 		drm_dbg_kms(&dev_priv->drm,
 			    "CPU backlight register was enabled, switching to PCH override\n");
 		/* Write converted CPU PWM value to PCH override register */
-		lpt_set_backlight(connector->base.state, panel->backlight.level);
+		lpt_set_backlight(connector->base.state, val);
 		intel_de_write(dev_priv, BLC_PWM_PCH_CTL1,
 			       pch_ctl1 | BLM_PCH_OVERRIDE_ENABLE);
 			       cpu_ctl2 & ~BLM_PWM_ENABLE);
 	}
+	val = intel_panel_compute_brightness(connector, val);
+	panel->backlight.level = clamp(val, panel->backlight.min,
+				       panel->backlight.max);
 	return 0;
 }

drivers/gpu/drm/i915/display/vlv_dsi.c+13−3

@@ -812,10 +812,20 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state, · 811 unmodified lines
812	intel_dsi_prepare(encoder, pipe_config);	812	intel_dsi_prepare(encoder, pipe_config);
813		813
814	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);	814	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
815	intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
816		815
817	/* Deassert reset */	816	/*
818	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);	817	* Give the panel time to power-on and then deassert its reset.
		818	* Depending on the VBT MIPI sequences version the deassert-seq
		819	* may contain the necessary delay, intel_dsi_msleep() will skip
		820	* the delay in that case. If there is no deassert-seq, then an
		821	* unconditional msleep is used to give the panel time to power-on.
		822	*/
		823	if (dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET]) {
		824	intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
		825	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
		826	} else {
		827	msleep(intel_dsi->panel_on_delay);
		828	}
819		829
820	if (IS_GEMINILAKE(dev_priv)) {	830	if (IS_GEMINILAKE(dev_priv)) {
821	glk_cold_boot = glk_dsi_enable_io(encoder);	831	glk_cold_boot = glk_dsi_enable_io(encoder);

drivers/gpu/drm/i915/gt/gen7_renderclear.c+94−63

@@ -7,8 +7,6 @@ · 6 unmodified lines
7	#include "i915_drv.h"	7	#include "i915_drv.h"
8	#include "intel_gpu_commands.h"	8	#include "intel_gpu_commands.h"
9		9
10	#define MAX_URB_ENTRIES 64
11	#define STATE_SIZE (4 * 1024)
12	#define GT3_INLINE_DATA_DELAYS 0x1E00	10	#define GT3_INLINE_DATA_DELAYS 0x1E00
13	#define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS))	11	#define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS))
14		12
@@ -34,38 +32,59 @@ struct batch_chunk { · 19 unmodified lines
34	};	32	};
35		33
36	struct batch_vals {	34	struct batch_vals {
37	u32 max_primitives;	35	u32 max_threads;
38	u32 max_urb_entries;
39	u32 cmd_size;
40	u32 state_size;
41	u32 state_start;	36	u32 state_start;
42	u32 batch_size;	37	u32 surface_start;
43	u32 surface_height;	38	u32 surface_height;
44	u32 surface_width;	39	u32 surface_width;
45	u32 scratch_size;	40	u32 size;
46	u32 max_size;
47	};	41	};
48		42
		43	static inline int num_primitives(const struct batch_vals *bv)
		44	{
		45	/*
		46	* We need to saturate the GPU with work in order to dispatch
		47	* a shader on every HW thread, and clear the thread-local registers.
		48	* In short, we have to dispatch work faster than the shaders can
		49	* run in order to fill the EU and occupy each HW thread.
		50	*/
		51	return bv->max_threads;
		52	}
		53
49	static void	54	static void
50	batch_get_defaults(struct drm_i915_private i915, struct batch_vals bv)	55	batch_get_defaults(struct drm_i915_private i915, struct batch_vals bv)
51	{	56	{
52	if (IS_HASWELL(i915)) {	57	if (IS_HASWELL(i915)) {
53	bv->max_primitives = 280;	58	switch (INTEL_INFO(i915)->gt) {
54	bv->max_urb_entries = MAX_URB_ENTRIES;	59	default:
		60	case 1:
		61	bv->max_threads = 70;
		62	break;
		63	case 2:
		64	bv->max_threads = 140;
		65	break;
		66	case 3:
		67	bv->max_threads = 280;
		68	break;
		69	}
55	bv->surface_height = 16 * 16;	70	bv->surface_height = 16 * 16;
56	bv->surface_width = 32 * 2 * 16;	71	bv->surface_width = 32 * 2 * 16;
57	} else {	72	} else {
58	bv->max_primitives = 128;	73	switch (INTEL_INFO(i915)->gt) {
59	bv->max_urb_entries = MAX_URB_ENTRIES / 2;	74	default:
		75	case 1: /* including vlv */
		76	bv->max_threads = 36;
		77	break;
		78	case 2:
		79	bv->max_threads = 128;
		80	break;
		81	}
60	bv->surface_height = 16 * 8;	82	bv->surface_height = 16 * 8;
61	bv->surface_width = 32 * 16;	83	bv->surface_width = 32 * 16;
62	}	84	}
63	bv->cmd_size = bv->max_primitives * 4096;	85	bv->state_start = round_up(SZ_1K + num_primitives(bv) * 64, SZ_4K);
64	bv->state_size = STATE_SIZE;	86	bv->surface_start = bv->state_start + SZ_4K;
65	bv->state_start = bv->cmd_size;	87	bv->size = bv->surface_start + bv->surface_height * bv->surface_width;
66	bv->batch_size = bv->cmd_size + bv->state_size;
67	bv->scratch_size = bv->surface_height * bv->surface_width;
68	bv->max_size = bv->batch_size + bv->scratch_size;
69	}	88	}
70		89
71	static void batch_init(struct batch_chunk *bc,	90	static void batch_init(struct batch_chunk *bc,
@@ -155,7 +174,8 @@ static u32 · 83 unmodified lines
155	gen7_fill_binding_table(struct batch_chunk *state,	174	gen7_fill_binding_table(struct batch_chunk *state,
156	const struct batch_vals *bv)	175	const struct batch_vals *bv)
157	{	176	{
158	u32 surface_start = gen7_fill_surface_state(state, bv->batch_size, bv);	177	u32 surface_start =
		178	gen7_fill_surface_state(state, bv->surface_start, bv);
159	u32 *cs = batch_alloc_items(state, 32, 8);	179	u32 *cs = batch_alloc_items(state, 32, 8);
160	u32 offset = batch_offset(state, cs);	180	u32 offset = batch_offset(state, cs);
161		181
@@ -214,9 +234,9 @@ static void · 52 unmodified lines
214	gen7_emit_state_base_address(struct batch_chunk *batch,	234	gen7_emit_state_base_address(struct batch_chunk *batch,
215	u32 surface_state_base)	235	u32 surface_state_base)
216	{	236	{
217	u32 *cs = batch_alloc_items(batch, 0, 12);	237	u32 *cs = batch_alloc_items(batch, 0, 10);
218		238
219	*cs++ = STATE_BASE_ADDRESS \| (12 - 2);	239	*cs++ = STATE_BASE_ADDRESS \| (10 - 2);
220	/* general */	240	/* general */
221	*cs++ = batch_addr(batch) \| BASE_ADDRESS_MODIFY;	241	*cs++ = batch_addr(batch) \| BASE_ADDRESS_MODIFY;
222	/* surface */	242	/* surface */
@@ -233,8 +253,6 @@ gen7_emit_state_base_address(struct batch_chunk *batch, · 10 unmodified lines
233	*cs++ = BASE_ADDRESS_MODIFY;	253	*cs++ = BASE_ADDRESS_MODIFY;
234	*cs++ = 0;	254	*cs++ = 0;
235	*cs++ = BASE_ADDRESS_MODIFY;	255	*cs++ = BASE_ADDRESS_MODIFY;
236	*cs++ = 0;
237	*cs++ = 0;
238	batch_advance(batch, cs);	256	batch_advance(batch, cs);
239	}	257	}
240		258
@@ -244,8 +262,7 @@ gen7_emit_vfe_state(struct batch_chunk *batch, · 3 unmodified lines
244	u32 urb_size, u32 curbe_size,	262	u32 urb_size, u32 curbe_size,
245	u32 mode)	263	u32 mode)
246	{	264	{
247	u32 urb_entries = bv->max_urb_entries;	265	u32 threads = bv->max_threads - 1;
248	u32 threads = bv->max_primitives - 1;
249	u32 *cs = batch_alloc_items(batch, 32, 8);	266	u32 *cs = batch_alloc_items(batch, 32, 8);
250		267
251	*cs++ = MEDIA_VFE_STATE \| (8 - 2);	268	*cs++ = MEDIA_VFE_STATE \| (8 - 2);
@@ -254,7 +271,7 @@ gen7_emit_vfe_state(struct batch_chunk *batch, · 2 unmodified lines
254	*cs++ = 0;	271	*cs++ = 0;
255		272
256	/* number of threads & urb entries for GPGPU vs Media Mode */	273	/* number of threads & urb entries for GPGPU vs Media Mode */
257	*cs++ = threads << 16 \| urb_entries << 8 \| mode << 2;	274	*cs++ = threads << 16 \| 1 << 8 \| mode << 2;
258		275
259	*cs++ = 0;	276	*cs++ = 0;
260		277
@@ -293,17 +310,12 @@ gen7_emit_media_object(struct batch_chunk *batch, · 32 unmodified lines
293	{	310	{
294	unsigned int x_offset = (media_object_index % 16) * 64;	311	unsigned int x_offset = (media_object_index % 16) * 64;
295	unsigned int y_offset = (media_object_index / 16) * 16;	312	unsigned int y_offset = (media_object_index / 16) * 16;
296	unsigned int inline_data_size;	313	unsigned int pkt = 6 + 3;
297	unsigned int media_batch_size;
298	unsigned int i;
299	u32 *cs;	314	u32 *cs;
300		315
301	inline_data_size = 112 * 8;	316	cs = batch_alloc_items(batch, 8, pkt);
302	media_batch_size = inline_data_size + 6;
303
304	cs = batch_alloc_items(batch, 8, media_batch_size);
305		317
306	*cs++ = MEDIA_OBJECT \| (media_batch_size - 2);	318	*cs++ = MEDIA_OBJECT \| (pkt - 2);
307		319
308	/* interface descriptor offset */	320	/* interface descriptor offset */
309	*cs++ = 0;	321	*cs++ = 0;
@@ -317,25 +329,44 @@ gen7_emit_media_object(struct batch_chunk *batch, · 7 unmodified lines
317	*cs++ = 0;	329	*cs++ = 0;
318		330
319	/* inline */	331	/* inline */
320	*cs++ = (y_offset << 16) \| (x_offset);	332	*cs++ = y_offset << 16 \| x_offset;
321	*cs++ = 0;	333	*cs++ = 0;
322	*cs++ = GT3_INLINE_DATA_DELAYS;	334	*cs++ = GT3_INLINE_DATA_DELAYS;
323	for (i = 3; i < inline_data_size; i++)
324	*cs++ = 0;
325		335
326	batch_advance(batch, cs);	336	batch_advance(batch, cs);
327	}	337	}
328		338
329	static void gen7_emit_pipeline_flush(struct batch_chunk *batch)	339	static void gen7_emit_pipeline_flush(struct batch_chunk *batch)
330	{	340	{
331	u32 *cs = batch_alloc_items(batch, 0, 5);	341	u32 *cs = batch_alloc_items(batch, 0, 4);
332		342
333	*cs++ = GFX_OP_PIPE_CONTROL(5);	343	*cs++ = GFX_OP_PIPE_CONTROL(4);
334	*cs++ = PIPE_CONTROL_STATE_CACHE_INVALIDATE \|	344	*cs++ = PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH \|
335	PIPE_CONTROL_GLOBAL_GTT_IVB;	345	PIPE_CONTROL_DEPTH_CACHE_FLUSH \|
		346	PIPE_CONTROL_DC_FLUSH_ENABLE \|
		347	PIPE_CONTROL_CS_STALL;
336	*cs++ = 0;	348	*cs++ = 0;
337	*cs++ = 0;	349	*cs++ = 0;
		350
		351	batch_advance(batch, cs);
		352	}
		353
		354	static void gen7_emit_pipeline_invalidate(struct batch_chunk *batch)
		355	{
		356	u32 *cs = batch_alloc_items(batch, 0, 8);
		357
		358	/* ivb: Stall before STATE_CACHE_INVALIDATE */
		359	*cs++ = GFX_OP_PIPE_CONTROL(4);
		360	*cs++ = PIPE_CONTROL_STALL_AT_SCOREBOARD \|
		361	PIPE_CONTROL_CS_STALL;
		362	*cs++ = 0;
		363	*cs++ = 0;
		364
		365	*cs++ = GFX_OP_PIPE_CONTROL(4);
		366	*cs++ = PIPE_CONTROL_STATE_CACHE_INVALIDATE;
338	*cs++ = 0;	367	*cs++ = 0;
		368	*cs++ = 0;
		369
339	batch_advance(batch, cs);	370	batch_advance(batch, cs);
340	}	371	}
341		372
@@ -344,34 +375,34 @@ static void emit_batch(struct i915_vma * const vma, · 2 unmodified lines
344	const struct batch_vals *bv)	375	const struct batch_vals *bv)
345	{	376	{
346	struct drm_i915_private *i915 = vma->vm->i915;	377	struct drm_i915_private *i915 = vma->vm->i915;
347	unsigned int desc_count = 64;	378	const unsigned int desc_count = 1;
348	const u32 urb_size = 112;	379	const unsigned int urb_size = 1;
349	struct batch_chunk cmds, state;	380	struct batch_chunk cmds, state;
350	u32 interface_descriptor;	381	u32 descriptors;
351	unsigned int i;	382	unsigned int i;
352		383
353	batch_init(&cmds, vma, start, 0, bv->cmd_size);	384	batch_init(&cmds, vma, start, 0, bv->state_start);
354	batch_init(&state, vma, start, bv->state_start, bv->state_size);	385	batch_init(&state, vma, start, bv->state_start, SZ_4K);
355		386
356	interface_descriptor =	387	descriptors = gen7_fill_interface_descriptor(&state, bv,
357	gen7_fill_interface_descriptor(&state, bv,	388	IS_HASWELL(i915) ?
358	IS_HASWELL(i915) ?	389	&cb_kernel_hsw :
359	&cb_kernel_hsw :	390	&cb_kernel_ivb,
360	&cb_kernel_ivb,	391	desc_count);
361	desc_count);	392
362	gen7_emit_pipeline_flush(&cmds);	393	gen7_emit_pipeline_invalidate(&cmds);
363	batch_add(&cmds, PIPELINE_SELECT \| PIPELINE_SELECT_MEDIA);	394	batch_add(&cmds, PIPELINE_SELECT \| PIPELINE_SELECT_MEDIA);
364	batch_add(&cmds, MI_NOOP);	395	batch_add(&cmds, MI_NOOP);
365	gen7_emit_state_base_address(&cmds, interface_descriptor);	396	gen7_emit_pipeline_invalidate(&cmds);
		397
366	gen7_emit_pipeline_flush(&cmds);	398	gen7_emit_pipeline_flush(&cmds);
		399	gen7_emit_state_base_address(&cmds, descriptors);
		400	gen7_emit_pipeline_invalidate(&cmds);
367		401
368	gen7_emit_vfe_state(&cmds, bv, urb_size - 1, 0, 0);	402	gen7_emit_vfe_state(&cmds, bv, urb_size - 1, 0, 0);
		403	gen7_emit_interface_descriptor_load(&cmds, descriptors, desc_count);
369		404
370	gen7_emit_interface_descriptor_load(&cmds,	405	for (i = 0; i < num_primitives(bv); i++)
371	interface_descriptor,
372	desc_count);
373
374	for (i = 0; i < bv->max_primitives; i++)
375	gen7_emit_media_object(&cmds, i);	406	gen7_emit_media_object(&cmds, i);
376		407
377	batch_add(&cmds, MI_BATCH_BUFFER_END);	408	batch_add(&cmds, MI_BATCH_BUFFER_END);
@@ -385,15 +416,15 @@ int gen7_setup_clear_gpr_bb(struct intel_engine_cs * const engine, · 7 unmodified lines
385		416
386	batch_get_defaults(engine->i915, &bv);	417	batch_get_defaults(engine->i915, &bv);
387	if (!vma)	418	if (!vma)
388	return bv.max_size;	419	return bv.size;
389		420
390	GEM_BUG_ON(vma->obj->base.size < bv.max_size);	421	GEM_BUG_ON(vma->obj->base.size < bv.size);
391		422
392	batch = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);	423	batch = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
393	if (IS_ERR(batch))	424	if (IS_ERR(batch))
394	return PTR_ERR(batch);	425	return PTR_ERR(batch);
395		426
396	emit_batch(vma, memset(batch, 0, bv.max_size), &bv);	427	emit_batch(vma, memset(batch, 0, bv.size), &bv);
397		428
398	i915_gem_object_flush_map(vma->obj);	429	i915_gem_object_flush_map(vma->obj);
399	__i915_gem_object_release_map(vma->obj);	430	__i915_gem_object_release_map(vma->obj);

drivers/gpu/drm/i915/gt/intel_ring_submission.c+4−2

 #include "gen6_ppgtt.h"
 #include "gen7_renderclear.h"
 #include "i915_drv.h"
+#include "i915_mitigations.h"
 #include "intel_breadcrumbs.h"
 #include "intel_context.h"
 #include "intel_gt.h"
 	GEM_BUG_ON(HAS_EXECLISTS(engine->i915));
 	if (engine->wa_ctx.vma && ce != engine->kernel_context) {
-		if (engine->wa_ctx.vma->private != ce) {
+		if (engine->wa_ctx.vma->private != ce &&
+		    i915_mitigate_clear_residuals()) {
 			ret = clear_residuals(rq);
 			if (ret)
 				return ret;
 	GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma);
-	if (IS_HASWELL(engine->i915) && engine->class == RENDER_CLASS) {
+	if (IS_GEN(engine->i915, 7) && engine->class == RENDER_CLASS) {
 		err = gen7_ctx_switch_bb_init(engine);
 		if (err)
 			goto err_ring_unpin;

drivers/gpu/drm/i915/gvt/display.c+57−24

 				  DDI_BUF_CTL_ENABLE);
 			vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE;
 		}
+		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
+			~(PORTA_HOTPLUG_ENABLE | PORTA_HOTPLUG_STATUS_MASK);
+		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
+			~(PORTB_HOTPLUG_ENABLE | PORTB_HOTPLUG_STATUS_MASK);
+		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
+			~(PORTC_HOTPLUG_ENABLE | PORTC_HOTPLUG_STATUS_MASK);
+		/* No hpd_invert set in vgpu vbt, need to clear invert mask */
+		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK;
+		vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK;
 		vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1));
 		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
 			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)) |=
 				(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
 				 TRANS_DDI_FUNC_ENABLE);
+			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
+				PORTA_HOTPLUG_ENABLE;
 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
 				GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
 		}
 				(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
 				 (PORT_B << TRANS_DDI_PORT_SHIFT) |
 				 TRANS_DDI_FUNC_ENABLE);
+			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
+				PORTB_HOTPLUG_ENABLE;
 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
 				GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
 		}
 				(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
 				 (PORT_B << TRANS_DDI_PORT_SHIFT) |
 				 TRANS_DDI_FUNC_ENABLE);
+			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
+				PORTC_HOTPLUG_ENABLE;
 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
 				GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
 		}
 				PORTD_HOTPLUG_STATUS_MASK;
 		intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG);
 	} else if (IS_BROXTON(i915)) {
-		if (connected) {
+		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
-			if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
+			if (connected) {
 				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
 					GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
+			} else {
+				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
+					~GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
 			}
-			if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
+			vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
-				vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
+				GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
-					SFUSE_STRAP_DDIB_DETECTED;
+			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
+				~PORTA_HOTPLUG_STATUS_MASK;
+			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
+				PORTA_HOTPLUG_LONG_DETECT;
+			intel_vgpu_trigger_virtual_event(vgpu, DP_A_HOTPLUG);
+		}
+		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
+			if (connected) {
 				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
 					GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
-			}
-			if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
 				vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
-					SFUSE_STRAP_DDIC_DETECTED;
+					SFUSE_STRAP_DDIB_DETECTED;
-				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
+			} else {
-					GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
-			}
-		} else {
-			if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
 				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
-					~GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
+					~GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
-			}
-			if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
 				vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
 					~SFUSE_STRAP_DDIB_DETECTED;
-				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
-					~GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
 			}
-			if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
+			vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
-				vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
+				GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
-					~SFUSE_STRAP_DDIC_DETECTED;
+			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
+				~PORTB_HOTPLUG_STATUS_MASK;
+			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
+				PORTB_HOTPLUG_LONG_DETECT;
+			intel_vgpu_trigger_virtual_event(vgpu, DP_B_HOTPLUG);
+		}
+		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
+			if (connected) {
+				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
+					GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
+				vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
+					SFUSE_STRAP_DDIC_DETECTED;
+			} else {
 				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
 					~GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
+				vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
+					~SFUSE_STRAP_DDIC_DETECTED;
 			}
+			vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
+				GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
+			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
+				~PORTC_HOTPLUG_STATUS_MASK;
+			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
+				PORTC_HOTPLUG_LONG_DETECT;
+			intel_vgpu_trigger_virtual_event(vgpu, DP_C_HOTPLUG);
 		}
-		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
-			PORTB_HOTPLUG_STATUS_MASK;
-		intel_vgpu_trigger_virtual_event(vgpu, DP_B_HOTPLUG);
 	}
 }

drivers/gpu/drm/i915/gvt/vgpu.c+2−3

 	if (ret)
 		goto out_clean_sched_policy;
-	if (IS_BROADWELL(dev_priv))
+	if (IS_BROADWELL(dev_priv) || IS_BROXTON(dev_priv))
 		ret = intel_gvt_hypervisor_set_edid(vgpu, PORT_B);
-	/* FixMe: Re-enable APL/BXT once vfio_edid enabled */
+	else
-	else if (!IS_BROXTON(dev_priv))
 		ret = intel_gvt_hypervisor_set_edid(vgpu, PORT_D);
 	if (ret)
 		goto out_clean_sched_policy;

drivers/gpu/drm/i915/i915_drv.c+4−0

 void i915_driver_shutdown(struct drm_i915_private *i915)
 {
+	disable_rpm_wakeref_asserts(&i915->runtime_pm);
 	i915_gem_suspend(i915);
 	drm_kms_helper_poll_disable(&i915->drm);
 	intel_suspend_encoders(i915);
 	intel_shutdown_encoders(i915);
+	enable_rpm_wakeref_asserts(&i915->runtime_pm);
 }
 static bool suspend_to_idle(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_mitigations.c+146−0

@@ -0,0 +1,146 @@
	1	// SPDX-License-Identifier: MIT
	2	/*
	3	* Copyright © 2021 Intel Corporation
	4	*/
	5
	6	#include <linux/kernel.h>
	7	#include <linux/moduleparam.h>
	8	#include <linux/slab.h>
	9	#include <linux/string.h>
	10
	11	#include "i915_drv.h"
	12	#include "i915_mitigations.h"
	13
	14	static unsigned long mitigations __read_mostly = ~0UL;
	15
	16	enum {
	17	CLEAR_RESIDUALS = 0,
	18	};
	19
	20	static const char * const names[] = {
	21	[CLEAR_RESIDUALS] = "residuals",
	22	};
	23
	24	bool i915_mitigate_clear_residuals(void)
	25	{
	26	return READ_ONCE(mitigations) & BIT(CLEAR_RESIDUALS);
	27	}
	28
	29	static int mitigations_set(const char val, const struct kernel_param kp)
	30	{
	31	unsigned long new = ~0UL;
	32	char str, sep, *tok;
	33	bool first = true;
	34	int err = 0;
	35
	36	BUILD_BUG_ON(ARRAY_SIZE(names) >= BITS_PER_TYPE(mitigations));
	37
	38	str = kstrdup(val, GFP_KERNEL);
	39	if (!str)
	40	return -ENOMEM;
	41
	42	for (sep = str; (tok = strsep(&sep, ","));) {
	43	bool enable = true;
	44	int i;
	45
	46	/* Be tolerant of leading/trailing whitespace */
	47	tok = strim(tok);
	48
	49	if (first) {
	50	first = false;
	51
	52	if (!strcmp(tok, "auto"))
	53	continue;
	54
	55	new = 0;
	56	if (!strcmp(tok, "off"))
	57	continue;
	58	}
	59
	60	if (*tok == '!') {
	61	enable = !enable;
	62	tok++;
	63	}
	64
	65	if (!strncmp(tok, "no", 2)) {
	66	enable = !enable;
	67	tok += 2;
	68	}
	69
	70	if (*tok == '\0')
	71	continue;
	72
	73	for (i = 0; i < ARRAY_SIZE(names); i++) {
	74	if (!strcmp(tok, names[i])) {
	75	if (enable)
	76	new \|= BIT(i);
	77	else
	78	new &= ~BIT(i);
	79	break;
	80	}
	81	}
	82	if (i == ARRAY_SIZE(names)) {
	83	pr_err("Bad \"%s.mitigations=%s\", '%s' is unknown\n",
	84	DRIVER_NAME, val, tok);
	85	err = -EINVAL;
	86	break;
	87	}
	88	}
	89	kfree(str);
	90	if (err)
	91	return err;
	92
	93	WRITE_ONCE(mitigations, new);
	94	return 0;
	95	}
	96
	97	static int mitigations_get(char buffer, const struct kernel_param kp)
	98	{
	99	unsigned long local = READ_ONCE(mitigations);
	100	int count, i;
	101	bool enable;
	102
	103	if (!local)
	104	return scnprintf(buffer, PAGE_SIZE, "%s\n", "off");
	105
	106	if (local & BIT(BITS_PER_LONG - 1)) {
	107	count = scnprintf(buffer, PAGE_SIZE, "%s,", "auto");
	108	enable = false;
	109	} else {
	110	enable = true;
	111	count = 0;
	112	}
	113
	114	for (i = 0; i < ARRAY_SIZE(names); i++) {
	115	if ((local & BIT(i)) != enable)
	116	continue;
	117
	118	count += scnprintf(buffer + count, PAGE_SIZE - count,
	119	"%s%s,", enable ? "" : "!", names[i]);
	120	}
	121
	122	buffer[count - 1] = '\n';
	123	return count;
	124	}
	125
	126	static const struct kernel_param_ops ops = {
	127	.set = mitigations_set,
	128	.get = mitigations_get,
	129	};
	130
	131	module_param_cb_unsafe(mitigations, &ops, NULL, 0600);
	132	MODULE_PARM_DESC(mitigations,
	133	"Selectively enable security mitigations for all Intel® GPUs in the system.\n"
	134	"\n"
	135	" auto -- enables all mitigations required for the platform [default]\n"
	136	" off -- disables all mitigations\n"
	137	"\n"
	138	"Individual mitigations can be enabled by passing a comma-separated string,\n"
	139	"e.g. mitigations=residuals to enable only clearing residuals or\n"
	140	"mitigations=auto,noresiduals to disable only the clear residual mitigation.\n"
	141	"Either '!' or 'no' may be used to switch from enabling the mitigation to\n"
	142	"disabling it.\n"
	143	"\n"
	144	"Active mitigations for Ivybridge, Baytrail, Haswell:\n"
	145	" residuals -- clear all thread-local registers between contexts"
	146	);

drivers/gpu/drm/i915/i915_mitigations.h+13−0

@@ -0,0 +1,13 @@
	1	/* SPDX-License-Identifier: MIT */
	2	/*
	3	* Copyright © 2021 Intel Corporation
	4	*/
	5
	6	#ifndef __I915_MITIGATIONS_H__
	7	#define __I915_MITIGATIONS_H__
	8
	9	#include <linux/types.h>
	10
	11	bool i915_mitigate_clear_residuals(void);
	12
	13	#endif /* __I915_MITIGATIONS_H__ */

drivers/gpu/drm/nouveau/dispnv50/Kbuild+1−0

@@ -37,6 +37,7 @@ nouveau-y += dispnv50/wimmc37b.o · 36 unmodified lines
37	nouveau-y += dispnv50/wndw.o	37	nouveau-y += dispnv50/wndw.o
38	nouveau-y += dispnv50/wndwc37e.o	38	nouveau-y += dispnv50/wndwc37e.o
39	nouveau-y += dispnv50/wndwc57e.o	39	nouveau-y += dispnv50/wndwc57e.o
		40	nouveau-y += dispnv50/wndwc67e.o
40		41
41	nouveau-y += dispnv50/base.o	42	nouveau-y += dispnv50/base.o
42	nouveau-y += dispnv50/base507c.o	43	nouveau-y += dispnv50/base507c.o

drivers/gpu/drm/nouveau/dispnv50/core.c+1−0

@@ -42,6 +42,7 @@ nv50_core_new(struct nouveau_drm drm, struct nv50_core *pcore) · 41 unmodified lines
42	int version;	42	int version;
43	int (new)(struct nouveau_drm , s32, struct nv50_core **);	43	int (new)(struct nouveau_drm , s32, struct nv50_core **);
44	} cores[] = {	44	} cores[] = {
		45	{ GA102_DISP_CORE_CHANNEL_DMA, 0, corec57d_new },
45	{ TU102_DISP_CORE_CHANNEL_DMA, 0, corec57d_new },	46	{ TU102_DISP_CORE_CHANNEL_DMA, 0, corec57d_new },
46	{ GV100_DISP_CORE_CHANNEL_DMA, 0, corec37d_new },	47	{ GV100_DISP_CORE_CHANNEL_DMA, 0, corec37d_new },
47	{ GP102_DISP_CORE_CHANNEL_DMA, 0, core917d_new },	48	{ GP102_DISP_CORE_CHANNEL_DMA, 0, core917d_new },

drivers/gpu/drm/nouveau/dispnv50/curs.c+1−0

@@ -31,6 +31,7 @@ nv50_curs_new(struct nouveau_drm drm, int head, struct nv50_wndw *pwndw) · 30 unmodified lines
31	int version;	31	int version;
32	int (new)(struct nouveau_drm , int, s32, struct nv50_wndw **);	32	int (new)(struct nouveau_drm , int, s32, struct nv50_wndw **);
33	} curses[] = {	33	} curses[] = {
		34	{ GA102_DISP_CURSOR, 0, cursc37a_new },
34	{ TU102_DISP_CURSOR, 0, cursc37a_new },	35	{ TU102_DISP_CURSOR, 0, cursc37a_new },
35	{ GV100_DISP_CURSOR, 0, cursc37a_new },	36	{ GV100_DISP_CURSOR, 0, cursc37a_new },
36	{ GK104_DISP_CURSOR, 0, curs907a_new },	37	{ GK104_DISP_CURSOR, 0, curs907a_new },

drivers/gpu/drm/nouveau/dispnv50/disp.c+2−2

@@ -222,7 +222,7 @@ nv50_dmac_wait(struct nvif_push *push, u32 size) · 221 unmodified lines
222		222
223	int	223	int
224	nv50_dmac_create(struct nvif_device device, struct nvif_object disp,	224	nv50_dmac_create(struct nvif_device device, struct nvif_object disp,
225	const s32 oclass, u8 head, void data, u32 size, u64 syncbuf,	225	const s32 oclass, u8 head, void data, u32 size, s64 syncbuf,
226	struct nv50_dmac *dmac)	226	struct nv50_dmac *dmac)
227	{	227	{
228	struct nouveau_cli cli = (void )device->object.client;	228	struct nouveau_cli cli = (void )device->object.client;
@@ -271,7 +271,7 @@ nv50_dmac_create(struct nvif_device device, struct nvif_object disp, · 42 unmodified lines
271	if (ret)	271	if (ret)
272	return ret;	272	return ret;
273		273
274	if (!syncbuf)	274	if (syncbuf < 0)
275	return 0;	275	return 0;
276		276
277	ret = nvif_object_ctor(&dmac->base.user, "kmsSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF,	277	ret = nvif_object_ctor(&dmac->base.user, "kmsSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF,

drivers/gpu/drm/nouveau/dispnv50/disp.h+1−1

@@ -95,7 +95,7 @@ struct nv50_outp_atom { · 94 unmodified lines
95		95
96	int nv50_dmac_create(struct nvif_device device, struct nvif_object disp,	96	int nv50_dmac_create(struct nvif_device device, struct nvif_object disp,
97	const s32 oclass, u8 head, void data, u32 size,	97	const s32 oclass, u8 head, void data, u32 size,
98	u64 syncbuf, struct nv50_dmac *dmac);	98	s64 syncbuf, struct nv50_dmac *dmac);
99	void nv50_dmac_destroy(struct nv50_dmac *);	99	void nv50_dmac_destroy(struct nv50_dmac *);
100		100
101	/*	101	/*

drivers/gpu/drm/nouveau/dispnv50/wimm.c+1−0

@@ -31,6 +31,7 @@ nv50_wimm_init(struct nouveau_drm drm, struct nv50_wndw wndw) · 30 unmodified lines
31	int version;	31	int version;
32	int (init)(struct nouveau_drm , s32, struct nv50_wndw *);	32	int (init)(struct nouveau_drm , s32, struct nv50_wndw *);
33	} wimms[] = {	33	} wimms[] = {
		34	{ GA102_DISP_WINDOW_IMM_CHANNEL_DMA, 0, wimmc37b_init },
34	{ TU102_DISP_WINDOW_IMM_CHANNEL_DMA, 0, wimmc37b_init },	35	{ TU102_DISP_WINDOW_IMM_CHANNEL_DMA, 0, wimmc37b_init },
35	{ GV100_DISP_WINDOW_IMM_CHANNEL_DMA, 0, wimmc37b_init },	36	{ GV100_DISP_WINDOW_IMM_CHANNEL_DMA, 0, wimmc37b_init },
36	{}	37	{}

drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c+1−1

@@ -76,7 +76,7 @@ wimmc37b_init_(const struct nv50_wimm_func func, struct nouveau_drm drm, · 75 unmodified lines
76	int ret;	76	int ret;
77		77
78	ret = nv50_dmac_create(&drm->client.device, &disp->disp->object,	78	ret = nv50_dmac_create(&drm->client.device, &disp->disp->object,
79	&oclass, 0, &args, sizeof(args), 0,	79	&oclass, 0, &args, sizeof(args), -1,
80	&wndw->wimm);	80	&wndw->wimm);
81	if (ret) {	81	if (ret) {
82	NV_ERROR(drm, "wimm%04x allocation failed: %d\n", oclass, ret);	82	NV_ERROR(drm, "wimm%04x allocation failed: %d\n", oclass, ret);

drivers/gpu/drm/nouveau/dispnv50/wndw.c+1−0

@@ -784,6 +784,7 @@ nv50_wndw_new(struct nouveau_drm *drm, enum drm_plane_type type, int index, · 783 unmodified lines
784	int (new)(struct nouveau_drm , enum drm_plane_type,	784	int (new)(struct nouveau_drm , enum drm_plane_type,
785	int, s32, struct nv50_wndw **);	785	int, s32, struct nv50_wndw **);
786	} wndws[] = {	786	} wndws[] = {
		787	{ GA102_DISP_WINDOW_CHANNEL_DMA, 0, wndwc67e_new },
787	{ TU102_DISP_WINDOW_CHANNEL_DMA, 0, wndwc57e_new },	788	{ TU102_DISP_WINDOW_CHANNEL_DMA, 0, wndwc57e_new },
788	{ GV100_DISP_WINDOW_CHANNEL_DMA, 0, wndwc37e_new },	789	{ GV100_DISP_WINDOW_CHANNEL_DMA, 0, wndwc37e_new },
789	{}	790	{}

drivers/gpu/drm/nouveau/dispnv50/wndw.h+8−0

@@ -129,6 +129,14 @@ int wndwc37e_update(struct nv50_wndw , u32 ); · 128 unmodified lines
129		129
130	int wndwc57e_new(struct nouveau_drm *, enum drm_plane_type, int, s32,	130	int wndwc57e_new(struct nouveau_drm *, enum drm_plane_type, int, s32,
131	struct nv50_wndw **);	131	struct nv50_wndw **);
		132	bool wndwc57e_ilut(struct nv50_wndw , struct nv50_wndw_atom , int);
		133	int wndwc57e_ilut_set(struct nv50_wndw , struct nv50_wndw_atom );
		134	int wndwc57e_ilut_clr(struct nv50_wndw *);
		135	int wndwc57e_csc_set(struct nv50_wndw , struct nv50_wndw_atom );
		136	int wndwc57e_csc_clr(struct nv50_wndw *);
		137
		138	int wndwc67e_new(struct nouveau_drm *, enum drm_plane_type, int, s32,
		139	struct nv50_wndw **);
132		140
133	int nv50_wndw_new(struct nouveau_drm *, enum drm_plane_type, int index,	141	int nv50_wndw_new(struct nouveau_drm *, enum drm_plane_type, int index,
134	struct nv50_wndw **);	142	struct nv50_wndw **);

drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c+5−5

@@ -80,7 +80,7 @@ wndwc57e_image_set(struct nv50_wndw wndw, struct nv50_wndw_atom asyw) · 79 unmodified lines
80	return 0;	80	return 0;
81	}	81	}
82		82
83	static int	83	int
84	wndwc57e_csc_clr(struct nv50_wndw *wndw)	84	wndwc57e_csc_clr(struct nv50_wndw *wndw)
85	{	85	{
86	struct nvif_push *push = wndw->wndw.push;	86	struct nvif_push *push = wndw->wndw.push;
@@ -98,7 +98,7 @@ wndwc57e_csc_clr(struct nv50_wndw *wndw) · 11 unmodified lines
98	return 0;	98	return 0;
99	}	99	}
100		100
101	static int	101	int
102	wndwc57e_csc_set(struct nv50_wndw wndw, struct nv50_wndw_atom asyw)	102	wndwc57e_csc_set(struct nv50_wndw wndw, struct nv50_wndw_atom asyw)
103	{	103	{
104	struct nvif_push *push = wndw->wndw.push;	104	struct nvif_push *push = wndw->wndw.push;
@@ -111,7 +111,7 @@ wndwc57e_csc_set(struct nv50_wndw wndw, struct nv50_wndw_atom asyw) · 6 unmodified lines
111	return 0;	111	return 0;
112	}	112	}
113		113
114	static int	114	int
115	wndwc57e_ilut_clr(struct nv50_wndw *wndw)	115	wndwc57e_ilut_clr(struct nv50_wndw *wndw)
116	{	116	{
117	struct nvif_push *push = wndw->wndw.push;	117	struct nvif_push *push = wndw->wndw.push;
@@ -124,7 +124,7 @@ wndwc57e_ilut_clr(struct nv50_wndw *wndw) · 6 unmodified lines
124	return 0;	124	return 0;
125	}	125	}
126		126
127	static int	127	int
128	wndwc57e_ilut_set(struct nv50_wndw wndw, struct nv50_wndw_atom asyw)	128	wndwc57e_ilut_set(struct nv50_wndw wndw, struct nv50_wndw_atom asyw)
129	{	129	{
130	struct nvif_push *push = wndw->wndw.push;	130	struct nvif_push *push = wndw->wndw.push;
@@ -179,7 +179,7 @@ wndwc57e_ilut_load(struct drm_color_lut in, int size, void __iomem mem) · 48 unmodified lines
179	writew(readw(mem - 4), mem + 4);	179	writew(readw(mem - 4), mem + 4);
180	}	180	}
181		181
182	static bool	182	bool
183	wndwc57e_ilut(struct nv50_wndw wndw, struct nv50_wndw_atom asyw, int size)	183	wndwc57e_ilut(struct nv50_wndw wndw, struct nv50_wndw_atom asyw, int size)
184	{	184	{
185	if (size = size ? size : 1024, size != 256 && size != 1024)	185	if (size = size ? size : 1024, size != 256 && size != 1024)

drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c+106−0

@@ -0,0 +1,106 @@
	1	/*
	2	* Copyright 2021 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22	#include "wndw.h"
	23	#include "atom.h"
	24
	25	#include <nvif/pushc37b.h>
	26
	27	#include <nvhw/class/clc57e.h>
	28
	29	static int
	30	wndwc67e_image_set(struct nv50_wndw wndw, struct nv50_wndw_atom asyw)
	31	{
	32	struct nvif_push *push = wndw->wndw.push;
	33	int ret;
	34
	35	if ((ret = PUSH_WAIT(push, 17)))
	36	return ret;
	37
	38	PUSH_MTHD(push, NVC57E, SET_PRESENT_CONTROL,
	39	NVVAL(NVC57E, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval) \|
	40	NVVAL(NVC57E, SET_PRESENT_CONTROL, BEGIN_MODE, asyw->image.mode) \|
	41	NVDEF(NVC57E, SET_PRESENT_CONTROL, TIMESTAMP_MODE, DISABLE));
	42
	43	PUSH_MTHD(push, NVC57E, SET_SIZE,
	44	NVVAL(NVC57E, SET_SIZE, WIDTH, asyw->image.w) \|
	45	NVVAL(NVC57E, SET_SIZE, HEIGHT, asyw->image.h),
	46
	47	SET_STORAGE,
	48	NVVAL(NVC57E, SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh),
	49
	50	SET_PARAMS,
	51	NVVAL(NVC57E, SET_PARAMS, FORMAT, asyw->image.format) \|
	52	NVDEF(NVC57E, SET_PARAMS, CLAMP_BEFORE_BLEND, DISABLE) \|
	53	NVDEF(NVC57E, SET_PARAMS, SWAP_UV, DISABLE) \|
	54	NVDEF(NVC57E, SET_PARAMS, FMT_ROUNDING_MODE, ROUND_TO_NEAREST),
	55
	56	SET_PLANAR_STORAGE(0),
	57	NVVAL(NVC57E, SET_PLANAR_STORAGE, PITCH, asyw->image.blocks[0]) \|
	58	NVVAL(NVC57E, SET_PLANAR_STORAGE, PITCH, asyw->image.pitch[0] >> 6));
	59
	60	PUSH_MTHD(push, NVC57E, SET_CONTEXT_DMA_ISO(0), asyw->image.handle, 1);
	61	PUSH_MTHD(push, NVC57E, SET_OFFSET(0), asyw->image.offset[0] >> 8);
	62
	63	PUSH_MTHD(push, NVC57E, SET_POINT_IN(0),
	64	NVVAL(NVC57E, SET_POINT_IN, X, asyw->state.src_x >> 16) \|
	65	NVVAL(NVC57E, SET_POINT_IN, Y, asyw->state.src_y >> 16));
	66
	67	PUSH_MTHD(push, NVC57E, SET_SIZE_IN,
	68	NVVAL(NVC57E, SET_SIZE_IN, WIDTH, asyw->state.src_w >> 16) \|
	69	NVVAL(NVC57E, SET_SIZE_IN, HEIGHT, asyw->state.src_h >> 16));
	70
	71	PUSH_MTHD(push, NVC57E, SET_SIZE_OUT,
	72	NVVAL(NVC57E, SET_SIZE_OUT, WIDTH, asyw->state.crtc_w) \|
	73	NVVAL(NVC57E, SET_SIZE_OUT, HEIGHT, asyw->state.crtc_h));
	74	return 0;
	75	}
	76
	77	static const struct nv50_wndw_func
	78	wndwc67e = {
	79	.acquire = wndwc37e_acquire,
	80	.release = wndwc37e_release,
	81	.sema_set = wndwc37e_sema_set,
	82	.sema_clr = wndwc37e_sema_clr,
	83	.ntfy_set = wndwc37e_ntfy_set,
	84	.ntfy_clr = wndwc37e_ntfy_clr,
	85	.ntfy_reset = corec37d_ntfy_init,
	86	.ntfy_wait_begun = base507c_ntfy_wait_begun,
	87	.ilut = wndwc57e_ilut,
	88	.ilut_identity = true,
	89	.ilut_size = 1024,
	90	.xlut_set = wndwc57e_ilut_set,
	91	.xlut_clr = wndwc57e_ilut_clr,
	92	.csc = base907c_csc,
	93	.csc_set = wndwc57e_csc_set,
	94	.csc_clr = wndwc57e_csc_clr,
	95	.image_set = wndwc67e_image_set,
	96	.image_clr = wndwc37e_image_clr,
	97	.blend_set = wndwc37e_blend_set,
	98	.update = wndwc37e_update,
	99	};
	100
	101	int
	102	wndwc67e_new(struct nouveau_drm *drm, enum drm_plane_type type, int index,
	103	s32 oclass, struct nv50_wndw **pwndw)
	104	{
	105	return wndwc37e_new_(&wndwc67e, drm, type, index, oclass, BIT(index >> 1), pwndw);
	106	}

drivers/gpu/drm/nouveau/include/nvif/cl0080.h+1−0

@@ -33,6 +33,7 @@ struct nv_device_info_v0 { · 32 unmodified lines
33	#define NV_DEVICE_INFO_V0_PASCAL 0x0a	33	#define NV_DEVICE_INFO_V0_PASCAL 0x0a
34	#define NV_DEVICE_INFO_V0_VOLTA 0x0b	34	#define NV_DEVICE_INFO_V0_VOLTA 0x0b
35	#define NV_DEVICE_INFO_V0_TURING 0x0c	35	#define NV_DEVICE_INFO_V0_TURING 0x0c
		36	#define NV_DEVICE_INFO_V0_AMPERE 0x0d
36	__u8 family;	37	__u8 family;
37	__u8 pad06[2];	38	__u8 pad06[2];
38	__u64 ram_size;	39	__u64 ram_size;

drivers/gpu/drm/nouveau/include/nvif/class.h+5−0

 #define GP102_DISP                                    /* cl5070.h */ 0x00009870
 #define GV100_DISP                                    /* cl5070.h */ 0x0000c370
 #define TU102_DISP                                    /* cl5070.h */ 0x0000c570
+#define GA102_DISP                                    /* cl5070.h */ 0x0000c670
 #define GV100_DISP_CAPS                                              0x0000c373
 #define GK104_DISP_CURSOR                             /* cl507a.h */ 0x0000917a
 #define GV100_DISP_CURSOR                             /* cl507a.h */ 0x0000c37a
 #define TU102_DISP_CURSOR                             /* cl507a.h */ 0x0000c57a
+#define GA102_DISP_CURSOR                             /* cl507a.h */ 0x0000c67a
 #define NV50_DISP_OVERLAY                             /* cl507b.h */ 0x0000507b
 #define G82_DISP_OVERLAY                              /* cl507b.h */ 0x0000827b
 #define GV100_DISP_WINDOW_IMM_CHANNEL_DMA             /* clc37b.h */ 0x0000c37b
 #define TU102_DISP_WINDOW_IMM_CHANNEL_DMA             /* clc37b.h */ 0x0000c57b
+#define GA102_DISP_WINDOW_IMM_CHANNEL_DMA             /* clc37b.h */ 0x0000c67b
 #define NV50_DISP_BASE_CHANNEL_DMA                    /* cl507c.h */ 0x0000507c
 #define G82_DISP_BASE_CHANNEL_DMA                     /* cl507c.h */ 0x0000827c
 #define GP102_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000987d
 #define GV100_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000c37d
 #define TU102_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000c57d
+#define GA102_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000c67d
 #define NV50_DISP_OVERLAY_CHANNEL_DMA                 /* cl507e.h */ 0x0000507e
 #define G82_DISP_OVERLAY_CHANNEL_DMA                  /* cl507e.h */ 0x0000827e
 #define GV100_DISP_WINDOW_CHANNEL_DMA                 /* clc37e.h */ 0x0000c37e
 #define TU102_DISP_WINDOW_CHANNEL_DMA                 /* clc37e.h */ 0x0000c57e
+#define GA102_DISP_WINDOW_CHANNEL_DMA                 /* clc37e.h */ 0x0000c67e
 #define NV50_TESLA                                                   0x00005097
 #define G82_TESLA                                                    0x00008297

drivers/gpu/drm/nouveau/include/nvkm/core/device.h+1−0

@@ -120,6 +120,7 @@ struct nvkm_device { · 119 unmodified lines
120	GP100 = 0x130,	120	GP100 = 0x130,
121	GV100 = 0x140,	121	GV100 = 0x140,
122	TU100 = 0x160,	122	TU100 = 0x160,
		123	GA100 = 0x170,
123	} card_type;	124	} card_type;
124	u32 chipset;	125	u32 chipset;
125	u8 chiprev;	126	u8 chiprev;

drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h+1−0

@@ -37,4 +37,5 @@ int gp100_disp_new(struct nvkm_device , int, struct nvkm_disp *); · 36 unmodified lines
37	int gp102_disp_new(struct nvkm_device , int, struct nvkm_disp *);	37	int gp102_disp_new(struct nvkm_device , int, struct nvkm_disp *);
38	int gv100_disp_new(struct nvkm_device , int, struct nvkm_disp *);	38	int gv100_disp_new(struct nvkm_device , int, struct nvkm_disp *);
39	int tu102_disp_new(struct nvkm_device , int, struct nvkm_disp *);	39	int tu102_disp_new(struct nvkm_device , int, struct nvkm_disp *);
		40	int ga102_disp_new(struct nvkm_device , int, struct nvkm_disp *);
40	#endif	41	#endif

drivers/gpu/drm/nouveau/include/nvkm/subdev/devinit.h+1−0

@@ -32,4 +32,5 @@ int gm107_devinit_new(struct nvkm_device , int, struct nvkm_devinit *); · 31 unmodified lines
32	int gm200_devinit_new(struct nvkm_device , int, struct nvkm_devinit *);	32	int gm200_devinit_new(struct nvkm_device , int, struct nvkm_devinit *);
33	int gv100_devinit_new(struct nvkm_device , int, struct nvkm_devinit *);	33	int gv100_devinit_new(struct nvkm_device , int, struct nvkm_devinit *);
34	int tu102_devinit_new(struct nvkm_device , int, struct nvkm_devinit *);	34	int tu102_devinit_new(struct nvkm_device , int, struct nvkm_devinit *);
		35	int ga100_devinit_new(struct nvkm_device , int, struct nvkm_devinit *);
35	#endif	36	#endif

drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h+2−0

@@ -86,6 +86,8 @@ int gp100_fb_new(struct nvkm_device , int, struct nvkm_fb *); · 85 unmodified lines
86	int gp102_fb_new(struct nvkm_device , int, struct nvkm_fb *);	86	int gp102_fb_new(struct nvkm_device , int, struct nvkm_fb *);
87	int gp10b_fb_new(struct nvkm_device , int, struct nvkm_fb *);	87	int gp10b_fb_new(struct nvkm_device , int, struct nvkm_fb *);
88	int gv100_fb_new(struct nvkm_device , int, struct nvkm_fb *);	88	int gv100_fb_new(struct nvkm_device , int, struct nvkm_fb *);
		89	int ga100_fb_new(struct nvkm_device , int, struct nvkm_fb *);
		90	int ga102_fb_new(struct nvkm_device , int, struct nvkm_fb *);
89		91
90	#include <subdev/bios.h>	92	#include <subdev/bios.h>
91	#include <subdev/bios/ramcfg.h>	93	#include <subdev/bios/ramcfg.h>

drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h+1−0

@@ -37,4 +37,5 @@ int nv50_gpio_new(struct nvkm_device , int, struct nvkm_gpio *); · 36 unmodified lines
37	int g94_gpio_new(struct nvkm_device , int, struct nvkm_gpio *);	37	int g94_gpio_new(struct nvkm_device , int, struct nvkm_gpio *);
38	int gf119_gpio_new(struct nvkm_device , int, struct nvkm_gpio *);	38	int gf119_gpio_new(struct nvkm_device , int, struct nvkm_gpio *);
39	int gk104_gpio_new(struct nvkm_device , int, struct nvkm_gpio *);	39	int gk104_gpio_new(struct nvkm_device , int, struct nvkm_gpio *);
		40	int ga102_gpio_new(struct nvkm_device , int, struct nvkm_gpio *);
40	#endif	41	#endif

drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h+1−0

@@ -92,6 +92,7 @@ int g94_i2c_new(struct nvkm_device , int, struct nvkm_i2c *); · 91 unmodified lines
92	int gf117_i2c_new(struct nvkm_device , int, struct nvkm_i2c *);	92	int gf117_i2c_new(struct nvkm_device , int, struct nvkm_i2c *);
93	int gf119_i2c_new(struct nvkm_device , int, struct nvkm_i2c *);	93	int gf119_i2c_new(struct nvkm_device , int, struct nvkm_i2c *);
94	int gk104_i2c_new(struct nvkm_device , int, struct nvkm_i2c *);	94	int gk104_i2c_new(struct nvkm_device , int, struct nvkm_i2c *);
		95	int gk110_i2c_new(struct nvkm_device , int, struct nvkm_i2c *);
95	int gm200_i2c_new(struct nvkm_device , int, struct nvkm_i2c *);	96	int gm200_i2c_new(struct nvkm_device , int, struct nvkm_i2c *);
96		97
97	static inline int	98	static inline int

drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h+1−0

@@ -32,4 +32,5 @@ int gk20a_mc_new(struct nvkm_device , int, struct nvkm_mc *); · 31 unmodified lines
32	int gp100_mc_new(struct nvkm_device , int, struct nvkm_mc *);	32	int gp100_mc_new(struct nvkm_device , int, struct nvkm_mc *);
33	int gp10b_mc_new(struct nvkm_device , int, struct nvkm_mc *);	33	int gp10b_mc_new(struct nvkm_device , int, struct nvkm_mc *);
34	int tu102_mc_new(struct nvkm_device , int, struct nvkm_mc *);	34	int tu102_mc_new(struct nvkm_device , int, struct nvkm_mc *);
		35	int ga100_mc_new(struct nvkm_device , int, struct nvkm_mc *);
35	#endif	36	#endif

drivers/gpu/drm/nouveau/nouveau_backlight.c+1−0

@@ -256,6 +256,7 @@ nouveau_backlight_init(struct drm_connector *connector) · 255 unmodified lines
256	case NV_DEVICE_INFO_V0_PASCAL:	256	case NV_DEVICE_INFO_V0_PASCAL:
257	case NV_DEVICE_INFO_V0_VOLTA:	257	case NV_DEVICE_INFO_V0_VOLTA:
258	case NV_DEVICE_INFO_V0_TURING:	258	case NV_DEVICE_INFO_V0_TURING:
		259	case NV_DEVICE_INFO_V0_AMPERE: //XXX: not confirmed
259	ret = nv50_backlight_init(nv_encoder, &props, &ops);	260	ret = nv50_backlight_init(nv_encoder, &props, &ops);
260	break;	261	break;
261	default:	262	default:

drivers/gpu/drm/nouveau/nvif/disp.c+1−0

@@ -35,6 +35,7 @@ nvif_disp_ctor(struct nvif_device device, const char name, s32 oclass, · 34 unmodified lines
35	struct nvif_disp *disp)	35	struct nvif_disp *disp)
36	{	36	{
37	static const struct nvif_mclass disps[] = {	37	static const struct nvif_mclass disps[] = {
		38	{ GA102_DISP, -1 },
38	{ TU102_DISP, -1 },	39	{ TU102_DISP, -1 },
39	{ GV100_DISP, -1 },	40	{ GV100_DISP, -1 },
40	{ GP102_DISP, -1 },	41	{ GP102_DISP, -1 },

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c+78−9

@@ -1815,7 +1815,7 @@ nvf0_chipset = { · 1814 unmodified lines
1815	.fb = gk110_fb_new,	1815	.fb = gk110_fb_new,
1816	.fuse = gf100_fuse_new,	1816	.fuse = gf100_fuse_new,
1817	.gpio = gk104_gpio_new,	1817	.gpio = gk104_gpio_new,
1818	.i2c = gk104_i2c_new,	1818	.i2c = gk110_i2c_new,
1819	.ibus = gk104_ibus_new,	1819	.ibus = gk104_ibus_new,
1820	.iccsense = gf100_iccsense_new,	1820	.iccsense = gf100_iccsense_new,
1821	.imem = nv50_instmem_new,	1821	.imem = nv50_instmem_new,
@@ -1853,7 +1853,7 @@ nvf1_chipset = { · 31 unmodified lines
1853	.fb = gk110_fb_new,	1853	.fb = gk110_fb_new,
1854	.fuse = gf100_fuse_new,	1854	.fuse = gf100_fuse_new,
1855	.gpio = gk104_gpio_new,	1855	.gpio = gk104_gpio_new,
1856	.i2c = gk104_i2c_new,	1856	.i2c = gk110_i2c_new,
1857	.ibus = gk104_ibus_new,	1857	.ibus = gk104_ibus_new,
1858	.iccsense = gf100_iccsense_new,	1858	.iccsense = gf100_iccsense_new,
1859	.imem = nv50_instmem_new,	1859	.imem = nv50_instmem_new,
@@ -1891,7 +1891,7 @@ nv106_chipset = { · 31 unmodified lines
1891	.fb = gk110_fb_new,	1891	.fb = gk110_fb_new,
1892	.fuse = gf100_fuse_new,	1892	.fuse = gf100_fuse_new,
1893	.gpio = gk104_gpio_new,	1893	.gpio = gk104_gpio_new,
1894	.i2c = gk104_i2c_new,	1894	.i2c = gk110_i2c_new,
1895	.ibus = gk104_ibus_new,	1895	.ibus = gk104_ibus_new,
1896	.iccsense = gf100_iccsense_new,	1896	.iccsense = gf100_iccsense_new,
1897	.imem = nv50_instmem_new,	1897	.imem = nv50_instmem_new,
@@ -1929,7 +1929,7 @@ nv108_chipset = { · 31 unmodified lines
1929	.fb = gk110_fb_new,	1929	.fb = gk110_fb_new,
1930	.fuse = gf100_fuse_new,	1930	.fuse = gf100_fuse_new,
1931	.gpio = gk104_gpio_new,	1931	.gpio = gk104_gpio_new,
1932	.i2c = gk104_i2c_new,	1932	.i2c = gk110_i2c_new,
1933	.ibus = gk104_ibus_new,	1933	.ibus = gk104_ibus_new,
1934	.iccsense = gf100_iccsense_new,	1934	.iccsense = gf100_iccsense_new,
1935	.imem = nv50_instmem_new,	1935	.imem = nv50_instmem_new,
@@ -1967,7 +1967,7 @@ nv117_chipset = { · 31 unmodified lines
1967	.fb = gm107_fb_new,	1967	.fb = gm107_fb_new,
1968	.fuse = gm107_fuse_new,	1968	.fuse = gm107_fuse_new,
1969	.gpio = gk104_gpio_new,	1969	.gpio = gk104_gpio_new,
1970	.i2c = gk104_i2c_new,	1970	.i2c = gk110_i2c_new,
1971	.ibus = gk104_ibus_new,	1971	.ibus = gk104_ibus_new,
1972	.iccsense = gf100_iccsense_new,	1972	.iccsense = gf100_iccsense_new,
1973	.imem = nv50_instmem_new,	1973	.imem = nv50_instmem_new,
@@ -2003,7 +2003,7 @@ nv118_chipset = { · 29 unmodified lines
2003	.fb = gm107_fb_new,	2003	.fb = gm107_fb_new,
2004	.fuse = gm107_fuse_new,	2004	.fuse = gm107_fuse_new,
2005	.gpio = gk104_gpio_new,	2005	.gpio = gk104_gpio_new,
2006	.i2c = gk104_i2c_new,	2006	.i2c = gk110_i2c_new,
2007	.ibus = gk104_ibus_new,	2007	.ibus = gk104_ibus_new,
2008	.iccsense = gf100_iccsense_new,	2008	.iccsense = gf100_iccsense_new,
2009	.imem = nv50_instmem_new,	2009	.imem = nv50_instmem_new,
@@ -2652,6 +2652,61 @@ nv168_chipset = { · 642 unmodified lines
2652	.sec2 = tu102_sec2_new,	2652	.sec2 = tu102_sec2_new,
2653	};	2653	};
2654		2654
		2655	static const struct nvkm_device_chip
		2656	nv170_chipset = {
		2657	.name = "GA100",
		2658	.bar = tu102_bar_new,
		2659	.bios = nvkm_bios_new,
		2660	.devinit = ga100_devinit_new,
		2661	.fb = ga100_fb_new,
		2662	.gpio = gk104_gpio_new,
		2663	.i2c = gm200_i2c_new,
		2664	.ibus = gm200_ibus_new,
		2665	.imem = nv50_instmem_new,
		2666	.mc = ga100_mc_new,
		2667	.mmu = tu102_mmu_new,
		2668	.pci = gp100_pci_new,
		2669	.timer = gk20a_timer_new,
		2670	};
		2671
		2672	static const struct nvkm_device_chip
		2673	nv172_chipset = {
		2674	.name = "GA102",
		2675	.bar = tu102_bar_new,
		2676	.bios = nvkm_bios_new,
		2677	.devinit = ga100_devinit_new,
		2678	.fb = ga102_fb_new,
		2679	.gpio = ga102_gpio_new,
		2680	.i2c = gm200_i2c_new,
		2681	.ibus = gm200_ibus_new,
		2682	.imem = nv50_instmem_new,
		2683	.mc = ga100_mc_new,
		2684	.mmu = tu102_mmu_new,
		2685	.pci = gp100_pci_new,
		2686	.timer = gk20a_timer_new,
		2687	.disp = ga102_disp_new,
		2688	.dma = gv100_dma_new,
		2689	};
		2690
		2691	static const struct nvkm_device_chip
		2692	nv174_chipset = {
		2693	.name = "GA104",
		2694	.bar = tu102_bar_new,
		2695	.bios = nvkm_bios_new,
		2696	.devinit = ga100_devinit_new,
		2697	.fb = ga102_fb_new,
		2698	.gpio = ga102_gpio_new,
		2699	.i2c = gm200_i2c_new,
		2700	.ibus = gm200_ibus_new,
		2701	.imem = nv50_instmem_new,
		2702	.mc = ga100_mc_new,
		2703	.mmu = tu102_mmu_new,
		2704	.pci = gp100_pci_new,
		2705	.timer = gk20a_timer_new,
		2706	.disp = ga102_disp_new,
		2707	.dma = gv100_dma_new,
		2708	};
		2709
2655	static int	2710	static int
2656	nvkm_device_event_ctor(struct nvkm_object object, void data, u32 size,	2711	nvkm_device_event_ctor(struct nvkm_object object, void data, u32 size,
2657	struct nvkm_notify *notify)	2712	struct nvkm_notify *notify)
@@ -3063,6 +3118,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func, · 405 unmodified lines
3063	case 0x130: device->card_type = GP100; break;	3118	case 0x130: device->card_type = GP100; break;
3064	case 0x140: device->card_type = GV100; break;	3119	case 0x140: device->card_type = GV100; break;
3065	case 0x160: device->card_type = TU100; break;	3120	case 0x160: device->card_type = TU100; break;
		3121	case 0x170: device->card_type = GA100; break;
3066	default:	3122	default:
3067	break;	3123	break;
3068	}	3124	}
@@ -3160,10 +3216,23 @@ nvkm_device_ctor(const struct nvkm_device_func *func, · 91 unmodified lines
3160	case 0x166: device->chip = &nv166_chipset; break;	3216	case 0x166: device->chip = &nv166_chipset; break;
3161	case 0x167: device->chip = &nv167_chipset; break;	3217	case 0x167: device->chip = &nv167_chipset; break;
3162	case 0x168: device->chip = &nv168_chipset; break;	3218	case 0x168: device->chip = &nv168_chipset; break;
		3219	case 0x172: device->chip = &nv172_chipset; break;
		3220	case 0x174: device->chip = &nv174_chipset; break;
3163	default:	3221	default:
3164	nvdev_error(device, "unknown chipset (%08x)\n", boot0);	3222	if (nvkm_boolopt(device->cfgopt, "NvEnableUnsupportedChipsets", false)) {
3165	ret = -ENODEV;	3223	switch (device->chipset) {
3166	goto done;	3224	case 0x170: device->chip = &nv170_chipset; break;
		3225	default:
		3226	break;
		3227	}
		3228	}
		3229
		3230	if (!device->chip) {
		3231	nvdev_error(device, "unknown chipset (%08x)\n", boot0);
		3232	ret = -ENODEV;
		3233	goto done;
		3234	}
		3235	break;
3167	}	3236	}
3168		3237
3169	nvdev_info(device, "NVIDIA %s (%08x)\n",	3238	nvdev_info(device, "NVIDIA %s (%08x)\n",

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c+1−0

@@ -176,6 +176,7 @@ nvkm_udevice_info(struct nvkm_udevice udev, void data, u32 size) · 175 unmodified lines
176	case GP100: args->v0.family = NV_DEVICE_INFO_V0_PASCAL; break;	176	case GP100: args->v0.family = NV_DEVICE_INFO_V0_PASCAL; break;
177	case GV100: args->v0.family = NV_DEVICE_INFO_V0_VOLTA; break;	177	case GV100: args->v0.family = NV_DEVICE_INFO_V0_VOLTA; break;
178	case TU100: args->v0.family = NV_DEVICE_INFO_V0_TURING; break;	178	case TU100: args->v0.family = NV_DEVICE_INFO_V0_TURING; break;
		179	case GA100: args->v0.family = NV_DEVICE_INFO_V0_AMPERE; break;
179	default:	180	default:
180	args->v0.family = 0;	181	args->v0.family = 0;
181	break;	182	break;

drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild+3−0

 nvkm-y += nvkm/engine/disp/gp102.o
 nvkm-y += nvkm/engine/disp/gv100.o
 nvkm-y += nvkm/engine/disp/tu102.o
+nvkm-y += nvkm/engine/disp/ga102.o
 nvkm-y += nvkm/engine/disp/vga.o
 nvkm-y += nvkm/engine/disp/head.o
 nvkm-y += nvkm/engine/disp/sorgp100.o
 nvkm-y += nvkm/engine/disp/sorgv100.o
 nvkm-y += nvkm/engine/disp/sortu102.o
+nvkm-y += nvkm/engine/disp/sorga102.o
 nvkm-y += nvkm/engine/disp/outp.o
 nvkm-y += nvkm/engine/disp/dp.o
 nvkm-y += nvkm/engine/disp/rootgp102.o
 nvkm-y += nvkm/engine/disp/rootgv100.o
 nvkm-y += nvkm/engine/disp/roottu102.o
+nvkm-y += nvkm/engine/disp/rootga102.o
 nvkm-y += nvkm/engine/disp/capsgv100.o

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c+27−6

 #include <nvif/event.h>
+/* IED scripts are no longer used by UEFI/RM from Ampere, but have been updated for
+ * the x86 option ROM.  However, the relevant VBIOS table versions weren't modified,
+ * so we're unable to detect this in a nice way.
+ */
+#define AMPERE_IED_HACK(disp) ((disp)->engine.subdev.device->card_type >= GA100)
 struct lt_state {
 	struct nvkm_dp *dp;
 	u8  stat[6];
 		dp->dpcd[DPCD_RC02] &= ~DPCD_RC02_TPS3_SUPPORTED;
 	lt.pc2 = dp->dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED;
+	if (AMPERE_IED_HACK(disp) && (lnkcmp = lt.dp->info.script[0])) {
+		/* Execute BeforeLinkTraining script from DP Info table. */
+		while (ior->dp.bw < nvbios_rd08(bios, lnkcmp))
+			lnkcmp += 3;
+		lnkcmp = nvbios_rd16(bios, lnkcmp + 1);
+		nvbios_init(&dp->outp.disp->engine.subdev, lnkcmp,
+			init.outp = &dp->outp.info;
+			init.or   = ior->id;
+			init.link = ior->asy.link;
+		);
+	}
 	/* Set desired link configuration on the source. */
 	if ((lnkcmp = lt.dp->info.lnkcmp)) {
 		if (dp->version < 0x30) {
 		);
 	}
-	/* Execute BeforeLinkTraining script from DP Info table. */
+	if (!AMPERE_IED_HACK(dp->outp.disp)) {
-	nvbios_init(&dp->outp.disp->engine.subdev, dp->info.script[0],
+		/* Execute BeforeLinkTraining script from DP Info table. */
-		init.outp = &dp->outp.info;
+		nvbios_init(&dp->outp.disp->engine.subdev, dp->info.script[0],
-		init.or   = dp->outp.ior->id;
+			init.outp = &dp->outp.info;
-		init.link = dp->outp.ior->asy.link;
+			init.or   = dp->outp.ior->id;
-	);
+			init.link = dp->outp.ior->asy.link;
+		);
+	}
 }
 static const struct dp_rates {

drivers/gpu/drm/nouveau/nvkm/engine/disp/ga102.c+46−0

@@ -0,0 +1,46 @@
	1	/*
	2	* Copyright 2021 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22	#include "nv50.h"
	23	#include "head.h"
	24	#include "ior.h"
	25	#include "channv50.h"
	26	#include "rootnv50.h"
	27
	28	static const struct nv50_disp_func
	29	ga102_disp = {
	30	.init = tu102_disp_init,
	31	.fini = gv100_disp_fini,
	32	.intr = gv100_disp_intr,
	33	.uevent = &gv100_disp_chan_uevent,
	34	.super = gv100_disp_super,
	35	.root = &ga102_disp_root_oclass,
	36	.wndw = { .cnt = gv100_disp_wndw_cnt },
	37	.head = { .cnt = gv100_head_cnt, .new = gv100_head_new },
	38	.sor = { .cnt = gv100_sor_cnt, .new = ga102_sor_new },
	39	.ramht_size = 0x2000,
	40	};
	41
	42	int
	43	ga102_disp_new(struct nvkm_device device, int index, struct nvkm_disp *pdisp)
	44	{
	45	return nv50_disp_new_(&ga102_disp, device, index, pdisp);
	46	}

drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h+4−0

 void gv100_sor_dp_audio_sym(struct nvkm_ior *, int, u16, u32);
 void gv100_sor_dp_watermark(struct nvkm_ior *, int, u8);
+void tu102_sor_dp_vcpi(struct nvkm_ior *, int, u8, u8, u16, u16);
 void g84_hdmi_ctrl(struct nvkm_ior *, int, bool, u8, u8, u8 *, u8 , u8 *, u8);
 void gt215_hdmi_ctrl(struct nvkm_ior *, int, bool, u8, u8, u8 *, u8 , u8 *, u8);
 void gf119_hdmi_ctrl(struct nvkm_ior *, int, bool, u8, u8, u8 *, u8 , u8 *, u8);
 int gv100_sor_new(struct nvkm_disp *, int);
 int tu102_sor_new(struct nvkm_disp *, int);
+int ga102_sor_new(struct nvkm_disp *, int);
 #endif

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h+2−0

@@ -86,6 +86,8 @@ void gv100_disp_intr(struct nv50_disp *); · 85 unmodified lines
86	void gv100_disp_super(struct work_struct *);	86	void gv100_disp_super(struct work_struct *);
87	int gv100_disp_wndw_cnt(struct nvkm_disp , unsigned long );	87	int gv100_disp_wndw_cnt(struct nvkm_disp , unsigned long );
88		88
		89	int tu102_disp_init(struct nv50_disp *);
		90
89	void nv50_disp_dptmds_war_2(struct nv50_disp , struct dcb_output );	91	void nv50_disp_dptmds_war_2(struct nv50_disp , struct dcb_output );
90	void nv50_disp_dptmds_war_3(struct nv50_disp , struct dcb_output );	92	void nv50_disp_dptmds_war_3(struct nv50_disp , struct dcb_output );
91	void nv50_disp_update_sppll1(struct nv50_disp *);	93	void nv50_disp_update_sppll1(struct nv50_disp *);

drivers/gpu/drm/nouveau/nvkm/engine/disp/rootga102.c+52−0

@@ -0,0 +1,52 @@
	1	/*
	2	* Copyright 2021 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22	#include "rootnv50.h"
	23	#include "channv50.h"
	24
	25	#include <nvif/class.h>
	26
	27	static const struct nv50_disp_root_func
	28	ga102_disp_root = {
	29	.user = {
	30	{{-1,-1,GV100_DISP_CAPS }, gv100_disp_caps_new },
	31	{{0,0,GA102_DISP_CURSOR }, gv100_disp_curs_new },
	32	{{0,0,GA102_DISP_WINDOW_IMM_CHANNEL_DMA}, gv100_disp_wimm_new },
	33	{{0,0,GA102_DISP_CORE_CHANNEL_DMA }, gv100_disp_core_new },
	34	{{0,0,GA102_DISP_WINDOW_CHANNEL_DMA }, gv100_disp_wndw_new },
	35	{}
	36	},
	37	};
	38
	39	static int
	40	ga102_disp_root_new(struct nvkm_disp disp, const struct nvkm_oclass oclass,
	41	void data, u32 size, struct nvkm_object *pobject)
	42	{
	43	return nv50_disp_root_new_(&ga102_disp_root, disp, oclass, data, size, pobject);
	44	}
	45
	46	const struct nvkm_disp_oclass
	47	ga102_disp_root_oclass = {
	48	.base.oclass = GA102_DISP,
	49	.base.minver = -1,
	50	.base.maxver = -1,
	51	.ctor = ga102_disp_root_new,
	52	};

drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.h+1−0

@@ -41,4 +41,5 @@ extern const struct nvkm_disp_oclass gp100_disp_root_oclass; · 40 unmodified lines
41	extern const struct nvkm_disp_oclass gp102_disp_root_oclass;	41	extern const struct nvkm_disp_oclass gp102_disp_root_oclass;
42	extern const struct nvkm_disp_oclass gv100_disp_root_oclass;	42	extern const struct nvkm_disp_oclass gv100_disp_root_oclass;
43	extern const struct nvkm_disp_oclass tu102_disp_root_oclass;	43	extern const struct nvkm_disp_oclass tu102_disp_root_oclass;
		44	extern const struct nvkm_disp_oclass ga102_disp_root_oclass;
44	#endif	45	#endif

drivers/gpu/drm/nouveau/nvkm/engine/disp/sorga102.c+140−0

@@ -0,0 +1,140 @@
	1	/*
	2	* Copyright 2021 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22	#include "ior.h"
	23
	24	#include <subdev/timer.h>
	25
	26	static int
	27	ga102_sor_dp_links(struct nvkm_ior sor, struct nvkm_i2c_aux aux)
	28	{
	29	struct nvkm_device *device = sor->disp->engine.subdev.device;
	30	const u32 soff = nv50_ior_base(sor);
	31	const u32 loff = nv50_sor_link(sor);
	32	u32 dpctrl = 0x00000000;
	33	u32 clksor = 0x00000000;
	34
	35	switch (sor->dp.bw) {
	36	case 0x06: clksor \|= 0x00000000; break;
	37	case 0x0a: clksor \|= 0x00040000; break;
	38	case 0x14: clksor \|= 0x00080000; break;
	39	case 0x1e: clksor \|= 0x000c0000; break;
	40	default:
	41	WARN_ON(1);
	42	return -EINVAL;
	43	}
	44
	45	dpctrl \|= ((1 << sor->dp.nr) - 1) << 16;
	46	if (sor->dp.mst)
	47	dpctrl \|= 0x40000000;
	48	if (sor->dp.ef)
	49	dpctrl \|= 0x00004000;
	50
	51	nvkm_mask(device, 0x612300 + soff, 0x007c0000, clksor);
	52
	53	/XXX/
	54	nvkm_msec(device, 40, NVKM_DELAY);
	55	nvkm_mask(device, 0x612300 + soff, 0x00030000, 0x00010000);
	56	nvkm_mask(device, 0x61c10c + loff, 0x00000003, 0x00000001);
	57
	58	nvkm_mask(device, 0x61c10c + loff, 0x401f4000, dpctrl);
	59	return 0;
	60	}
	61
	62	static void
	63	ga102_sor_clock(struct nvkm_ior *sor)
	64	{
	65	struct nvkm_device *device = sor->disp->engine.subdev.device;
	66	u32 div2 = 0;
	67	if (sor->asy.proto == TMDS) {
	68	if (sor->tmds.high_speed)
	69	div2 = 1;
	70	}
	71	nvkm_wr32(device, 0x00ec08 + (sor->id * 0x10), 0x00000000);
	72	nvkm_wr32(device, 0x00ec04 + (sor->id * 0x10), div2);
	73	}
	74
	75	static const struct nvkm_ior_func
	76	ga102_sor_hda = {
	77	.route = {
	78	.get = gm200_sor_route_get,
	79	.set = gm200_sor_route_set,
	80	},
	81	.state = gv100_sor_state,
	82	.power = nv50_sor_power,
	83	.clock = ga102_sor_clock,
	84	.hdmi = {
	85	.ctrl = gv100_hdmi_ctrl,
	86	.scdc = gm200_hdmi_scdc,
	87	},
	88	.dp = {
	89	.lanes = { 0, 1, 2, 3 },
	90	.links = ga102_sor_dp_links,
	91	.power = g94_sor_dp_power,
	92	.pattern = gm107_sor_dp_pattern,
	93	.drive = gm200_sor_dp_drive,
	94	.vcpi = tu102_sor_dp_vcpi,
	95	.audio = gv100_sor_dp_audio,
	96	.audio_sym = gv100_sor_dp_audio_sym,
	97	.watermark = gv100_sor_dp_watermark,
	98	},
	99	.hda = {
	100	.hpd = gf119_hda_hpd,
	101	.eld = gf119_hda_eld,
	102	.device_entry = gv100_hda_device_entry,
	103	},
	104	};
	105
	106	static const struct nvkm_ior_func
	107	ga102_sor = {
	108	.route = {
	109	.get = gm200_sor_route_get,
	110	.set = gm200_sor_route_set,
	111	},
	112	.state = gv100_sor_state,
	113	.power = nv50_sor_power,
	114	.clock = ga102_sor_clock,
	115	.hdmi = {
	116	.ctrl = gv100_hdmi_ctrl,
	117	.scdc = gm200_hdmi_scdc,
	118	},
	119	.dp = {
	120	.lanes = { 0, 1, 2, 3 },
	121	.links = ga102_sor_dp_links,
	122	.power = g94_sor_dp_power,
	123	.pattern = gm107_sor_dp_pattern,
	124	.drive = gm200_sor_dp_drive,
	125	.vcpi = tu102_sor_dp_vcpi,
	126	.audio = gv100_sor_dp_audio,
	127	.audio_sym = gv100_sor_dp_audio_sym,
	128	.watermark = gv100_sor_dp_watermark,
	129	},
	130	};
	131
	132	int
	133	ga102_sor_new(struct nvkm_disp *disp, int id)
	134	{
	135	struct nvkm_device *device = disp->engine.subdev.device;
	136	u32 hda = nvkm_rd32(device, 0x08a15c);
	137	if (hda & BIT(id))
	138	return nvkm_ior_new_(&ga102_sor_hda, disp, SOR, id);
	139	return nvkm_ior_new_(&ga102_sor, disp, SOR, id);
	140	}

drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c+1−1

@@ -23,7 +23,7 @@ · 22 unmodified lines
23		23
24	#include <subdev/timer.h>	24	#include <subdev/timer.h>
25		25
26	static void	26	void
27	tu102_sor_dp_vcpi(struct nvkm_ior *sor, int head,	27	tu102_sor_dp_vcpi(struct nvkm_ior *sor, int head,
28	u8 slot, u8 slot_nr, u16 pbn, u16 aligned)	28	u8 slot, u8 slot_nr, u16 pbn, u16 aligned)
29	{	29	{

drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c+1−1

@@ -28,7 +28,7 @@ · 27 unmodified lines
28	#include <core/gpuobj.h>	28	#include <core/gpuobj.h>
29	#include <subdev/timer.h>	29	#include <subdev/timer.h>
30		30
31	static int	31	int
32	tu102_disp_init(struct nv50_disp *disp)	32	tu102_disp_init(struct nv50_disp *disp)
33	{	33	{
34	struct nvkm_device *device = disp->base.engine.subdev.device;	34	struct nvkm_device *device = disp->base.engine.subdev.device;

drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c+1−1

@@ -75,7 +75,7 @@ shadow_image(struct nvkm_bios bios, int idx, u32 offset, struct shadow mthd) · 74 unmodified lines
75	nvkm_debug(subdev, "%08x: type %02x, %d bytes\n",	75	nvkm_debug(subdev, "%08x: type %02x, %d bytes\n",
76	image.base, image.type, image.size);	76	image.base, image.type, image.size);
77		77
78	if (!shadow_fetch(bios, mthd, image.size)) {	78	if (!shadow_fetch(bios, mthd, image.base + image.size)) {
79	nvkm_debug(subdev, "%08x: fetch failed\n", image.base);	79	nvkm_debug(subdev, "%08x: fetch failed\n", image.base);
80	return 0;	80	return 0;
81	}	81	}

drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c+3−0

 		return NULL;
 	/* we can't get the bios image pointer without PDISP */
+	if (device->card_type >= GA100)
+		addr = device->chipset == 0x170; /*XXX: find the fuse reg for this */
+	else
 	if (device->card_type >= GM100)
 		addr = nvkm_rd32(device, 0x021c04);
 	else

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/Kbuild+1−0

@@ -15,3 +15,4 @@ nvkm-y += nvkm/subdev/devinit/gm107.o · 14 unmodified lines
15	nvkm-y += nvkm/subdev/devinit/gm200.o	15	nvkm-y += nvkm/subdev/devinit/gm200.o
16	nvkm-y += nvkm/subdev/devinit/gv100.o	16	nvkm-y += nvkm/subdev/devinit/gv100.o
17	nvkm-y += nvkm/subdev/devinit/tu102.o	17	nvkm-y += nvkm/subdev/devinit/tu102.o
		18	nvkm-y += nvkm/subdev/devinit/ga100.o

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ga100.c+76−0

@@ -0,0 +1,76 @@
	1	/*
	2	* Copyright 2021 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22	#include "nv50.h"
	23
	24	#include <subdev/bios.h>
	25	#include <subdev/bios/pll.h>
	26	#include <subdev/clk/pll.h>
	27
	28	static int
	29	ga100_devinit_pll_set(struct nvkm_devinit *init, u32 type, u32 freq)
	30	{
	31	struct nvkm_subdev *subdev = &init->subdev;
	32	struct nvkm_device *device = subdev->device;
	33	struct nvbios_pll info;
	34	int head = type - PLL_VPLL0;
	35	int N, fN, M, P;
	36	int ret;
	37
	38	ret = nvbios_pll_parse(device->bios, type, &info);
	39	if (ret)
	40	return ret;
	41
	42	ret = gt215_pll_calc(subdev, &info, freq, &N, &fN, &M, &P);
	43	if (ret < 0)
	44	return ret;
	45
	46	switch (info.type) {
	47	case PLL_VPLL0:
	48	case PLL_VPLL1:
	49	case PLL_VPLL2:
	50	case PLL_VPLL3:
	51	nvkm_wr32(device, 0x00ef00 + (head * 0x40), 0x02080004);
	52	nvkm_wr32(device, 0x00ef18 + (head * 0x40), (N << 16) \| fN);
	53	nvkm_wr32(device, 0x00ef04 + (head * 0x40), (P << 16) \| M);
	54	nvkm_wr32(device, 0x00e9c0 + (head * 0x04), 0x00000001);
	55	break;
	56	default:
	57	nvkm_warn(subdev, "%08x/%dKhz unimplemented\n", type, freq);
	58	ret = -EINVAL;
	59	break;
	60	}
	61
	62	return ret;
	63	}
	64
	65	static const struct nvkm_devinit_func
	66	ga100_devinit = {
	67	.init = nv50_devinit_init,
	68	.post = tu102_devinit_post,
	69	.pll_set = ga100_devinit_pll_set,
	70	};
	71
	72	int
	73	ga100_devinit_new(struct nvkm_device device, int index, struct nvkm_devinit *pinit)
	74	{
	75	return nv50_devinit_new_(&ga100_devinit, device, index, pinit);
	76	}

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h+1−0

@@ -19,4 +19,5 @@ void nvkm_devinit_ctor(const struct nvkm_devinit_func , struct nvkm_device , · 18 unmodified lines
19	int index, struct nvkm_devinit *);	19	int index, struct nvkm_devinit *);
20		20
21	int nv04_devinit_post(struct nvkm_devinit *, bool);	21	int nv04_devinit_post(struct nvkm_devinit *, bool);
		22	int tu102_devinit_post(struct nvkm_devinit *, bool);
22	#endif	23	#endif

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/tu102.c+1−1

@@ -65,7 +65,7 @@ tu102_devinit_pll_set(struct nvkm_devinit *init, u32 type, u32 freq) · 64 unmodified lines
65	return ret;	65	return ret;
66	}	66	}
67		67
68	static int	68	int
69	tu102_devinit_post(struct nvkm_devinit *base, bool post)	69	tu102_devinit_post(struct nvkm_devinit *base, bool post)
70	{	70	{
71	struct nv50_devinit *init = nv50_devinit(base);	71	struct nv50_devinit *init = nv50_devinit(base);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild+3−0

 nvkm-y += nvkm/subdev/fb/gp102.o
 nvkm-y += nvkm/subdev/fb/gp10b.o
 nvkm-y += nvkm/subdev/fb/gv100.o
+nvkm-y += nvkm/subdev/fb/ga100.o
+nvkm-y += nvkm/subdev/fb/ga102.o
 nvkm-y += nvkm/subdev/fb/ram.o
 nvkm-y += nvkm/subdev/fb/ramnv04.o
 nvkm-y += nvkm/subdev/fb/ramgm107.o
 nvkm-y += nvkm/subdev/fb/ramgm200.o
 nvkm-y += nvkm/subdev/fb/ramgp100.o
+nvkm-y += nvkm/subdev/fb/ramga102.o
 nvkm-y += nvkm/subdev/fb/sddr2.o
 nvkm-y += nvkm/subdev/fb/sddr3.o
 nvkm-y += nvkm/subdev/fb/gddr3.o

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga100.c+40−0

@@ -0,0 +1,40 @@
	1	/*
	2	* Copyright 2021 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22	#include "gf100.h"
	23	#include "ram.h"
	24
	25	static const struct nvkm_fb_func
	26	ga100_fb = {
	27	.dtor = gf100_fb_dtor,
	28	.oneinit = gf100_fb_oneinit,
	29	.init = gp100_fb_init,
	30	.init_page = gv100_fb_init_page,
	31	.init_unkn = gp100_fb_init_unkn,
	32	.ram_new = gp100_ram_new,
	33	.default_bigpage = 16,
	34	};
	35
	36	int
	37	ga100_fb_new(struct nvkm_device device, int index, struct nvkm_fb *pfb)
	38	{
	39	return gp102_fb_new_(&ga100_fb, device, index, pfb);
	40	}

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga102.c+40−0

@@ -0,0 +1,40 @@
	1	/*
	2	* Copyright 2021 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22	#include "gf100.h"
	23	#include "ram.h"
	24
	25	static const struct nvkm_fb_func
	26	ga102_fb = {
	27	.dtor = gf100_fb_dtor,
	28	.oneinit = gf100_fb_oneinit,
	29	.init = gp100_fb_init,
	30	.init_page = gv100_fb_init_page,
	31	.init_unkn = gp100_fb_init_unkn,
	32	.ram_new = ga102_ram_new,
	33	.default_bigpage = 16,
	34	};
	35
	36	int
	37	ga102_fb_new(struct nvkm_device device, int index, struct nvkm_fb *pfb)
	38	{
	39	return gp102_fb_new_(&ga102_fb, device, index, pfb);
	40	}

drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.c+1−1

@@ -22,7 +22,7 @@ · 21 unmodified lines
22	#include "gf100.h"	22	#include "gf100.h"
23	#include "ram.h"	23	#include "ram.h"
24		24
25	static int	25	int
26	gv100_fb_init_page(struct nvkm_fb *fb)	26	gv100_fb_init_page(struct nvkm_fb *fb)
27	{	27	{
28	return (fb->page == 16) ? 0 : -EINVAL;	28	return (fb->page == 16) ? 0 : -EINVAL;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h+2−0

@@ -82,4 +82,6 @@ int gp102_fb_new_(const struct nvkm_fb_func , struct nvkm_device , int, · 81 unmodified lines
82	struct nvkm_fb **);	82	struct nvkm_fb **);
83	bool gp102_fb_vpr_scrub_required(struct nvkm_fb *);	83	bool gp102_fb_vpr_scrub_required(struct nvkm_fb *);
84	int gp102_fb_vpr_scrub(struct nvkm_fb *);	84	int gp102_fb_vpr_scrub(struct nvkm_fb *);
		85
		86	int gv100_fb_init_page(struct nvkm_fb *);
85	#endif	87	#endif

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h+1−0

@@ -70,4 +70,5 @@ int gk104_ram_new(struct nvkm_fb , struct nvkm_ram *); · 69 unmodified lines
70	int gm107_ram_new(struct nvkm_fb , struct nvkm_ram *);	70	int gm107_ram_new(struct nvkm_fb , struct nvkm_ram *);
71	int gm200_ram_new(struct nvkm_fb , struct nvkm_ram *);	71	int gm200_ram_new(struct nvkm_fb , struct nvkm_ram *);
72	int gp100_ram_new(struct nvkm_fb , struct nvkm_ram *);	72	int gp100_ram_new(struct nvkm_fb , struct nvkm_ram *);
		73	int ga102_ram_new(struct nvkm_fb , struct nvkm_ram *);
73	#endif	74	#endif

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramga102.c+40−0

@@ -0,0 +1,40 @@
	1	/*
	2	* Copyright 2021 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22	#include "ram.h"
	23
	24	#include <subdev/bios.h>
	25	#include <subdev/bios/init.h>
	26	#include <subdev/bios/rammap.h>
	27
	28	static const struct nvkm_ram_func
	29	ga102_ram = {
	30	};
	31
	32	int
	33	ga102_ram_new(struct nvkm_fb fb, struct nvkm_ram *pram)
	34	{
	35	struct nvkm_device *device = fb->subdev.device;
	36	enum nvkm_ram_type type = nvkm_fb_bios_memtype(device->bios);
	37	u32 size = nvkm_rd32(device, 0x1183a4);
	38
	39	return nvkm_ram_new_(&ga102_ram, fb, type, (u64)size << 20, pram);
	40	}

drivers/gpu/drm/nouveau/nvkm/subdev/gpio/Kbuild+1−0

@@ -5,3 +5,4 @@ nvkm-y += nvkm/subdev/gpio/nv50.o · 4 unmodified lines
5	nvkm-y += nvkm/subdev/gpio/g94.o	5	nvkm-y += nvkm/subdev/gpio/g94.o
6	nvkm-y += nvkm/subdev/gpio/gf119.o	6	nvkm-y += nvkm/subdev/gpio/gf119.o
7	nvkm-y += nvkm/subdev/gpio/gk104.o	7	nvkm-y += nvkm/subdev/gpio/gk104.o
		8	nvkm-y += nvkm/subdev/gpio/ga102.o

drivers/gpu/drm/nouveau/nvkm/subdev/gpio/ga102.c+118−0

@@ -0,0 +1,118 @@
	1	/*
	2	* Copyright 2021 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22	#include "priv.h"
	23
	24	static void
	25	ga102_gpio_reset(struct nvkm_gpio *gpio, u8 match)
	26	{
	27	struct nvkm_device *device = gpio->subdev.device;
	28	struct nvkm_bios *bios = device->bios;
	29	u8 ver, len;
	30	u16 entry;
	31	int ent = -1;
	32
	33	while ((entry = dcb_gpio_entry(bios, 0, ++ent, &ver, &len))) {
	34	u32 data = nvbios_rd32(bios, entry);
	35	u8 line = (data & 0x0000003f);
	36	u8 defs = !!(data & 0x00000080);
	37	u8 func = (data & 0x0000ff00) >> 8;
	38	u8 unk0 = (data & 0x00ff0000) >> 16;
	39	u8 unk1 = (data & 0x1f000000) >> 24;
	40
	41	if ( func == DCB_GPIO_UNUSED \|\|
	42	(match != DCB_GPIO_UNUSED && match != func))
	43	continue;
	44
	45	nvkm_gpio_set(gpio, 0, func, line, defs);
	46
	47	nvkm_mask(device, 0x021200 + (line * 4), 0xff, unk0);
	48	if (unk1--)
	49	nvkm_mask(device, 0x00d740 + (unk1 * 4), 0xff, line);
	50	}
	51	}
	52
	53	static int
	54	ga102_gpio_drive(struct nvkm_gpio *gpio, int line, int dir, int out)
	55	{
	56	struct nvkm_device *device = gpio->subdev.device;
	57	u32 data = ((dir ^ 1) << 13) \| (out << 12);
	58	nvkm_mask(device, 0x021200 + (line * 4), 0x00003000, data);
	59	nvkm_mask(device, 0x00d604, 0x00000001, 0x00000001); /* update? */
	60	return 0;
	61	}
	62
	63	static int
	64	ga102_gpio_sense(struct nvkm_gpio *gpio, int line)
	65	{
	66	struct nvkm_device *device = gpio->subdev.device;
	67	return !!(nvkm_rd32(device, 0x021200 + (line * 4)) & 0x00004000);
	68	}
	69
	70	static void
	71	ga102_gpio_intr_stat(struct nvkm_gpio gpio, u32 hi, u32 *lo)
	72	{
	73	struct nvkm_device *device = gpio->subdev.device;
	74	u32 intr0 = nvkm_rd32(device, 0x021640);
	75	u32 intr1 = nvkm_rd32(device, 0x02164c);
	76	u32 stat0 = nvkm_rd32(device, 0x021648) & intr0;
	77	u32 stat1 = nvkm_rd32(device, 0x021654) & intr1;
	78	*lo = (stat1 & 0xffff0000) \| (stat0 >> 16);
	79	*hi = (stat1 << 16) \| (stat0 & 0x0000ffff);
	80	nvkm_wr32(device, 0x021640, intr0);
	81	nvkm_wr32(device, 0x02164c, intr1);
	82	}
	83
	84	static void
	85	ga102_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data)
	86	{
	87	struct nvkm_device *device = gpio->subdev.device;
	88	u32 inte0 = nvkm_rd32(device, 0x021648);
	89	u32 inte1 = nvkm_rd32(device, 0x021654);
	90	if (type & NVKM_GPIO_LO)
	91	inte0 = (inte0 & ~(mask << 16)) \| (data << 16);
	92	if (type & NVKM_GPIO_HI)
	93	inte0 = (inte0 & ~(mask & 0xffff)) \| (data & 0xffff);
	94	mask >>= 16;
	95	data >>= 16;
	96	if (type & NVKM_GPIO_LO)
	97	inte1 = (inte1 & ~(mask << 16)) \| (data << 16);
	98	if (type & NVKM_GPIO_HI)
	99	inte1 = (inte1 & ~mask) \| data;
	100	nvkm_wr32(device, 0x021648, inte0);
	101	nvkm_wr32(device, 0x021654, inte1);
	102	}
	103
	104	static const struct nvkm_gpio_func
	105	ga102_gpio = {
	106	.lines = 32,
	107	.intr_stat = ga102_gpio_intr_stat,
	108	.intr_mask = ga102_gpio_intr_mask,
	109	.drive = ga102_gpio_drive,
	110	.sense = ga102_gpio_sense,
	111	.reset = ga102_gpio_reset,
	112	};
	113
	114	int
	115	ga102_gpio_new(struct nvkm_device device, int index, struct nvkm_gpio *pgpio)
	116	{
	117	return nvkm_gpio_new_(&ga102_gpio, device, index, pgpio);
	118	}

drivers/gpu/drm/nouveau/nvkm/subdev/i2c/Kbuild+1−0

@@ -7,6 +7,7 @@ nvkm-y += nvkm/subdev/i2c/g94.o · 6 unmodified lines
7	nvkm-y += nvkm/subdev/i2c/gf117.o	7	nvkm-y += nvkm/subdev/i2c/gf117.o
8	nvkm-y += nvkm/subdev/i2c/gf119.o	8	nvkm-y += nvkm/subdev/i2c/gf119.o
9	nvkm-y += nvkm/subdev/i2c/gk104.o	9	nvkm-y += nvkm/subdev/i2c/gk104.o
		10	nvkm-y += nvkm/subdev/i2c/gk110.o
10	nvkm-y += nvkm/subdev/i2c/gm200.o	11	nvkm-y += nvkm/subdev/i2c/gm200.o
11		12
12	nvkm-y += nvkm/subdev/i2c/pad.o	13	nvkm-y += nvkm/subdev/i2c/pad.o

drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.h+7−0

@@ -3,6 +3,13 @@ · 2 unmodified lines
3	#define __NVKM_I2C_AUX_H__	3	#define __NVKM_I2C_AUX_H__
4	#include "pad.h"	4	#include "pad.h"
5		5
		6	static inline void
		7	nvkm_i2c_aux_autodpcd(struct nvkm_i2c *i2c, int aux, bool enable)
		8	{
		9	if (i2c->func->aux_autodpcd)
		10	i2c->func->aux_autodpcd(i2c, aux, false);
		11	}
		12
6	struct nvkm_i2c_aux_func {	13	struct nvkm_i2c_aux_func {
7	bool address_only;	14	bool address_only;
8	int (xfer)(struct nvkm_i2c_aux , bool retry, u8 type,	15	int (xfer)(struct nvkm_i2c_aux , bool retry, u8 type,

drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c+7−3

@@ -77,7 +77,8 @@ g94_i2c_aux_xfer(struct nvkm_i2c_aux *obj, bool retry, · 76 unmodified lines
77	u8 type, u32 addr, u8 data, u8 size)	77	u8 type, u32 addr, u8 data, u8 size)
78	{	78	{
79	struct g94_i2c_aux *aux = g94_i2c_aux(obj);	79	struct g94_i2c_aux *aux = g94_i2c_aux(obj);
80	struct nvkm_device *device = aux->base.pad->i2c->subdev.device;	80	struct nvkm_i2c *i2c = aux->base.pad->i2c;
		81	struct nvkm_device *device = i2c->subdev.device;
81	const u32 base = aux->ch * 0x50;	82	const u32 base = aux->ch * 0x50;
82	u32 ctrl, stat, timeout, retries = 0;	83	u32 ctrl, stat, timeout, retries = 0;
83	u32 xbuf[4] = {};	84	u32 xbuf[4] = {};
@@ -96,6 +97,8 @@ g94_i2c_aux_xfer(struct nvkm_i2c_aux *obj, bool retry, · 12 unmodified lines
96	goto out;	97	goto out;
97	}	98	}
98		99
		100	nvkm_i2c_aux_autodpcd(i2c, aux->ch, false);
		101
99	if (!(type & 1)) {	102	if (!(type & 1)) {
100	memcpy(xbuf, data, *size);	103	memcpy(xbuf, data, *size);
101	for (i = 0; i < 16; i += 4) {	104	for (i = 0; i < 16; i += 4) {
@@ -128,7 +131,7 @@ g94_i2c_aux_xfer(struct nvkm_i2c_aux *obj, bool retry, · 26 unmodified lines
128	if (!timeout--) {	131	if (!timeout--) {
129	AUX_ERR(&aux->base, "timeout %08x", ctrl);	132	AUX_ERR(&aux->base, "timeout %08x", ctrl);
130	ret = -EIO;	133	ret = -EIO;
131	goto out;	134	goto out_err;
132	}	135	}
133	} while (ctrl & 0x00010000);	136	} while (ctrl & 0x00010000);
134	ret = 0;	137	ret = 0;
@@ -154,7 +157,8 @@ g94_i2c_aux_xfer(struct nvkm_i2c_aux *obj, bool retry, · 19 unmodified lines
154	memcpy(data, xbuf, *size);	157	memcpy(data, xbuf, *size);
155	*size = stat & 0x0000001f;	158	*size = stat & 0x0000001f;
156	}	159	}
157		160	out_err:
		161	nvkm_i2c_aux_autodpcd(i2c, aux->ch, true);
158	out:	162	out:
159	g94_i2c_aux_fini(aux);	163	g94_i2c_aux_fini(aux);
160	return ret < 0 ? ret : (stat & 0x000f0000) >> 16;	164	return ret < 0 ? ret : (stat & 0x000f0000) >> 16;

drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c+11−6

 gm200_i2c_aux_fini(struct gm200_i2c_aux *aux)
 {
 	struct nvkm_device *device = aux->base.pad->i2c->subdev.device;
-	nvkm_mask(device, 0x00d954 + (aux->ch * 0x50), 0x00310000, 0x00000000);
+	nvkm_mask(device, 0x00d954 + (aux->ch * 0x50), 0x00710000, 0x00000000);
 }
 static int
 			AUX_ERR(&aux->base, "begin idle timeout %08x", ctrl);
 			return -EBUSY;
 		}
-	} while (ctrl & 0x03010000);
+	} while (ctrl & 0x07010000);
 	/* set some magic, and wait up to 1ms for it to appear */
-	nvkm_mask(device, 0x00d954 + (aux->ch * 0x50), 0x00300000, ureq);
+	nvkm_mask(device, 0x00d954 + (aux->ch * 0x50), 0x00700000, ureq);
 	timeout = 1000;
 	do {
 		ctrl = nvkm_rd32(device, 0x00d954 + (aux->ch * 0x50));
 			gm200_i2c_aux_fini(aux);
 			return -EBUSY;
 		}
-	} while ((ctrl & 0x03000000) != urep);
+	} while ((ctrl & 0x07000000) != urep);
 	return 0;
 }
 		   u8 type, u32 addr, u8 *data, u8 *size)
 {
 	struct gm200_i2c_aux *aux = gm200_i2c_aux(obj);
-	struct nvkm_device *device = aux->base.pad->i2c->subdev.device;
+	struct nvkm_i2c *i2c = aux->base.pad->i2c;
+	struct nvkm_device *device = i2c->subdev.device;
 	const u32 base = aux->ch * 0x50;
 	u32 ctrl, stat, timeout, retries = 0;
 	u32 xbuf[4] = {};
 		goto out;
 	}
+	nvkm_i2c_aux_autodpcd(i2c, aux->ch, false);
 	if (!(type & 1)) {
 		memcpy(xbuf, data, *size);
 		for (i = 0; i < 16; i += 4) {
 			if (!timeout--) {
 				AUX_ERR(&aux->base, "timeout %08x", ctrl);
 				ret = -EIO;
-				goto out;
+				goto out_err;
 			}
 		} while (ctrl & 0x00010000);
 		ret = 0;
 		*size = stat & 0x0000001f;
 	}
+out_err:
+	nvkm_i2c_aux_autodpcd(i2c, aux->ch, true);
 out:
 	gm200_i2c_aux_fini(aux);
 	return ret < 0 ? ret : (stat & 0x000f0000) >> 16;

drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk110.c+45−0

@@ -0,0 +1,45 @@
	1	/*
	2	* Copyright 2021 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22	#include "priv.h"
	23	#include "pad.h"
	24
	25	static void
	26	gk110_aux_autodpcd(struct nvkm_i2c *i2c, int aux, bool enable)
	27	{
	28	nvkm_mask(i2c->subdev.device, 0x00e4f8 + (aux * 0x50), 0x00010000, enable << 16);
	29	}
	30
	31	static const struct nvkm_i2c_func
	32	gk110_i2c = {
	33	.pad_x_new = gf119_i2c_pad_x_new,
	34	.pad_s_new = gf119_i2c_pad_s_new,
	35	.aux = 4,
	36	.aux_stat = gk104_aux_stat,
	37	.aux_mask = gk104_aux_mask,
	38	.aux_autodpcd = gk110_aux_autodpcd,
	39	};
	40
	41	int
	42	gk110_i2c_new(struct nvkm_device device, int index, struct nvkm_i2c *pi2c)
	43	{
	44	return nvkm_i2c_new_(&gk110_i2c, device, index, pi2c);
	45	}

drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm200.c+7−0

 #include "priv.h"
 #include "pad.h"
+static void
+gm200_aux_autodpcd(struct nvkm_i2c *i2c, int aux, bool enable)
+{
+	nvkm_mask(i2c->subdev.device, 0x00d968 + (aux * 0x50), 0x00010000, enable << 16);
+}
 static const struct nvkm_i2c_func
 gm200_i2c = {
 	.pad_x_new = gf119_i2c_pad_x_new,
 	.aux = 8,
 	.aux_stat = gk104_aux_stat,
 	.aux_mask = gk104_aux_mask,
+	.aux_autodpcd = gm200_aux_autodpcd,
 };
 int

drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.h+1−1

@@ -1,7 +1,7 @@
1	/* SPDX-License-Identifier: MIT */	1	/* SPDX-License-Identifier: MIT */
2	#ifndef __NVKM_I2C_PAD_H__	2	#ifndef __NVKM_I2C_PAD_H__
3	#define __NVKM_I2C_PAD_H__	3	#define __NVKM_I2C_PAD_H__
4	#include <subdev/i2c.h>	4	#include "priv.h"
5		5
6	struct nvkm_i2c_pad {	6	struct nvkm_i2c_pad {
7	const struct nvkm_i2c_pad_func *func;	7	const struct nvkm_i2c_pad_func *func;

drivers/gpu/drm/nouveau/nvkm/subdev/i2c/priv.h+4−0

 	/* mask on/off interrupt types for a given set of auxch
 	 */
 	void (*aux_mask)(struct nvkm_i2c *, u32, u32, u32);
+	/* enable/disable HW-initiated DPCD reads
+	 */
+	void (*aux_autodpcd)(struct nvkm_i2c *, int aux, bool enable);
 };
 void g94_aux_stat(struct nvkm_i2c *, u32 *, u32 *, u32 *, u32 *);

drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf100.c+7−3

  * Authors: Ben Skeggs
  */
 #include "priv.h"
+#include <subdev/timer.h>
 static void
 gf100_ibus_intr_hub(struct nvkm_subdev *ibus, int i)
 	u32 data = nvkm_rd32(device, 0x122124 + (i * 0x0400));
 	u32 stat = nvkm_rd32(device, 0x122128 + (i * 0x0400));
 	nvkm_debug(ibus, "HUB%d: %06x %08x (%08x)\n", i, addr, data, stat);
-	nvkm_mask(device, 0x122128 + (i * 0x0400), 0x00000200, 0x00000000);
 }
 static void
 	u32 data = nvkm_rd32(device, 0x124124 + (i * 0x0400));
 	u32 stat = nvkm_rd32(device, 0x124128 + (i * 0x0400));
 	nvkm_debug(ibus, "ROP%d: %06x %08x (%08x)\n", i, addr, data, stat);
-	nvkm_mask(device, 0x124128 + (i * 0x0400), 0x00000200, 0x00000000);
 }
 static void
 	u32 data = nvkm_rd32(device, 0x128124 + (i * 0x0400));
 	u32 stat = nvkm_rd32(device, 0x128128 + (i * 0x0400));
 	nvkm_debug(ibus, "GPC%d: %06x %08x (%08x)\n", i, addr, data, stat);
-	nvkm_mask(device, 0x128128 + (i * 0x0400), 0x00000200, 0x00000000);
 }
 void
 			intr1 &= ~stat;
 		}
 	}
+	nvkm_mask(device, 0x121c4c, 0x0000003f, 0x00000002);
+	nvkm_msec(device, 2000,
+		if (!(nvkm_rd32(device, 0x121c4c) & 0x0000003f))
+			break;
+	);
 }
 static int

drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk104.c+7−3

  * Authors: Ben Skeggs
  */
 #include "priv.h"
+#include <subdev/timer.h>
 static void
 gk104_ibus_intr_hub(struct nvkm_subdev *ibus, int i)
 	u32 data = nvkm_rd32(device, 0x122124 + (i * 0x0800));
 	u32 stat = nvkm_rd32(device, 0x122128 + (i * 0x0800));
 	nvkm_debug(ibus, "HUB%d: %06x %08x (%08x)\n", i, addr, data, stat);
-	nvkm_mask(device, 0x122128 + (i * 0x0800), 0x00000200, 0x00000000);
 }
 static void
 	u32 data = nvkm_rd32(device, 0x124124 + (i * 0x0800));
 	u32 stat = nvkm_rd32(device, 0x124128 + (i * 0x0800));
 	nvkm_debug(ibus, "ROP%d: %06x %08x (%08x)\n", i, addr, data, stat);
-	nvkm_mask(device, 0x124128 + (i * 0x0800), 0x00000200, 0x00000000);
 }
 static void
 	u32 data = nvkm_rd32(device, 0x128124 + (i * 0x0800));
 	u32 stat = nvkm_rd32(device, 0x128128 + (i * 0x0800));
 	nvkm_debug(ibus, "GPC%d: %06x %08x (%08x)\n", i, addr, data, stat);
-	nvkm_mask(device, 0x128128 + (i * 0x0800), 0x00000200, 0x00000000);
 }
 void
 			intr1 &= ~stat;
 		}
 	}
+	nvkm_mask(device, 0x12004c, 0x0000003f, 0x00000002);
+	nvkm_msec(device, 2000,
+		if (!(nvkm_rd32(device, 0x12004c) & 0x0000003f))
+			break;
+	);
 }
 static int

drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild+1−0

@@ -14,3 +14,4 @@ nvkm-y += nvkm/subdev/mc/gk20a.o · 13 unmodified lines
14	nvkm-y += nvkm/subdev/mc/gp100.o	14	nvkm-y += nvkm/subdev/mc/gp100.o
15	nvkm-y += nvkm/subdev/mc/gp10b.o	15	nvkm-y += nvkm/subdev/mc/gp10b.o
16	nvkm-y += nvkm/subdev/mc/tu102.o	16	nvkm-y += nvkm/subdev/mc/tu102.o
		17	nvkm-y += nvkm/subdev/mc/ga100.o

drivers/gpu/drm/nouveau/nvkm/subdev/mc/ga100.c+74−0

@@ -0,0 +1,74 @@
	1	/*
	2	* Copyright 2021 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22	#include "priv.h"
	23
	24	static void
	25	ga100_mc_intr_unarm(struct nvkm_mc *mc)
	26	{
	27	nvkm_wr32(mc->subdev.device, 0xb81610, 0x00000004);
	28	}
	29
	30	static void
	31	ga100_mc_intr_rearm(struct nvkm_mc *mc)
	32	{
	33	nvkm_wr32(mc->subdev.device, 0xb81608, 0x00000004);
	34	}
	35
	36	static void
	37	ga100_mc_intr_mask(struct nvkm_mc *mc, u32 mask, u32 intr)
	38	{
	39	nvkm_wr32(mc->subdev.device, 0xb81210, mask & intr );
	40	nvkm_wr32(mc->subdev.device, 0xb81410, mask & ~(mask & intr));
	41	}
	42
	43	static u32
	44	ga100_mc_intr_stat(struct nvkm_mc *mc)
	45	{
	46	u32 intr_top = nvkm_rd32(mc->subdev.device, 0xb81600), intr = 0x00000000;
	47	if (intr_top & 0x00000004)
	48	intr = nvkm_mask(mc->subdev.device, 0xb81010, 0x00000000, 0x00000000);
	49	return intr;
	50	}
	51
	52	static void
	53	ga100_mc_init(struct nvkm_mc *mc)
	54	{
	55	nv50_mc_init(mc);
	56	nvkm_wr32(mc->subdev.device, 0xb81210, 0xffffffff);
	57	}
	58
	59	static const struct nvkm_mc_func
	60	ga100_mc = {
	61	.init = ga100_mc_init,
	62	.intr = gp100_mc_intr,
	63	.intr_unarm = ga100_mc_intr_unarm,
	64	.intr_rearm = ga100_mc_intr_rearm,
	65	.intr_mask = ga100_mc_intr_mask,
	66	.intr_stat = ga100_mc_intr_stat,
	67	.reset = gk104_mc_reset,
	68	};
	69
	70	int
	71	ga100_mc_new(struct nvkm_device device, int index, struct nvkm_mc *pmc)
	72	{
	73	return nvkm_mc_new_(&ga100_mc, device, index, pmc);
	74	}

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c+3−3

@@ -316,9 +316,9 @@ nvkm_mmu_vram(struct nvkm_mmu *mmu) · 315 unmodified lines
316	{	316	{
317	struct nvkm_device *device = mmu->subdev.device;	317	struct nvkm_device *device = mmu->subdev.device;
318	struct nvkm_mm *mm = &device->fb->ram->vram;	318	struct nvkm_mm *mm = &device->fb->ram->vram;
319	const u32 sizeN = nvkm_mm_heap_size(mm, NVKM_RAM_MM_NORMAL);	319	const u64 sizeN = nvkm_mm_heap_size(mm, NVKM_RAM_MM_NORMAL);
320	const u32 sizeU = nvkm_mm_heap_size(mm, NVKM_RAM_MM_NOMAP);	320	const u64 sizeU = nvkm_mm_heap_size(mm, NVKM_RAM_MM_NOMAP);
321	const u32 sizeM = nvkm_mm_heap_size(mm, NVKM_RAM_MM_MIXED);	321	const u64 sizeM = nvkm_mm_heap_size(mm, NVKM_RAM_MM_MIXED);
322	u8 type = NVKM_MEM_KIND * !!mmu->func->kind;	322	u8 type = NVKM_MEM_KIND * !!mmu->func->kind;
323	u8 heap = NVKM_MEM_VRAM;	323	u8 heap = NVKM_MEM_VRAM;
324	int heapM, heapN, heapU;	324	int heapM, heapN, heapU;

drivers/gpu/drm/ttm/ttm_pool.c+11−11

@@ -66,7 +66,7 @@ static struct ttm_pool_type global_uncached[MAX_ORDER]; · 65 unmodified lines
66	static struct ttm_pool_type global_dma32_write_combined[MAX_ORDER];	66	static struct ttm_pool_type global_dma32_write_combined[MAX_ORDER];
67	static struct ttm_pool_type global_dma32_uncached[MAX_ORDER];	67	static struct ttm_pool_type global_dma32_uncached[MAX_ORDER];
68		68
69	static spinlock_t shrinker_lock;	69	static struct mutex shrinker_lock;
70	static struct list_head shrinker_list;	70	static struct list_head shrinker_list;
71	static struct shrinker mm_shrinker;	71	static struct shrinker mm_shrinker;
72		72
@@ -190,7 +190,7 @@ static int ttm_pool_map(struct ttm_pool *pool, unsigned int order, · 117 unmodified lines
190	size_t size = (1ULL << order) * PAGE_SIZE;	190	size_t size = (1ULL << order) * PAGE_SIZE;
191		191
192	addr = dma_map_page(pool->dev, p, 0, size, DMA_BIDIRECTIONAL);	192	addr = dma_map_page(pool->dev, p, 0, size, DMA_BIDIRECTIONAL);
193	if (dma_mapping_error(pool->dev, **dma_addr))	193	if (dma_mapping_error(pool->dev, addr))
194	return -EFAULT;	194	return -EFAULT;
195	}	195	}
196		196
@@ -249,9 +249,9 @@ static void ttm_pool_type_init(struct ttm_pool_type pt, struct ttm_pool pool, · 52 unmodified lines
249	spin_lock_init(&pt->lock);	249	spin_lock_init(&pt->lock);
250	INIT_LIST_HEAD(&pt->pages);	250	INIT_LIST_HEAD(&pt->pages);
251		251
252	spin_lock(&shrinker_lock);	252	mutex_lock(&shrinker_lock);
253	list_add_tail(&pt->shrinker_list, &shrinker_list);	253	list_add_tail(&pt->shrinker_list, &shrinker_list);
254	spin_unlock(&shrinker_lock);	254	mutex_unlock(&shrinker_lock);
255	}	255	}
256		256
257	/* Remove a pool_type from the global shrinker list and free all pages */	257	/* Remove a pool_type from the global shrinker list and free all pages */
@@ -259,9 +259,9 @@ static void ttm_pool_type_fini(struct ttm_pool_type *pt) · 1 unmodified line
259	{	259	{
260	struct page p, tmp;	260	struct page p, tmp;
261		261
262	spin_lock(&shrinker_lock);	262	mutex_lock(&shrinker_lock);
263	list_del(&pt->shrinker_list);	263	list_del(&pt->shrinker_list);
264	spin_unlock(&shrinker_lock);	264	mutex_unlock(&shrinker_lock);
265		265
266	list_for_each_entry_safe(p, tmp, &pt->pages, lru)	266	list_for_each_entry_safe(p, tmp, &pt->pages, lru)
267	ttm_pool_free_page(pt->pool, pt->caching, pt->order, p);	267	ttm_pool_free_page(pt->pool, pt->caching, pt->order, p);
@@ -302,7 +302,7 @@ static unsigned int ttm_pool_shrink(void) · 34 unmodified lines
302	unsigned int num_freed;	302	unsigned int num_freed;
303	struct page *p;	303	struct page *p;
304		304
305	spin_lock(&shrinker_lock);	305	mutex_lock(&shrinker_lock);
306	pt = list_first_entry(&shrinker_list, typeof(*pt), shrinker_list);	306	pt = list_first_entry(&shrinker_list, typeof(*pt), shrinker_list);
307		307
308	p = ttm_pool_type_take(pt);	308	p = ttm_pool_type_take(pt);
@@ -314,7 +314,7 @@ static unsigned int ttm_pool_shrink(void) · 5 unmodified lines
314	}	314	}
315		315
316	list_move_tail(&pt->shrinker_list, &shrinker_list);	316	list_move_tail(&pt->shrinker_list, &shrinker_list);
317	spin_unlock(&shrinker_lock);	317	mutex_unlock(&shrinker_lock);
318		318
319	return num_freed;	319	return num_freed;
320	}	320	}
@@ -564,7 +564,7 @@ int ttm_pool_debugfs(struct ttm_pool pool, struct seq_file m) · 243 unmodified lines
564	{	564	{
565	unsigned int i;	565	unsigned int i;
566		566
567	spin_lock(&shrinker_lock);	567	mutex_lock(&shrinker_lock);
568		568
569	seq_puts(m, "\t ");	569	seq_puts(m, "\t ");
570	for (i = 0; i < MAX_ORDER; ++i)	570	for (i = 0; i < MAX_ORDER; ++i)
@@ -600,7 +600,7 @@ int ttm_pool_debugfs(struct ttm_pool pool, struct seq_file m) · 29 unmodified lines
600	seq_printf(m, "\ntotal\t: %8lu of %8lu\n",	600	seq_printf(m, "\ntotal\t: %8lu of %8lu\n",
601	atomic_long_read(&allocated_pages), page_pool_size);	601	atomic_long_read(&allocated_pages), page_pool_size);
602		602
603	spin_unlock(&shrinker_lock);	603	mutex_unlock(&shrinker_lock);
604		604
605	return 0;	605	return 0;
606	}	606	}
@@ -644,7 +644,7 @@ int ttm_pool_mgr_init(unsigned long num_pages) · 37 unmodified lines
644	if (!page_pool_size)	644	if (!page_pool_size)
645	page_pool_size = num_pages;	645	page_pool_size = num_pages;
646		646
647	spin_lock_init(&shrinker_lock);	647	mutex_init(&shrinker_lock);
648	INIT_LIST_HEAD(&shrinker_list);	648	INIT_LIST_HEAD(&shrinker_list);
649		649
650	for (i = 0; i < MAX_ORDER; ++i) {	650	for (i = 0; i < MAX_ORDER; ++i) {

drivers/infiniband/core/cma_configfs.c+3−1

@@ -131,8 +131,10 @@ static ssize_t default_roce_mode_store(struct config_item *item, · 130 unmodified lines
131	return ret;	131	return ret;
132		132
133	gid_type = ib_cache_gid_parse_type_str(buf);	133	gid_type = ib_cache_gid_parse_type_str(buf);
134	if (gid_type < 0)	134	if (gid_type < 0) {
		135	cma_configfs_params_put(cma_dev);
135	return -EINVAL;	136	return -EINVAL;
		137	}
136		138
137	ret = cma_set_default_gid_type(cma_dev, group->port_num, gid_type);	139	ret = cma_set_default_gid_type(cma_dev, group->port_num, gid_type);
138		140

drivers/infiniband/core/restrack.c+1−0

@@ -254,6 +254,7 @@ void rdma_restrack_add(struct rdma_restrack_entry *res) · 253 unmodified lines
254	} else {	254	} else {
255	ret = xa_alloc_cyclic(&rt->xa, &res->id, res, xa_limit_32b,	255	ret = xa_alloc_cyclic(&rt->xa, &res->id, res, xa_limit_32b,
256	&rt->next_id, GFP_KERNEL);	256	&rt->next_id, GFP_KERNEL);
		257	ret = (ret < 0) ? ret : 0;
257	}	258	}
258		259
259	out:	260	out:

drivers/infiniband/core/ucma.c+72−63

@@ -95,8 +95,6 @@ struct ucma_context { · 94 unmodified lines
95	u64 uid;	95	u64 uid;
96		96
97	struct list_head list;	97	struct list_head list;
98	/* sync between removal event and id destroy, protected by file mut */
99	int destroying;
100	struct work_struct close_work;	98	struct work_struct close_work;
101	};	99	};
102		100
@@ -122,7 +120,7 @@ static DEFINE_XARRAY_ALLOC(ctx_table); · 19 unmodified lines
122	static DEFINE_XARRAY_ALLOC(multicast_table);	120	static DEFINE_XARRAY_ALLOC(multicast_table);
123		121
124	static const struct file_operations ucma_fops;	122	static const struct file_operations ucma_fops;
125	static int __destroy_id(struct ucma_context *ctx);	123	static int ucma_destroy_private_ctx(struct ucma_context *ctx);
126		124
127	static inline struct ucma_context *_ucma_find_context(int id,	125	static inline struct ucma_context *_ucma_find_context(int id,
128	struct ucma_file *file)	126	struct ucma_file *file)
@@ -179,19 +177,14 @@ static void ucma_close_id(struct work_struct *work) · 50 unmodified lines
179		177
180	/* once all inflight tasks are finished, we close all underlying	178	/* once all inflight tasks are finished, we close all underlying
181	* resources. The context is still alive till its explicit destryoing	179	* resources. The context is still alive till its explicit destryoing
182	* by its creator.	180	* by its creator. This puts back the xarray's reference.
183	*/	181	*/
184	ucma_put_ctx(ctx);	182	ucma_put_ctx(ctx);
185	wait_for_completion(&ctx->comp);	183	wait_for_completion(&ctx->comp);
186	/* No new events will be generated after destroying the id. */	184	/* No new events will be generated after destroying the id. */
187	rdma_destroy_id(ctx->cm_id);	185	rdma_destroy_id(ctx->cm_id);
188		186
189	/*	187	/* Reading the cm_id without holding a positive ref is not allowed */
190	* At this point ctx->ref is zero so the only place the ctx can be is in
191	* a uevent or in __destroy_id(). Since the former doesn't touch
192	* ctx->cm_id and the latter sync cancels this, there is no races with
193	* this store.
194	*/
195	ctx->cm_id = NULL;	188	ctx->cm_id = NULL;
196	}	189	}
197		190
@@ -204,7 +197,6 @@ static struct ucma_context ucma_alloc_ctx(struct ucma_file file) · 6 unmodified lines
204	return NULL;	197	return NULL;
205		198
206	INIT_WORK(&ctx->close_work, ucma_close_id);	199	INIT_WORK(&ctx->close_work, ucma_close_id);
207	refcount_set(&ctx->ref, 1);
208	init_completion(&ctx->comp);	200	init_completion(&ctx->comp);
209	/* So list_del() will work if we don't do ucma_finish_ctx() */	201	/* So list_del() will work if we don't do ucma_finish_ctx() */
210	INIT_LIST_HEAD(&ctx->list);	202	INIT_LIST_HEAD(&ctx->list);
@@ -218,6 +210,13 @@ static struct ucma_context ucma_alloc_ctx(struct ucma_file file) · 7 unmodified lines
218	return ctx;	210	return ctx;
219	}	211	}
220		212
		213	static void ucma_set_ctx_cm_id(struct ucma_context *ctx,
		214	struct rdma_cm_id *cm_id)
		215	{
		216	refcount_set(&ctx->ref, 1);
		217	ctx->cm_id = cm_id;
		218	}
		219
221	static void ucma_finish_ctx(struct ucma_context *ctx)	220	static void ucma_finish_ctx(struct ucma_context *ctx)
222	{	221	{
223	lockdep_assert_held(&ctx->file->mut);	222	lockdep_assert_held(&ctx->file->mut);
@@ -303,7 +302,7 @@ static int ucma_connect_event_handler(struct rdma_cm_id *cm_id, · 79 unmodified lines
303	ctx = ucma_alloc_ctx(listen_ctx->file);	302	ctx = ucma_alloc_ctx(listen_ctx->file);
304	if (!ctx)	303	if (!ctx)
305	goto err_backlog;	304	goto err_backlog;
306	ctx->cm_id = cm_id;	305	ucma_set_ctx_cm_id(ctx, cm_id);
307		306
308	uevent = ucma_create_uevent(listen_ctx, event);	307	uevent = ucma_create_uevent(listen_ctx, event);
309	if (!uevent)	308	if (!uevent)
@@ -321,8 +320,7 @@ static int ucma_connect_event_handler(struct rdma_cm_id *cm_id, · 11 unmodified lines
321	return 0;	320	return 0;
322		321
323	err_alloc:	322	err_alloc:
324	xa_erase(&ctx_table, ctx->id);	323	ucma_destroy_private_ctx(ctx);
325	kfree(ctx);
326	err_backlog:	324	err_backlog:
327	atomic_inc(&listen_ctx->backlog);	325	atomic_inc(&listen_ctx->backlog);
328	/* Returning error causes the new ID to be destroyed */	326	/* Returning error causes the new ID to be destroyed */
@@ -356,8 +354,12 @@ static int ucma_event_handler(struct rdma_cm_id *cm_id, · 27 unmodified lines
356	wake_up_interruptible(&ctx->file->poll_wait);	354	wake_up_interruptible(&ctx->file->poll_wait);
357	}	355	}
358		356
359	if (event->event == RDMA_CM_EVENT_DEVICE_REMOVAL && !ctx->destroying)	357	if (event->event == RDMA_CM_EVENT_DEVICE_REMOVAL) {
360	queue_work(system_unbound_wq, &ctx->close_work);	358	xa_lock(&ctx_table);
		359	if (xa_load(&ctx_table, ctx->id) == ctx)
		360	queue_work(system_unbound_wq, &ctx->close_work);
		361	xa_unlock(&ctx_table);
		362	}
361	return 0;	363	return 0;
362	}	364	}
363		365
@@ -461,13 +463,12 @@ static ssize_t ucma_create_id(struct ucma_file file, const char __user inbuf, · 97 unmodified lines
461	ret = PTR_ERR(cm_id);	463	ret = PTR_ERR(cm_id);
462	goto err1;	464	goto err1;
463	}	465	}
464	ctx->cm_id = cm_id;	466	ucma_set_ctx_cm_id(ctx, cm_id);
465		467
466	resp.id = ctx->id;	468	resp.id = ctx->id;
467	if (copy_to_user(u64_to_user_ptr(cmd.response),	469	if (copy_to_user(u64_to_user_ptr(cmd.response),
468	&resp, sizeof(resp))) {	470	&resp, sizeof(resp))) {
469	xa_erase(&ctx_table, ctx->id);	471	ucma_destroy_private_ctx(ctx);
470	__destroy_id(ctx);
471	return -EFAULT;	472	return -EFAULT;
472	}	473	}
473		474
@@ -477,8 +478,7 @@ static ssize_t ucma_create_id(struct ucma_file file, const char __user inbuf, · 3 unmodified lines
477	return 0;	478	return 0;
478		479
479	err1:	480	err1:
480	xa_erase(&ctx_table, ctx->id);	481	ucma_destroy_private_ctx(ctx);
481	kfree(ctx);
482	return ret;	482	return ret;
483	}	483	}
484		484
@@ -516,68 +516,73 @@ static void ucma_cleanup_mc_events(struct ucma_multicast *mc) · 31 unmodified lines
516	rdma_unlock_handler(mc->ctx->cm_id);	516	rdma_unlock_handler(mc->ctx->cm_id);
517	}	517	}
518		518
519	/*	519	static int ucma_cleanup_ctx_events(struct ucma_context *ctx)
520	* ucma_free_ctx is called after the underlying rdma CM-ID is destroyed. At
521	* this point, no new events will be reported from the hardware. However, we
522	* still need to cleanup the UCMA context for this ID. Specifically, there
523	* might be events that have not yet been consumed by the user space software.
524	* mutex. After that we release them as needed.
525	*/
526	static int ucma_free_ctx(struct ucma_context *ctx)
527	{	520	{
528	int events_reported;	521	int events_reported;
529	struct ucma_event uevent, tmp;	522	struct ucma_event uevent, tmp;
530	LIST_HEAD(list);	523	LIST_HEAD(list);
531		524
532	ucma_cleanup_multicast(ctx);	525	/* Cleanup events not yet reported to the user.*/
533
534	/* Cleanup events not yet reported to the user. */
535	mutex_lock(&ctx->file->mut);	526	mutex_lock(&ctx->file->mut);
536	list_for_each_entry_safe(uevent, tmp, &ctx->file->event_list, list) {	527	list_for_each_entry_safe(uevent, tmp, &ctx->file->event_list, list) {
537	if (uevent->ctx == ctx \|\| uevent->conn_req_ctx == ctx)	528	if (uevent->ctx != ctx)
		529	continue;
		530
		531	if (uevent->resp.event == RDMA_CM_EVENT_CONNECT_REQUEST &&
		532	xa_cmpxchg(&ctx_table, uevent->conn_req_ctx->id,
		533	uevent->conn_req_ctx, XA_ZERO_ENTRY,
		534	GFP_KERNEL) == uevent->conn_req_ctx) {
538	list_move_tail(&uevent->list, &list);	535	list_move_tail(&uevent->list, &list);
		536	continue;
		537	}
		538	list_del(&uevent->list);
		539	kfree(uevent);
539	}	540	}
540	list_del(&ctx->list);	541	list_del(&ctx->list);
541	events_reported = ctx->events_reported;	542	events_reported = ctx->events_reported;
542	mutex_unlock(&ctx->file->mut);	543	mutex_unlock(&ctx->file->mut);
543		544
544	/*	545	/*
545	* If this was a listening ID then any connections spawned from it	546	* If this was a listening ID then any connections spawned from it that
546	* that have not been delivered to userspace are cleaned up too.	547	* have not been delivered to userspace are cleaned up too. Must be done
547	* Must be done outside any locks.	548	* outside any locks.
548	*/	549	*/
549	list_for_each_entry_safe(uevent, tmp, &list, list) {	550	list_for_each_entry_safe(uevent, tmp, &list, list) {
550	list_del(&uevent->list);	551	ucma_destroy_private_ctx(uevent->conn_req_ctx);
551	if (uevent->resp.event == RDMA_CM_EVENT_CONNECT_REQUEST &&
552	uevent->conn_req_ctx != ctx)
553	__destroy_id(uevent->conn_req_ctx);
554	kfree(uevent);	552	kfree(uevent);
555	}	553	}
556
557	mutex_destroy(&ctx->mutex);
558	kfree(ctx);
559	return events_reported;	554	return events_reported;
560	}	555	}
561		556
562	static int __destroy_id(struct ucma_context *ctx)	557	/*
		558	* When this is called the xarray must have a XA_ZERO_ENTRY in the ctx->id (ie
		559	* the ctx is not public to the user). This either because:
		560	* - ucma_finish_ctx() hasn't been called
		561	* - xa_cmpxchg() succeed to remove the entry (only one thread can succeed)
		562	*/
		563	static int ucma_destroy_private_ctx(struct ucma_context *ctx)
563	{	564	{
		565	int events_reported;
		566
564	/*	567	/*
565	* If the refcount is already 0 then ucma_close_id() has already	568	* Destroy the underlying cm_id. New work queuing is prevented now by
566	* destroyed the cm_id, otherwise holding the refcount keeps cm_id	569	* the removal from the xarray. Once the work is cancled ref will either
567	* valid. Prevent queue_work() from being called.	570	* be 0 because the work ran to completion and consumed the ref from the
		571	* xarray, or it will be positive because we still have the ref from the
		572	* xarray. This can also be 0 in cases where cm_id was never set
568	*/	573	*/
569	if (refcount_inc_not_zero(&ctx->ref)) {
570	rdma_lock_handler(ctx->cm_id);
571	ctx->destroying = 1;
572	rdma_unlock_handler(ctx->cm_id);
573	ucma_put_ctx(ctx);
574	}
575
576	cancel_work_sync(&ctx->close_work);	574	cancel_work_sync(&ctx->close_work);
577	/* At this point it's guaranteed that there is no inflight closing task */	575	if (refcount_read(&ctx->ref))
578	if (ctx->cm_id)
579	ucma_close_id(&ctx->close_work);	576	ucma_close_id(&ctx->close_work);
580	return ucma_free_ctx(ctx);	577
		578	events_reported = ucma_cleanup_ctx_events(ctx);
		579	ucma_cleanup_multicast(ctx);
		580
		581	WARN_ON(xa_cmpxchg(&ctx_table, ctx->id, XA_ZERO_ENTRY, NULL,
		582	GFP_KERNEL) != NULL);
		583	mutex_destroy(&ctx->mutex);
		584	kfree(ctx);
		585	return events_reported;
581	}	586	}
582		587
583	static ssize_t ucma_destroy_id(struct ucma_file file, const char __user inbuf,	588	static ssize_t ucma_destroy_id(struct ucma_file file, const char __user inbuf,
@@ -596,14 +601,17 @@ static ssize_t ucma_destroy_id(struct ucma_file file, const char __user inbuf, · 12 unmodified lines
596		601
597	xa_lock(&ctx_table);	602	xa_lock(&ctx_table);
598	ctx = _ucma_find_context(cmd.id, file);	603	ctx = _ucma_find_context(cmd.id, file);
599	if (!IS_ERR(ctx))	604	if (!IS_ERR(ctx)) {
600	__xa_erase(&ctx_table, ctx->id);	605	if (__xa_cmpxchg(&ctx_table, ctx->id, ctx, XA_ZERO_ENTRY,
		606	GFP_KERNEL) != ctx)
		607	ctx = ERR_PTR(-ENOENT);
		608	}
601	xa_unlock(&ctx_table);	609	xa_unlock(&ctx_table);
602		610
603	if (IS_ERR(ctx))	611	if (IS_ERR(ctx))
604	return PTR_ERR(ctx);	612	return PTR_ERR(ctx);
605		613
606	resp.events_reported = __destroy_id(ctx);	614	resp.events_reported = ucma_destroy_private_ctx(ctx);
607	if (copy_to_user(u64_to_user_ptr(cmd.response),	615	if (copy_to_user(u64_to_user_ptr(cmd.response),
608	&resp, sizeof(resp)))	616	&resp, sizeof(resp)))
609	ret = -EFAULT;	617	ret = -EFAULT;
@@ -1777,15 +1785,16 @@ static int ucma_close(struct inode inode, struct file filp) · 1167 unmodified lines
1777	* prevented by this being a FD release function. The list_add_tail() in	1785	* prevented by this being a FD release function. The list_add_tail() in
1778	* ucma_connect_event_handler() can run concurrently, however it only	1786	* ucma_connect_event_handler() can run concurrently, however it only
1779	* adds to the list after a listening ID. By only reading the first of	1787	* adds to the list after a listening ID. By only reading the first of
1780	* the list, and relying on __destroy_id() to block	1788	* the list, and relying on ucma_destroy_private_ctx() to block
1781	* ucma_connect_event_handler(), no additional locking is needed.	1789	* ucma_connect_event_handler(), no additional locking is needed.
1782	*/	1790	*/
1783	while (!list_empty(&file->ctx_list)) {	1791	while (!list_empty(&file->ctx_list)) {
1784	struct ucma_context *ctx = list_first_entry(	1792	struct ucma_context *ctx = list_first_entry(
1785	&file->ctx_list, struct ucma_context, list);	1793	&file->ctx_list, struct ucma_context, list);
1786		1794
1787	xa_erase(&ctx_table, ctx->id);	1795	WARN_ON(xa_cmpxchg(&ctx_table, ctx->id, ctx, XA_ZERO_ENTRY,
1788	__destroy_id(ctx);	1796	GFP_KERNEL) != ctx);
		1797	ucma_destroy_private_ctx(ctx);
1789	}	1798	}
1790	kfree(file);	1799	kfree(file);
1791	return 0;	1800	return 0;

drivers/infiniband/core/umem.c+1−1

@@ -135,7 +135,7 @@ unsigned long ib_umem_find_best_pgsz(struct ib_umem *umem, · 134 unmodified lines
135	*/	135	*/
136	if (mask)	136	if (mask)
137	pgsz_bitmap &= GENMASK(count_trailing_zeros(mask), 0);	137	pgsz_bitmap &= GENMASK(count_trailing_zeros(mask), 0);
138	return rounddown_pow_of_two(pgsz_bitmap);	138	return pgsz_bitmap ? rounddown_pow_of_two(pgsz_bitmap) : 0;
139	}	139	}
140	EXPORT_SYMBOL(ib_umem_find_best_pgsz);	140	EXPORT_SYMBOL(ib_umem_find_best_pgsz);
141		141

drivers/infiniband/hw/mlx5/main.c+2−2

@@ -3956,7 +3956,7 @@ static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) · 3955 unmodified lines
3956		3956
3957	err = set_has_smi_cap(dev);	3957	err = set_has_smi_cap(dev);
3958	if (err)	3958	if (err)
3959	return err;	3959	goto err_mp;
3960		3960
3961	if (!mlx5_core_mp_enabled(mdev)) {	3961	if (!mlx5_core_mp_enabled(mdev)) {
3962	for (i = 1; i <= dev->num_ports; i++) {	3962	for (i = 1; i <= dev->num_ports; i++) {
@@ -4319,7 +4319,7 @@ static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) · 356 unmodified lines
4319		4319
4320	err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);	4320	err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4321	if (err)	4321	if (err)
4322	mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);	4322	mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4323		4323
4324	return err;	4324	return err;
4325	}	4325	}

drivers/infiniband/hw/ocrdma/ocrdma_verbs.c+1−1

 		pr_err("%s(%d) Freeing in use pdid=0x%x.\n",
 		       __func__, dev->id, pd->id);
 	}
-	kfree(uctx->cntxt_pd);
 	uctx->cntxt_pd = NULL;
 	_ocrdma_dealloc_pd(dev, pd);
+	kfree(pd);
 }
 static struct ocrdma_pd *ocrdma_get_ucontext_pd(struct ocrdma_ucontext *uctx)

drivers/infiniband/hw/usnic/usnic_ib_verbs.c+3−0

 		}
 		usnic_uiom_free_dev_list(dev_list);
+		dev_list = NULL;
 	}
 	/* Try to find resources on an unused vf */
 qp_grp_check:
 	if (IS_ERR_OR_NULL(qp_grp)) {
 		usnic_err("Failed to allocate qp_grp\n");
+		if (usnic_ib_share_vf)
+			usnic_uiom_free_dev_list(dev_list);
 		return ERR_PTR(qp_grp ? PTR_ERR(qp_grp) : -ENOMEM);
 	}
 	return qp_grp;

drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c+2−0

 }
 static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
+	{ .compatible = "qcom,msm8998-smmu-v2" },
 	{ .compatible = "qcom,sc7180-smmu-500" },
+	{ .compatible = "qcom,sdm630-smmu-v2" },
 	{ .compatible = "qcom,sdm845-smmu-500" },
 	{ .compatible = "qcom,sm8150-smmu-500" },
 	{ .compatible = "qcom,sm8250-smmu-500" },

drivers/iommu/intel/iommu.c+0−1

@@ -38,7 +38,6 @@ · 37 unmodified lines
38	#include <linux/dmi.h>	38	#include <linux/dmi.h>
39	#include <linux/pci-ats.h>	39	#include <linux/pci-ats.h>
40	#include <linux/memblock.h>	40	#include <linux/memblock.h>
41	#include <linux/dma-map-ops.h>
42	#include <linux/dma-direct.h>	41	#include <linux/dma-direct.h>
43	#include <linux/crash_dump.h>	42	#include <linux/crash_dump.h>
44	#include <linux/numa.h>	43	#include <linux/numa.h>

drivers/iommu/intel/svm.c+20−2

@@ -118,8 +118,10 @@ void intel_svm_check(struct intel_iommu *iommu) · 117 unmodified lines
118	iommu->flags \|= VTD_FLAG_SVM_CAPABLE;	118	iommu->flags \|= VTD_FLAG_SVM_CAPABLE;
119	}	119	}
120		120
121	static void intel_flush_svm_range_dev (struct intel_svm svm, struct intel_svm_dev sdev,	121	static void __flush_svm_range_dev(struct intel_svm *svm,
122	unsigned long address, unsigned long pages, int ih)	122	struct intel_svm_dev *sdev,
		123	unsigned long address,
		124	unsigned long pages, int ih)
123	{	125	{
124	struct qi_desc desc;	126	struct qi_desc desc;
125		127
@@ -170,6 +172,22 @@ static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_d · 44 unmodified lines
170	}	172	}
171	}	173	}
172		174
		175	static void intel_flush_svm_range_dev(struct intel_svm *svm,
		176	struct intel_svm_dev *sdev,
		177	unsigned long address,
		178	unsigned long pages, int ih)
		179	{
		180	unsigned long shift = ilog2(__roundup_pow_of_two(pages));
		181	unsigned long align = (1ULL << (VTD_PAGE_SHIFT + shift));
		182	unsigned long start = ALIGN_DOWN(address, align);
		183	unsigned long end = ALIGN(address + (pages << VTD_PAGE_SHIFT), align);
		184
		185	while (start < end) {
		186	__flush_svm_range_dev(svm, sdev, start, align >> VTD_PAGE_SHIFT, ih);
		187	start += align;
		188	}
		189	}
		190
173	static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address,	191	static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address,
174	unsigned long pages, int ih)	192	unsigned long pages, int ih)
175	{	193	{

drivers/md/Kconfig+2−0

 	select BLK_DEV_INTEGRITY
 	select DM_BUFIO
 	select CRYPTO
+	select CRYPTO_SKCIPHER
 	select ASYNC_XOR
 	help
 	  This device-mapper target emulates a block device that has
 	tristate "Drive-managed zoned block device target support"
 	depends on BLK_DEV_DM
 	depends on BLK_DEV_ZONED
+	select CRC32
 	help
 	  This device-mapper target takes a host-managed or host-aware zoned
 	  block device and exposes most of its capacity as a regular block

drivers/md/dm-bufio.c+6−0

 }
 EXPORT_SYMBOL_GPL(dm_bufio_get_device_size);
+struct dm_io_client *dm_bufio_get_dm_io_client(struct dm_bufio_client *c)
+{
+	return c->dm_io;
+}
+EXPORT_SYMBOL_GPL(dm_bufio_get_dm_io_client);
 sector_t dm_bufio_get_block_number(struct dm_buffer *b)
 {
 	return b->block;

drivers/md/dm-crypt.c+152−18

@@ -1454,13 +1454,16 @@ static int crypt_convert_block_skcipher(struct crypt_config *cc, · 1453 unmodified lines
1454	static void kcryptd_async_done(struct crypto_async_request *async_req,	1454	static void kcryptd_async_done(struct crypto_async_request *async_req,
1455	int error);	1455	int error);
1456		1456
1457	static void crypt_alloc_req_skcipher(struct crypt_config *cc,	1457	static int crypt_alloc_req_skcipher(struct crypt_config *cc,
1458	struct convert_context *ctx)	1458	struct convert_context *ctx)
1459	{	1459	{
1460	unsigned key_index = ctx->cc_sector & (cc->tfms_count - 1);	1460	unsigned key_index = ctx->cc_sector & (cc->tfms_count - 1);
1461		1461
1462	if (!ctx->r.req)	1462	if (!ctx->r.req) {
1463	ctx->r.req = mempool_alloc(&cc->req_pool, GFP_NOIO);	1463	ctx->r.req = mempool_alloc(&cc->req_pool, in_interrupt() ? GFP_ATOMIC : GFP_NOIO);
		1464	if (!ctx->r.req)
		1465	return -ENOMEM;
		1466	}
1464		1467
1465	skcipher_request_set_tfm(ctx->r.req, cc->cipher_tfm.tfms[key_index]);	1468	skcipher_request_set_tfm(ctx->r.req, cc->cipher_tfm.tfms[key_index]);
1466		1469
@@ -1471,13 +1474,18 @@ static void crypt_alloc_req_skcipher(struct crypt_config *cc, · 4 unmodified lines
1471	skcipher_request_set_callback(ctx->r.req,	1474	skcipher_request_set_callback(ctx->r.req,
1472	CRYPTO_TFM_REQ_MAY_BACKLOG,	1475	CRYPTO_TFM_REQ_MAY_BACKLOG,
1473	kcryptd_async_done, dmreq_of_req(cc, ctx->r.req));	1476	kcryptd_async_done, dmreq_of_req(cc, ctx->r.req));
		1477
		1478	return 0;
1474	}	1479	}
1475		1480
1476	static void crypt_alloc_req_aead(struct crypt_config *cc,	1481	static int crypt_alloc_req_aead(struct crypt_config *cc,
1477	struct convert_context *ctx)	1482	struct convert_context *ctx)
1478	{	1483	{
1479	if (!ctx->r.req_aead)	1484	if (!ctx->r.req) {
1480	ctx->r.req_aead = mempool_alloc(&cc->req_pool, GFP_NOIO);	1485	ctx->r.req = mempool_alloc(&cc->req_pool, in_interrupt() ? GFP_ATOMIC : GFP_NOIO);
		1486	if (!ctx->r.req)
		1487	return -ENOMEM;
		1488	}
1481		1489
1482	aead_request_set_tfm(ctx->r.req_aead, cc->cipher_tfm.tfms_aead[0]);	1490	aead_request_set_tfm(ctx->r.req_aead, cc->cipher_tfm.tfms_aead[0]);
1483		1491
@@ -1488,15 +1496,17 @@ static void crypt_alloc_req_aead(struct crypt_config *cc, · 4 unmodified lines
1488	aead_request_set_callback(ctx->r.req_aead,	1496	aead_request_set_callback(ctx->r.req_aead,
1489	CRYPTO_TFM_REQ_MAY_BACKLOG,	1497	CRYPTO_TFM_REQ_MAY_BACKLOG,
1490	kcryptd_async_done, dmreq_of_req(cc, ctx->r.req_aead));	1498	kcryptd_async_done, dmreq_of_req(cc, ctx->r.req_aead));
		1499
		1500	return 0;
1491	}	1501	}
1492		1502
1493	static void crypt_alloc_req(struct crypt_config *cc,	1503	static int crypt_alloc_req(struct crypt_config *cc,
1494	struct convert_context *ctx)	1504	struct convert_context *ctx)
1495	{	1505	{
1496	if (crypt_integrity_aead(cc))	1506	if (crypt_integrity_aead(cc))
1497	crypt_alloc_req_aead(cc, ctx);	1507	return crypt_alloc_req_aead(cc, ctx);
1498	else	1508	else
1499	crypt_alloc_req_skcipher(cc, ctx);	1509	return crypt_alloc_req_skcipher(cc, ctx);
1500	}	1510	}
1501		1511
1502	static void crypt_free_req_skcipher(struct crypt_config *cc,	1512	static void crypt_free_req_skcipher(struct crypt_config *cc,
@@ -1529,17 +1539,28 @@ static void crypt_free_req(struct crypt_config cc, void req, struct bio *base_ · 26 unmodified lines
1529	* Encrypt / decrypt data from one bio to another one (can be the same one)	1539	* Encrypt / decrypt data from one bio to another one (can be the same one)
1530	*/	1540	*/
1531	static blk_status_t crypt_convert(struct crypt_config *cc,	1541	static blk_status_t crypt_convert(struct crypt_config *cc,
1532	struct convert_context *ctx, bool atomic)	1542	struct convert_context *ctx, bool atomic, bool reset_pending)
1533	{	1543	{
1534	unsigned int tag_offset = 0;	1544	unsigned int tag_offset = 0;
1535	unsigned int sector_step = cc->sector_size >> SECTOR_SHIFT;	1545	unsigned int sector_step = cc->sector_size >> SECTOR_SHIFT;
1536	int r;	1546	int r;
1537		1547
1538	atomic_set(&ctx->cc_pending, 1);	1548	/*
		1549	* if reset_pending is set we are dealing with the bio for the first time,
		1550	* else we're continuing to work on the previous bio, so don't mess with
		1551	* the cc_pending counter
		1552	*/
		1553	if (reset_pending)
		1554	atomic_set(&ctx->cc_pending, 1);
1539		1555
1540	while (ctx->iter_in.bi_size && ctx->iter_out.bi_size) {	1556	while (ctx->iter_in.bi_size && ctx->iter_out.bi_size) {
1541		1557
1542	crypt_alloc_req(cc, ctx);	1558	r = crypt_alloc_req(cc, ctx);
		1559	if (r) {
		1560	complete(&ctx->restart);
		1561	return BLK_STS_DEV_RESOURCE;
		1562	}
		1563
1543	atomic_inc(&ctx->cc_pending);	1564	atomic_inc(&ctx->cc_pending);
1544		1565
1545	if (crypt_integrity_aead(cc))	1566	if (crypt_integrity_aead(cc))
@@ -1553,7 +1574,25 @@ static blk_status_t crypt_convert(struct crypt_config *cc, · 7 unmodified lines
1553	* but the driver request queue is full, let's wait.	1574	* but the driver request queue is full, let's wait.
1554	*/	1575	*/
1555	case -EBUSY:	1576	case -EBUSY:
1556	wait_for_completion(&ctx->restart);	1577	if (in_interrupt()) {
		1578	if (try_wait_for_completion(&ctx->restart)) {
		1579	/*
		1580	* we don't have to block to wait for completion,
		1581	* so proceed
		1582	*/
		1583	} else {
		1584	/*
		1585	* we can't wait for completion without blocking
		1586	* exit and continue processing in a workqueue
		1587	*/
		1588	ctx->r.req = NULL;
		1589	ctx->cc_sector += sector_step;
		1590	tag_offset++;
		1591	return BLK_STS_DEV_RESOURCE;
		1592	}
		1593	} else {
		1594	wait_for_completion(&ctx->restart);
		1595	}
1557	reinit_completion(&ctx->restart);	1596	reinit_completion(&ctx->restart);
1558	fallthrough;	1597	fallthrough;
1559	/*	1598	/*
@@ -1691,6 +1730,12 @@ static void crypt_inc_pending(struct dm_crypt_io *io) · 131 unmodified lines
1691	atomic_inc(&io->io_pending);	1730	atomic_inc(&io->io_pending);
1692	}	1731	}
1693		1732
		1733	static void kcryptd_io_bio_endio(struct work_struct *work)
		1734	{
		1735	struct dm_crypt_io *io = container_of(work, struct dm_crypt_io, work);
		1736	bio_endio(io->base_bio);
		1737	}
		1738
1694	/*	1739	/*
1695	* One of the bios was finished. Check for completion of	1740	* One of the bios was finished. Check for completion of
1696	* the whole request and correctly clean up the buffer.	1741	* the whole request and correctly clean up the buffer.
@@ -1713,7 +1758,23 @@ static void crypt_dec_pending(struct dm_crypt_io *io) · 16 unmodified lines
1713	kfree(io->integrity_metadata);	1758	kfree(io->integrity_metadata);
1714		1759
1715	base_bio->bi_status = error;	1760	base_bio->bi_status = error;
1716	bio_endio(base_bio);	1761
		1762	/*
		1763	* If we are running this function from our tasklet,
		1764	* we can't call bio_endio() here, because it will call
		1765	* clone_endio() from dm.c, which in turn will
		1766	* free the current struct dm_crypt_io structure with
		1767	* our tasklet. In this case we need to delay bio_endio()
		1768	* execution to after the tasklet is done and dequeued.
		1769	*/
		1770	if (tasklet_trylock(&io->tasklet)) {
		1771	tasklet_unlock(&io->tasklet);
		1772	bio_endio(base_bio);
		1773	return;
		1774	}
		1775
		1776	INIT_WORK(&io->work, kcryptd_io_bio_endio);
		1777	queue_work(cc->io_queue, &io->work);
1717	}	1778	}
1718		1779
1719	/*	1780	/*
@@ -1945,6 +2006,37 @@ static bool kcryptd_crypt_write_inline(struct crypt_config *cc, · 225 unmodified lines
1945	}	2006	}
1946	}	2007	}
1947		2008
		2009	static void kcryptd_crypt_write_continue(struct work_struct *work)
		2010	{
		2011	struct dm_crypt_io *io = container_of(work, struct dm_crypt_io, work);
		2012	struct crypt_config *cc = io->cc;
		2013	struct convert_context *ctx = &io->ctx;
		2014	int crypt_finished;
		2015	sector_t sector = io->sector;
		2016	blk_status_t r;
		2017
		2018	wait_for_completion(&ctx->restart);
		2019	reinit_completion(&ctx->restart);
		2020
		2021	r = crypt_convert(cc, &io->ctx, true, false);
		2022	if (r)
		2023	io->error = r;
		2024	crypt_finished = atomic_dec_and_test(&ctx->cc_pending);
		2025	if (!crypt_finished && kcryptd_crypt_write_inline(cc, ctx)) {
		2026	/* Wait for completion signaled by kcryptd_async_done() */
		2027	wait_for_completion(&ctx->restart);
		2028	crypt_finished = 1;
		2029	}
		2030
		2031	/* Encryption was already finished, submit io now */
		2032	if (crypt_finished) {
		2033	kcryptd_crypt_write_io_submit(io, 0);
		2034	io->sector = sector;
		2035	}
		2036
		2037	crypt_dec_pending(io);
		2038	}
		2039
1948	static void kcryptd_crypt_write_convert(struct dm_crypt_io *io)	2040	static void kcryptd_crypt_write_convert(struct dm_crypt_io *io)
1949	{	2041	{
1950	struct crypt_config *cc = io->cc;	2042	struct crypt_config *cc = io->cc;
@@ -1973,7 +2065,17 @@ static void kcryptd_crypt_write_convert(struct dm_crypt_io *io) · 22 unmodified lines
1973		2065
1974	crypt_inc_pending(io);	2066	crypt_inc_pending(io);
1975	r = crypt_convert(cc, ctx,	2067	r = crypt_convert(cc, ctx,
1976	test_bit(DM_CRYPT_NO_WRITE_WORKQUEUE, &cc->flags));	2068	test_bit(DM_CRYPT_NO_WRITE_WORKQUEUE, &cc->flags), true);
		2069	/*
		2070	* Crypto API backlogged the request, because its queue was full
		2071	* and we're in softirq context, so continue from a workqueue
		2072	* (TODO: is it actually possible to be in softirq in the write path?)
		2073	*/
		2074	if (r == BLK_STS_DEV_RESOURCE) {
		2075	INIT_WORK(&io->work, kcryptd_crypt_write_continue);
		2076	queue_work(cc->crypt_queue, &io->work);
		2077	return;
		2078	}
1977	if (r)	2079	if (r)
1978	io->error = r;	2080	io->error = r;
1979	crypt_finished = atomic_dec_and_test(&ctx->cc_pending);	2081	crypt_finished = atomic_dec_and_test(&ctx->cc_pending);
@@ -1998,6 +2100,25 @@ static void kcryptd_crypt_read_done(struct dm_crypt_io *io) · 18 unmodified lines
1998	crypt_dec_pending(io);	2100	crypt_dec_pending(io);
1999	}	2101	}
2000		2102
		2103	static void kcryptd_crypt_read_continue(struct work_struct *work)
		2104	{
		2105	struct dm_crypt_io *io = container_of(work, struct dm_crypt_io, work);
		2106	struct crypt_config *cc = io->cc;
		2107	blk_status_t r;
		2108
		2109	wait_for_completion(&io->ctx.restart);
		2110	reinit_completion(&io->ctx.restart);
		2111
		2112	r = crypt_convert(cc, &io->ctx, true, false);
		2113	if (r)
		2114	io->error = r;
		2115
		2116	if (atomic_dec_and_test(&io->ctx.cc_pending))
		2117	kcryptd_crypt_read_done(io);
		2118
		2119	crypt_dec_pending(io);
		2120	}
		2121
2001	static void kcryptd_crypt_read_convert(struct dm_crypt_io *io)	2122	static void kcryptd_crypt_read_convert(struct dm_crypt_io *io)
2002	{	2123	{
2003	struct crypt_config *cc = io->cc;	2124	struct crypt_config *cc = io->cc;
@@ -2009,7 +2130,16 @@ static void kcryptd_crypt_read_convert(struct dm_crypt_io *io) · 5 unmodified lines
2009	io->sector);	2130	io->sector);
2010		2131
2011	r = crypt_convert(cc, &io->ctx,	2132	r = crypt_convert(cc, &io->ctx,
2012	test_bit(DM_CRYPT_NO_READ_WORKQUEUE, &cc->flags));	2133	test_bit(DM_CRYPT_NO_READ_WORKQUEUE, &cc->flags), true);
		2134	/*
		2135	* Crypto API backlogged the request, because its queue was full
		2136	* and we're in softirq context, so continue from a workqueue
		2137	*/
		2138	if (r == BLK_STS_DEV_RESOURCE) {
		2139	INIT_WORK(&io->work, kcryptd_crypt_read_continue);
		2140	queue_work(cc->crypt_queue, &io->work);
		2141	return;
		2142	}
2013	if (r)	2143	if (r)
2014	io->error = r;	2144	io->error = r;
2015		2145
@@ -2091,8 +2221,12 @@ static void kcryptd_queue_crypt(struct dm_crypt_io *io) · 75 unmodified lines
2091		2221
2092	if ((bio_data_dir(io->base_bio) == READ && test_bit(DM_CRYPT_NO_READ_WORKQUEUE, &cc->flags)) \|\|	2222	if ((bio_data_dir(io->base_bio) == READ && test_bit(DM_CRYPT_NO_READ_WORKQUEUE, &cc->flags)) \|\|
2093	(bio_data_dir(io->base_bio) == WRITE && test_bit(DM_CRYPT_NO_WRITE_WORKQUEUE, &cc->flags))) {	2223	(bio_data_dir(io->base_bio) == WRITE && test_bit(DM_CRYPT_NO_WRITE_WORKQUEUE, &cc->flags))) {
2094	if (in_irq()) {	2224	/*
2095	/* Crypto API's "skcipher_walk_first() refuses to work in hard IRQ context */	2225	* in_irq(): Crypto API's skcipher_walk_first() refuses to work in hard IRQ context.
		2226	* irqs_disabled(): the kernel may run some IO completion from the idle thread, but
		2227	* it is being executed with irqs disabled.
		2228	*/
		2229	if (in_irq() \|\| irqs_disabled()) {
2096	tasklet_init(&io->tasklet, kcryptd_crypt_tasklet, (unsigned long)&io->work);	2230	tasklet_init(&io->tasklet, kcryptd_crypt_tasklet, (unsigned long)&io->work);
2097	tasklet_schedule(&io->tasklet);	2231	tasklet_schedule(&io->tasklet);
2098	return;	2232	return;

drivers/md/dm-integrity.c+50−12

 #undef MAY_BE_HASH
 }
-static void dm_integrity_flush_buffers(struct dm_integrity_c *ic)
+struct flush_request {
+	struct dm_io_request io_req;
+	struct dm_io_region io_reg;
+	struct dm_integrity_c *ic;
+	struct completion comp;
+};
+static void flush_notify(unsigned long error, void *fr_)
+{
+	struct flush_request *fr = fr_;
+	if (unlikely(error != 0))
+		dm_integrity_io_error(fr->ic, "flusing disk cache", -EIO);
+	complete(&fr->comp);
+}
+static void dm_integrity_flush_buffers(struct dm_integrity_c *ic, bool flush_data)
 {
 	int r;
+	struct flush_request fr;
+	if (!ic->meta_dev)
+		flush_data = false;
+	if (flush_data) {
+		fr.io_req.bi_op = REQ_OP_WRITE,
+		fr.io_req.bi_op_flags = REQ_PREFLUSH | REQ_SYNC,
+		fr.io_req.mem.type = DM_IO_KMEM,
+		fr.io_req.mem.ptr.addr = NULL,
+		fr.io_req.notify.fn = flush_notify,
+		fr.io_req.notify.context = &fr;
+		fr.io_req.client = dm_bufio_get_dm_io_client(ic->bufio),
+		fr.io_reg.bdev = ic->dev->bdev,
+		fr.io_reg.sector = 0,
+		fr.io_reg.count = 0,
+		fr.ic = ic;
+		init_completion(&fr.comp);
+		r = dm_io(&fr.io_req, 1, &fr.io_reg, NULL);
+		BUG_ON(r);
+	}
 	r = dm_bufio_write_dirty_buffers(ic->bufio);
 	if (unlikely(r))
 		dm_integrity_io_error(ic, "writing tags", r);
+	if (flush_data)
+		wait_for_completion(&fr.comp);
 }
 static void sleep_on_endio_wait(struct dm_integrity_c *ic)
 	if (unlikely(dio->op == REQ_OP_DISCARD) && likely(ic->mode != 'D')) {
 		integrity_metadata(&dio->work);
-		dm_integrity_flush_buffers(ic);
+		dm_integrity_flush_buffers(ic, false);
 		dio->in_flight = (atomic_t)ATOMIC_INIT(1);
 		dio->completion = NULL;
 	flushes = bio_list_get(&ic->flush_bio_list);
 	if (unlikely(ic->mode != 'J')) {
 		spin_unlock_irq(&ic->endio_wait.lock);
-		dm_integrity_flush_buffers(ic);
+		dm_integrity_flush_buffers(ic, true);
 		goto release_flush_bios;
 	}
 	complete_journal_op(&comp);
 	wait_for_completion_io(&comp.comp);
-	dm_integrity_flush_buffers(ic);
+	dm_integrity_flush_buffers(ic, true);
 }
 static void integrity_writer(struct work_struct *w)
 {
 	int r;
-	dm_integrity_flush_buffers(ic);
+	dm_integrity_flush_buffers(ic, false);
 	if (dm_integrity_failed(ic))
 		return;
 	unsigned long limit;
 	struct bio *bio;
-	dm_integrity_flush_buffers(ic);
+	dm_integrity_flush_buffers(ic, false);
 	range.logical_sector = 0;
 	range.n_sectors = ic->provided_data_sectors;
 	add_new_range_and_wait(ic, &range);
 	spin_unlock_irq(&ic->endio_wait.lock);
-	dm_integrity_flush_buffers(ic);
+	dm_integrity_flush_buffers(ic, true);
-	if (ic->meta_dev)
-		blkdev_issue_flush(ic->dev->bdev, GFP_NOIO);
 	limit = ic->provided_data_sectors;
 	if (ic->sb->flags & cpu_to_le32(SB_FLAG_RECALCULATING)) {
 		if (ic->meta_dev)
 			queue_work(ic->writer_wq, &ic->writer_work);
 		drain_workqueue(ic->writer_wq);
-		dm_integrity_flush_buffers(ic);
+		dm_integrity_flush_buffers(ic, true);
 	}
 	if (ic->mode == 'B') {
-		dm_integrity_flush_buffers(ic);
+		dm_integrity_flush_buffers(ic, true);
 #if 1
 		/* set to 0 to test bitmap replay code */
 		init_journal(ic, 0, ic->journal_sections, 0);
 	unsigned extra_args;
 	struct dm_arg_set as;
 	static const struct dm_arg _args[] = {
-		{0, 9, "Invalid number of feature args"},
+		{0, 15, "Invalid number of feature args"},
 	};
 	unsigned journal_sectors, interleave_sectors, buffer_sectors, journal_watermark, sync_msec;
 	bool should_write_sb;

drivers/md/dm-raid.c+3−3

@@ -3729,10 +3729,10 @@ static void raid_io_hints(struct dm_target ti, struct queue_limits limits) · 3728 unmodified lines
3729	blk_limits_io_opt(limits, chunk_size_bytes * mddev_data_stripes(rs));	3729	blk_limits_io_opt(limits, chunk_size_bytes * mddev_data_stripes(rs));
3730		3730
3731	/*	3731	/*
3732	* RAID1 and RAID10 personalities require bio splitting,	3732	* RAID0 and RAID10 personalities require bio splitting,
3733	* RAID0/4/5/6 don't and process large discard bios properly.	3733	* RAID1/4/5/6 don't and process large discard bios properly.
3734	*/	3734	*/
3735	if (rs_is_raid1(rs) \|\| rs_is_raid10(rs)) {	3735	if (rs_is_raid0(rs) \|\| rs_is_raid10(rs)) {
3736	limits->discard_granularity = chunk_size_bytes;	3736	limits->discard_granularity = chunk_size_bytes;
3737	limits->max_discard_sectors = rs->md.chunk_sectors;	3737	limits->max_discard_sectors = rs->md.chunk_sectors;
3738	}	3738	}

drivers/md/dm-snap.c+24−0

 	 * for them to be committed.
 	 */
 	struct bio_list bios_queued_during_merge;
+	/*
+	 * Flush data after merge.
+	 */
+	struct bio flush_bio;
 };
 /*
 static void error_bios(struct bio *bio);
+static int flush_data(struct dm_snapshot *s)
+{
+	struct bio *flush_bio = &s->flush_bio;
+	bio_reset(flush_bio);
+	bio_set_dev(flush_bio, s->origin->bdev);
+	flush_bio->bi_opf = REQ_OP_WRITE | REQ_PREFLUSH;
+	return submit_bio_wait(flush_bio);
+}
 static void merge_callback(int read_err, unsigned long write_err, void *context)
 {
 	struct dm_snapshot *s = context;
 		goto shut;
 	}
+	if (flush_data(s) < 0) {
+		DMERR("Flush after merge failed: shutting down merge");
+		goto shut;
+	}
 	if (s->store->type->commit_merge(s->store,
 					 s->num_merging_chunks) < 0) {
 		DMERR("Write error in exception store: shutting down merge");
 	s->first_merging_chunk = 0;
 	s->num_merging_chunks = 0;
 	bio_list_init(&s->bios_queued_during_merge);
+	bio_init(&s->flush_bio, NULL, 0);
 	/* Allocate hash table for COW data */
 	if (init_hash_tables(s)) {
 	dm_exception_store_destroy(s->store);
+	bio_uninit(&s->flush_bio);
 	dm_put_device(ti, s->cow);
 	dm_put_device(ti, s->origin);

drivers/md/dm.c+1−1

@@ -562,7 +562,7 @@ static int dm_blk_ioctl(struct block_device *bdev, fmode_t mode, · 561 unmodified lines
562	* subset of the parent bdev; require extra privileges.	562	* subset of the parent bdev; require extra privileges.
563	*/	563	*/
564	if (!capable(CAP_SYS_RAWIO)) {	564	if (!capable(CAP_SYS_RAWIO)) {
565	DMWARN_LIMIT(	565	DMDEBUG_LIMIT(
566	"%s: sending ioctl %x to DM device without required privilege.",	566	"%s: sending ioctl %x to DM device without required privilege.",
567	current->comm, cmd);	567	current->comm, cmd);
568	r = -ENOIOCTLCMD;	568	r = -ENOIOCTLCMD;

drivers/net/can/dev/dev.c+2−2

 	cf->can_id |= CAN_ERR_RESTARTED;
-	netif_rx_ni(skb);
 	stats->rx_packets++;
 	stats->rx_bytes += cf->len;
+	netif_rx_ni(skb);
 restart:
 	netdev_dbg(dev, "restarted\n");
 	priv->can_stats.restarts++;

drivers/net/can/usb/peak_usb/pcan_usb_fd.c+4−4

 	else
 		memcpy(cfd->data, rm->d, cfd->len);
-	peak_usb_netif_rx(skb, &usb_if->time_ref, le32_to_cpu(rm->ts_low));
 	netdev->stats.rx_packets++;
 	netdev->stats.rx_bytes += cfd->len;
+	peak_usb_netif_rx(skb, &usb_if->time_ref, le32_to_cpu(rm->ts_low));
 	return 0;
 }
 	if (!skb)
 		return -ENOMEM;
-	peak_usb_netif_rx(skb, &usb_if->time_ref, le32_to_cpu(sm->ts_low));
 	netdev->stats.rx_packets++;
 	netdev->stats.rx_bytes += cf->len;
+	peak_usb_netif_rx(skb, &usb_if->time_ref, le32_to_cpu(sm->ts_low));
 	return 0;
 }

drivers/net/can/vxcan.c+4−2

 	struct net_device *peer;
 	struct canfd_frame *cfd = (struct canfd_frame *)skb->data;
 	struct net_device_stats *peerstats, *srcstats = &dev->stats;
+	u8 len;
 	if (can_dropped_invalid_skb(dev, skb))
 		return NETDEV_TX_OK;
 	skb->dev        = peer;
 	skb->ip_summed  = CHECKSUM_UNNECESSARY;
+	len = cfd->len;
 	if (netif_rx_ni(skb) == NET_RX_SUCCESS) {
 		srcstats->tx_packets++;
-		srcstats->tx_bytes += cfd->len;
+		srcstats->tx_bytes += len;
 		peerstats = &peer->stats;
 		peerstats->rx_packets++;
-		peerstats->rx_bytes += cfd->len;
+		peerstats->rx_bytes += len;
 	}
 out_unlock:

drivers/net/dsa/b53/b53_common.c+1−1

@@ -1400,7 +1400,7 @@ static int b53_vlan_prepare(struct dsa_switch *ds, int port, · 1399 unmodified lines
1400	!(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED))	1400	!(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED))
1401	return -EINVAL;	1401	return -EINVAL;
1402		1402
1403	if (vlan->vid > dev->num_vlans)	1403	if (vlan->vid >= dev->num_vlans)
1404	return -ERANGE;	1404	return -ERANGE;
1405		1405
1406	b53_enable_vlan(dev, true, ds->vlan_filtering);	1406	b53_enable_vlan(dev, true, ds->vlan_filtering);

drivers/net/dsa/mv88e6xxx/global1_vtu.c+4−0

 		if (err)
 			return err;
+		err = mv88e6185_g1_stu_data_read(chip, entry);
+		if (err)
+			return err;
 		/* VTU DBNum[3:0] are located in VTU Operation 3:0
 		 * VTU DBNum[5:4] are located in VTU Operation 9:8
 		 */

drivers/net/ethernet/broadcom/bcmsysport.c+4−2

 	priv = netdev_priv(dev);
 	priv->clk = devm_clk_get_optional(&pdev->dev, "sw_sysport");
-	if (IS_ERR(priv->clk))
+	if (IS_ERR(priv->clk)) {
-		return PTR_ERR(priv->clk);
+		ret = PTR_ERR(priv->clk);
+		goto err_free_netdev;
+	}
 	/* Allocate number of TX rings */
 	priv->tx_rings = devm_kcalloc(&pdev->dev, txq,

drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c+6−0

 	int pf = rvu_get_pf(req->hdr.pcifunc);
 	u8 cgx_id, lmac_id;
+	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
+		return -EPERM;
 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
 	cgx_lmac_addr_set(cgx_id, lmac_id, req->mac_addr);
 	int rc = 0, i;
 	u64 cfg;
+	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
+		return -EPERM;
 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
 	rsp->hdr.rc = rc;

drivers/net/ethernet/mscc/ocelot.c+18−5

@@ -60,14 +60,27 @@ int ocelot_mact_learn(struct ocelot *ocelot, int port, · 59 unmodified lines
60	const unsigned char mac[ETH_ALEN],	60	const unsigned char mac[ETH_ALEN],
61	unsigned int vid, enum macaccess_entry_type type)	61	unsigned int vid, enum macaccess_entry_type type)
62	{	62	{
		63	u32 cmd = ANA_TABLES_MACACCESS_VALID \|
		64	ANA_TABLES_MACACCESS_DEST_IDX(port) \|
		65	ANA_TABLES_MACACCESS_ENTRYTYPE(type) \|
		66	ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN);
		67	unsigned int mc_ports;
		68
		69	/* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */
		70	if (type == ENTRYTYPE_MACv4)
		71	mc_ports = (mac[1] << 8) \| mac[2];
		72	else if (type == ENTRYTYPE_MACv6)
		73	mc_ports = (mac[0] << 8) \| mac[1];
		74	else
		75	mc_ports = 0;
		76
		77	if (mc_ports & BIT(ocelot->num_phys_ports))
		78	cmd \|= ANA_TABLES_MACACCESS_MAC_CPU_COPY;
		79
63	ocelot_mact_select(ocelot, mac, vid);	80	ocelot_mact_select(ocelot, mac, vid);
64		81
65	/* Issue a write command */	82	/* Issue a write command */
66	ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID \|	83	ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS);
67	ANA_TABLES_MACACCESS_DEST_IDX(port) \|
68	ANA_TABLES_MACACCESS_ENTRYTYPE(type) \|
69	ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN),
70	ANA_TABLES_MACACCESS);
71		84
72	return ocelot_mact_wait_for_completion(ocelot);	85	return ocelot_mact_wait_for_completion(ocelot);
73	}	86	}

drivers/net/ethernet/mscc/ocelot_net.c+1−3

 	struct net_device *dev = netdev_notifier_info_to_dev(ptr);
 	int ret = 0;
-	if (!ocelot_netdevice_dev_check(dev))
-		return 0;
 	if (event == NETDEV_PRECHANGEUPPER &&
+	    ocelot_netdevice_dev_check(dev) &&
 	    netif_is_lag_master(info->upper_dev)) {
 		struct netdev_lag_upper_info *lag_upper_info = info->upper_info;
 		struct netlink_ext_ack *extack;

drivers/net/ethernet/renesas/sh_eth.c+28−2

@@ -2606,10 +2606,10 @@ static int sh_eth_close(struct net_device *ndev) · 2605 unmodified lines
2606	/* Free all the skbuffs in the Rx queue and the DMA buffer. */	2606	/* Free all the skbuffs in the Rx queue and the DMA buffer. */
2607	sh_eth_ring_free(ndev);	2607	sh_eth_ring_free(ndev);
2608		2608
2609	pm_runtime_put_sync(&mdp->pdev->dev);
2610
2611	mdp->is_opened = 0;	2609	mdp->is_opened = 0;
2612		2610
		2611	pm_runtime_put(&mdp->pdev->dev);
		2612
2613	return 0;	2613	return 0;
2614	}	2614	}
2615		2615
@@ -3034,6 +3034,28 @@ static int sh_mdio_release(struct sh_eth_private *mdp) · 418 unmodified lines
3034	return 0;	3034	return 0;
3035	}	3035	}
3036		3036
		3037	static int sh_mdiobb_read(struct mii_bus *bus, int phy, int reg)
		3038	{
		3039	int res;
		3040
		3041	pm_runtime_get_sync(bus->parent);
		3042	res = mdiobb_read(bus, phy, reg);
		3043	pm_runtime_put(bus->parent);
		3044
		3045	return res;
		3046	}
		3047
		3048	static int sh_mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val)
		3049	{
		3050	int res;
		3051
		3052	pm_runtime_get_sync(bus->parent);
		3053	res = mdiobb_write(bus, phy, reg, val);
		3054	pm_runtime_put(bus->parent);
		3055
		3056	return res;
		3057	}
		3058
3037	/* MDIO bus init function */	3059	/* MDIO bus init function */
3038	static int sh_mdio_init(struct sh_eth_private *mdp,	3060	static int sh_mdio_init(struct sh_eth_private *mdp,
3039	struct sh_eth_plat_data *pd)	3061	struct sh_eth_plat_data *pd)
@@ -3058,6 +3080,10 @@ static int sh_mdio_init(struct sh_eth_private *mdp, · 18 unmodified lines
3058	if (!mdp->mii_bus)	3080	if (!mdp->mii_bus)
3059	return -ENOMEM;	3081	return -ENOMEM;
3060		3082
		3083	/* Wrap accessors with Runtime PM-aware ops */
		3084	mdp->mii_bus->read = sh_mdiobb_read;
		3085	mdp->mii_bus->write = sh_mdiobb_write;
		3086
3061	/* Hook up MII support for ethtool */	3087	/* Hook up MII support for ethtool */
3062	mdp->mii_bus->name = "sh_mii";	3088	mdp->mii_bus->name = "sh_mii";
3063	mdp->mii_bus->parent = dev;	3089	mdp->mii_bus->parent = dev;

drivers/net/mdio/mdio-bitbang.c+4−2

 	return dev_addr;
 }
-static int mdiobb_read(struct mii_bus *bus, int phy, int reg)
+int mdiobb_read(struct mii_bus *bus, int phy, int reg)
 {
 	struct mdiobb_ctrl *ctrl = bus->priv;
 	int ret, i;
 	mdiobb_get_bit(ctrl);
 	return ret;
 }
+EXPORT_SYMBOL(mdiobb_read);
-static int mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val)
+int mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val)
 {
 	struct mdiobb_ctrl *ctrl = bus->priv;
 	mdiobb_get_bit(ctrl);
 	return 0;
 }
+EXPORT_SYMBOL(mdiobb_write);
 struct mii_bus *alloc_mdio_bitbang(struct mdiobb_ctrl *ctrl)
 {

drivers/net/usb/cdc_ncm.c+11−1

 	uint32_t rx_speed = le32_to_cpu(data->DLBitRRate);
 	uint32_t tx_speed = le32_to_cpu(data->ULBitRate);
+	/* if the speed hasn't changed, don't report it.
+	 * RTL8156 shipped before 2021 sends notification about every 32ms.
+	 */
+	if (dev->rx_speed == rx_speed && dev->tx_speed == tx_speed)
+		return;
+	dev->rx_speed = rx_speed;
+	dev->tx_speed = tx_speed;
 	/*
 	 * Currently the USB-NET API does not support reporting the actual
 	 * device speed. Do print it instead.
 		 * USB_CDC_NOTIFY_NETWORK_CONNECTION notification shall be
 		 * sent by device after USB_CDC_NOTIFY_SPEED_CHANGE.
 		 */
-		usbnet_link_change(dev, !!event->wValue, 0);
+		if (netif_carrier_ok(dev->net) != !!event->wValue)
+			usbnet_link_change(dev, !!event->wValue, 0);
 		break;
 	case USB_CDC_NOTIFY_SPEED_CHANGE:

drivers/nvme/host/core.c+8−3

 	NULL,
 };
+static inline bool nvme_discovery_ctrl(struct nvme_ctrl *ctrl)
+{
+	return ctrl->opts && ctrl->opts->discovery_nqn;
+}
 static bool nvme_validate_cntlid(struct nvme_subsystem *subsys,
 		struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
 {
 		}
 		if ((id->cmic & NVME_CTRL_CMIC_MULTI_CTRL) ||
-		    (ctrl->opts && ctrl->opts->discovery_nqn))
+		    nvme_discovery_ctrl(ctrl))
 			continue;
 		dev_err(ctrl->device,
 			goto out_free;
 		}
-		if (!ctrl->opts->discovery_nqn && !ctrl->kas) {
+		if (!nvme_discovery_ctrl(ctrl) && !ctrl->kas) {
 			dev_err(ctrl->device,
 				"keep-alive support is mandatory for fabrics\n");
 			ret = -EINVAL;
 	if (ret < 0)
 		return ret;
-	if (!ctrl->identified) {
+	if (!ctrl->identified && !nvme_discovery_ctrl(ctrl)) {
 		ret = nvme_hwmon_init(ctrl);
 		if (ret < 0)
 			return ret;

drivers/nvme/host/tcp.c+2−2

@@ -201,7 +201,7 @@ static inline size_t nvme_tcp_req_cur_offset(struct nvme_tcp_request *req) · 200 unmodified lines
201		201
202	static inline size_t nvme_tcp_req_cur_length(struct nvme_tcp_request *req)	202	static inline size_t nvme_tcp_req_cur_length(struct nvme_tcp_request *req)
203	{	203	{
204	return min_t(size_t, req->iter.bvec->bv_len - req->iter.iov_offset,	204	return min_t(size_t, iov_iter_single_seg_count(&req->iter),
205	req->pdu_len - req->pdu_sent);	205	req->pdu_len - req->pdu_sent);
206	}	206	}
207		207
@@ -286,7 +286,7 @@ static inline void nvme_tcp_queue_request(struct nvme_tcp_request *req, · 78 unmodified lines
286	* directly, otherwise queue io_work. Also, only do that if we	286	* directly, otherwise queue io_work. Also, only do that if we
287	* are on the same cpu, so we don't introduce contention.	287	* are on the same cpu, so we don't introduce contention.
288	*/	288	*/
289	if (queue->io_cpu == smp_processor_id() &&	289	if (queue->io_cpu == __smp_processor_id() &&
290	sync && empty && mutex_trylock(&queue->send_mutex)) {	290	sync && empty && mutex_trylock(&queue->send_mutex)) {
291	queue->more_requests = !last;	291	queue->more_requests = !last;
292	nvme_tcp_send_all(queue);	292	nvme_tcp_send_all(queue);

drivers/nvme/target/rdma.c+8−8

 	}
 	ndev->inline_data_size = nport->inline_data_size;
 	ndev->inline_page_count = inline_page_count;
+	if (nport->pi_enable && !(cm_id->device->attrs.device_cap_flags &
+				  IB_DEVICE_INTEGRITY_HANDOVER)) {
+		pr_warn("T10-PI is not supported by device %s. Disabling it\n",
+			cm_id->device->name);
+		nport->pi_enable = false;
+	}
 	ndev->device = cm_id->device;
 	kref_init(&ndev->ref);
 		goto out_destroy_id;
 	}
-	if (port->nport->pi_enable &&
-	    !(cm_id->device->attrs.device_cap_flags &
-	      IB_DEVICE_INTEGRITY_HANDOVER)) {
-		pr_err("T10-PI is not supported for %pISpcs\n", addr);
-		ret = -EINVAL;
-		goto out_destroy_id;
-	}
 	port->cm_id = cm_id;
 	return 0;

drivers/perf/arm_pmu.c+0−5

 	return per_cpu(hw_events->irq, cpu);
 }
-bool arm_pmu_irq_is_nmi(void)
-{
-	return has_nmi;
-}
 /*
  * PMU hardware loses all context when a CPU goes offline.
  * When a CPU is hotplugged back in, since some hardware registers are

drivers/scsi/mpt3sas/Kconfig+1−1

@@ -79,5 +79,5 @@ config SCSI_MPT2SAS · 78 unmodified lines
79	select SCSI_MPT3SAS	79	select SCSI_MPT3SAS
80	depends on PCI && SCSI	80	depends on PCI && SCSI
81	help	81	help
82	Dummy config option for backwards compatiblity: configure the MPT3SAS	82	Dummy config option for backwards compatibility: configure the MPT3SAS
83	driver instead.	83	driver instead.

drivers/scsi/qedi/qedi_main.c+2−2

@@ -2245,7 +2245,7 @@ qedi_show_boot_tgt_info(struct qedi_ctx *qedi, int type, · 2244 unmodified lines
2245	chap_name);	2245	chap_name);
2246	break;	2246	break;
2247	case ISCSI_BOOT_TGT_CHAP_SECRET:	2247	case ISCSI_BOOT_TGT_CHAP_SECRET:
2248	rc = sprintf(buf, "%.*s\n", NVM_ISCSI_CFG_CHAP_NAME_MAX_LEN,	2248	rc = sprintf(buf, "%.*s\n", NVM_ISCSI_CFG_CHAP_PWD_MAX_LEN,
2249	chap_secret);	2249	chap_secret);
2250	break;	2250	break;
2251	case ISCSI_BOOT_TGT_REV_CHAP_NAME:	2251	case ISCSI_BOOT_TGT_REV_CHAP_NAME:
@@ -2253,7 +2253,7 @@ qedi_show_boot_tgt_info(struct qedi_ctx *qedi, int type, · 1 unmodified line
2253	mchap_name);	2253	mchap_name);
2254	break;	2254	break;
2255	case ISCSI_BOOT_TGT_REV_CHAP_SECRET:	2255	case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
2256	rc = sprintf(buf, "%.*s\n", NVM_ISCSI_CFG_CHAP_NAME_MAX_LEN,	2256	rc = sprintf(buf, "%.*s\n", NVM_ISCSI_CFG_CHAP_PWD_MAX_LEN,
2257	mchap_secret);	2257	mchap_secret);
2258	break;	2258	break;
2259	case ISCSI_BOOT_TGT_FLAGS:	2259	case ISCSI_BOOT_TGT_FLAGS:

drivers/scsi/scsi_debug.c+3−2

 		k = sdeb_zbc_model_str(sdeb_zbc_model_s);
 		if (k < 0) {
 			ret = k;
-			goto free_vm;
+			goto free_q_arr;
 		}
 		sdeb_zbc_model = k;
 		switch (sdeb_zbc_model) {
 			break;
 		default:
 			pr_err("Invalid ZBC model\n");
-			return -EINVAL;
+			ret = -EINVAL;
+			goto free_q_arr;
 		}
 	}
 	if (sdeb_zbc_model != BLK_ZONED_NONE) {

drivers/scsi/sd.c+3−3

 		}
 	}
-	if (sdp->no_write_same)
+	if (sdp->no_write_same) {
+		rq->rq_flags |= RQF_QUIET;
 		return BLK_STS_TARGET;
+	}
 	if (sdkp->ws16 || lba > 0xffffffff || nr_blocks > 0xffff)
 		return sd_setup_write_same16_cmnd(cmd, false);
 static int sd_remove(struct device *dev)
 {
 	struct scsi_disk *sdkp;
-	dev_t devt;
 	sdkp = dev_get_drvdata(dev);
-	devt = disk_devt(sdkp->disk);
 	scsi_autopm_get_device(sdkp->device);
 	async_synchronize_full_domain(&scsi_sd_pm_domain);

drivers/scsi/ufs/ufshcd.c+10−14

 	if (ret)
 		dev_err(hba->dev, "%s: En WB flush during H8: failed: %d\n",
 			__func__, ret);
-	ufshcd_wb_toggle_flush(hba, true);
+	if (!(hba->quirks & UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL))
+		ufshcd_wb_toggle_flush(hba, true);
 }
 static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba)
 static inline void ufshcd_wb_toggle_flush(struct ufs_hba *hba, bool enable)
 {
-	if (hba->quirks & UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL)
-		return;
 	if (enable)
 		ufshcd_wb_buf_flush_enable(hba);
 	else
 {
 	struct Scsi_Host *host;
 	struct ufs_hba *hba;
-	unsigned int tag;
 	u32 pos;
 	int err;
-	u8 resp = 0xF;
+	u8 resp = 0xF, lun;
-	struct ufshcd_lrb *lrbp;
 	unsigned long flags;
 	host = cmd->device->host;
 	hba = shost_priv(host);
-	tag = cmd->request->tag;
-	lrbp = &hba->lrb[tag];
+	lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
-	err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
+	err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp);
 	if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
 		if (!err)
 			err = resp;
 	/* clear the commands that were pending for corresponding LUN */
 	for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
-		if (hba->lrb[pos].lun == lrbp->lun) {
+		if (hba->lrb[pos].lun == lun) {
 			err = ufshcd_clear_cmd(hba, pos);
 			if (err)
 				break;
 			ufshcd_wb_need_flush(hba));
 	}
+	flush_work(&hba->eeh_work);
 	if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) {
 		if (!ufshcd_is_runtime_pm(pm_op))
 			/* ensure that bkops is disabled */
 		}
 	}
-	flush_work(&hba->eeh_work);
 	/*
 	 * In the case of DeepSleep, the device is expected to remain powered
 	 * with the link off, so do not check for bkops.
 	if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
 	     hba->curr_dev_pwr_mode) &&
 	    (ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl) ==
-	     hba->uic_link_state))
+	     hba->uic_link_state) &&
+	     !hba->dev_info.b_rpm_dev_flush_capable)
 		goto out;
 	if (pm_runtime_suspended(hba->dev)) {

drivers/spi/spi-cadence.c+4−2

 	void __iomem *regs;
 	struct clk *ref_clk;
 	struct clk *pclk;
+	unsigned int clk_rate;
 	u32 speed_hz;
 	const u8 *txbuf;
 	u8 *rxbuf;
 	u32 ctrl_reg, baud_rate_val;
 	unsigned long frequency;
-	frequency = clk_get_rate(xspi->ref_clk);
+	frequency = xspi->clk_rate;
 	ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
 	master->auto_runtime_pm = true;
 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
+	xspi->clk_rate = clk_get_rate(xspi->ref_clk);
 	/* Set to default valid value */
-	master->max_speed_hz = clk_get_rate(xspi->ref_clk) / 4;
+	master->max_speed_hz = xspi->clk_rate / 4;
 	xspi->speed_hz = master->max_speed_hz;
 	master->bits_per_word_mask = SPI_BPW_MASK(8);

drivers/spi/spi-fsl-spi.c+2−3

 {
 	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 	struct fsl_spi_platform_data *pdata;
-	bool pol = spi->mode & SPI_CS_HIGH;
 	struct spi_mpc8xxx_cs	*cs = spi->controller_state;
 	pdata = spi->dev.parent->parent->platform_data;
 	if (value == BITBANG_CS_INACTIVE) {
 		if (pdata->cs_control)
-			pdata->cs_control(spi, !pol);
+			pdata->cs_control(spi, false);
 	}
 	if (value == BITBANG_CS_ACTIVE) {
 		fsl_spi_change_mode(spi);
 		if (pdata->cs_control)
-			pdata->cs_control(spi, pol);
+			pdata->cs_control(spi, true);
 	}
 }

drivers/tty/serial/sifive.c+1−0

@@ -1000,6 +1000,7 @@ static int sifive_serial_probe(struct platform_device *pdev) · 999 unmodified lines
1000	/* Set up clock divider */	1000	/* Set up clock divider */
1001	ssp->clkin_rate = clk_get_rate(ssp->clk);	1001	ssp->clkin_rate = clk_get_rate(ssp->clk);
1002	ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE;	1002	ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE;
		1003	ssp->port.uartclk = ssp->baud_rate * 16;
1003	__ssp_update_div(ssp);	1004	__ssp_update_div(ssp);
1004		1005
1005	platform_set_drvdata(pdev, ssp);	1006	platform_set_drvdata(pdev, ssp);

drivers/xen/events/events_base.c+0−10

@@ -2060,16 +2060,6 @@ static struct irq_chip xen_percpu_chip __read_mostly = { · 2059 unmodified lines
2060	.irq_ack = ack_dynirq,	2060	.irq_ack = ack_dynirq,
2061	};	2061	};
2062		2062
2063	int xen_set_callback_via(uint64_t via)
2064	{
2065	struct xen_hvm_param a;
2066	a.domid = DOMID_SELF;
2067	a.index = HVM_PARAM_CALLBACK_IRQ;
2068	a.value = via;
2069	return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
2070	}
2071	EXPORT_SYMBOL_GPL(xen_set_callback_via);
2072
2073	#ifdef CONFIG_XEN_PVHVM	2063	#ifdef CONFIG_XEN_PVHVM
2074	/* Vector callbacks are better than PCI interrupts to receive event	2064	/* Vector callbacks are better than PCI interrupts to receive event
2075	* channel notifications because we can receive vector callbacks on any	2065	* channel notifications because we can receive vector callbacks on any

drivers/xen/platform-pci.c+7−1

 			dev_warn(&pdev->dev, "request_irq failed err=%d\n", ret);
 			goto out;
 		}
+		/*
+		 * It doesn't strictly *have* to run on CPU0 but it sure
+		 * as hell better process the event channel ports delivered
+		 * to CPU0.
+		 */
+		irq_set_affinity(pdev->irq, cpumask_of(0));
 		callback_via = get_callback_via(pdev);
 		ret = xen_set_callback_via(callback_via);
 		if (ret) {
 	ret = gnttab_init();
 	if (ret)
 		goto grant_out;
-	xenbus_probe(NULL);
 	return 0;
 grant_out:
 	gnttab_free_auto_xlat_frames();

drivers/xen/privcmd.c+19−6

 	return 0;
 }
-static long privcmd_ioctl_mmap_resource(struct file *file, void __user *udata)
+static long privcmd_ioctl_mmap_resource(struct file *file,
+				struct privcmd_mmap_resource __user *udata)
 {
 	struct privcmd_data *data = file->private_data;
 	struct mm_struct *mm = current->mm;
 	struct vm_area_struct *vma;
 	struct privcmd_mmap_resource kdata;
 	xen_pfn_t *pfns = NULL;
-	struct xen_mem_acquire_resource xdata;
+	struct xen_mem_acquire_resource xdata = { };
 	int rc;
 	if (copy_from_user(&kdata, udata, sizeof(kdata)))
 	if (data->domid != DOMID_INVALID && data->domid != kdata.dom)
 		return -EPERM;
+	/* Both fields must be set or unset */
+	if (!!kdata.addr != !!kdata.num)
+		return -EINVAL;
+	xdata.domid = kdata.dom;
+	xdata.type = kdata.type;
+	xdata.id = kdata.id;
+	if (!kdata.addr && !kdata.num) {
+		/* Query the size of the resource. */
+		rc = HYPERVISOR_memory_op(XENMEM_acquire_resource, &xdata);
+		if (rc)
+			return rc;
+		return __put_user(xdata.nr_frames, &udata->num);
+	}
 	mmap_write_lock(mm);
 	vma = find_vma(mm, kdata.addr);
 	} else
 		vma->vm_private_data = PRIV_VMA_LOCKED;
-	memset(&xdata, 0, sizeof(xdata));
-	xdata.domid = kdata.dom;
-	xdata.type = kdata.type;
-	xdata.id = kdata.id;
 	xdata.frame = kdata.idx;
 	xdata.nr_frames = kdata.num;
 	set_xen_guest_handle(xdata.frame_list, pfns);

drivers/xen/xenbus/xenbus.h+1−0

@@ -115,6 +115,7 @@ int xenbus_probe_node(struct xen_bus_type *bus, · 114 unmodified lines
115	const char *type,	115	const char *type,
116	const char *nodename);	116	const char *nodename);
117	int xenbus_probe_devices(struct xen_bus_type *bus);	117	int xenbus_probe_devices(struct xen_bus_type *bus);
		118	void xenbus_probe(void);
118		119
119	void xenbus_dev_changed(const char node, struct xen_bus_type bus);	120	void xenbus_dev_changed(const char node, struct xen_bus_type bus);
120		121

drivers/xen/xenbus/xenbus_comms.c+0−8

 static int xenbus_irq;
 static struct task_struct *xenbus_task;
-static DECLARE_WORK(probe_work, xenbus_probe);
 static irqreturn_t wake_waiting(int irq, void *unused)
 {
-	if (unlikely(xenstored_ready == 0)) {
-		xenstored_ready = 1;
-		schedule_work(&probe_work);
-	}
 	wake_up(&xb_waitq);
 	return IRQ_HANDLED;
 }

drivers/xen/xenbus/xenbus_probe.c+67−14

@@ -683,29 +683,76 @@ void unregister_xenstore_notifier(struct notifier_block *nb) · 682 unmodified lines
683	}	683	}
684	EXPORT_SYMBOL_GPL(unregister_xenstore_notifier);	684	EXPORT_SYMBOL_GPL(unregister_xenstore_notifier);
685		685
686	void xenbus_probe(struct work_struct *unused)	686	void xenbus_probe(void)
687	{	687	{
688	xenstored_ready = 1;	688	xenstored_ready = 1;
689		689
		690	/*
		691	* In the HVM case, xenbus_init() deferred its call to
		692	* xs_init() in case callbacks were not operational yet.
		693	* So do it now.
		694	*/
		695	if (xen_store_domain_type == XS_HVM)
		696	xs_init();
		697
690	/* Notify others that xenstore is up */	698	/* Notify others that xenstore is up */
691	blocking_notifier_call_chain(&xenstore_chain, 0, NULL);	699	blocking_notifier_call_chain(&xenstore_chain, 0, NULL);
692	}	700	}
693	EXPORT_SYMBOL_GPL(xenbus_probe);
694		701
695	static int __init xenbus_probe_initcall(void)	702	/*
		703	* Returns true when XenStore init must be deferred in order to
		704	* allow the PCI platform device to be initialised, before we
		705	* can actually have event channel interrupts working.
		706	*/
		707	static bool xs_hvm_defer_init_for_callback(void)
696	{	708	{
697	if (!xen_domain())	709	#ifdef CONFIG_XEN_PVHVM
698	return -ENODEV;	710	return xen_store_domain_type == XS_HVM &&
		711	!xen_have_vector_callback;
		712	#else
		713	return false;
		714	#endif
		715	}
699		716
700	if (xen_initial_domain() \|\| xen_hvm_domain())	717	static int __init xenbus_probe_initcall(void)
701	return 0;	718	{
		719	/*
		720	* Probe XenBus here in the XS_PV case, and also XS_HVM unless we
		721	* need to wait for the platform PCI device to come up.
		722	*/
		723	if (xen_store_domain_type == XS_PV \|\|
		724	(xen_store_domain_type == XS_HVM &&
		725	!xs_hvm_defer_init_for_callback()))
		726	xenbus_probe();
702		727
703	xenbus_probe(NULL);
704	return 0;	728	return 0;
705	}	729	}
706
707	device_initcall(xenbus_probe_initcall);	730	device_initcall(xenbus_probe_initcall);
708		731
		732	int xen_set_callback_via(uint64_t via)
		733	{
		734	struct xen_hvm_param a;
		735	int ret;
		736
		737	a.domid = DOMID_SELF;
		738	a.index = HVM_PARAM_CALLBACK_IRQ;
		739	a.value = via;
		740
		741	ret = HYPERVISOR_hvm_op(HVMOP_set_param, &a);
		742	if (ret)
		743	return ret;
		744
		745	/*
		746	* If xenbus_probe_initcall() deferred the xenbus_probe()
		747	* due to the callback not functioning yet, we can do it now.
		748	*/
		749	if (!xenstored_ready && xs_hvm_defer_init_for_callback())
		750	xenbus_probe();
		751
		752	return ret;
		753	}
		754	EXPORT_SYMBOL_GPL(xen_set_callback_via);
		755
709	/* Set up event channel for xenstored which is run as a local process	756	/* Set up event channel for xenstored which is run as a local process
710	* (this is normally used only in dom0)	757	* (this is normally used only in dom0)
711	*/	758	*/
@@ -818,11 +865,17 @@ static int __init xenbus_init(void) · 106 unmodified lines
818	break;	865	break;
819	}	866	}
820		867
821	/* Initialize the interface to xenstore. */	868	/*
822	err = xs_init();	869	* HVM domains may not have a functional callback yet. In that
823	if (err) {	870	* case let xs_init() be called from xenbus_probe(), which will
824	pr_warn("Error initializing xenstore comms: %i\n", err);	871	* get invoked at an appropriate time.
825	goto out_error;	872	*/
		873	if (xen_store_domain_type != XS_HVM) {
		874	err = xs_init();
		875	if (err) {
		876	pr_warn("Error initializing xenstore comms: %i\n", err);
		877	goto out_error;
		878	}
826	}	879	}
827		880
828	if ((xen_store_domain_type != XS_LOCAL) &&	881	if ((xen_store_domain_type != XS_LOCAL) &&

fs/cachefiles/rdwr.c+0−2

 	inode = d_backing_inode(object->backer);
 	ASSERT(S_ISREG(inode->i_mode));
-	ASSERT(inode->i_mapping->a_ops->readpages);
 	/* calculate the shift required to use bmap */
 	shift = PAGE_SHIFT - inode->i_sb->s_blocksize_bits;
 	inode = d_backing_inode(object->backer);
 	ASSERT(S_ISREG(inode->i_mode));
-	ASSERT(inode->i_mapping->a_ops->readpages);
 	/* calculate the shift required to use bmap */
 	shift = PAGE_SHIFT - inode->i_sb->s_blocksize_bits;

fs/cifs/connect.c+1−1

@@ -3740,7 +3740,7 @@ cifs_setup_session(const unsigned int xid, struct cifs_ses *ses, · 3739 unmodified lines
3740		3740
3741	if (!ses->binding) {	3741	if (!ses->binding) {
3742	ses->capabilities = server->capabilities;	3742	ses->capabilities = server->capabilities;
3743	if (linuxExtEnabled == 0)	3743	if (!linuxExtEnabled)
3744	ses->capabilities &= (~server->vals->cap_unix);	3744	ses->capabilities &= (~server->vals->cap_unix);
3745		3745
3746	if (ses->auth_key.response) {	3746	if (ses->auth_key.response) {

fs/cifs/dfs_cache.c+2−1

@@ -1260,7 +1260,8 @@ void dfs_cache_del_vol(const char *fullpath) · 1259 unmodified lines
1260	vi = find_vol(fullpath);	1260	vi = find_vol(fullpath);
1261	spin_unlock(&vol_list_lock);	1261	spin_unlock(&vol_list_lock);
1262		1262
1263	kref_put(&vi->refcnt, vol_release);	1263	if (!IS_ERR(vi))
		1264	kref_put(&vi->refcnt, vol_release);
1264	}	1265	}
1265		1266
1266	/**	1267	/**

fs/cifs/fs_context.c+1−3

 int
 smb3_fs_context_dup(struct smb3_fs_context *new_ctx, struct smb3_fs_context *ctx)
 {
-	int rc = 0;
 	memcpy(new_ctx, ctx, sizeof(*ctx));
 	new_ctx->prepath = NULL;
 	new_ctx->mount_options = NULL;
 	DUP_CTX_STR(nodename);
 	DUP_CTX_STR(iocharset);
-	return rc;
+	return 0;
 }
 static int

fs/cifs/smb2pdu.c+1−1

@@ -3248,7 +3248,7 @@ close_exit: · 3247 unmodified lines
3248	free_rsp_buf(resp_buftype, rsp);	3248	free_rsp_buf(resp_buftype, rsp);
3249		3249
3250	/* retry close in a worker thread if this one is interrupted */	3250	/* retry close in a worker thread if this one is interrupted */
3251	if (rc == -EINTR) {	3251	if (is_interrupt_error(rc)) {
3252	int tmp_rc;	3252	int tmp_rc;
3253		3253
3254	tmp_rc = smb2_handle_cancelled_close(tcon, persistent_fid,	3254	tmp_rc = smb2_handle_cancelled_close(tcon, persistent_fid,

fs/cifs/smb2pdu.h+1−1

@@ -424,7 +424,7 @@ struct smb2_rdma_transform_capabilities_context { · 423 unmodified lines
424	__le16 TransformCount;	424	__le16 TransformCount;
425	__u16 Reserved1;	425	__u16 Reserved1;
426	__u32 Reserved2;	426	__u32 Reserved2;
427	__le16 RDMATransformIds[1];	427	__le16 RDMATransformIds[];
428	} __packed;	428	} __packed;
429		429
430	/* Signing algorithms */	430	/* Signing algorithms */

fs/ext4/ext4_jbd2.c+0−17

@@ -372,20 +372,3 @@ int __ext4_handle_dirty_metadata(const char *where, unsigned int line, · 371 unmodified lines
372	}	372	}
373	return err;	373	return err;
374	}	374	}
375
376	int __ext4_handle_dirty_super(const char *where, unsigned int line,
377	handle_t handle, struct super_block sb)
378	{
379	struct buffer_head *bh = EXT4_SB(sb)->s_sbh;
380	int err = 0;
381
382	ext4_superblock_csum_set(sb);
383	if (ext4_handle_valid(handle)) {
384	err = jbd2_journal_dirty_metadata(handle, bh);
385	if (err)
386	ext4_journal_abort_handle(where, line, __func__,
387	bh, handle, err);
388	} else
389	mark_buffer_dirty(bh);
390	return err;
391	}

fs/ext4/ext4_jbd2.h+0−5

 				 handle_t *handle, struct inode *inode,
 				 struct buffer_head *bh);
-int __ext4_handle_dirty_super(const char *where, unsigned int line,
-			      handle_t *handle, struct super_block *sb);
 #define ext4_journal_get_write_access(handle, bh) \
 	__ext4_journal_get_write_access(__func__, __LINE__, (handle), (bh))
 #define ext4_forget(handle, is_metadata, inode, bh, block_nr) \
 #define ext4_handle_dirty_metadata(handle, inode, bh) \
 	__ext4_handle_dirty_metadata(__func__, __LINE__, (handle), (inode), \
 				     (bh))
-#define ext4_handle_dirty_super(handle, sb) \
-	__ext4_handle_dirty_super(__func__, __LINE__, (handle), (sb))
 handle_t *__ext4_journal_start_sb(struct super_block *sb, unsigned int line,
 				  int type, int blocks, int rsv_blocks,

fs/ext4/fast_commit.c+18−17

 	trace_ext4_fc_track_range(inode, start, end, ret);
 }
-static void ext4_fc_submit_bh(struct super_block *sb)
+static void ext4_fc_submit_bh(struct super_block *sb, bool is_tail)
 {
 	int write_flags = REQ_SYNC;
 	struct buffer_head *bh = EXT4_SB(sb)->s_fc_bh;
-	/* TODO: REQ_FUA | REQ_PREFLUSH is unnecessarily expensive. */
+	/* Add REQ_FUA | REQ_PREFLUSH only its tail */
-	if (test_opt(sb, BARRIER))
+	if (test_opt(sb, BARRIER) && is_tail)
 		write_flags |= REQ_FUA | REQ_PREFLUSH;
 	lock_buffer(bh);
 	set_buffer_dirty(bh);
 		*crc = ext4_chksum(sbi, *crc, tl, sizeof(*tl));
 	if (pad_len > 0)
 		ext4_fc_memzero(sb, tl + 1, pad_len, crc);
-	ext4_fc_submit_bh(sb);
+	ext4_fc_submit_bh(sb, false);
 	ret = jbd2_fc_get_buf(EXT4_SB(sb)->s_journal, &bh);
 	if (ret)
 	tail.fc_crc = cpu_to_le32(crc);
 	ext4_fc_memcpy(sb, dst, &tail.fc_crc, sizeof(tail.fc_crc), NULL);
-	ext4_fc_submit_bh(sb);
+	ext4_fc_submit_bh(sb, true);
 	return 0;
 }
 	list_splice_init(&sbi->s_fc_dentry_q[FC_Q_STAGING],
 				&sbi->s_fc_dentry_q[FC_Q_MAIN]);
 	list_splice_init(&sbi->s_fc_q[FC_Q_STAGING],
-				&sbi->s_fc_q[FC_Q_STAGING]);
+				&sbi->s_fc_q[FC_Q_MAIN]);
 	ext4_clear_mount_flag(sb, EXT4_MF_FC_COMMITTING);
 	ext4_clear_mount_flag(sb, EXT4_MF_FC_INELIGIBLE);
 	entry.len = darg.dname_len;
 	inode = ext4_iget(sb, darg.ino, EXT4_IGET_NORMAL);
-	if (IS_ERR_OR_NULL(inode)) {
+	if (IS_ERR(inode)) {
 		jbd_debug(1, "Inode %d not found", darg.ino);
 		return 0;
 	}
 	old_parent = ext4_iget(sb, darg.parent_ino,
 				EXT4_IGET_NORMAL);
-	if (IS_ERR_OR_NULL(old_parent)) {
+	if (IS_ERR(old_parent)) {
 		jbd_debug(1, "Dir with inode  %d not found", darg.parent_ino);
 		iput(inode);
 		return 0;
 			darg.parent_ino, darg.dname_len);
 	inode = ext4_iget(sb, darg.ino, EXT4_IGET_NORMAL);
-	if (IS_ERR_OR_NULL(inode)) {
+	if (IS_ERR(inode)) {
 		jbd_debug(1, "Inode not found.");
 		return 0;
 	}
 	trace_ext4_fc_replay(sb, tag, ino, 0, 0);
 	inode = ext4_iget(sb, ino, EXT4_IGET_NORMAL);
-	if (!IS_ERR_OR_NULL(inode)) {
+	if (!IS_ERR(inode)) {
 		ext4_ext_clear_bb(inode);
 		iput(inode);
 	}
+	inode = NULL;
 	ext4_fc_record_modified_inode(sb, ino);
 	/* Given that we just wrote the inode on disk, this SHOULD succeed. */
 	inode = ext4_iget(sb, ino, EXT4_IGET_NORMAL);
-	if (IS_ERR_OR_NULL(inode)) {
+	if (IS_ERR(inode)) {
 		jbd_debug(1, "Inode not found.");
 		return -EFSCORRUPTED;
 	}
 		goto out;
 	inode = ext4_iget(sb, darg.ino, EXT4_IGET_NORMAL);
-	if (IS_ERR_OR_NULL(inode)) {
+	if (IS_ERR(inode)) {
 		jbd_debug(1, "inode %d not found.", darg.ino);
 		inode = NULL;
 		ret = -EINVAL;
 		 * dot and dot dot dirents are setup properly.
 		 */
 		dir = ext4_iget(sb, darg.parent_ino, EXT4_IGET_NORMAL);
-		if (IS_ERR_OR_NULL(dir)) {
+		if (IS_ERR(dir)) {
 			jbd_debug(1, "Dir %d not found.", darg.ino);
 			goto out;
 		}
 	inode = ext4_iget(sb, le32_to_cpu(fc_add_ex->fc_ino),
 				EXT4_IGET_NORMAL);
-	if (IS_ERR_OR_NULL(inode)) {
+	if (IS_ERR(inode)) {
 		jbd_debug(1, "Inode not found.");
 		return 0;
 	}
 		le32_to_cpu(lrange->fc_ino), cur, remaining);
 	inode = ext4_iget(sb, le32_to_cpu(lrange->fc_ino), EXT4_IGET_NORMAL);
-	if (IS_ERR_OR_NULL(inode)) {
+	if (IS_ERR(inode)) {
 		jbd_debug(1, "Inode %d not found", le32_to_cpu(lrange->fc_ino));
 		return 0;
 	}
 	for (i = 0; i < state->fc_modified_inodes_used; i++) {
 		inode = ext4_iget(sb, state->fc_modified_inodes[i],
 			EXT4_IGET_NORMAL);
-		if (IS_ERR_OR_NULL(inode)) {
+		if (IS_ERR(inode)) {
 			jbd_debug(1, "Inode %d not found.",
 				state->fc_modified_inodes[i]);
 			continue;
 			if (ret > 0) {
 				path = ext4_find_extent(inode, map.m_lblk, NULL, 0);
-				if (!IS_ERR_OR_NULL(path)) {
+				if (!IS_ERR(path)) {
 					for (j = 0; j < path->p_depth; j++)
 						ext4_mb_mark_bb(inode->i_sb,
 							path[j].p_block, 1, 1);

fs/ext4/file.c+5−2

 	err = ext4_journal_get_write_access(handle, sbi->s_sbh);
 	if (err)
 		goto out_journal;
-	strlcpy(sbi->s_es->s_last_mounted, cp,
+	lock_buffer(sbi->s_sbh);
+	strncpy(sbi->s_es->s_last_mounted, cp,
 		sizeof(sbi->s_es->s_last_mounted));
-	ext4_handle_dirty_super(handle, sb);
+	ext4_superblock_csum_set(sb);
+	unlock_buffer(sbi->s_sbh);
+	ext4_handle_dirty_metadata(handle, NULL, sbi->s_sbh);
 out_journal:
 	ext4_journal_stop(handle);
 out:

fs/ext4/inode.c+5−1

 		err = ext4_journal_get_write_access(handle, EXT4_SB(sb)->s_sbh);
 		if (err)
 			goto out_brelse;
+		lock_buffer(EXT4_SB(sb)->s_sbh);
 		ext4_set_feature_large_file(sb);
+		ext4_superblock_csum_set(sb);
+		unlock_buffer(EXT4_SB(sb)->s_sbh);
 		ext4_handle_sync(handle);
-		err = ext4_handle_dirty_super(handle, sb);
+		err = ext4_handle_dirty_metadata(handle, NULL,
+						 EXT4_SB(sb)->s_sbh);
 	}
 	ext4_update_inode_fsync_trans(handle, inode, need_datasync);
 out_brelse:

fs/ext4/ioctl.c+3−0

 			err = ext4_journal_get_write_access(handle, sbi->s_sbh);
 			if (err)
 				goto pwsalt_err_journal;
+			lock_buffer(sbi->s_sbh);
 			generate_random_uuid(sbi->s_es->s_encrypt_pw_salt);
+			ext4_superblock_csum_set(sb);
+			unlock_buffer(sbi->s_sbh);
 			err = ext4_handle_dirty_metadata(handle, NULL,
 							 sbi->s_sbh);
 		pwsalt_err_journal:

fs/ext4/namei.c+17−10

 	    (le32_to_cpu(sbi->s_es->s_inodes_count))) {
 		/* Insert this inode at the head of the on-disk orphan list */
 		NEXT_ORPHAN(inode) = le32_to_cpu(sbi->s_es->s_last_orphan);
+		lock_buffer(sbi->s_sbh);
 		sbi->s_es->s_last_orphan = cpu_to_le32(inode->i_ino);
+		ext4_superblock_csum_set(sb);
+		unlock_buffer(sbi->s_sbh);
 		dirty = true;
 	}
 	list_add(&EXT4_I(inode)->i_orphan, &sbi->s_orphan);
 	mutex_unlock(&sbi->s_orphan_lock);
 	if (dirty) {
-		err = ext4_handle_dirty_super(handle, sb);
+		err = ext4_handle_dirty_metadata(handle, NULL, sbi->s_sbh);
 		rc = ext4_mark_iloc_dirty(handle, inode, &iloc);
 		if (!err)
 			err = rc;
 			mutex_unlock(&sbi->s_orphan_lock);
 			goto out_brelse;
 		}
+		lock_buffer(sbi->s_sbh);
 		sbi->s_es->s_last_orphan = cpu_to_le32(ino_next);
+		ext4_superblock_csum_set(inode->i_sb);
+		unlock_buffer(sbi->s_sbh);
 		mutex_unlock(&sbi->s_orphan_lock);
-		err = ext4_handle_dirty_super(handle, inode->i_sb);
+		err = ext4_handle_dirty_metadata(handle, NULL, sbi->s_sbh);
 	} else {
 		struct ext4_iloc iloc2;
 		struct inode *i_prev =
 			return retval2;
 		}
 	}
-	brelse(ent->bh);
-	ent->bh = NULL;
 	return retval;
 }
 		}
 	}
+	old_file_type = old.de->file_type;
 	if (IS_DIRSYNC(old.dir) || IS_DIRSYNC(new.dir))
 		ext4_handle_sync(handle);
 	force_reread = (new.dir->i_ino == old.dir->i_ino &&
 			ext4_test_inode_flag(new.dir, EXT4_INODE_INLINE_DATA));
-	old_file_type = old.de->file_type;
 	if (whiteout) {
 		/*
 		 * Do this before adding a new entry, so the old entry is sure
 	retval = 0;
 end_rename:
-	brelse(old.dir_bh);
-	brelse(old.bh);
-	brelse(new.bh);
 	if (whiteout) {
-		if (retval)
+		if (retval) {
+			ext4_setent(handle, &old,
+				old.inode->i_ino, old_file_type);
 			drop_nlink(whiteout);
+		}
 		unlock_new_inode(whiteout);
 		iput(whiteout);
 	}
+	brelse(old.dir_bh);
+	brelse(old.bh);
+	brelse(new.bh);
 	if (handle)
 		ext4_journal_stop(handle);
 	return retval;

fs/ext4/resize.c+16−4

 	EXT4_SB(sb)->s_gdb_count++;
 	ext4_kvfree_array_rcu(o_group_desc);
+	lock_buffer(EXT4_SB(sb)->s_sbh);
 	le16_add_cpu(&es->s_reserved_gdt_blocks, -1);
-	err = ext4_handle_dirty_super(handle, sb);
+	ext4_superblock_csum_set(sb);
+	unlock_buffer(EXT4_SB(sb)->s_sbh);
+	err = ext4_handle_dirty_metadata(handle, NULL, EXT4_SB(sb)->s_sbh);
 	if (err)
 		ext4_std_error(sb, err);
 	return err;
 	reserved_blocks *= blocks_count;
 	do_div(reserved_blocks, 100);
+	lock_buffer(sbi->s_sbh);
 	ext4_blocks_count_set(es, ext4_blocks_count(es) + blocks_count);
 	ext4_free_blocks_count_set(es, ext4_free_blocks_count(es) + free_blocks);
 	le32_add_cpu(&es->s_inodes_count, EXT4_INODES_PER_GROUP(sb) *
 	 * active. */
 	ext4_r_blocks_count_set(es, ext4_r_blocks_count(es) +
 				reserved_blocks);
+	ext4_superblock_csum_set(sb);
+	unlock_buffer(sbi->s_sbh);
 	/* Update the free space counts */
 	percpu_counter_add(&sbi->s_freeclusters_counter,
 	ext4_update_super(sb, flex_gd);
-	err = ext4_handle_dirty_super(handle, sb);
+	err = ext4_handle_dirty_metadata(handle, NULL, sbi->s_sbh);
 exit_journal:
 	err2 = ext4_journal_stop(handle);
 		goto errout;
 	}
+	lock_buffer(EXT4_SB(sb)->s_sbh);
 	ext4_blocks_count_set(es, o_blocks_count + add);
 	ext4_free_blocks_count_set(es, ext4_free_blocks_count(es) + add);
+	ext4_superblock_csum_set(sb);
+	unlock_buffer(EXT4_SB(sb)->s_sbh);
 	ext4_debug("freeing blocks %llu through %llu\n", o_blocks_count,
 		   o_blocks_count + add);
 	/* We add the blocks to the bitmap and set the group need init bit */
 	err = ext4_group_add_blocks(handle, sb, o_blocks_count, add);
 	if (err)
 		goto errout;
-	ext4_handle_dirty_super(handle, sb);
+	ext4_handle_dirty_metadata(handle, NULL, EXT4_SB(sb)->s_sbh);
 	ext4_debug("freed blocks %llu through %llu\n", o_blocks_count,
 		   o_blocks_count + add);
 errout:
 	if (err)
 		goto errout;
+	lock_buffer(sbi->s_sbh);
 	ext4_clear_feature_resize_inode(sb);
 	ext4_set_feature_meta_bg(sb);
 	sbi->s_es->s_first_meta_bg =
 		cpu_to_le32(num_desc_blocks(sb, sbi->s_groups_count));
+	ext4_superblock_csum_set(sb);
+	unlock_buffer(sbi->s_sbh);
-	err = ext4_handle_dirty_super(handle, sb);
+	err = ext4_handle_dirty_metadata(handle, NULL, sbi->s_sbh);
 	if (err) {
 		ext4_std_error(sb, err);
 		goto errout;

fs/ext4/super.c+118−72

 static int ext4_load_journal(struct super_block *, struct ext4_super_block *,
 			     unsigned long journal_devnum);
 static int ext4_show_options(struct seq_file *seq, struct dentry *root);
-static int ext4_commit_super(struct super_block *sb, int sync);
+static void ext4_update_super(struct super_block *sb);
+static int ext4_commit_super(struct super_block *sb);
 static int ext4_mark_recovery_complete(struct super_block *sb,
 					struct ext4_super_block *es);
 static int ext4_clear_journal_err(struct super_block *sb,
 	return EXT4_ERR_UNKNOWN;
 }
-static void __save_error_info(struct super_block *sb, int error,
+static void save_error_info(struct super_block *sb, int error,
-			      __u32 ino, __u64 block,
+			    __u32 ino, __u64 block,
-			      const char *func, unsigned int line)
+			    const char *func, unsigned int line)
 {
 	struct ext4_sb_info *sbi = EXT4_SB(sb);
-	EXT4_SB(sb)->s_mount_state |= EXT4_ERROR_FS;
-	if (bdev_read_only(sb->s_bdev))
-		return;
 	/* We default to EFSCORRUPTED error... */
 	if (error == 0)
 		error = EFSCORRUPTED;
 	spin_unlock(&sbi->s_error_lock);
 }
-static void save_error_info(struct super_block *sb, int error,
-			    __u32 ino, __u64 block,
-			    const char *func, unsigned int line)
-{
-	__save_error_info(sb, error, ino, block, func, line);
-	if (!bdev_read_only(sb->s_bdev))
-		ext4_commit_super(sb, 1);
-}
 /* Deal with the reporting of failure conditions on a filesystem such as
  * inconsistencies detected or read IO failures.
  *
  * used to deal with unrecoverable failures such as journal IO errors or ENOMEM
  * at a critical moment in log management.
  */
-static void ext4_handle_error(struct super_block *sb, bool force_ro)
+static void ext4_handle_error(struct super_block *sb, bool force_ro, int error,
+			      __u32 ino, __u64 block,
+			      const char *func, unsigned int line)
 {
 	journal_t *journal = EXT4_SB(sb)->s_journal;
+	bool continue_fs = !force_ro && test_opt(sb, ERRORS_CONT);
+	EXT4_SB(sb)->s_mount_state |= EXT4_ERROR_FS;
 	if (test_opt(sb, WARN_ON_ERROR))
 		WARN_ON_ONCE(1);
-	if (sb_rdonly(sb) || (!force_ro && test_opt(sb, ERRORS_CONT)))
+	if (!continue_fs && !sb_rdonly(sb)) {
+		ext4_set_mount_flag(sb, EXT4_MF_FS_ABORTED);
+		if (journal)
+			jbd2_journal_abort(journal, -EIO);
+	}
+	if (!bdev_read_only(sb->s_bdev)) {
+		save_error_info(sb, error, ino, block, func, line);
+		/*
+		 * In case the fs should keep running, we need to writeout
+		 * superblock through the journal. Due to lock ordering
+		 * constraints, it may not be safe to do it right here so we
+		 * defer superblock flushing to a workqueue.
+		 */
+		if (continue_fs)
+			schedule_work(&EXT4_SB(sb)->s_error_work);
+		else
+			ext4_commit_super(sb);
+	}
+	if (sb_rdonly(sb) || continue_fs)
 		return;
-	ext4_set_mount_flag(sb, EXT4_MF_FS_ABORTED);
-	if (journal)
-		jbd2_journal_abort(journal, -EIO);
 	/*
 	 * We force ERRORS_RO behavior when system is rebooting. Otherwise we
 	 * could panic during 'reboot -f' as the underlying device got already
 {
 	struct ext4_sb_info *sbi = container_of(work, struct ext4_sb_info,
 						s_error_work);
+	journal_t *journal = sbi->s_journal;
+	handle_t *handle;
-	ext4_commit_super(sbi->s_sb, 1);
+	/*
+	 * If the journal is still running, we have to write out superblock
+	 * through the journal to avoid collisions of other journalled sb
+	 * updates.
+	 *
+	 * We use directly jbd2 functions here to avoid recursing back into
+	 * ext4 error handling code during handling of previous errors.
+	 */
+	if (!sb_rdonly(sbi->s_sb) && journal) {
+		handle = jbd2_journal_start(journal, 1);
+		if (IS_ERR(handle))
+			goto write_directly;
+		if (jbd2_journal_get_write_access(handle, sbi->s_sbh)) {
+			jbd2_journal_stop(handle);
+			goto write_directly;
+		}
+		ext4_update_super(sbi->s_sb);
+		if (jbd2_journal_dirty_metadata(handle, sbi->s_sbh)) {
+			jbd2_journal_stop(handle);
+			goto write_directly;
+		}
+		jbd2_journal_stop(handle);
+		return;
+	}
+write_directly:
+	/*
+	 * Write through journal failed. Write sb directly to get error info
+	 * out and hope for the best.
+	 */
+	ext4_commit_super(sbi->s_sb);
 }
 #define ext4_error_ratelimit(sb)					\
 		       sb->s_id, function, line, current->comm, &vaf);
 		va_end(args);
 	}
-	save_error_info(sb, error, 0, block, function, line);
+	ext4_handle_error(sb, force_ro, error, 0, block, function, line);
-	ext4_handle_error(sb, force_ro);
 }
 void __ext4_error_inode(struct inode *inode, const char *function,
 			       current->comm, &vaf);
 		va_end(args);
 	}
-	save_error_info(inode->i_sb, error, inode->i_ino, block,
+	ext4_handle_error(inode->i_sb, false, error, inode->i_ino, block,
-			function, line);
+			  function, line);
-	ext4_handle_error(inode->i_sb, false);
 }
 void __ext4_error_file(struct file *file, const char *function,
 			       current->comm, path, &vaf);
 		va_end(args);
 	}
-	save_error_info(inode->i_sb, EFSCORRUPTED, inode->i_ino, block,
+	ext4_handle_error(inode->i_sb, false, EFSCORRUPTED, inode->i_ino, block,
-			function, line);
+			  function, line);
-	ext4_handle_error(inode->i_sb, false);
 }
 const char *ext4_decode_error(struct super_block *sb, int errno,
 		       sb->s_id, function, line, errstr);
 	}
-	save_error_info(sb, -errno, 0, 0, function, line);
+	ext4_handle_error(sb, false, -errno, 0, 0, function, line);
-	ext4_handle_error(sb, false);
 }
 void __ext4_msg(struct super_block *sb,
 	if (test_opt(sb, ERRORS_CONT)) {
 		if (test_opt(sb, WARN_ON_ERROR))
 			WARN_ON_ONCE(1);
-		__save_error_info(sb, EFSCORRUPTED, ino, block, function, line);
+		EXT4_SB(sb)->s_mount_state |= EXT4_ERROR_FS;
-		schedule_work(&EXT4_SB(sb)->s_error_work);
+		if (!bdev_read_only(sb->s_bdev)) {
+			save_error_info(sb, EFSCORRUPTED, ino, block, function,
+					line);
+			schedule_work(&EXT4_SB(sb)->s_error_work);
+		}
 		return;
 	}
 	ext4_unlock_group(sb, grp);
-	save_error_info(sb, EFSCORRUPTED, ino, block, function, line);
+	ext4_handle_error(sb, false, EFSCORRUPTED, ino, block, function, line);
-	ext4_handle_error(sb, false);
 	/*
 	 * We only get here in the ERRORS_RO case; relocking the group
 	 * may be dangerous, but nothing bad will happen since the
 		es->s_state = cpu_to_le16(sbi->s_mount_state);
 	}
 	if (!sb_rdonly(sb))
-		ext4_commit_super(sb, 1);
+		ext4_commit_super(sb);
 	rcu_read_lock();
 	group_desc = rcu_dereference(sbi->s_group_desc);
 	if (sbi->s_journal)
 		ext4_set_feature_journal_needs_recovery(sb);
-	err = ext4_commit_super(sb, 1);
+	err = ext4_commit_super(sb);
 done:
 	if (test_opt(sb, DEBUG))
 		printk(KERN_INFO "[EXT4 FS bs=%lu, gc=%u, "
 	if (DUMMY_ENCRYPTION_ENABLED(sbi) && !sb_rdonly(sb) &&
 	    !ext4_has_feature_encrypt(sb)) {
 		ext4_set_feature_encrypt(sb);
-		ext4_commit_super(sb, 1);
+		ext4_commit_super(sb);
 	}
 	/*
 		es->s_journal_dev = cpu_to_le32(journal_devnum);
 		/* Make sure we flush the recovery flag to disk. */
-		ext4_commit_super(sb, 1);
+		ext4_commit_super(sb);
 	}
 	return 0;
 	return err;
 }
-static int ext4_commit_super(struct super_block *sb, int sync)
+/* Copy state of EXT4_SB(sb) into buffer for on-disk superblock */
+static void ext4_update_super(struct super_block *sb)
 {
 	struct ext4_sb_info *sbi = EXT4_SB(sb);
-	struct ext4_super_block *es = EXT4_SB(sb)->s_es;
+	struct ext4_super_block *es = sbi->s_es;
-	struct buffer_head *sbh = EXT4_SB(sb)->s_sbh;
+	struct buffer_head *sbh = sbi->s_sbh;
-	int error = 0;
-	if (!sbh || block_device_ejected(sb))
-		return error;
+	lock_buffer(sbh);
 	/*
 	 * If the file system is mounted read-only, don't update the
 	 * superblock write time.  This avoids updating the superblock
 	if (!(sb->s_flags & SB_RDONLY))
 		ext4_update_tstamp(es, s_wtime);
 	es->s_kbytes_written =
-		cpu_to_le64(EXT4_SB(sb)->s_kbytes_written +
+		cpu_to_le64(sbi->s_kbytes_written +
 		    ((part_stat_read(sb->s_bdev, sectors[STAT_WRITE]) -
-		      EXT4_SB(sb)->s_sectors_written_start) >> 1));
+		      sbi->s_sectors_written_start) >> 1));
-	if (percpu_counter_initialized(&EXT4_SB(sb)->s_freeclusters_counter))
+	if (percpu_counter_initialized(&sbi->s_freeclusters_counter))
 		ext4_free_blocks_count_set(es,
-			EXT4_C2B(EXT4_SB(sb), percpu_counter_sum_positive(
+			EXT4_C2B(sbi, percpu_counter_sum_positive(
-				&EXT4_SB(sb)->s_freeclusters_counter)));
+				&sbi->s_freeclusters_counter)));
-	if (percpu_counter_initialized(&EXT4_SB(sb)->s_freeinodes_counter))
+	if (percpu_counter_initialized(&sbi->s_freeinodes_counter))
 		es->s_free_inodes_count =
 			cpu_to_le32(percpu_counter_sum_positive(
-				&EXT4_SB(sb)->s_freeinodes_counter));
+				&sbi->s_freeinodes_counter));
 	/* Copy error information to the on-disk superblock */
 	spin_lock(&sbi->s_error_lock);
 	if (sbi->s_add_error_count > 0) {
 	}
 	spin_unlock(&sbi->s_error_lock);
-	BUFFER_TRACE(sbh, "marking dirty");
 	ext4_superblock_csum_set(sb);
-	if (sync)
+	unlock_buffer(sbh);
-		lock_buffer(sbh);
+}
+static int ext4_commit_super(struct super_block *sb)
+{
+	struct buffer_head *sbh = EXT4_SB(sb)->s_sbh;
+	int error = 0;
+	if (!sbh || block_device_ejected(sb))
+		return error;
+	ext4_update_super(sb);
 	if (buffer_write_io_error(sbh) || !buffer_uptodate(sbh)) {
 		/*
 		 * Oh, dear.  A previous attempt to write the
 		clear_buffer_write_io_error(sbh);
 		set_buffer_uptodate(sbh);
 	}
+	BUFFER_TRACE(sbh, "marking dirty");
 	mark_buffer_dirty(sbh);
-	if (sync) {
+	error = __sync_dirty_buffer(sbh,
-		unlock_buffer(sbh);
+		REQ_SYNC | (test_opt(sb, BARRIER) ? REQ_FUA : 0));
-		error = __sync_dirty_buffer(sbh,
+	if (buffer_write_io_error(sbh)) {
-			REQ_SYNC | (test_opt(sb, BARRIER) ? REQ_FUA : 0));
+		ext4_msg(sb, KERN_ERR, "I/O error while writing "
-		if (buffer_write_io_error(sbh)) {
+		       "superblock");
-			ext4_msg(sb, KERN_ERR, "I/O error while writing "
+		clear_buffer_write_io_error(sbh);
-			       "superblock");
+		set_buffer_uptodate(sbh);
-			clear_buffer_write_io_error(sbh);
-			set_buffer_uptodate(sbh);
-		}
 	}
 	return error;
 }
 	if (ext4_has_feature_journal_needs_recovery(sb) && sb_rdonly(sb)) {
 		ext4_clear_feature_journal_needs_recovery(sb);
-		ext4_commit_super(sb, 1);
+		ext4_commit_super(sb);
 	}
 out:
 	jbd2_journal_unlock_updates(journal);
 		EXT4_SB(sb)->s_mount_state |= EXT4_ERROR_FS;
 		es->s_state |= cpu_to_le16(EXT4_ERROR_FS);
-		ext4_commit_super(sb, 1);
+		ext4_commit_super(sb);
 		jbd2_journal_clear_err(journal);
 		jbd2_journal_update_sb_errno(journal);
 		ext4_clear_feature_journal_needs_recovery(sb);
 	}
-	error = ext4_commit_super(sb, 1);
+	error = ext4_commit_super(sb);
 out:
 	if (journal)
 		/* we rely on upper layer to stop further updates */
 		ext4_set_feature_journal_needs_recovery(sb);
 	}
-	ext4_commit_super(sb, 1);
+	ext4_commit_super(sb);
 	return 0;
 }
 	}
 	if (sbi->s_journal == NULL && !(old_sb_flags & SB_RDONLY)) {
-		err = ext4_commit_super(sb, 1);
+		err = ext4_commit_super(sb);
 		if (err)
 			goto restore_opts;
 	}

fs/ext4/xattr.c+4−1

 	BUFFER_TRACE(EXT4_SB(sb)->s_sbh, "get_write_access");
 	if (ext4_journal_get_write_access(handle, EXT4_SB(sb)->s_sbh) == 0) {
+		lock_buffer(EXT4_SB(sb)->s_sbh);
 		ext4_set_feature_xattr(sb);
-		ext4_handle_dirty_super(handle, sb);
+		ext4_superblock_csum_set(sb);
+		unlock_buffer(EXT4_SB(sb)->s_sbh);
+		ext4_handle_dirty_metadata(handle, NULL, EXT4_SB(sb)->s_sbh);
 	}
 }

fs/io_uring.c+41−5

@@ -354,6 +354,7 @@ struct io_ring_ctx { · 353 unmodified lines
354	unsigned cq_entries;	354	unsigned cq_entries;
355	unsigned cq_mask;	355	unsigned cq_mask;
356	atomic_t cq_timeouts;	356	atomic_t cq_timeouts;
		357	unsigned cq_last_tm_flush;
357	unsigned long cq_check_overflow;	358	unsigned long cq_check_overflow;
358	struct wait_queue_head cq_wait;	359	struct wait_queue_head cq_wait;
359	struct fasync_struct *cq_fasync;	360	struct fasync_struct *cq_fasync;
@@ -1106,6 +1107,9 @@ static void io_sq_thread_drop_mm_files(void) · 746 unmodified lines
1106		1107
1107	static int __io_sq_thread_acquire_files(struct io_ring_ctx *ctx)	1108	static int __io_sq_thread_acquire_files(struct io_ring_ctx *ctx)
1108	{	1109	{
		1110	if (current->flags & PF_EXITING)
		1111	return -EFAULT;
		1112
1109	if (!current->files) {	1113	if (!current->files) {
1110	struct files_struct *files;	1114	struct files_struct *files;
1111	struct nsproxy *nsproxy;	1115	struct nsproxy *nsproxy;
@@ -1133,6 +1137,8 @@ static int __io_sq_thread_acquire_mm(struct io_ring_ctx *ctx) · 21 unmodified lines
1133	{	1137	{
1134	struct mm_struct *mm;	1138	struct mm_struct *mm;
1135		1139
		1140	if (current->flags & PF_EXITING)
		1141	return -EFAULT;
1136	if (current->mm)	1142	if (current->mm)
1137	return 0;	1143	return 0;
1138		1144
@@ -1634,19 +1640,38 @@ static void __io_queue_deferred(struct io_ring_ctx *ctx) · 495 unmodified lines
1634		1640
1635	static void io_flush_timeouts(struct io_ring_ctx *ctx)	1641	static void io_flush_timeouts(struct io_ring_ctx *ctx)
1636	{	1642	{
1637	while (!list_empty(&ctx->timeout_list)) {	1643	u32 seq;
		1644
		1645	if (list_empty(&ctx->timeout_list))
		1646	return;
		1647
		1648	seq = ctx->cached_cq_tail - atomic_read(&ctx->cq_timeouts);
		1649
		1650	do {
		1651	u32 events_needed, events_got;
1638	struct io_kiocb *req = list_first_entry(&ctx->timeout_list,	1652	struct io_kiocb *req = list_first_entry(&ctx->timeout_list,
1639	struct io_kiocb, timeout.list);	1653	struct io_kiocb, timeout.list);
1640		1654
1641	if (io_is_timeout_noseq(req))	1655	if (io_is_timeout_noseq(req))
1642	break;	1656	break;
1643	if (req->timeout.target_seq != ctx->cached_cq_tail	1657
1644	- atomic_read(&ctx->cq_timeouts))	1658	/*
		1659	* Since seq can easily wrap around over time, subtract
		1660	* the last seq at which timeouts were flushed before comparing.
		1661	* Assuming not more than 2^31-1 events have happened since,
		1662	* these subtractions won't have wrapped, so we can check if
		1663	* target is in [last_seq, current_seq] by comparing the two.
		1664	*/
		1665	events_needed = req->timeout.target_seq - ctx->cq_last_tm_flush;
		1666	events_got = seq - ctx->cq_last_tm_flush;
		1667	if (events_got < events_needed)
1645	break;	1668	break;
1646		1669
1647	list_del_init(&req->timeout.list);	1670	list_del_init(&req->timeout.list);
1648	io_kill_timeout(req);	1671	io_kill_timeout(req);
1649	}	1672	} while (!list_empty(&ctx->timeout_list));
		1673
		1674	ctx->cq_last_tm_flush = seq;
1650	}	1675	}
1651		1676
1652	static void io_commit_cqring(struct io_ring_ctx *ctx)	1677	static void io_commit_cqring(struct io_ring_ctx *ctx)
@@ -5832,6 +5857,12 @@ static int io_timeout(struct io_kiocb *req) · 4179 unmodified lines
5832	tail = ctx->cached_cq_tail - atomic_read(&ctx->cq_timeouts);	5857	tail = ctx->cached_cq_tail - atomic_read(&ctx->cq_timeouts);
5833	req->timeout.target_seq = tail + off;	5858	req->timeout.target_seq = tail + off;
5834		5859
		5860	/* Update the last seq here in case io_flush_timeouts() hasn't.
		5861	* This is safe because ->completion_lock is held, and submissions
		5862	* and completions are never mixed in the same ->completion_lock section.
		5863	*/
		5864	ctx->cq_last_tm_flush = tail;
		5865
5835	/*	5866	/*
5836	* Insertion sort, ensuring the first entry in the list is always	5867	* Insertion sort, ensuring the first entry in the list is always
5837	* the one we need first.	5868	* the one we need first.
@@ -7056,6 +7087,7 @@ static int io_sq_thread(void *data) · 1218 unmodified lines
7056		7087
7057	if (sqt_spin \|\| !time_after(jiffies, timeout)) {	7088	if (sqt_spin \|\| !time_after(jiffies, timeout)) {
7058	io_run_task_work();	7089	io_run_task_work();
		7090	io_sq_thread_drop_mm_files();
7059	cond_resched();	7091	cond_resched();
7060	if (sqt_spin)	7092	if (sqt_spin)
7061	timeout = jiffies + sqd->sq_thread_idle;	7093	timeout = jiffies + sqd->sq_thread_idle;
@@ -7093,6 +7125,7 @@ static int io_sq_thread(void *data) · 31 unmodified lines
7093	}	7125	}
7094		7126
7095	io_run_task_work();	7127	io_run_task_work();
		7128	io_sq_thread_drop_mm_files();
7096		7129
7097	if (cur_css)	7130	if (cur_css)
7098	io_sq_thread_unassociate_blkcg();	7131	io_sq_thread_unassociate_blkcg();
@@ -8888,7 +8921,8 @@ static void io_disable_sqo_submit(struct io_ring_ctx *ctx) · 1789 unmodified lines
8888	mutex_unlock(&ctx->uring_lock);	8921	mutex_unlock(&ctx->uring_lock);
8889		8922
8890	/* make sure callers enter the ring to get error */	8923	/* make sure callers enter the ring to get error */
8891	io_ring_set_wakeup_flag(ctx);	8924	if (ctx->rings)
		8925	io_ring_set_wakeup_flag(ctx);
8892	}	8926	}
8893		8927
8894	/*	8928	/*
@@ -9067,6 +9101,7 @@ void __io_uring_task_cancel(void) · 172 unmodified lines
9067	finish_wait(&tctx->wait, &wait);	9101	finish_wait(&tctx->wait, &wait);
9068	} while (1);	9102	} while (1);
9069		9103
		9104	finish_wait(&tctx->wait, &wait);
9070	atomic_dec(&tctx->in_idle);	9105	atomic_dec(&tctx->in_idle);
9071		9106
9072	io_uring_remove_task_files(tctx);	9107	io_uring_remove_task_files(tctx);
@@ -9700,6 +9735,7 @@ static int io_uring_create(unsigned entries, struct io_uring_params *p, · 627 unmodified lines
9700	*/	9735	*/
9701	ret = io_uring_install_fd(ctx, file);	9736	ret = io_uring_install_fd(ctx, file);
9702	if (ret < 0) {	9737	if (ret < 0) {
		9738	io_disable_sqo_submit(ctx);
9703	/* fput will clean it up */	9739	/* fput will clean it up */
9704	fput(file);	9740	fput(file);
9705	return ret;	9741	return ret;

fs/namespace.c+5−2

 {
 	struct mount *mnt = real_mount(path->mnt);
-	if (flags & ~(MNT_FORCE | MNT_DETACH | MNT_EXPIRE | UMOUNT_NOFOLLOW))
-		return -EINVAL;
 	if (!may_mount())
 		return -EPERM;
 	if (path->dentry != path->mnt->mnt_root)
 	return 0;
 }
+// caller is responsible for flags being sane
 int path_umount(struct path *path, int flags)
 {
 	struct mount *mnt = real_mount(path->mnt);
 	struct path path;
 	int ret;
+	// basic validity checks done first
+	if (flags & ~(MNT_FORCE | MNT_DETACH | MNT_EXPIRE | UMOUNT_NOFOLLOW))
+		return -EINVAL;
 	if (!(flags & UMOUNT_NOFOLLOW))
 		lookup_flags |= LOOKUP_FOLLOW;
 	ret = user_path_at(AT_FDCWD, name, lookup_flags, &path);

fs/nfsd/nfs3xdr.c+6−1

 	if (isdotent(name, namlen)) {
 		if (namlen == 2) {
 			dchild = dget_parent(dparent);
-			/* filesystem root - cannot return filehandle for ".." */
+			/*
+			 * Don't return filehandle for ".." if we're at
+			 * the filesystem or export root:
+			 */
 			if (dchild == dparent)
 				goto out;
+			if (dparent == exp->ex_path.dentry)
+				goto out;
 		} else
 			dchild = dget(dparent);
 	} else

fs/proc/task_mmu.c+30−23

 };
 #ifdef CONFIG_MEM_SOFT_DIRTY
+#define is_cow_mapping(flags) (((flags) & (VM_SHARED | VM_MAYWRITE)) == VM_MAYWRITE)
+static inline bool pte_is_pinned(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
+{
+	struct page *page;
+	if (!pte_write(pte))
+		return false;
+	if (!is_cow_mapping(vma->vm_flags))
+		return false;
+	if (likely(!atomic_read(&vma->vm_mm->has_pinned)))
+		return false;
+	page = vm_normal_page(vma, addr, pte);
+	if (!page)
+		return false;
+	return page_maybe_dma_pinned(page);
+}
 static inline void clear_soft_dirty(struct vm_area_struct *vma,
 		unsigned long addr, pte_t *pte)
 {
 	if (pte_present(ptent)) {
 		pte_t old_pte;
+		if (pte_is_pinned(vma, addr, ptent))
+			return;
 		old_pte = ptep_modify_prot_start(vma, addr, pte);
 		ptent = pte_wrprotect(old_pte);
 		ptent = pte_clear_soft_dirty(ptent);
 			.type = type,
 		};
+		if (mmap_write_lock_killable(mm)) {
+			count = -EINTR;
+			goto out_mm;
+		}
 		if (type == CLEAR_REFS_MM_HIWATER_RSS) {
-			if (mmap_write_lock_killable(mm)) {
-				count = -EINTR;
-				goto out_mm;
-			}
 			/*
 			 * Writing 5 to /proc/pid/clear_refs resets the peak
 			 * resident set size to this mm's current rss value.
 			 */
 			reset_mm_hiwater_rss(mm);
-			mmap_write_unlock(mm);
+			goto out_unlock;
-			goto out_mm;
 		}
-		if (mmap_read_lock_killable(mm)) {
-			count = -EINTR;
-			goto out_mm;
-		}
 		tlb_gather_mmu(&tlb, mm, 0, -1);
 		if (type == CLEAR_REFS_SOFT_DIRTY) {
 			for (vma = mm->mmap; vma; vma = vma->vm_next) {
 				if (!(vma->vm_flags & VM_SOFTDIRTY))
 					continue;
-				mmap_read_unlock(mm);
+				vma->vm_flags &= ~VM_SOFTDIRTY;
-				if (mmap_write_lock_killable(mm)) {
+				vma_set_page_prot(vma);
-					count = -EINTR;
-					goto out_mm;
-				}
-				for (vma = mm->mmap; vma; vma = vma->vm_next) {
-					vma->vm_flags &= ~VM_SOFTDIRTY;
-					vma_set_page_prot(vma);
-				}
-				mmap_write_downgrade(mm);
-				break;
 			}
 			mmu_notifier_range_init(&range, MMU_NOTIFY_SOFT_DIRTY,
 		if (type == CLEAR_REFS_SOFT_DIRTY)
 			mmu_notifier_invalidate_range_end(&range);
 		tlb_finish_mmu(&tlb, 0, -1);
-		mmap_read_unlock(mm);
+out_unlock:
+		mmap_write_unlock(mm);
 out_mm:
 		mmput(mm);
 	}

include/asm-generic/bitops/atomic.h+3−3

@@ -11,19 +11,19 @@ · 10 unmodified lines
11	* See Documentation/atomic_bitops.txt for details.	11	* See Documentation/atomic_bitops.txt for details.
12	*/	12	*/
13		13
14	static inline void set_bit(unsigned int nr, volatile unsigned long *p)	14	static __always_inline void set_bit(unsigned int nr, volatile unsigned long *p)
15	{	15	{
16	p += BIT_WORD(nr);	16	p += BIT_WORD(nr);
17	atomic_long_or(BIT_MASK(nr), (atomic_long_t *)p);	17	atomic_long_or(BIT_MASK(nr), (atomic_long_t *)p);
18	}	18	}
19		19
20	static inline void clear_bit(unsigned int nr, volatile unsigned long *p)	20	static __always_inline void clear_bit(unsigned int nr, volatile unsigned long *p)
21	{	21	{
22	p += BIT_WORD(nr);	22	p += BIT_WORD(nr);
23	atomic_long_andnot(BIT_MASK(nr), (atomic_long_t *)p);	23	atomic_long_andnot(BIT_MASK(nr), (atomic_long_t *)p);
24	}	24	}
25		25
26	static inline void change_bit(unsigned int nr, volatile unsigned long *p)	26	static __always_inline void change_bit(unsigned int nr, volatile unsigned long *p)
27	{	27	{
28	p += BIT_WORD(nr);	28	p += BIT_WORD(nr);
29	atomic_long_xor(BIT_MASK(nr), (atomic_long_t *)p);	29	atomic_long_xor(BIT_MASK(nr), (atomic_long_t *)p);

include/linux/compiler-gcc.h+6−0

 /* https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58145 */
 #if GCC_VERSION < 40900
 # error Sorry, your version of GCC is too old - please use 4.9 or newer.
+#elif defined(CONFIG_ARM64) && GCC_VERSION < 50100
+/*
+ * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63293
+ * https://lore.kernel.org/r/20210107111841.GN1551@shell.armlinux.org.uk
+ */
+# error Sorry, your version of GCC is too old - please use 5.1 or newer.
 #endif
 /*

include/linux/dm-bufio.h+1−0

@@ -150,6 +150,7 @@ void dm_bufio_set_minimum_buffers(struct dm_bufio_client *c, unsigned n); · 149 unmodified lines
150		150
151	unsigned dm_bufio_get_block_size(struct dm_bufio_client *c);	151	unsigned dm_bufio_get_block_size(struct dm_bufio_client *c);
152	sector_t dm_bufio_get_device_size(struct dm_bufio_client *c);	152	sector_t dm_bufio_get_device_size(struct dm_bufio_client *c);
		153	struct dm_io_client dm_bufio_get_dm_io_client(struct dm_bufio_client c);
153	sector_t dm_bufio_get_block_number(struct dm_buffer *b);	154	sector_t dm_bufio_get_block_number(struct dm_buffer *b);
154	void dm_bufio_get_block_data(struct dm_buffer b);	155	void dm_bufio_get_block_data(struct dm_buffer b);
155	void dm_bufio_get_aux_data(struct dm_buffer b);	156	void dm_bufio_get_aux_data(struct dm_buffer b);

include/linux/kasan.h+5−1

 #define KASAN_SHADOW_INIT 0
 #endif
+#ifndef PTE_HWTABLE_PTRS
+#define PTE_HWTABLE_PTRS 0
+#endif
 extern unsigned char kasan_early_shadow_page[PAGE_SIZE];
-extern pte_t kasan_early_shadow_pte[PTRS_PER_PTE];
+extern pte_t kasan_early_shadow_pte[PTRS_PER_PTE + PTE_HWTABLE_PTRS];
 extern pmd_t kasan_early_shadow_pmd[PTRS_PER_PMD];
 extern pud_t kasan_early_shadow_pud[PTRS_PER_PUD];
 extern p4d_t kasan_early_shadow_p4d[MAX_PTRS_PER_P4D];

include/linux/mdio-bitbang.h+3−0

@@ -35,6 +35,9 @@ struct mdiobb_ctrl { · 34 unmodified lines
35	const struct mdiobb_ops *ops;	35	const struct mdiobb_ops *ops;
36	};	36	};
37		37
		38	int mdiobb_read(struct mii_bus *bus, int phy, int reg);
		39	int mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val);
		40
38	/* The returned bus is not yet registered with the phy layer. */	41	/* The returned bus is not yet registered with the phy layer. */
39	struct mii_bus alloc_mdio_bitbang(struct mdiobb_ctrl ctrl);	42	struct mii_bus alloc_mdio_bitbang(struct mdiobb_ctrl ctrl);
40		43

include/linux/memcontrol.h+1−1

@@ -665,7 +665,7 @@ static inline struct lruvec mem_cgroup_page_lruvec(struct page page, · 664 unmodified lines
665	{	665	{
666	struct mem_cgroup *memcg = page_memcg(page);	666	struct mem_cgroup *memcg = page_memcg(page);
667		667
668	VM_WARN_ON_ONCE_PAGE(!memcg, page);	668	VM_WARN_ON_ONCE_PAGE(!memcg && !mem_cgroup_disabled(), page);
669	return mem_cgroup_lruvec(memcg, pgdat);	669	return mem_cgroup_lruvec(memcg, pgdat);
670	}	670	}
671		671

include/linux/perf/arm_pmu.h+0−2

@@ -163,8 +163,6 @@ int arm_pmu_acpi_probe(armpmu_init_fn init_fn); · 162 unmodified lines
163	static inline int arm_pmu_acpi_probe(armpmu_init_fn init_fn) { return 0; }	163	static inline int arm_pmu_acpi_probe(armpmu_init_fn init_fn) { return 0; }
164	#endif	164	#endif
165		165
166	bool arm_pmu_irq_is_nmi(void);
167
168	/* Internal functions only for core arm_pmu code */	166	/* Internal functions only for core arm_pmu code */
169	struct arm_pmu *armpmu_alloc(void);	167	struct arm_pmu *armpmu_alloc(void);
170	struct arm_pmu *armpmu_alloc_atomic(void);	168	struct arm_pmu *armpmu_alloc_atomic(void);

include/linux/usb/usbnet.h+2−0

@@ -81,6 +81,8 @@ struct usbnet { · 80 unmodified lines
81	# define EVENT_LINK_CHANGE 11	81	# define EVENT_LINK_CHANGE 11
82	# define EVENT_SET_RX_MODE 12	82	# define EVENT_SET_RX_MODE 12
83	# define EVENT_NO_IP_ALIGN 13	83	# define EVENT_NO_IP_ALIGN 13
		84	u32 rx_speed; /* in bps - NOT Mbps */
		85	u32 tx_speed; /* in bps - NOT Mbps */
84	};	86	};
85		87
86	static inline struct usb_driver driver_of(struct usb_interface intf)	88	static inline struct usb_driver driver_of(struct usb_interface intf)

include/net/cfg80211.h+4−1

 /**
- * @struct cfg80211_sar_chan_ranges - sar frequency ranges
+ * struct cfg80211_sar_freq_ranges - sar frequency ranges
  * @start_freq:  start range edge frequency
  * @end_freq:    end range edge frequency
  */
  *	This callback may sleep.
  * @reset_tid_config: Reset TID specific configuration for the peer, for the
  *	given TIDs. This callback may sleep.
+ *
+ * @set_sar_specs: Update the SAR (TX power) settings.
  */
 struct cfg80211_ops {
 	int	(*suspend)(struct wiphy *wiphy, struct cfg80211_wowlan *wow);
  * @max_data_retry_count: maximum supported per TID retry count for
  *	configuration through the %NL80211_TID_CONFIG_ATTR_RETRY_SHORT and
  *	%NL80211_TID_CONFIG_ATTR_RETRY_LONG attributes
+ * @sar_capa: SAR control capabilities
  */
 struct wiphy {
 	/* assign these fields before you register the wiphy */

include/net/inet_connection_sock.h+3−0

  * @icsk_ext_hdr_len:	   Network protocol overhead (IP/IPv6 options)
  * @icsk_ack:		   Delayed ACK control data
  * @icsk_mtup;		   MTU probing control data
+ * @icsk_probes_tstamp:    Probe timestamp (cleared by non-zero window ack)
+ * @icsk_user_timeout:	   TCP_USER_TIMEOUT value
  */
 struct inet_connection_sock {
 	/* inet_sock has to be the first member! */
 		u32		  probe_timestamp;
 	} icsk_mtup;
+	u32			  icsk_probes_tstamp;
 	u32			  icsk_user_timeout;
 	u64			  icsk_ca_priv[104 / sizeof(u64)];

include/net/mac80211.h+1−0

@@ -3880,6 +3880,7 @@ enum ieee80211_reconfig_type { · 3879 unmodified lines
3880	* This callback may sleep.	3880	* This callback may sleep.
3881	* @sta_set_4addr: Called to notify the driver when a station starts/stops using	3881	* @sta_set_4addr: Called to notify the driver when a station starts/stops using
3882	* 4-address mode	3882	* 4-address mode
		3883	* @set_sar_specs: Update the SAR (TX power) settings.
3883	*/	3884	*/
3884	struct ieee80211_ops {	3885	struct ieee80211_ops {
3885	void (tx)(struct ieee80211_hw hw,	3886	void (tx)(struct ieee80211_hw hw,

include/net/sock.h+12−5

 	sk->sk_txhash = net_tx_rndhash();
 }
-static inline void sk_rethink_txhash(struct sock *sk)
+static inline bool sk_rethink_txhash(struct sock *sk)
 {
-	if (sk->sk_txhash)
+	if (sk->sk_txhash) {
 		sk_set_txhash(sk);
+		return true;
+	}
+	return false;
 }
 static inline struct dst_entry *
 	return dst;
 }
-static inline void dst_negative_advice(struct sock *sk)
+static inline void __dst_negative_advice(struct sock *sk)
 {
 	struct dst_entry *ndst, *dst = __sk_dst_get(sk);
-	sk_rethink_txhash(sk);
 	if (dst && dst->ops->negative_advice) {
 		ndst = dst->ops->negative_advice(dst);
 	}
 }
+static inline void dst_negative_advice(struct sock *sk)
+{
+	sk_rethink_txhash(sk);
+	__dst_negative_advice(sk);
+}
 static inline void
 __sk_dst_set(struct sock *sk, struct dst_entry *dst)
 {

include/trace/events/sunrpc.h+53−6

@@ -1424,13 +1424,61 @@ TRACE_EVENT(rpcb_unregister, · 1423 unmodified lines
1424	)	1424	)
1425	);	1425	);
1426		1426
		1427	/* Record an xdr_buf containing a fully-formed RPC message */
		1428	DECLARE_EVENT_CLASS(svc_xdr_msg_class,
		1429	TP_PROTO(
		1430	const struct xdr_buf *xdr
		1431	),
		1432
		1433	TP_ARGS(xdr),
		1434
		1435	TP_STRUCT__entry(
		1436	__field(u32, xid)
		1437	__field(const void *, head_base)
		1438	__field(size_t, head_len)
		1439	__field(const void *, tail_base)
		1440	__field(size_t, tail_len)
		1441	__field(unsigned int, page_len)
		1442	__field(unsigned int, msg_len)
		1443	),
		1444
		1445	TP_fast_assign(
		1446	__be32 p = (__be32 )xdr->head[0].iov_base;
		1447
		1448	__entry->xid = be32_to_cpu(*p);
		1449	__entry->head_base = p;
		1450	__entry->head_len = xdr->head[0].iov_len;
		1451	__entry->tail_base = xdr->tail[0].iov_base;
		1452	__entry->tail_len = xdr->tail[0].iov_len;
		1453	__entry->page_len = xdr->page_len;
		1454	__entry->msg_len = xdr->len;
		1455	),
		1456
		1457	TP_printk("xid=0x%08x head=[%p,%zu] page=%u tail=[%p,%zu] len=%u",
		1458	__entry->xid,
		1459	__entry->head_base, __entry->head_len, __entry->page_len,
		1460	__entry->tail_base, __entry->tail_len, __entry->msg_len
		1461	)
		1462	);
		1463
		1464	#define DEFINE_SVCXDRMSG_EVENT(name) \
		1465	DEFINE_EVENT(svc_xdr_msg_class, \
		1466	svc_xdr_##name, \
		1467	TP_PROTO( \
		1468	const struct xdr_buf *xdr \
		1469	), \
		1470	TP_ARGS(xdr))
		1471
		1472	DEFINE_SVCXDRMSG_EVENT(recvfrom);
		1473
		1474	/* Record an xdr_buf containing arbitrary data, tagged with an XID */
1427	DECLARE_EVENT_CLASS(svc_xdr_buf_class,	1475	DECLARE_EVENT_CLASS(svc_xdr_buf_class,
1428	TP_PROTO(	1476	TP_PROTO(
1429	const struct svc_rqst *rqst,	1477	__be32 xid,
1430	const struct xdr_buf *xdr	1478	const struct xdr_buf *xdr
1431	),	1479	),
1432		1480
1433	TP_ARGS(rqst, xdr),	1481	TP_ARGS(xid, xdr),
1434		1482
1435	TP_STRUCT__entry(	1483	TP_STRUCT__entry(
1436	__field(u32, xid)	1484	__field(u32, xid)
@@ -1443,7 +1491,7 @@ DECLARE_EVENT_CLASS(svc_xdr_buf_class, · 6 unmodified lines
1443	),	1491	),
1444		1492
1445	TP_fast_assign(	1493	TP_fast_assign(
1446	__entry->xid = be32_to_cpu(rqst->rq_xid);	1494	__entry->xid = be32_to_cpu(xid);
1447	__entry->head_base = xdr->head[0].iov_base;	1495	__entry->head_base = xdr->head[0].iov_base;
1448	__entry->head_len = xdr->head[0].iov_len;	1496	__entry->head_len = xdr->head[0].iov_len;
1449	__entry->tail_base = xdr->tail[0].iov_base;	1497	__entry->tail_base = xdr->tail[0].iov_base;
@@ -1463,12 +1511,11 @@ DECLARE_EVENT_CLASS(svc_xdr_buf_class, · 13 unmodified lines
1463	DEFINE_EVENT(svc_xdr_buf_class, \	1511	DEFINE_EVENT(svc_xdr_buf_class, \
1464	svc_xdr_##name, \	1512	svc_xdr_##name, \
1465	TP_PROTO( \	1513	TP_PROTO( \
1466	const struct svc_rqst *rqst, \	1514	__be32 xid, \
1467	const struct xdr_buf *xdr \	1515	const struct xdr_buf *xdr \
1468	), \	1516	), \
1469	TP_ARGS(rqst, xdr))	1517	TP_ARGS(xid, xdr))
1470		1518
1471	DEFINE_SVCXDRBUF_EVENT(recvfrom);
1472	DEFINE_SVCXDRBUF_EVENT(sendto);	1519	DEFINE_SVCXDRBUF_EVENT(sendto);
1473		1520
1474	/*	1521	/*

include/xen/xenbus.h+1−1

@@ -192,7 +192,7 @@ void xs_suspend_cancel(void); · 191 unmodified lines
192		192
193	struct work_struct;	193	struct work_struct;
194		194
195	void xenbus_probe(struct work_struct *);	195	void xenbus_probe(void);
196		196
197	#define XENBUS_IS_ERR_READ(str) ({ \	197	#define XENBUS_IS_ERR_READ(str) ({ \
198	if (!IS_ERR(str) && strlen(str) == 0) { \	198	if (!IS_ERR(str) && strlen(str) == 0) { \

kernel/bpf/bpf_inode_storage.c+6−3

 	 * bpf_local_storage_update expects the owner to have a
 	 * valid storage pointer.
 	 */
-	if (!inode_storage_ptr(inode))
+	if (!inode || !inode_storage_ptr(inode))
 		return (unsigned long)NULL;
 	sdata = inode_storage_lookup(inode, map, true);
 	if (sdata)
 		return (unsigned long)sdata->data;
-	/* This helper must only called from where the inode is gurranteed
+	/* This helper must only called from where the inode is guaranteed
 	 * to have a refcount and cannot be freed.
 	 */
 	if (flags & BPF_LOCAL_STORAGE_GET_F_CREATE) {
 BPF_CALL_2(bpf_inode_storage_delete,
 	   struct bpf_map *, map, struct inode *, inode)
 {
-	/* This helper must only called from where the inode is gurranteed
+	if (!inode)
+		return -EINVAL;
+	/* This helper must only called from where the inode is guaranteed
 	 * to have a refcount and cannot be freed.
 	 */
 	return inode_storage_delete(inode, map);

kernel/bpf/bpf_task_storage.c+4−1

 	 * bpf_local_storage_update expects the owner to have a
 	 * valid storage pointer.
 	 */
-	if (!task_storage_ptr(task))
+	if (!task || !task_storage_ptr(task))
 		return (unsigned long)NULL;
 	sdata = task_storage_lookup(task, map, true);
 BPF_CALL_2(bpf_task_storage_delete, struct bpf_map *, map, struct task_struct *,
 	   task)
 {
+	if (!task)
+		return -EINVAL;
 	/* This helper must only be called from places where the lifetime of the task
 	 * is guaranteed. Either by being refcounted or by being protected
 	 * by an RCU read-side critical section.

kernel/bpf/btf.c+1−1

@@ -4172,7 +4172,7 @@ static int btf_parse_hdr(struct btf_verifier_env *env) · 4171 unmodified lines
4172	return -ENOTSUPP;	4172	return -ENOTSUPP;
4173	}	4173	}
4174		4174
4175	if (btf_data_size == hdr->hdr_len) {	4175	if (!btf->base_btf && btf_data_size == hdr->hdr_len) {
4176	btf_verifier_log(env, "No data");	4176	btf_verifier_log(env, "No data");
4177	return -EINVAL;	4177	return -EINVAL;
4178	}	4178	}

kernel/bpf/cgroup.c+3−2

 		if (ctx.optlen != 0) {
 			*optlen = ctx.optlen;
 			*kernel_optval = ctx.optval;
+			/* export and don't free sockopt buf */
+			return 0;
 		}
 	}
 out:
-	if (ret)
+	sockopt_free_buf(&ctx);
-		sockopt_free_buf(&ctx);
 	return ret;
 }

kernel/bpf/helpers.c+1−1

@@ -108,7 +108,7 @@ BPF_CALL_2(bpf_map_peek_elem, struct bpf_map , map, void , value) · 107 unmodified lines
108	}	108	}
109		109
110	const struct bpf_func_proto bpf_map_peek_elem_proto = {	110	const struct bpf_func_proto bpf_map_peek_elem_proto = {
111	.func = bpf_map_pop_elem,	111	.func = bpf_map_peek_elem,
112	.gpl_only = false,	112	.gpl_only = false,
113	.ret_type = RET_INTEGER,	113	.ret_type = RET_INTEGER,
114	.arg1_type = ARG_CONST_MAP_PTR,	114	.arg1_type = ARG_CONST_MAP_PTR,

kernel/bpf/syscall.c+4−2

 out_put_prog:
 	if (tgt_prog_fd && tgt_prog)
 		bpf_prog_put(tgt_prog);
-	bpf_prog_put(prog);
 	return err;
 }
 			tp_name = prog->aux->attach_func_name;
 			break;
 		}
-		return bpf_tracing_prog_attach(prog, 0, 0);
+		err = bpf_tracing_prog_attach(prog, 0, 0);
+		if (err >= 0)
+			return err;
+		goto out_put_prog;
 	case BPF_PROG_TYPE_RAW_TRACEPOINT:
 	case BPF_PROG_TYPE_RAW_TRACEPOINT_WRITABLE:
 		if (strncpy_from_user(buf,

kernel/bpf/verifier.c+5−3

 	case PTR_TO_RDWR_BUF:
 	case PTR_TO_RDWR_BUF_OR_NULL:
 	case PTR_TO_PERCPU_BTF_ID:
+	case PTR_TO_MEM:
+	case PTR_TO_MEM_OR_NULL:
 		return true;
 	default:
 		return false;
 	return res < a;
 }
-static bool signed_add32_overflows(s64 a, s64 b)
+static bool signed_add32_overflows(s32 a, s32 b)
 {
 	/* Do the add in u32, where overflow is well-defined */
 	s32 res = (s32)((u32)a + (u32)b);
 	return res < a;
 }
-static bool signed_sub_overflows(s32 a, s32 b)
+static bool signed_sub_overflows(s64 a, s64 b)
 {
 	/* Do the sub in u64, where overflow is well-defined */
 	s64 res = (s64)((u64)a - (u64)b);
 static bool signed_sub32_overflows(s32 a, s32 b)
 {
-	/* Do the sub in u64, where overflow is well-defined */
+	/* Do the sub in u32, where overflow is well-defined */
 	s32 res = (s32)((u32)a - (u32)b);
 	if (b < 0)

kernel/signal.c+3−0

@@ -2550,6 +2550,9 @@ bool get_signal(struct ksignal *ksig) · 2549 unmodified lines
2550	struct signal_struct *signal = current->signal;	2550	struct signal_struct *signal = current->signal;
2551	int signr;	2551	int signr;
2552		2552
		2553	if (unlikely(current->task_works))
		2554	task_work_run();
		2555
2553	/*	2556	/*
2554	* For non-generic architectures, check for TIF_NOTIFY_SIGNAL so	2557	* For non-generic architectures, check for TIF_NOTIFY_SIGNAL so
2555	* that the arch handlers don't all have to do it. If we get here	2558	* that the arch handlers don't all have to do it. If we get here

lib/iov_iter.c+1−1

@@ -1658,7 +1658,7 @@ static int copy_compat_iovec_from_user(struct iovec *iov, · 1657 unmodified lines
1658	(const struct compat_iovec __user *)uvec;	1658	(const struct compat_iovec __user *)uvec;
1659	int ret = -EFAULT, i;	1659	int ret = -EFAULT, i;
1660		1660
1661	if (!user_access_begin(uvec, nr_segs * sizeof(*uvec)))	1661	if (!user_access_begin(uiov, nr_segs * sizeof(*uiov)))
1662	return -EFAULT;	1662	return -EFAULT;
1663		1663
1664	for (i = 0; i < nr_segs; i++) {	1664	for (i = 0; i < nr_segs; i++) {

mm/hugetlb.c+1−1

@@ -4371,7 +4371,7 @@ retry: · 4370 unmodified lines
4371	* So we need to block hugepage fault by PG_hwpoison bit check.	4371	* So we need to block hugepage fault by PG_hwpoison bit check.
4372	*/	4372	*/
4373	if (unlikely(PageHWPoison(page))) {	4373	if (unlikely(PageHWPoison(page))) {
4374	ret = VM_FAULT_HWPOISON \|	4374	ret = VM_FAULT_HWPOISON_LARGE \|
4375	VM_FAULT_SET_HINDEX(hstate_index(h));	4375	VM_FAULT_SET_HINDEX(hstate_index(h));
4376	goto backout_unlocked;	4376	goto backout_unlocked;
4377	}	4377	}

mm/kasan/init.c+2−1

@@ -64,7 +64,8 @@ static inline bool kasan_pmd_table(pud_t pud) · 63 unmodified lines
64	return false;	64	return false;
65	}	65	}
66	#endif	66	#endif
67	pte_t kasan_early_shadow_pte[PTRS_PER_PTE] __page_aligned_bss;	67	pte_t kasan_early_shadow_pte[PTRS_PER_PTE + PTE_HWTABLE_PTRS]
		68	__page_aligned_bss;
68		69
69	static inline bool kasan_pte_table(pmd_t pmd)	70	static inline bool kasan_pte_table(pmd_t pmd)
70	{	71	{

mm/memory-failure.c+1−1

@@ -1940,7 +1940,7 @@ retry: · 1939 unmodified lines
1940	goto retry;	1940	goto retry;
1941	}	1941	}
1942	} else if (ret == -EIO) {	1942	} else if (ret == -EIO) {
1943	pr_info("%s: %#lx: unknown page type: %lx (%pGP)\n",	1943	pr_info("%s: %#lx: unknown page type: %lx (%pGp)\n",
1944	__func__, pfn, page->flags, &page->flags);	1944	__func__, pfn, page->flags, &page->flags);
1945	}	1945	}
1946		1946

mm/mempolicy.c+1−1

@@ -1111,7 +1111,7 @@ int do_migrate_pages(struct mm_struct mm, const nodemask_t from, · 1110 unmodified lines
1111	const nodemask_t *to, int flags)	1111	const nodemask_t *to, int flags)
1112	{	1112	{
1113	int busy = 0;	1113	int busy = 0;
1114	int err;	1114	int err = 0;
1115	nodemask_t tmp;	1115	nodemask_t tmp;
1116		1116
1117	migrate_prep();	1117	migrate_prep();

mm/page_alloc.c+16−15

@@ -2862,20 +2862,20 @@ __rmqueue(struct zone *zone, unsigned int order, int migratetype, · 2861 unmodified lines
2862	{	2862	{
2863	struct page *page;	2863	struct page *page;
2864		2864
2865	#ifdef CONFIG_CMA	2865	if (IS_ENABLED(CONFIG_CMA)) {
2866	/*	2866	/*
2867	* Balance movable allocations between regular and CMA areas by	2867	* Balance movable allocations between regular and CMA areas by
2868	* allocating from CMA when over half of the zone's free memory	2868	* allocating from CMA when over half of the zone's free memory
2869	* is in the CMA area.	2869	* is in the CMA area.
2870	*/	2870	*/
2871	if (alloc_flags & ALLOC_CMA &&	2871	if (alloc_flags & ALLOC_CMA &&
2872	zone_page_state(zone, NR_FREE_CMA_PAGES) >	2872	zone_page_state(zone, NR_FREE_CMA_PAGES) >
2873	zone_page_state(zone, NR_FREE_PAGES) / 2) {	2873	zone_page_state(zone, NR_FREE_PAGES) / 2) {
2874	page = __rmqueue_cma_fallback(zone, order);	2874	page = __rmqueue_cma_fallback(zone, order);
2875	if (page)	2875	if (page)
2876	return page;	2876	goto out;
		2877	}
2877	}	2878	}
2878	#endif
2879	retry:	2879	retry:
2880	page = __rmqueue_smallest(zone, order, migratetype);	2880	page = __rmqueue_smallest(zone, order, migratetype);
2881	if (unlikely(!page)) {	2881	if (unlikely(!page)) {
@@ -2886,8 +2886,9 @@ retry: · 4 unmodified lines
2886	alloc_flags))	2886	alloc_flags))
2887	goto retry;	2887	goto retry;
2888	}	2888	}
2889		2889	out:
2890	trace_mm_page_alloc_zone_locked(page, order, migratetype);	2890	if (page)
		2891	trace_mm_page_alloc_zone_locked(page, order, migratetype);
2891	return page;	2892	return page;
2892	}	2893	}
2893		2894

mm/process_vm_access.c+1−0

@@ -9,6 +9,7 @@ · 8 unmodified lines
9	#include <linux/mm.h>	9	#include <linux/mm.h>
10	#include <linux/uio.h>	10	#include <linux/uio.h>
11	#include <linux/sched.h>	11	#include <linux/sched.h>
		12	#include <linux/compat.h>
12	#include <linux/sched/mm.h>	13	#include <linux/sched/mm.h>
13	#include <linux/highmem.h>	14	#include <linux/highmem.h>
14	#include <linux/ptrace.h>	15	#include <linux/ptrace.h>

mm/slub.c+1−1

@@ -1973,7 +1973,7 @@ static void get_partial_node(struct kmem_cache s, struct kmem_cache_node *n, · 1972 unmodified lines
1973		1973
1974	t = acquire_slab(s, n, page, object == NULL, &objects);	1974	t = acquire_slab(s, n, page, object == NULL, &objects);
1975	if (!t)	1975	if (!t)
1976	break;	1976	continue; /* cmpxchg raced */
1977		1977
1978	available += objects;	1978	available += objects;
1979	if (!object) {	1979	if (!object) {

mm/vmalloc.c+3−1

 		return NULL;
 	}
-	if (flags & VM_MAP_PUT_PAGES)
+	if (flags & VM_MAP_PUT_PAGES) {
 		area->pages = pages;
+		area->nr_pages = count;
+	}
 	return area->addr;
 }
 EXPORT_SYMBOL(vmap);

mm/vmscan.c+2−0

 			if (!PageSwapCache(page)) {
 				if (!(sc->gfp_mask & __GFP_IO))
 					goto keep_locked;
+				if (page_maybe_dma_pinned(page))
+					goto keep_locked;
 				if (PageTransHuge(page)) {
 					/* cannot split THP, skip it */
 					if (!can_split_huge_page(page, NULL))

net/bpf/test_run.c+2−1

@@ -272,7 +272,8 @@ int bpf_prog_test_run_raw_tp(struct bpf_prog *prog, · 271 unmodified lines
272	kattr->test.repeat)	272	kattr->test.repeat)
273	return -EINVAL;	273	return -EINVAL;
274		274
275	if (ctx_size_in < prog->aux->max_ctx_offset)	275	if (ctx_size_in < prog->aux->max_ctx_offset \|\|
		276	ctx_size_in > MAX_BPF_FUNC_ARGS * sizeof(u64))
276	return -EINVAL;	277	return -EINVAL;
277		278
278	if ((kattr->test.flags & BPF_F_TEST_RUN_ON_CPU) == 0 && cpu != 0)	279	if ((kattr->test.flags & BPF_F_TEST_RUN_ON_CPU) == 0 && cpu != 0)

net/core/dev.c+5−0

 		}
 	}
+	if ((features & NETIF_F_HW_TLS_RX) && !(features & NETIF_F_RXCSUM)) {
+		netdev_dbg(dev, "Dropping TLS RX HW offload feature since no RXCSUM feature.\n");
+		features &= ~NETIF_F_HW_TLS_RX;
+	}
 	return features;
 }

net/core/devlink.c+2−2

@@ -4146,7 +4146,7 @@ out: · 4145 unmodified lines
4146	static int devlink_nl_cmd_port_param_get_doit(struct sk_buff *skb,	4146	static int devlink_nl_cmd_port_param_get_doit(struct sk_buff *skb,
4147	struct genl_info *info)	4147	struct genl_info *info)
4148	{	4148	{
4149	struct devlink_port *devlink_port = info->user_ptr[0];	4149	struct devlink_port *devlink_port = info->user_ptr[1];
4150	struct devlink_param_item *param_item;	4150	struct devlink_param_item *param_item;
4151	struct sk_buff *msg;	4151	struct sk_buff *msg;
4152	int err;	4152	int err;
@@ -4175,7 +4175,7 @@ static int devlink_nl_cmd_port_param_get_doit(struct sk_buff *skb, · 22 unmodified lines
4175	static int devlink_nl_cmd_port_param_set_doit(struct sk_buff *skb,	4175	static int devlink_nl_cmd_port_param_set_doit(struct sk_buff *skb,
4176	struct genl_info *info)	4176	struct genl_info *info)
4177	{	4177	{
4178	struct devlink_port *devlink_port = info->user_ptr[0];	4178	struct devlink_port *devlink_port = info->user_ptr[1];
4179		4179
4180	return __devlink_nl_cmd_param_set_doit(devlink_port->devlink,	4180	return __devlink_nl_cmd_param_set_doit(devlink_port->devlink,
4181	devlink_port->index,	4181	devlink_port->index,

net/core/gen_estimator.c+7−4

 	u64 rate, brate;
 	est_fetch_counters(est, &b);
-	brate = (b.bytes - est->last_bytes) << (10 - est->ewma_log - est->intvl_log);
+	brate = (b.bytes - est->last_bytes) << (10 - est->intvl_log);
-	brate -= (est->avbps >> est->ewma_log);
+	brate = (brate >> est->ewma_log) - (est->avbps >> est->ewma_log);
-	rate = (b.packets - est->last_packets) << (10 - est->ewma_log - est->intvl_log);
+	rate = (b.packets - est->last_packets) << (10 - est->intvl_log);
-	rate -= (est->avpps >> est->ewma_log);
+	rate = (rate >> est->ewma_log) - (est->avpps >> est->ewma_log);
 	write_seqcount_begin(&est->seq);
 	est->avbps += brate;
 	if (parm->interval < -2 || parm->interval > 3)
 		return -EINVAL;
+	if (parm->ewma_log == 0 || parm->ewma_log >= 31)
+		return -EINVAL;
 	est = kzalloc(sizeof(*est), GFP_KERNEL);
 	if (!est)
 		return -ENOBUFS;

net/core/skbuff.c+5−1

 	len += NET_SKB_PAD;
-	if ((len > SKB_WITH_OVERHEAD(PAGE_SIZE)) ||
+	/* If requested length is either too small or too big,
+	 * we use kmalloc() for skb->head allocation.
+	 */
+	if (len <= SKB_WITH_OVERHEAD(1024) ||
+	    len > SKB_WITH_OVERHEAD(PAGE_SIZE) ||
 	    (gfp_mask & (__GFP_DIRECT_RECLAIM | GFP_DMA))) {
 		skb = __alloc_skb(len, gfp_mask, SKB_ALLOC_RX, NUMA_NO_NODE);
 		if (!skb)

net/ipv4/inet_connection_sock.c+1−0

@@ -851,6 +851,7 @@ struct sock inet_csk_clone_lock(const struct sock sk, · 850 unmodified lines
851	newicsk->icsk_retransmits = 0;	851	newicsk->icsk_retransmits = 0;
852	newicsk->icsk_backoff = 0;	852	newicsk->icsk_backoff = 0;
853	newicsk->icsk_probes_out = 0;	853	newicsk->icsk_probes_out = 0;
		854	newicsk->icsk_probes_tstamp = 0;
854		855
855	/* Deinitialize accept_queue to trap illegal accesses. */	856	/* Deinitialize accept_queue to trap illegal accesses. */
856	memset(&newicsk->icsk_accept_queue, 0, sizeof(newicsk->icsk_accept_queue));	857	memset(&newicsk->icsk_accept_queue, 0, sizeof(newicsk->icsk_accept_queue));

net/ipv4/netfilter/ipt_rpfilter.c+1−1

@@ -76,7 +76,7 @@ static bool rpfilter_mt(const struct sk_buff skb, struct xt_action_param par) · 75 unmodified lines
76	flow.daddr = iph->saddr;	76	flow.daddr = iph->saddr;
77	flow.saddr = rpfilter_get_saddr(iph->daddr);	77	flow.saddr = rpfilter_get_saddr(iph->daddr);
78	flow.flowi4_mark = info->flags & XT_RPFILTER_VALID_MARK ? skb->mark : 0;	78	flow.flowi4_mark = info->flags & XT_RPFILTER_VALID_MARK ? skb->mark : 0;
79	flow.flowi4_tos = RT_TOS(iph->tos);	79	flow.flowi4_tos = iph->tos & IPTOS_RT_MASK;
80	flow.flowi4_scope = RT_SCOPE_UNIVERSE;	80	flow.flowi4_scope = RT_SCOPE_UNIVERSE;
81	flow.flowi4_oif = l3mdev_master_ifindex_rcu(xt_in(par));	81	flow.flowi4_oif = l3mdev_master_ifindex_rcu(xt_in(par));
82		82

net/ipv4/tcp.c+1−0

@@ -2937,6 +2937,7 @@ int tcp_disconnect(struct sock *sk, int flags) · 2936 unmodified lines
2937		2937
2938	icsk->icsk_backoff = 0;	2938	icsk->icsk_backoff = 0;
2939	icsk->icsk_probes_out = 0;	2939	icsk->icsk_probes_out = 0;
		2940	icsk->icsk_probes_tstamp = 0;
2940	icsk->icsk_rto = TCP_TIMEOUT_INIT;	2941	icsk->icsk_rto = TCP_TIMEOUT_INIT;
2941	icsk->icsk_rto_min = TCP_RTO_MIN;	2942	icsk->icsk_rto_min = TCP_RTO_MIN;
2942	icsk->icsk_delack_max = TCP_DELACK_MAX;	2943	icsk->icsk_delack_max = TCP_DELACK_MAX;

net/ipv4/tcp_input.c+3−3

 		return;
 	if (!after(TCP_SKB_CB(head)->end_seq, tcp_wnd_end(tp))) {
 		icsk->icsk_backoff = 0;
+		icsk->icsk_probes_tstamp = 0;
 		inet_csk_clear_xmit_timer(sk, ICSK_TIME_PROBE0);
 		/* Socket must be waked up by subsequent tcp_data_snd_check().
 		 * This function is not for random using!
 	 * The receiver remembers and reflects via DSACKs. Leverage the
 	 * DSACK state and change the txhash to re-route speculatively.
 	 */
-	if (TCP_SKB_CB(skb)->seq == tcp_sk(sk)->duplicate_sack[0].start_seq) {
+	if (TCP_SKB_CB(skb)->seq == tcp_sk(sk)->duplicate_sack[0].start_seq &&
-		sk_rethink_txhash(sk);
+	    sk_rethink_txhash(sk))
 		NET_INC_STATS(sock_net(sk), LINUX_MIB_TCPDUPLICATEDATAREHASH);
-	}
 }
 static void tcp_send_dupack(struct sock *sk, const struct sk_buff *skb)

net/ipv4/tcp_ipv4.c+15−14

 		tcp_move_syn(newtp, req);
 		ireq->ireq_opt = NULL;
 	} else {
+		newinet->inet_opt = NULL;
 		if (!req_unhash && found_dup_sk) {
 			/* This code path should only be executed in the
 			 * syncookie case only
 			bh_unlock_sock(newsk);
 			sock_put(newsk);
 			newsk = NULL;
-		} else {
-			newinet->inet_opt = NULL;
 		}
 	}
 	return newsk;
 bool tcp_add_backlog(struct sock *sk, struct sk_buff *skb)
 {
 	u32 limit = READ_ONCE(sk->sk_rcvbuf) + READ_ONCE(sk->sk_sndbuf);
+	u32 tail_gso_size, tail_gso_segs;
 	struct skb_shared_info *shinfo;
 	const struct tcphdr *th;
 	struct tcphdr *thtail;
 	unsigned int hdrlen;
 	bool fragstolen;
 	u32 gso_segs;
+	u32 gso_size;
 	int delta;
 	/* In case all data was pulled from skb frags (in __pskb_pull_tail()),
 	 */
 	th = (const struct tcphdr *)skb->data;
 	hdrlen = th->doff * 4;
-	shinfo = skb_shinfo(skb);
-	if (!shinfo->gso_size)
-		shinfo->gso_size = skb->len - hdrlen;
-	if (!shinfo->gso_segs)
-		shinfo->gso_segs = 1;
 	tail = sk->sk_backlog.tail;
 	if (!tail)
 		goto no_coalesce;
 	__skb_pull(skb, hdrlen);
+	shinfo = skb_shinfo(skb);
+	gso_size = shinfo->gso_size ?: skb->len;
+	gso_segs = shinfo->gso_segs ?: 1;
+	shinfo = skb_shinfo(tail);
+	tail_gso_size = shinfo->gso_size ?: (tail->len - hdrlen);
+	tail_gso_segs = shinfo->gso_segs ?: 1;
 	if (skb_try_coalesce(tail, skb, &fragstolen, &delta)) {
 		TCP_SKB_CB(tail)->end_seq = TCP_SKB_CB(skb)->end_seq;
 		}
 		/* Not as strict as GRO. We only need to carry mss max value */
-		skb_shinfo(tail)->gso_size = max(shinfo->gso_size,
+		shinfo->gso_size = max(gso_size, tail_gso_size);
-						 skb_shinfo(tail)->gso_size);
+		shinfo->gso_segs = min_t(u32, gso_segs + tail_gso_segs, 0xFFFF);
-		gso_segs = skb_shinfo(tail)->gso_segs + shinfo->gso_segs;
-		skb_shinfo(tail)->gso_segs = min_t(u32, gso_segs, 0xFFFF);
 		sk->sk_backlog.len += delta;
 		__NET_INC_STATS(sock_net(sk),

net/ipv4/tcp_output.c+1−0

@@ -4084,6 +4084,7 @@ void tcp_send_probe0(struct sock *sk) · 4083 unmodified lines
4084	/* Cancel probe timer, if it is not required. */	4084	/* Cancel probe timer, if it is not required. */
4085	icsk->icsk_probes_out = 0;	4085	icsk->icsk_probes_out = 0;
4086	icsk->icsk_backoff = 0;	4086	icsk->icsk_backoff = 0;
		4087	icsk->icsk_probes_tstamp = 0;
4087	return;	4088	return;
4088	}	4089	}
4089		4090

net/ipv4/tcp_timer.c+15−21

@@ -219,14 +219,8 @@ static int tcp_write_timeout(struct sock *sk) · 218 unmodified lines
219	int retry_until;	219	int retry_until;
220		220
221	if ((1 << sk->sk_state) & (TCPF_SYN_SENT \| TCPF_SYN_RECV)) {	221	if ((1 << sk->sk_state) & (TCPF_SYN_SENT \| TCPF_SYN_RECV)) {
222	if (icsk->icsk_retransmits) {	222	if (icsk->icsk_retransmits)
223	dst_negative_advice(sk);	223	__dst_negative_advice(sk);
224	} else {
225	sk_rethink_txhash(sk);
226	tp->timeout_rehash++;
227	__NET_INC_STATS(sock_net(sk),
228	LINUX_MIB_TCPTIMEOUTREHASH);
229	}
230	retry_until = icsk->icsk_syn_retries ? : net->ipv4.sysctl_tcp_syn_retries;	224	retry_until = icsk->icsk_syn_retries ? : net->ipv4.sysctl_tcp_syn_retries;
231	expired = icsk->icsk_retransmits >= retry_until;	225	expired = icsk->icsk_retransmits >= retry_until;
232	} else {	226	} else {
@@ -234,12 +228,7 @@ static int tcp_write_timeout(struct sock *sk) · 1 unmodified line
234	/* Black hole detection */	228	/* Black hole detection */
235	tcp_mtu_probing(icsk, sk);	229	tcp_mtu_probing(icsk, sk);
236		230
237	dst_negative_advice(sk);	231	__dst_negative_advice(sk);
238	} else {
239	sk_rethink_txhash(sk);
240	tp->timeout_rehash++;
241	__NET_INC_STATS(sock_net(sk),
242	LINUX_MIB_TCPTIMEOUTREHASH);
243	}	232	}
244		233
245	retry_until = net->ipv4.sysctl_tcp_retries2;	234	retry_until = net->ipv4.sysctl_tcp_retries2;
@@ -270,6 +259,11 @@ static int tcp_write_timeout(struct sock *sk) · 24 unmodified lines
270	return 1;	259	return 1;
271	}	260	}
272		261
		262	if (sk_rethink_txhash(sk)) {
		263	tp->timeout_rehash++;
		264	__NET_INC_STATS(sock_net(sk), LINUX_MIB_TCPTIMEOUTREHASH);
		265	}
		266
273	return 0;	267	return 0;
274	}	268	}
275		269
@@ -349,6 +343,7 @@ static void tcp_probe_timer(struct sock *sk) · 73 unmodified lines
349		343
350	if (tp->packets_out \|\| !skb) {	344	if (tp->packets_out \|\| !skb) {
351	icsk->icsk_probes_out = 0;	345	icsk->icsk_probes_out = 0;
		346	icsk->icsk_probes_tstamp = 0;
352	return;	347	return;
353	}	348	}
354		349
@@ -360,13 +355,12 @@ static void tcp_probe_timer(struct sock *sk) · 5 unmodified lines
360	* corresponding system limit. We also implement similar policy when	355	* corresponding system limit. We also implement similar policy when
361	* we use RTO to probe window in tcp_retransmit_timer().	356	* we use RTO to probe window in tcp_retransmit_timer().
362	*/	357	*/
363	if (icsk->icsk_user_timeout) {	358	if (!icsk->icsk_probes_tstamp)
364	u32 elapsed = tcp_model_timeout(sk, icsk->icsk_probes_out,	359	icsk->icsk_probes_tstamp = tcp_jiffies32;
365	tcp_probe0_base(sk));	360	else if (icsk->icsk_user_timeout &&
366		361	(s32)(tcp_jiffies32 - icsk->icsk_probes_tstamp) >=
367	if (elapsed >= icsk->icsk_user_timeout)	362	msecs_to_jiffies(icsk->icsk_user_timeout))
368	goto abort;	363	goto abort;
369	}
370		364
371	max_probes = sock_net(sk)->ipv4.sysctl_tcp_retries2;	365	max_probes = sock_net(sk)->ipv4.sysctl_tcp_retries2;
372	if (sock_flag(sk, SOCK_DEAD)) {	366	if (sock_flag(sk, SOCK_DEAD)) {

net/ipv4/udp.c+2−1

 		 */
 		if (!inet_sk(sk)->inet_daddr && in_dev)
 			return ip_mc_validate_source(skb, iph->daddr,
-						     iph->saddr, iph->tos,
+						     iph->saddr,
+						     iph->tos & IPTOS_RT_MASK,
 						     skb->dev, in_dev, &itag);
 	}
 	return 0;

net/ipv6/addrconf.c+2−1

 		.fc_ifindex = dev->ifindex,
 		.fc_dst_len = 8,
 		.fc_flags = RTF_UP,
-		.fc_type = RTN_UNICAST,
+		.fc_type = RTN_MULTICAST,
 		.fc_nlinfo.nl_net = dev_net(dev),
+		.fc_protocol = RTPROT_KERNEL,
 	};
 	ipv6_addr_set(&cfg.fc_dst, htonl(0xFF000000), 0, 0, 0);

net/mac80211/debugfs.c+20−24

 {
 	struct ieee80211_local *local = file->private_data;
 	char buf[100];
-	size_t len;
-	if (count > sizeof(buf))
+	if (count >= sizeof(buf))
 		return -EINVAL;
 	if (copy_from_user(buf, user_buf, count))
 		return -EFAULT;
-	buf[sizeof(buf) - 1] = '\0';
+	if (count && buf[count - 1] == '\n')
-	len = strlen(buf);
+		buf[count - 1] = '\0';
-	if (len > 0 && buf[len-1] == '\n')
+	else
-		buf[len-1] = 0;
+		buf[count] = '\0';
 	if (sscanf(buf, "fq_limit %u", &local->fq.limit) == 1)
 		return count;
 {
 	struct ieee80211_local *local = file->private_data;
 	char buf[16];
-	size_t len;
-	if (count > sizeof(buf))
+	if (count >= sizeof(buf))
 		return -EINVAL;
 	if (copy_from_user(buf, user_buf, count))
 		return -EFAULT;
-	buf[sizeof(buf) - 1] = 0;
+	if (count && buf[count - 1] == '\n')
-	len = strlen(buf);
+		buf[count - 1] = '\0';
-	if (len > 0 && buf[len - 1] == '\n')
+	else
-		buf[len - 1] = 0;
+		buf[count] = '\0';
 	if (kstrtou16(buf, 0, &local->airtime_flags))
 		return -EINVAL;
 {
 	struct ieee80211_local *local = file->private_data;
 	char buf[100];
-	size_t len;
 	u32 ac, q_limit_low, q_limit_high, q_limit_low_old, q_limit_high_old;
 	struct sta_info *sta;
-	if (count > sizeof(buf))
+	if (count >= sizeof(buf))
 		return -EINVAL;
 	if (copy_from_user(buf, user_buf, count))
 		return -EFAULT;
-	buf[sizeof(buf) - 1] = 0;
+	if (count && buf[count - 1] == '\n')
-	len = strlen(buf);
+		buf[count - 1] = '\0';
-	if (len > 0 && buf[len - 1] == '\n')
+	else
-		buf[len - 1] = 0;
+		buf[count] = '\0';
 	if (sscanf(buf, "%u %u %u", &ac, &q_limit_low, &q_limit_high) != 3)
 		return -EINVAL;
 {
 	struct ieee80211_local *local = file->private_data;
 	char buf[3];
-	size_t len;
-	if (count > sizeof(buf))
+	if (count >= sizeof(buf))
 		return -EINVAL;
 	if (copy_from_user(buf, user_buf, count))
 		return -EFAULT;
-	buf[sizeof(buf) - 1] = '\0';
+	if (count && buf[count - 1] == '\n')
-	len = strlen(buf);
+		buf[count - 1] = '\0';
-	if (len > 0 && buf[len - 1] == '\n')
+	else
-		buf[len - 1] = 0;
+		buf[count] = '\0';
 	if (buf[0] == '0' && buf[1] == '\0')
 		local->force_tx_status = 0;

net/mac80211/rx.c+2−0

@@ -4176,6 +4176,8 @@ void ieee80211_check_fast_rx(struct sta_info *sta) · 4175 unmodified lines
4176		4176
4177	rcu_read_lock();	4177	rcu_read_lock();
4178	key = rcu_dereference(sta->ptk[sta->ptk_idx]);	4178	key = rcu_dereference(sta->ptk[sta->ptk_idx]);
		4179	if (!key)
		4180	key = rcu_dereference(sdata->default_unicast_key);
4179	if (key) {	4181	if (key) {
4180	switch (key->conf.cipher) {	4182	switch (key->conf.cipher) {
4181	case WLAN_CIPHER_SUITE_TKIP:	4183	case WLAN_CIPHER_SUITE_TKIP:

net/mac80211/tx.c+17−14

@@ -649,7 +649,7 @@ ieee80211_tx_h_select_key(struct ieee80211_tx_data *tx) · 648 unmodified lines
649	if (!skip_hw && tx->key &&	649	if (!skip_hw && tx->key &&
650	tx->key->flags & KEY_FLAG_UPLOADED_TO_HARDWARE)	650	tx->key->flags & KEY_FLAG_UPLOADED_TO_HARDWARE)
651	info->control.hw_key = &tx->key->conf;	651	info->control.hw_key = &tx->key->conf;
652	} else if (!ieee80211_is_mgmt(hdr->frame_control) && tx->sta &&	652	} else if (ieee80211_is_data_present(hdr->frame_control) && tx->sta &&
653	test_sta_flag(tx->sta, WLAN_STA_USES_ENCRYPTION)) {	653	test_sta_flag(tx->sta, WLAN_STA_USES_ENCRYPTION)) {
654	return TX_DROP;	654	return TX_DROP;
655	}	655	}
@@ -3809,7 +3809,7 @@ void __ieee80211_schedule_txq(struct ieee80211_hw *hw, · 3153 unmodified lines
3809	* get immediately moved to the back of the list on the next	3809	* get immediately moved to the back of the list on the next
3810	* call to ieee80211_next_txq().	3810	* call to ieee80211_next_txq().
3811	*/	3811	*/
3812	if (txqi->txq.sta &&	3812	if (txqi->txq.sta && local->airtime_flags &&
3813	wiphy_ext_feature_isset(local->hw.wiphy,	3813	wiphy_ext_feature_isset(local->hw.wiphy,
3814	NL80211_EXT_FEATURE_AIRTIME_FAIRNESS))	3814	NL80211_EXT_FEATURE_AIRTIME_FAIRNESS))
3815	list_add(&txqi->schedule_order,	3815	list_add(&txqi->schedule_order,
@@ -4251,7 +4251,6 @@ netdev_tx_t ieee80211_subif_start_xmit_8023(struct sk_buff *skb, · 435 unmodified lines
4251	struct ethhdr ehdr = (struct ethhdr )skb->data;	4251	struct ethhdr ehdr = (struct ethhdr )skb->data;
4252	struct ieee80211_key *key;	4252	struct ieee80211_key *key;
4253	struct sta_info *sta;	4253	struct sta_info *sta;
4254	bool offload = true;
4255		4254
4256	if (unlikely(skb->len < ETH_HLEN)) {	4255	if (unlikely(skb->len < ETH_HLEN)) {
4257	kfree_skb(skb);	4256	kfree_skb(skb);
@@ -4267,18 +4266,22 @@ netdev_tx_t ieee80211_subif_start_xmit_8023(struct sk_buff *skb, · 9 unmodified lines
4267		4266
4268	if (unlikely(IS_ERR_OR_NULL(sta) \|\| !sta->uploaded \|\|	4267	if (unlikely(IS_ERR_OR_NULL(sta) \|\| !sta->uploaded \|\|
4269	!test_sta_flag(sta, WLAN_STA_AUTHORIZED) \|\|	4268	!test_sta_flag(sta, WLAN_STA_AUTHORIZED) \|\|
4270	sdata->control_port_protocol == ehdr->h_proto))	4269	sdata->control_port_protocol == ehdr->h_proto))
4271	offload = false;	4270	goto skip_offload;
4272	else if ((key = rcu_dereference(sta->ptk[sta->ptk_idx])) &&	4271
4273	(!(key->flags & KEY_FLAG_UPLOADED_TO_HARDWARE) \|\|	4272	key = rcu_dereference(sta->ptk[sta->ptk_idx]);
4274	key->conf.cipher == WLAN_CIPHER_SUITE_TKIP))	4273	if (!key)
4275	offload = false;	4274	key = rcu_dereference(sdata->default_unicast_key);
4276		4275
4277	if (offload)	4276	if (key && (!(key->flags & KEY_FLAG_UPLOADED_TO_HARDWARE) \|\|
4278	ieee80211_8023_xmit(sdata, dev, sta, key, skb);	4277	key->conf.cipher == WLAN_CIPHER_SUITE_TKIP))
4279	else	4278	goto skip_offload;
4280	ieee80211_subif_start_xmit(skb, dev);	4279
		4280	ieee80211_8023_xmit(sdata, dev, sta, key, skb);
		4281	goto out;
4281		4282
		4283	skip_offload:
		4284	ieee80211_subif_start_xmit(skb, dev);
4282	out:	4285	out:
4283	rcu_read_unlock();	4286	rcu_read_unlock();
4284		4287

net/nfc/nci/core.c+1−1

@@ -508,7 +508,7 @@ static int nci_open_device(struct nci_dev *ndev) · 507 unmodified lines
508	};	508	};
509	unsigned long opt = 0;	509	unsigned long opt = 0;
510		510
511	if (!(ndev->nci_ver & NCI_VER_2_MASK))	511	if (ndev->nci_ver & NCI_VER_2_MASK)
512	opt = (unsigned long)&nci_init_v2_cmd;	512	opt = (unsigned long)&nci_init_v2_cmd;
513		513
514	rc = __nci_request(ndev, nci_init_req, opt,	514	rc = __nci_request(ndev, nci_init_req, opt,

net/sched/cls_flower.c+13−9

 		nla_opt_msk = nla_data(tb[TCA_FLOWER_KEY_ENC_OPTS_MASK]);
 		msk_depth = nla_len(tb[TCA_FLOWER_KEY_ENC_OPTS_MASK]);
+		if (!nla_ok(nla_opt_msk, msk_depth)) {
+			NL_SET_ERR_MSG(extack, "Invalid nested attribute for masks");
+			return -EINVAL;
+		}
 	}
 	nla_for_each_attr(nla_opt_key, nla_enc_key,
 				NL_SET_ERR_MSG(extack, "Key and mask miss aligned");
 				return -EINVAL;
 			}
-			if (msk_depth)
-				nla_opt_msk = nla_next(nla_opt_msk, &msk_depth);
 			break;
 		case TCA_FLOWER_KEY_ENC_OPTS_VXLAN:
 			if (key->enc_opts.dst_opt_type) {
 				NL_SET_ERR_MSG(extack, "Key and mask miss aligned");
 				return -EINVAL;
 			}
-			if (msk_depth)
-				nla_opt_msk = nla_next(nla_opt_msk, &msk_depth);
 			break;
 		case TCA_FLOWER_KEY_ENC_OPTS_ERSPAN:
 			if (key->enc_opts.dst_opt_type) {
 				NL_SET_ERR_MSG(extack, "Key and mask miss aligned");
 				return -EINVAL;
 			}
-			if (msk_depth)
-				nla_opt_msk = nla_next(nla_opt_msk, &msk_depth);
 			break;
 		default:
 			NL_SET_ERR_MSG(extack, "Unknown tunnel option type");
 			return -EINVAL;
 		}
+		if (!msk_depth)
+			continue;
+		if (!nla_ok(nla_opt_msk, msk_depth)) {
+			NL_SET_ERR_MSG(extack, "A mask attribute is invalid");
+			return -EINVAL;
+		}
+		nla_opt_msk = nla_next(nla_opt_msk, &msk_depth);
 	}
 	return 0;

net/sched/cls_tcindex.c+6−2

@@ -366,9 +366,13 @@ tcindex_set_parms(struct net net, struct tcf_proto tp, unsigned long base, · 365 unmodified lines
366	if (tb[TCA_TCINDEX_MASK])	366	if (tb[TCA_TCINDEX_MASK])
367	cp->mask = nla_get_u16(tb[TCA_TCINDEX_MASK]);	367	cp->mask = nla_get_u16(tb[TCA_TCINDEX_MASK]);
368		368
369	if (tb[TCA_TCINDEX_SHIFT])	369	if (tb[TCA_TCINDEX_SHIFT]) {
370	cp->shift = nla_get_u32(tb[TCA_TCINDEX_SHIFT]);	370	cp->shift = nla_get_u32(tb[TCA_TCINDEX_SHIFT]);
371		371	if (cp->shift > 16) {
		372	err = -EINVAL;
		373	goto errout;
		374	}
		375	}
372	if (!cp->hash) {	376	if (!cp->hash) {
373	/* Hash not specified, use perfect hash if the upper limit	377	/* Hash not specified, use perfect hash if the upper limit
374	* of the hashing index is below the threshold.	378	* of the hashing index is below the threshold.

net/sched/sch_api.c+2−1

@@ -412,7 +412,8 @@ struct qdisc_rate_table qdisc_get_rtab(struct tc_ratespec r, · 411 unmodified lines
412	{	412	{
413	struct qdisc_rate_table *rtab;	413	struct qdisc_rate_table *rtab;
414		414
415	if (tab == NULL \|\| r->rate == 0 \|\| r->cell_log == 0 \|\|	415	if (tab == NULL \|\| r->rate == 0 \|\|
		416	r->cell_log == 0 \|\| r->cell_log >= 32 \|\|
416	nla_len(tab) != TC_RTAB_SIZE) {	417	nla_len(tab) != TC_RTAB_SIZE) {
417	NL_SET_ERR_MSG(extack, "Invalid rate table parameters for searching");	418	NL_SET_ERR_MSG(extack, "Invalid rate table parameters for searching");
418	return NULL;	419	return NULL;

net/sunrpc/svc_xprt.c+2−2

 	err = -EAGAIN;
 	if (len <= 0)
 		goto out_release;
+	trace_svc_xdr_recvfrom(&rqstp->rq_arg);
 	clear_bit(XPT_OLD, &xprt->xpt_flags);
 	if (serv->sv_stats)
 		serv->sv_stats->netcnt++;
-	trace_svc_xdr_recvfrom(rqstp, &rqstp->rq_arg);
 	return len;
 out_release:
 	rqstp->rq_res.len = 0;
 	xb->len = xb->head[0].iov_len +
 		xb->page_len +
 		xb->tail[0].iov_len;
-	trace_svc_xdr_sendto(rqstp, xb);
+	trace_svc_xdr_sendto(rqstp->rq_xid, xb);
 	trace_svc_stats_latency(rqstp);
 	len = xprt->xpt_ops->xpo_sendto(rqstp);

net/wireless/reg.c+10−1

  * Copyright 2008-2011	Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
  * Copyright 2013-2014  Intel Mobile Communications GmbH
  * Copyright      2017  Intel Deutschland GmbH
- * Copyright (C) 2018 - 2019 Intel Corporation
+ * Copyright (C) 2018 - 2021 Intel Corporation
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
 	return rcu_dereference_rtnl(cfg80211_regdomain);
 }
+/*
+ * Returns the regulatory domain associated with the wiphy.
+ *
+ * Requires either RTNL or RCU protection
+ */
 const struct ieee80211_regdomain *get_wiphy_regdom(struct wiphy *wiphy)
 {
 	return rcu_dereference_rtnl(wiphy->regd);
 	if (IS_ERR(new_regd))
 		return;
+	rtnl_lock();
 	tmp = get_wiphy_regdom(wiphy);
 	rcu_assign_pointer(wiphy->regd, new_regd);
 	rcu_free_regdom(tmp);
+	rtnl_unlock();
 }
 EXPORT_SYMBOL(wiphy_apply_custom_regulatory);

net/xdp/xsk.c+2−2

@@ -108,9 +108,9 @@ EXPORT_SYMBOL(xsk_get_pool_from_qid); · 107 unmodified lines
108		108
109	void xsk_clear_pool_at_qid(struct net_device *dev, u16 queue_id)	109	void xsk_clear_pool_at_qid(struct net_device *dev, u16 queue_id)
110	{	110	{
111	if (queue_id < dev->real_num_rx_queues)	111	if (queue_id < dev->num_rx_queues)
112	dev->_rx[queue_id].pool = NULL;	112	dev->_rx[queue_id].pool = NULL;
113	if (queue_id < dev->real_num_tx_queues)	113	if (queue_id < dev->num_tx_queues)
114	dev->_tx[queue_id].pool = NULL;	114	dev->_tx[queue_id].pool = NULL;
115	}	115	}
116		116

security/lsm_audit.c+5−2

 		struct inode *inode;
 		audit_log_format(ab, " name=");
+		spin_lock(&a->u.dentry->d_lock);
 		audit_log_untrustedstring(ab, a->u.dentry->d_name.name);
+		spin_unlock(&a->u.dentry->d_lock);
 		inode = d_backing_inode(a->u.dentry);
 		if (inode) {
 		dentry = d_find_alias(inode);
 		if (dentry) {
 			audit_log_format(ab, " name=");
-			audit_log_untrustedstring(ab,
+			spin_lock(&dentry->d_lock);
-					 dentry->d_name.name);
+			audit_log_untrustedstring(ab, dentry->d_name.name);
+			spin_unlock(&dentry->d_lock);
 			dput(dentry);
 		}
 		audit_log_format(ab, " dev=");

tools/bootconfig/scripts/bconf2ftrace.sh+1−0

@@ -152,6 +152,7 @@ setup_instance() { # [instance] · 151 unmodified lines
152	set_array_of ${instance}.options ${instancedir}/trace_options	152	set_array_of ${instance}.options ${instancedir}/trace_options
153	set_value_of ${instance}.trace_clock ${instancedir}/trace_clock	153	set_value_of ${instance}.trace_clock ${instancedir}/trace_clock
154	set_value_of ${instance}.cpumask ${instancedir}/tracing_cpumask	154	set_value_of ${instance}.cpumask ${instancedir}/tracing_cpumask
		155	set_value_of ${instance}.tracing_on ${instancedir}/tracing_on
155	set_value_of ${instance}.tracer ${instancedir}/current_tracer	156	set_value_of ${instance}.tracer ${instancedir}/current_tracer
156	set_array_of ${instance}.ftrace.filters \	157	set_array_of ${instance}.ftrace.filters \
157	${instancedir}/set_ftrace_filter	158	${instancedir}/set_ftrace_filter

tools/bootconfig/scripts/ftrace2bconf.sh+4−0

 	if [ `echo $val | sed -e s/f//g`x != x ]; then
 		emit_kv $PREFIX.cpumask = $val
 	fi
+	val=`cat $INSTANCE/tracing_on`
+	if [ `echo $val | sed -e s/f//g`x != x ]; then
+		emit_kv $PREFIX.tracing_on = $val
+	fi
 	val=
 	for i in `cat $INSTANCE/set_event`; do

tools/include/linux/build_bug.h+0−5

@@ -79,9 +79,4 @@ · 78 unmodified lines
79	#define __static_assert(expr, msg, ...) _Static_assert(expr, msg)	79	#define __static_assert(expr, msg, ...) _Static_assert(expr, msg)
80	#endif // static_assert	80	#endif // static_assert
81		81
82	#ifdef __GENKSYMS__
83	/* genksyms gets confused by _Static_assert */
84	#define _Static_assert(expr, ...)
85	#endif
86
87	#endif /* _LINUX_BUILD_BUG_H */	82	#endif /* _LINUX_BUILD_BUG_H */

tools/include/uapi/linux/kvm.h+2−0

 #define KVM_EXIT_X86_RDMSR        29
 #define KVM_EXIT_X86_WRMSR        30
 #define KVM_EXIT_DIRTY_RING_FULL  31
+#define KVM_EXIT_AP_RESET_HOLD    32
 /* For KVM_EXIT_INTERNAL_ERROR */
 /* Emulate instruction failed. */
 #define KVM_MP_STATE_CHECK_STOP        6
 #define KVM_MP_STATE_OPERATING         7
 #define KVM_MP_STATE_LOAD              8
+#define KVM_MP_STATE_AP_RESET_HOLD     9
 struct kvm_mp_state {
 	__u32 mp_state;

tools/lib/bpf/btf.c+0−5

 	}
 	meta_left = btf->raw_size - sizeof(*hdr);
-	if (!meta_left) {
-		pr_debug("BTF has no data\n");
-		return -EINVAL;
-	}
 	if (meta_left < hdr->str_off + hdr->str_len) {
 		pr_debug("Invalid BTF total size:%u\n", btf->raw_size);
 		return -EINVAL;

tools/lib/perf/tests/test-cpumap.c+1−1

@@ -27,5 +27,5 @@ int main(int argc, char **argv) · 26 unmodified lines
27	perf_cpu_map__put(cpus);	27	perf_cpu_map__put(cpus);
28		28
29	__T_END;	29	__T_END;
30	return 0;	30	return tests_failed == 0 ? 0 : -1;
31	}	31	}

tools/lib/perf/tests/test-evlist.c+4−3

 	char path[PATH_MAX];
 	int id, err, pid, go_pipe[2];
 	union perf_event *event;
-	char bf;
 	int count = 0;
 	snprintf(path, PATH_MAX, "%s/kernel/debug/tracing/events/syscalls/sys_enter_prctl/id",
 		 sysfs__mountpoint());
 	if (filename__read_int(path, &id)) {
+		tests_failed++;
 		fprintf(stderr, "error: failed to get tracepoint id: %s\n", path);
 		return -1;
 	}
 	pid = fork();
 	if (!pid) {
 		int i;
+		char bf;
 		read(go_pipe[0], &bf, 1);
 	perf_evlist__enable(evlist);
 	/* kick the child and wait for it to finish */
-	write(go_pipe[1], &bf, 1);
+	write(go_pipe[1], "A", 1);
 	waitpid(pid, NULL, 0);
 	/*
 	test_mmap_cpus();
 	__T_END;
-	return 0;
+	return tests_failed == 0 ? 0 : -1;
 }

tools/lib/perf/tests/test-evsel.c+1−1

@@ -131,5 +131,5 @@ int main(int argc, char **argv) · 130 unmodified lines
131	test_stat_thread_enable();	131	test_stat_thread_enable();
132		132
133	__T_END;	133	__T_END;
134	return 0;	134	return tests_failed == 0 ? 0 : -1;
135	}	135	}

tools/lib/perf/tests/test-threadmap.c+1−1

@@ -27,5 +27,5 @@ int main(int argc, char **argv) · 26 unmodified lines
27	perf_thread_map__put(threads);	27	perf_thread_map__put(threads);
28		28
29	__T_END;	29	__T_END;
30	return 0;	30	return tests_failed == 0 ? 0 : -1;
31	}	31	}

tools/perf/examples/bpf/5sec.c+1−1

@@ -39,7 +39,7 @@ · 38 unmodified lines
39	Copyright (C) 2018 Red Hat, Inc., Arnaldo Carvalho de Melo <acme@redhat.com>	39	Copyright (C) 2018 Red Hat, Inc., Arnaldo Carvalho de Melo <acme@redhat.com>
40	*/	40	*/
41		41
42	#include <bpf/bpf.h>	42	#include <bpf.h>
43		43
44	#define NSEC_PER_SEC 1000000000L	44	#define NSEC_PER_SEC 1000000000L
45		45

tools/perf/tests/shell/stat+shadow_stat.sh+14−16

 test_global_aggr()
 {
-	local cyc
 	perf stat -a --no-big-num -e cycles,instructions sleep 1  2>&1 | \
 	grep -e cycles -e instructions | \
 	while read num evt hash ipc rest
 	do
 		# skip not counted events
-		if [[ $num == "<not" ]]; then
+		if [ "$num" = "<not" ]; then
 			continue
 		fi
 		# save cycles count
-		if [[ $evt == "cycles" ]]; then
+		if [ "$evt" = "cycles" ]; then
 			cyc=$num
 			continue
 		fi
 		# skip if no cycles
-		if [[ -z $cyc ]]; then
+		if [ -z "$cyc" ]; then
 			continue
 		fi
 		# use printf for rounding and a leading zero
-		local res=`printf "%.2f" $(echo "scale=6; $num / $cyc" | bc -q)`
+		res=`printf "%.2f" $(echo "scale=6; $num / $cyc" | bc -q)`
-		if [[ $ipc != $res ]]; then
+		if [ "$ipc" != "$res" ]; then
 			echo "IPC is different: $res != $ipc  ($num / $cyc)"
 			exit 1
 		fi
 test_no_aggr()
 {
-	declare -A results
 	perf stat -a -A --no-big-num -e cycles,instructions sleep 1  2>&1 | \
 	grep ^CPU | \
 	while read cpu num evt hash ipc rest
 	do
 		# skip not counted events
-		if [[ $num == "<not" ]]; then
+		if [ "$num" = "<not" ]; then
 			continue
 		fi
 		# save cycles count
-		if [[ $evt == "cycles" ]]; then
+		if [ "$evt" = "cycles" ]; then
-			results[$cpu]=$num
+			results="$results $cpu:$num"
 			continue
 		fi
+		cyc=${results##* $cpu:}
+		cyc=${cyc%% *}
 		# skip if no cycles
-		local cyc=${results[$cpu]}
+		if [ -z "$cyc" ]; then
-		if [[ -z $cyc ]]; then
 			continue
 		fi
 		# use printf for rounding and a leading zero
-		local res=`printf "%.2f" $(echo "scale=6; $num / $cyc" | bc -q)`
+		res=`printf "%.2f" $(echo "scale=6; $num / $cyc" | bc -q)`
-		if [[ $ipc != $res ]]; then
+		if [ "$ipc" != "$res" ]; then
 			echo "IPC is different for $cpu: $res != $ipc  ($num / $cyc)"
 			exit 1
 		fi

tools/perf/util/header.c+8−0

@@ -3323,6 +3323,14 @@ int perf_session__write_header(struct perf_session *session, · 3322 unmodified lines
3323	attr_offset = lseek(ff.fd, 0, SEEK_CUR);	3323	attr_offset = lseek(ff.fd, 0, SEEK_CUR);
3324		3324
3325	evlist__for_each_entry(evlist, evsel) {	3325	evlist__for_each_entry(evlist, evsel) {
		3326	if (evsel->core.attr.size < sizeof(evsel->core.attr)) {
		3327	/*
		3328	* We are likely in "perf inject" and have read
		3329	* from an older file. Update attr size so that
		3330	* reader gets the right offset to the ids.
		3331	*/
		3332	evsel->core.attr.size = sizeof(evsel->core.attr);
		3333	}
3326	f_attr = (struct perf_file_attr){	3334	f_attr = (struct perf_file_attr){
3327	.attr = evsel->core.attr,	3335	.attr = evsel->core.attr,
3328	.ids = {	3336	.ids = {

tools/perf/util/machine.c+2−2

@@ -2980,7 +2980,7 @@ int machines__for_each_thread(struct machines *machines, · 2979 unmodified lines
2980		2980
2981	pid_t machine__get_current_tid(struct machine *machine, int cpu)	2981	pid_t machine__get_current_tid(struct machine *machine, int cpu)
2982	{	2982	{
2983	int nr_cpus = min(machine->env->nr_cpus_online, MAX_NR_CPUS);	2983	int nr_cpus = min(machine->env->nr_cpus_avail, MAX_NR_CPUS);
2984		2984
2985	if (cpu < 0 \|\| cpu >= nr_cpus \|\| !machine->current_tid)	2985	if (cpu < 0 \|\| cpu >= nr_cpus \|\| !machine->current_tid)
2986	return -1;	2986	return -1;
@@ -2992,7 +2992,7 @@ int machine__set_current_tid(struct machine *machine, int cpu, pid_t pid, · 5 unmodified lines
2992	pid_t tid)	2992	pid_t tid)
2993	{	2993	{
2994	struct thread *thread;	2994	struct thread *thread;
2995	int nr_cpus = min(machine->env->nr_cpus_online, MAX_NR_CPUS);	2995	int nr_cpus = min(machine->env->nr_cpus_avail, MAX_NR_CPUS);
2996		2996
2997	if (cpu < 0)	2997	if (cpu < 0)
2998	return -EINVAL;	2998	return -EINVAL;

tools/perf/util/session.c+1−1

@@ -2404,7 +2404,7 @@ int perf_session__cpu_bitmap(struct perf_session *session, · 2403 unmodified lines
2404	{	2404	{
2405	int i, err = -1;	2405	int i, err = -1;
2406	struct perf_cpu_map *map;	2406	struct perf_cpu_map *map;
2407	int nr_cpus = min(session->header.env.nr_cpus_online, MAX_NR_CPUS);	2407	int nr_cpus = min(session->header.env.nr_cpus_avail, MAX_NR_CPUS);
2408		2408
2409	for (i = 0; i < PERF_TYPE_MAX; ++i) {	2409	for (i = 0; i < PERF_TYPE_MAX; ++i) {
2410	struct evsel *evsel;	2410	struct evsel *evsel;

tools/perf/util/stat-shadow.c+189−177

@@ -8,6 +8,7 @@ · 7 unmodified lines
8	#include "evlist.h"	8	#include "evlist.h"
9	#include "expr.h"	9	#include "expr.h"
10	#include "metricgroup.h"	10	#include "metricgroup.h"
		11	#include "cgroup.h"
11	#include <linux/zalloc.h>	12	#include <linux/zalloc.h>
12		13
13	/*	14	/*
@@ -28,6 +29,7 @@ struct saved_value { · 14 unmodified lines
28	enum stat_type type;	29	enum stat_type type;
29	int ctx;	30	int ctx;
30	int cpu;	31	int cpu;
		32	struct cgroup *cgrp;
31	struct runtime_stat *stat;	33	struct runtime_stat *stat;
32	struct stats stats;	34	struct stats stats;
33	u64 metric_total;	35	u64 metric_total;
@@ -57,6 +59,9 @@ static int saved_value_cmp(struct rb_node rb_node, const void entry) · 23 unmodified lines
57	if (a->ctx != b->ctx)	59	if (a->ctx != b->ctx)
58	return a->ctx - b->ctx;	60	return a->ctx - b->ctx;
59		61
		62	if (a->cgrp != b->cgrp)
		63	return (char )a->cgrp < (char )b->cgrp ? -1 : +1;
		64
60	if (a->evsel == NULL && b->evsel == NULL) {	65	if (a->evsel == NULL && b->evsel == NULL) {
61	if (a->stat == b->stat)	66	if (a->stat == b->stat)
62	return 0;	67	return 0;
@@ -100,7 +105,8 @@ static struct saved_value saved_value_lookup(struct evsel evsel, · 37 unmodified lines
100	bool create,	105	bool create,
101	enum stat_type type,	106	enum stat_type type,
102	int ctx,	107	int ctx,
103	struct runtime_stat *st)	108	struct runtime_stat *st,
		109	struct cgroup *cgrp)
104	{	110	{
105	struct rblist *rblist;	111	struct rblist *rblist;
106	struct rb_node *nd;	112	struct rb_node *nd;
@@ -110,10 +116,15 @@ static struct saved_value saved_value_lookup(struct evsel evsel, · 3 unmodified lines
110	.type = type,	116	.type = type,
111	.ctx = ctx,	117	.ctx = ctx,
112	.stat = st,	118	.stat = st,
		119	.cgrp = cgrp,
113	};	120	};
114		121
115	rblist = &st->value_list;	122	rblist = &st->value_list;
116		123
		124	/* don't use context info for clock events */
		125	if (type == STAT_NSECS)
		126	dm.ctx = 0;
		127
117	nd = rblist__find(rblist, &dm);	128	nd = rblist__find(rblist, &dm);
118	if (nd)	129	if (nd)
119	return container_of(nd, struct saved_value, rb_node);	130	return container_of(nd, struct saved_value, rb_node);
@@ -191,12 +202,18 @@ void perf_stat__reset_shadow_per_stat(struct runtime_stat *st) · 71 unmodified lines
191	reset_stat(st);	202	reset_stat(st);
192	}	203	}
193		204
		205	struct runtime_stat_data {
		206	int ctx;
		207	struct cgroup *cgrp;
		208	};
		209
194	static void update_runtime_stat(struct runtime_stat *st,	210	static void update_runtime_stat(struct runtime_stat *st,
195	enum stat_type type,	211	enum stat_type type,
196	int ctx, int cpu, u64 count)	212	int cpu, u64 count,
		213	struct runtime_stat_data *rsd)
197	{	214	{
198	struct saved_value *v = saved_value_lookup(NULL, cpu, true,	215	struct saved_value *v = saved_value_lookup(NULL, cpu, true, type,
199	type, ctx, st);	216	rsd->ctx, st, rsd->cgrp);
200		217
201	if (v)	218	if (v)
202	update_stats(&v->stats, count);	219	update_stats(&v->stats, count);
@@ -210,82 +227,86 @@ static void update_runtime_stat(struct runtime_stat *st, · 7 unmodified lines
210	void perf_stat__update_shadow_stats(struct evsel *counter, u64 count,	227	void perf_stat__update_shadow_stats(struct evsel *counter, u64 count,
211	int cpu, struct runtime_stat *st)	228	int cpu, struct runtime_stat *st)
212	{	229	{
213	int ctx = evsel_context(counter);
214	u64 count_ns = count;	230	u64 count_ns = count;
215	struct saved_value *v;	231	struct saved_value *v;
		232	struct runtime_stat_data rsd = {
		233	.ctx = evsel_context(counter),
		234	.cgrp = counter->cgrp,
		235	};
216		236
217	count *= counter->scale;	237	count *= counter->scale;
218		238
219	if (evsel__is_clock(counter))	239	if (evsel__is_clock(counter))
220	update_runtime_stat(st, STAT_NSECS, 0, cpu, count_ns);	240	update_runtime_stat(st, STAT_NSECS, cpu, count_ns, &rsd);
221	else if (evsel__match(counter, HARDWARE, HW_CPU_CYCLES))	241	else if (evsel__match(counter, HARDWARE, HW_CPU_CYCLES))
222	update_runtime_stat(st, STAT_CYCLES, ctx, cpu, count);	242	update_runtime_stat(st, STAT_CYCLES, cpu, count, &rsd);
223	else if (perf_stat_evsel__is(counter, CYCLES_IN_TX))	243	else if (perf_stat_evsel__is(counter, CYCLES_IN_TX))
224	update_runtime_stat(st, STAT_CYCLES_IN_TX, ctx, cpu, count);	244	update_runtime_stat(st, STAT_CYCLES_IN_TX, cpu, count, &rsd);
225	else if (perf_stat_evsel__is(counter, TRANSACTION_START))	245	else if (perf_stat_evsel__is(counter, TRANSACTION_START))
226	update_runtime_stat(st, STAT_TRANSACTION, ctx, cpu, count);	246	update_runtime_stat(st, STAT_TRANSACTION, cpu, count, &rsd);
227	else if (perf_stat_evsel__is(counter, ELISION_START))	247	else if (perf_stat_evsel__is(counter, ELISION_START))
228	update_runtime_stat(st, STAT_ELISION, ctx, cpu, count);	248	update_runtime_stat(st, STAT_ELISION, cpu, count, &rsd);
229	else if (perf_stat_evsel__is(counter, TOPDOWN_TOTAL_SLOTS))	249	else if (perf_stat_evsel__is(counter, TOPDOWN_TOTAL_SLOTS))
230	update_runtime_stat(st, STAT_TOPDOWN_TOTAL_SLOTS,	250	update_runtime_stat(st, STAT_TOPDOWN_TOTAL_SLOTS,
231	ctx, cpu, count);	251	cpu, count, &rsd);
232	else if (perf_stat_evsel__is(counter, TOPDOWN_SLOTS_ISSUED))	252	else if (perf_stat_evsel__is(counter, TOPDOWN_SLOTS_ISSUED))
233	update_runtime_stat(st, STAT_TOPDOWN_SLOTS_ISSUED,	253	update_runtime_stat(st, STAT_TOPDOWN_SLOTS_ISSUED,
234	ctx, cpu, count);	254	cpu, count, &rsd);
235	else if (perf_stat_evsel__is(counter, TOPDOWN_SLOTS_RETIRED))	255	else if (perf_stat_evsel__is(counter, TOPDOWN_SLOTS_RETIRED))
236	update_runtime_stat(st, STAT_TOPDOWN_SLOTS_RETIRED,	256	update_runtime_stat(st, STAT_TOPDOWN_SLOTS_RETIRED,
237	ctx, cpu, count);	257	cpu, count, &rsd);
238	else if (perf_stat_evsel__is(counter, TOPDOWN_FETCH_BUBBLES))	258	else if (perf_stat_evsel__is(counter, TOPDOWN_FETCH_BUBBLES))
239	update_runtime_stat(st, STAT_TOPDOWN_FETCH_BUBBLES,	259	update_runtime_stat(st, STAT_TOPDOWN_FETCH_BUBBLES,
240	ctx, cpu, count);	260	cpu, count, &rsd);
241	else if (perf_stat_evsel__is(counter, TOPDOWN_RECOVERY_BUBBLES))	261	else if (perf_stat_evsel__is(counter, TOPDOWN_RECOVERY_BUBBLES))
242	update_runtime_stat(st, STAT_TOPDOWN_RECOVERY_BUBBLES,	262	update_runtime_stat(st, STAT_TOPDOWN_RECOVERY_BUBBLES,
243	ctx, cpu, count);	263	cpu, count, &rsd);
244	else if (perf_stat_evsel__is(counter, TOPDOWN_RETIRING))	264	else if (perf_stat_evsel__is(counter, TOPDOWN_RETIRING))
245	update_runtime_stat(st, STAT_TOPDOWN_RETIRING,	265	update_runtime_stat(st, STAT_TOPDOWN_RETIRING,
246	ctx, cpu, count);	266	cpu, count, &rsd);
247	else if (perf_stat_evsel__is(counter, TOPDOWN_BAD_SPEC))	267	else if (perf_stat_evsel__is(counter, TOPDOWN_BAD_SPEC))
248	update_runtime_stat(st, STAT_TOPDOWN_BAD_SPEC,	268	update_runtime_stat(st, STAT_TOPDOWN_BAD_SPEC,
249	ctx, cpu, count);	269	cpu, count, &rsd);
250	else if (perf_stat_evsel__is(counter, TOPDOWN_FE_BOUND))	270	else if (perf_stat_evsel__is(counter, TOPDOWN_FE_BOUND))
251	update_runtime_stat(st, STAT_TOPDOWN_FE_BOUND,	271	update_runtime_stat(st, STAT_TOPDOWN_FE_BOUND,
252	ctx, cpu, count);	272	cpu, count, &rsd);
253	else if (perf_stat_evsel__is(counter, TOPDOWN_BE_BOUND))	273	else if (perf_stat_evsel__is(counter, TOPDOWN_BE_BOUND))
254	update_runtime_stat(st, STAT_TOPDOWN_BE_BOUND,	274	update_runtime_stat(st, STAT_TOPDOWN_BE_BOUND,
255	ctx, cpu, count);	275	cpu, count, &rsd);
256	else if (evsel__match(counter, HARDWARE, HW_STALLED_CYCLES_FRONTEND))	276	else if (evsel__match(counter, HARDWARE, HW_STALLED_CYCLES_FRONTEND))
257	update_runtime_stat(st, STAT_STALLED_CYCLES_FRONT,	277	update_runtime_stat(st, STAT_STALLED_CYCLES_FRONT,
258	ctx, cpu, count);	278	cpu, count, &rsd);
259	else if (evsel__match(counter, HARDWARE, HW_STALLED_CYCLES_BACKEND))	279	else if (evsel__match(counter, HARDWARE, HW_STALLED_CYCLES_BACKEND))
260	update_runtime_stat(st, STAT_STALLED_CYCLES_BACK,	280	update_runtime_stat(st, STAT_STALLED_CYCLES_BACK,
261	ctx, cpu, count);	281	cpu, count, &rsd);
262	else if (evsel__match(counter, HARDWARE, HW_BRANCH_INSTRUCTIONS))	282	else if (evsel__match(counter, HARDWARE, HW_BRANCH_INSTRUCTIONS))
263	update_runtime_stat(st, STAT_BRANCHES, ctx, cpu, count);	283	update_runtime_stat(st, STAT_BRANCHES, cpu, count, &rsd);
264	else if (evsel__match(counter, HARDWARE, HW_CACHE_REFERENCES))	284	else if (evsel__match(counter, HARDWARE, HW_CACHE_REFERENCES))
265	update_runtime_stat(st, STAT_CACHEREFS, ctx, cpu, count);	285	update_runtime_stat(st, STAT_CACHEREFS, cpu, count, &rsd);
266	else if (evsel__match(counter, HW_CACHE, HW_CACHE_L1D))	286	else if (evsel__match(counter, HW_CACHE, HW_CACHE_L1D))
267	update_runtime_stat(st, STAT_L1_DCACHE, ctx, cpu, count);	287	update_runtime_stat(st, STAT_L1_DCACHE, cpu, count, &rsd);
268	else if (evsel__match(counter, HW_CACHE, HW_CACHE_L1I))	288	else if (evsel__match(counter, HW_CACHE, HW_CACHE_L1I))
269	update_runtime_stat(st, STAT_L1_ICACHE, ctx, cpu, count);	289	update_runtime_stat(st, STAT_L1_ICACHE, cpu, count, &rsd);
270	else if (evsel__match(counter, HW_CACHE, HW_CACHE_LL))	290	else if (evsel__match(counter, HW_CACHE, HW_CACHE_LL))
271	update_runtime_stat(st, STAT_LL_CACHE, ctx, cpu, count);	291	update_runtime_stat(st, STAT_LL_CACHE, cpu, count, &rsd);
272	else if (evsel__match(counter, HW_CACHE, HW_CACHE_DTLB))	292	else if (evsel__match(counter, HW_CACHE, HW_CACHE_DTLB))
273	update_runtime_stat(st, STAT_DTLB_CACHE, ctx, cpu, count);	293	update_runtime_stat(st, STAT_DTLB_CACHE, cpu, count, &rsd);
274	else if (evsel__match(counter, HW_CACHE, HW_CACHE_ITLB))	294	else if (evsel__match(counter, HW_CACHE, HW_CACHE_ITLB))
275	update_runtime_stat(st, STAT_ITLB_CACHE, ctx, cpu, count);	295	update_runtime_stat(st, STAT_ITLB_CACHE, cpu, count, &rsd);
276	else if (perf_stat_evsel__is(counter, SMI_NUM))	296	else if (perf_stat_evsel__is(counter, SMI_NUM))
277	update_runtime_stat(st, STAT_SMI_NUM, ctx, cpu, count);	297	update_runtime_stat(st, STAT_SMI_NUM, cpu, count, &rsd);
278	else if (perf_stat_evsel__is(counter, APERF))	298	else if (perf_stat_evsel__is(counter, APERF))
279	update_runtime_stat(st, STAT_APERF, ctx, cpu, count);	299	update_runtime_stat(st, STAT_APERF, cpu, count, &rsd);
280		300
281	if (counter->collect_stat) {	301	if (counter->collect_stat) {
282	v = saved_value_lookup(counter, cpu, true, STAT_NONE, 0, st);	302	v = saved_value_lookup(counter, cpu, true, STAT_NONE, 0, st,
		303	rsd.cgrp);
283	update_stats(&v->stats, count);	304	update_stats(&v->stats, count);
284	if (counter->metric_leader)	305	if (counter->metric_leader)
285	v->metric_total += count;	306	v->metric_total += count;
286	} else if (counter->metric_leader) {	307	} else if (counter->metric_leader) {
287	v = saved_value_lookup(counter->metric_leader,	308	v = saved_value_lookup(counter->metric_leader,
288	cpu, true, STAT_NONE, 0, st);	309	cpu, true, STAT_NONE, 0, st, rsd.cgrp);
289	v->metric_total += count;	310	v->metric_total += count;
290	v->metric_other++;	311	v->metric_other++;
291	}	312	}
@@ -422,11 +443,12 @@ void perf_stat__collect_metric_expr(struct evlist *evsel_list) · 130 unmodified lines
422	}	443	}
423		444
424	static double runtime_stat_avg(struct runtime_stat *st,	445	static double runtime_stat_avg(struct runtime_stat *st,
425	enum stat_type type, int ctx, int cpu)	446	enum stat_type type, int cpu,
		447	struct runtime_stat_data *rsd)
426	{	448	{
427	struct saved_value *v;	449	struct saved_value *v;
428		450
429	v = saved_value_lookup(NULL, cpu, false, type, ctx, st);	451	v = saved_value_lookup(NULL, cpu, false, type, rsd->ctx, st, rsd->cgrp);
430	if (!v)	452	if (!v)
431	return 0.0;	453	return 0.0;
432		454
@@ -434,11 +456,12 @@ static double runtime_stat_avg(struct runtime_stat *st, · 1 unmodified line
434	}	456	}
435		457
436	static double runtime_stat_n(struct runtime_stat *st,	458	static double runtime_stat_n(struct runtime_stat *st,
437	enum stat_type type, int ctx, int cpu)	459	enum stat_type type, int cpu,
		460	struct runtime_stat_data *rsd)
438	{	461	{
439	struct saved_value *v;	462	struct saved_value *v;
440		463
441	v = saved_value_lookup(NULL, cpu, false, type, ctx, st);	464	v = saved_value_lookup(NULL, cpu, false, type, rsd->ctx, st, rsd->cgrp);
442	if (!v)	465	if (!v)
443	return 0.0;	466	return 0.0;
444		467
@@ -446,16 +469,15 @@ static double runtime_stat_n(struct runtime_stat *st, · 1 unmodified line
446	}	469	}
447		470
448	static void print_stalled_cycles_frontend(struct perf_stat_config *config,	471	static void print_stalled_cycles_frontend(struct perf_stat_config *config,
449	int cpu,	472	int cpu, double avg,
450	struct evsel *evsel, double avg,
451	struct perf_stat_output_ctx *out,	473	struct perf_stat_output_ctx *out,
452	struct runtime_stat *st)	474	struct runtime_stat *st,
		475	struct runtime_stat_data *rsd)
453	{	476	{
454	double total, ratio = 0.0;	477	double total, ratio = 0.0;
455	const char *color;	478	const char *color;
456	int ctx = evsel_context(evsel);
457		479
458	total = runtime_stat_avg(st, STAT_CYCLES, ctx, cpu);	480	total = runtime_stat_avg(st, STAT_CYCLES, cpu, rsd);
459		481
460	if (total)	482	if (total)
461	ratio = avg / total * 100.0;	483	ratio = avg / total * 100.0;
@@ -470,16 +492,15 @@ static void print_stalled_cycles_frontend(struct perf_stat_config *config, · 8 unmodified lines
470	}	492	}
471		493
472	static void print_stalled_cycles_backend(struct perf_stat_config *config,	494	static void print_stalled_cycles_backend(struct perf_stat_config *config,
473	int cpu,	495	int cpu, double avg,
474	struct evsel *evsel, double avg,
475	struct perf_stat_output_ctx *out,	496	struct perf_stat_output_ctx *out,
476	struct runtime_stat *st)	497	struct runtime_stat *st,
		498	struct runtime_stat_data *rsd)
477	{	499	{
478	double total, ratio = 0.0;	500	double total, ratio = 0.0;
479	const char *color;	501	const char *color;
480	int ctx = evsel_context(evsel);
481		502
482	total = runtime_stat_avg(st, STAT_CYCLES, ctx, cpu);	503	total = runtime_stat_avg(st, STAT_CYCLES, cpu, rsd);
483		504
484	if (total)	505	if (total)
485	ratio = avg / total * 100.0;	506	ratio = avg / total * 100.0;
@@ -490,17 +511,15 @@ static void print_stalled_cycles_backend(struct perf_stat_config *config, · 4 unmodified lines
490	}	511	}
491		512
492	static void print_branch_misses(struct perf_stat_config *config,	513	static void print_branch_misses(struct perf_stat_config *config,
493	int cpu,	514	int cpu, double avg,
494	struct evsel *evsel,
495	double avg,
496	struct perf_stat_output_ctx *out,	515	struct perf_stat_output_ctx *out,
497	struct runtime_stat *st)	516	struct runtime_stat *st,
		517	struct runtime_stat_data *rsd)
498	{	518	{
499	double total, ratio = 0.0;	519	double total, ratio = 0.0;
500	const char *color;	520	const char *color;
501	int ctx = evsel_context(evsel);
502		521
503	total = runtime_stat_avg(st, STAT_BRANCHES, ctx, cpu);	522	total = runtime_stat_avg(st, STAT_BRANCHES, cpu, rsd);
504		523
505	if (total)	524	if (total)
506	ratio = avg / total * 100.0;	525	ratio = avg / total * 100.0;
@@ -511,18 +530,15 @@ static void print_branch_misses(struct perf_stat_config *config, · 4 unmodified lines
511	}	530	}
512		531
513	static void print_l1_dcache_misses(struct perf_stat_config *config,	532	static void print_l1_dcache_misses(struct perf_stat_config *config,
514	int cpu,	533	int cpu, double avg,
515	struct evsel *evsel,
516	double avg,
517	struct perf_stat_output_ctx *out,	534	struct perf_stat_output_ctx *out,
518	struct runtime_stat *st)	535	struct runtime_stat *st,
519		536	struct runtime_stat_data *rsd)
520	{	537	{
521	double total, ratio = 0.0;	538	double total, ratio = 0.0;
522	const char *color;	539	const char *color;
523	int ctx = evsel_context(evsel);
524		540
525	total = runtime_stat_avg(st, STAT_L1_DCACHE, ctx, cpu);	541	total = runtime_stat_avg(st, STAT_L1_DCACHE, cpu, rsd);
526		542
527	if (total)	543	if (total)
528	ratio = avg / total * 100.0;	544	ratio = avg / total * 100.0;
@@ -533,18 +549,15 @@ static void print_l1_dcache_misses(struct perf_stat_config *config, · 4 unmodified lines
533	}	549	}
534		550
535	static void print_l1_icache_misses(struct perf_stat_config *config,	551	static void print_l1_icache_misses(struct perf_stat_config *config,
536	int cpu,	552	int cpu, double avg,
537	struct evsel *evsel,
538	double avg,
539	struct perf_stat_output_ctx *out,	553	struct perf_stat_output_ctx *out,
540	struct runtime_stat *st)	554	struct runtime_stat *st,
541		555	struct runtime_stat_data *rsd)
542	{	556	{
543	double total, ratio = 0.0;	557	double total, ratio = 0.0;
544	const char *color;	558	const char *color;
545	int ctx = evsel_context(evsel);
546		559
547	total = runtime_stat_avg(st, STAT_L1_ICACHE, ctx, cpu);	560	total = runtime_stat_avg(st, STAT_L1_ICACHE, cpu, rsd);
548		561
549	if (total)	562	if (total)
550	ratio = avg / total * 100.0;	563	ratio = avg / total * 100.0;
@@ -554,17 +567,15 @@ static void print_l1_icache_misses(struct perf_stat_config *config, · 3 unmodified lines
554	}	567	}
555		568
556	static void print_dtlb_cache_misses(struct perf_stat_config *config,	569	static void print_dtlb_cache_misses(struct perf_stat_config *config,
557	int cpu,	570	int cpu, double avg,
558	struct evsel *evsel,
559	double avg,
560	struct perf_stat_output_ctx *out,	571	struct perf_stat_output_ctx *out,
561	struct runtime_stat *st)	572	struct runtime_stat *st,
		573	struct runtime_stat_data *rsd)
562	{	574	{
563	double total, ratio = 0.0;	575	double total, ratio = 0.0;
564	const char *color;	576	const char *color;
565	int ctx = evsel_context(evsel);
566		577
567	total = runtime_stat_avg(st, STAT_DTLB_CACHE, ctx, cpu);	578	total = runtime_stat_avg(st, STAT_DTLB_CACHE, cpu, rsd);
568		579
569	if (total)	580	if (total)
570	ratio = avg / total * 100.0;	581	ratio = avg / total * 100.0;
@@ -574,17 +585,15 @@ static void print_dtlb_cache_misses(struct perf_stat_config *config, · 3 unmodified lines
574	}	585	}
575		586
576	static void print_itlb_cache_misses(struct perf_stat_config *config,	587	static void print_itlb_cache_misses(struct perf_stat_config *config,
577	int cpu,	588	int cpu, double avg,
578	struct evsel *evsel,
579	double avg,
580	struct perf_stat_output_ctx *out,	589	struct perf_stat_output_ctx *out,
581	struct runtime_stat *st)	590	struct runtime_stat *st,
		591	struct runtime_stat_data *rsd)
582	{	592	{
583	double total, ratio = 0.0;	593	double total, ratio = 0.0;
584	const char *color;	594	const char *color;
585	int ctx = evsel_context(evsel);
586		595
587	total = runtime_stat_avg(st, STAT_ITLB_CACHE, ctx, cpu);	596	total = runtime_stat_avg(st, STAT_ITLB_CACHE, cpu, rsd);
588		597
589	if (total)	598	if (total)
590	ratio = avg / total * 100.0;	599	ratio = avg / total * 100.0;
@@ -594,17 +603,15 @@ static void print_itlb_cache_misses(struct perf_stat_config *config, · 3 unmodified lines
594	}	603	}
595		604
596	static void print_ll_cache_misses(struct perf_stat_config *config,	605	static void print_ll_cache_misses(struct perf_stat_config *config,
597	int cpu,	606	int cpu, double avg,
598	struct evsel *evsel,
599	double avg,
600	struct perf_stat_output_ctx *out,	607	struct perf_stat_output_ctx *out,
601	struct runtime_stat *st)	608	struct runtime_stat *st,
		609	struct runtime_stat_data *rsd)
602	{	610	{
603	double total, ratio = 0.0;	611	double total, ratio = 0.0;
604	const char *color;	612	const char *color;
605	int ctx = evsel_context(evsel);
606		613
607	total = runtime_stat_avg(st, STAT_LL_CACHE, ctx, cpu);	614	total = runtime_stat_avg(st, STAT_LL_CACHE, cpu, rsd);
608		615
609	if (total)	616	if (total)
610	ratio = avg / total * 100.0;	617	ratio = avg / total * 100.0;
@@ -662,56 +669,61 @@ static double sanitize_val(double x) · 51 unmodified lines
662	return x;	669	return x;
663	}	670	}
664		671
665	static double td_total_slots(int ctx, int cpu, struct runtime_stat *st)	672	static double td_total_slots(int cpu, struct runtime_stat *st,
		673	struct runtime_stat_data *rsd)
666	{	674	{
667	return runtime_stat_avg(st, STAT_TOPDOWN_TOTAL_SLOTS, ctx, cpu);	675	return runtime_stat_avg(st, STAT_TOPDOWN_TOTAL_SLOTS, cpu, rsd);
668	}	676	}
669		677
670	static double td_bad_spec(int ctx, int cpu, struct runtime_stat *st)	678	static double td_bad_spec(int cpu, struct runtime_stat *st,
		679	struct runtime_stat_data *rsd)
671	{	680	{
672	double bad_spec = 0;	681	double bad_spec = 0;
673	double total_slots;	682	double total_slots;
674	double total;	683	double total;
675		684
676	total = runtime_stat_avg(st, STAT_TOPDOWN_SLOTS_ISSUED, ctx, cpu) -	685	total = runtime_stat_avg(st, STAT_TOPDOWN_SLOTS_ISSUED, cpu, rsd) -
677	runtime_stat_avg(st, STAT_TOPDOWN_SLOTS_RETIRED, ctx, cpu) +	686	runtime_stat_avg(st, STAT_TOPDOWN_SLOTS_RETIRED, cpu, rsd) +
678	runtime_stat_avg(st, STAT_TOPDOWN_RECOVERY_BUBBLES, ctx, cpu);	687	runtime_stat_avg(st, STAT_TOPDOWN_RECOVERY_BUBBLES, cpu, rsd);
679		688
680	total_slots = td_total_slots(ctx, cpu, st);	689	total_slots = td_total_slots(cpu, st, rsd);
681	if (total_slots)	690	if (total_slots)
682	bad_spec = total / total_slots;	691	bad_spec = total / total_slots;
683	return sanitize_val(bad_spec);	692	return sanitize_val(bad_spec);
684	}	693	}
685		694
686	static double td_retiring(int ctx, int cpu, struct runtime_stat *st)	695	static double td_retiring(int cpu, struct runtime_stat *st,
		696	struct runtime_stat_data *rsd)
687	{	697	{
688	double retiring = 0;	698	double retiring = 0;
689	double total_slots = td_total_slots(ctx, cpu, st);	699	double total_slots = td_total_slots(cpu, st, rsd);
690	double ret_slots = runtime_stat_avg(st, STAT_TOPDOWN_SLOTS_RETIRED,	700	double ret_slots = runtime_stat_avg(st, STAT_TOPDOWN_SLOTS_RETIRED,
691	ctx, cpu);	701	cpu, rsd);
692		702
693	if (total_slots)	703	if (total_slots)
694	retiring = ret_slots / total_slots;	704	retiring = ret_slots / total_slots;
695	return retiring;	705	return retiring;
696	}	706	}
697		707
698	static double td_fe_bound(int ctx, int cpu, struct runtime_stat *st)	708	static double td_fe_bound(int cpu, struct runtime_stat *st,
		709	struct runtime_stat_data *rsd)
699	{	710	{
700	double fe_bound = 0;	711	double fe_bound = 0;
701	double total_slots = td_total_slots(ctx, cpu, st);	712	double total_slots = td_total_slots(cpu, st, rsd);
702	double fetch_bub = runtime_stat_avg(st, STAT_TOPDOWN_FETCH_BUBBLES,	713	double fetch_bub = runtime_stat_avg(st, STAT_TOPDOWN_FETCH_BUBBLES,
703	ctx, cpu);	714	cpu, rsd);
704		715
705	if (total_slots)	716	if (total_slots)
706	fe_bound = fetch_bub / total_slots;	717	fe_bound = fetch_bub / total_slots;
707	return fe_bound;	718	return fe_bound;
708	}	719	}
709		720
710	static double td_be_bound(int ctx, int cpu, struct runtime_stat *st)	721	static double td_be_bound(int cpu, struct runtime_stat *st,
		722	struct runtime_stat_data *rsd)
711	{	723	{
712	double sum = (td_fe_bound(ctx, cpu, st) +	724	double sum = (td_fe_bound(cpu, st, rsd) +
713	td_bad_spec(ctx, cpu, st) +	725	td_bad_spec(cpu, st, rsd) +
714	td_retiring(ctx, cpu, st));	726	td_retiring(cpu, st, rsd));
715	if (sum == 0)	727	if (sum == 0)
716	return 0;	728	return 0;
717	return sanitize_val(1.0 - sum);	729	return sanitize_val(1.0 - sum);
@@ -722,15 +734,15 @@ static double td_be_bound(int ctx, int cpu, struct runtime_stat *st) · 4 unmodified lines
722	* the ratios we need to recreate the sum.	734	* the ratios we need to recreate the sum.
723	*/	735	*/
724		736
725	static double td_metric_ratio(int ctx, int cpu,	737	static double td_metric_ratio(int cpu, enum stat_type type,
726	enum stat_type type,	738	struct runtime_stat *stat,
727	struct runtime_stat *stat)	739	struct runtime_stat_data *rsd)
728	{	740	{
729	double sum = runtime_stat_avg(stat, STAT_TOPDOWN_RETIRING, ctx, cpu) +	741	double sum = runtime_stat_avg(stat, STAT_TOPDOWN_RETIRING, cpu, rsd) +
730	runtime_stat_avg(stat, STAT_TOPDOWN_FE_BOUND, ctx, cpu) +	742	runtime_stat_avg(stat, STAT_TOPDOWN_FE_BOUND, cpu, rsd) +
731	runtime_stat_avg(stat, STAT_TOPDOWN_BE_BOUND, ctx, cpu) +	743	runtime_stat_avg(stat, STAT_TOPDOWN_BE_BOUND, cpu, rsd) +
732	runtime_stat_avg(stat, STAT_TOPDOWN_BAD_SPEC, ctx, cpu);	744	runtime_stat_avg(stat, STAT_TOPDOWN_BAD_SPEC, cpu, rsd);
733	double d = runtime_stat_avg(stat, type, ctx, cpu);	745	double d = runtime_stat_avg(stat, type, cpu, rsd);
734		746
735	if (sum)	747	if (sum)
736	return d / sum;	748	return d / sum;
@@ -742,34 +754,33 @@ static double td_metric_ratio(int ctx, int cpu, · 5 unmodified lines
742	* We allow two missing.	754	* We allow two missing.
743	*/	755	*/
744		756
745	static bool full_td(int ctx, int cpu,	757	static bool full_td(int cpu, struct runtime_stat *stat,
746	struct runtime_stat *stat)	758	struct runtime_stat_data *rsd)
747	{	759	{
748	int c = 0;	760	int c = 0;
749		761
750	if (runtime_stat_avg(stat, STAT_TOPDOWN_RETIRING, ctx, cpu) > 0)	762	if (runtime_stat_avg(stat, STAT_TOPDOWN_RETIRING, cpu, rsd) > 0)
751	c++;	763	c++;
752	if (runtime_stat_avg(stat, STAT_TOPDOWN_BE_BOUND, ctx, cpu) > 0)	764	if (runtime_stat_avg(stat, STAT_TOPDOWN_BE_BOUND, cpu, rsd) > 0)
753	c++;	765	c++;
754	if (runtime_stat_avg(stat, STAT_TOPDOWN_FE_BOUND, ctx, cpu) > 0)	766	if (runtime_stat_avg(stat, STAT_TOPDOWN_FE_BOUND, cpu, rsd) > 0)
755	c++;	767	c++;
756	if (runtime_stat_avg(stat, STAT_TOPDOWN_BAD_SPEC, ctx, cpu) > 0)	768	if (runtime_stat_avg(stat, STAT_TOPDOWN_BAD_SPEC, cpu, rsd) > 0)
757	c++;	769	c++;
758	return c >= 2;	770	return c >= 2;
759	}	771	}
760		772
761	static void print_smi_cost(struct perf_stat_config *config,	773	static void print_smi_cost(struct perf_stat_config *config, int cpu,
762	int cpu, struct evsel *evsel,
763	struct perf_stat_output_ctx *out,	774	struct perf_stat_output_ctx *out,
764	struct runtime_stat *st)	775	struct runtime_stat *st,
		776	struct runtime_stat_data *rsd)
765	{	777	{
766	double smi_num, aperf, cycles, cost = 0.0;	778	double smi_num, aperf, cycles, cost = 0.0;
767	int ctx = evsel_context(evsel);
768	const char *color = NULL;	779	const char *color = NULL;
769		780
770	smi_num = runtime_stat_avg(st, STAT_SMI_NUM, ctx, cpu);	781	smi_num = runtime_stat_avg(st, STAT_SMI_NUM, cpu, rsd);
771	aperf = runtime_stat_avg(st, STAT_APERF, ctx, cpu);	782	aperf = runtime_stat_avg(st, STAT_APERF, cpu, rsd);
772	cycles = runtime_stat_avg(st, STAT_CYCLES, ctx, cpu);	783	cycles = runtime_stat_avg(st, STAT_CYCLES, cpu, rsd);
773		784
774	if ((cycles == 0) \|\| (aperf == 0))	785	if ((cycles == 0) \|\| (aperf == 0))
775	return;	786	return;
@@ -804,7 +815,8 @@ static int prepare_metric(struct evsel **metric_events, · 28 unmodified lines
804	scale = 1e-9;	815	scale = 1e-9;
805	} else {	816	} else {
806	v = saved_value_lookup(metric_events[i], cpu, false,	817	v = saved_value_lookup(metric_events[i], cpu, false,
807	STAT_NONE, 0, st);	818	STAT_NONE, 0, st,
		819	metric_events[i]->cgrp);
808	if (!v)	820	if (!v)
809	break;	821	break;
810	stats = &v->stats;	822	stats = &v->stats;
@@ -930,12 +942,15 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, · 119 unmodified lines
930	print_metric_t print_metric = out->print_metric;	942	print_metric_t print_metric = out->print_metric;
931	double total, ratio = 0.0, total2;	943	double total, ratio = 0.0, total2;
932	const char *color = NULL;	944	const char *color = NULL;
933	int ctx = evsel_context(evsel);	945	struct runtime_stat_data rsd = {
		946	.ctx = evsel_context(evsel),
		947	.cgrp = evsel->cgrp,
		948	};
934	struct metric_event *me;	949	struct metric_event *me;
935	int num = 1;	950	int num = 1;
936		951
937	if (evsel__match(evsel, HARDWARE, HW_INSTRUCTIONS)) {	952	if (evsel__match(evsel, HARDWARE, HW_INSTRUCTIONS)) {
938	total = runtime_stat_avg(st, STAT_CYCLES, ctx, cpu);	953	total = runtime_stat_avg(st, STAT_CYCLES, cpu, &rsd);
939		954
940	if (total) {	955	if (total) {
941	ratio = avg / total;	956	ratio = avg / total;
@@ -945,12 +960,11 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, · 3 unmodified lines
945	print_metric(config, ctxp, NULL, NULL, "insn per cycle", 0);	960	print_metric(config, ctxp, NULL, NULL, "insn per cycle", 0);
946	}	961	}
947		962
948	total = runtime_stat_avg(st, STAT_STALLED_CYCLES_FRONT,	963	total = runtime_stat_avg(st, STAT_STALLED_CYCLES_FRONT, cpu, &rsd);
949	ctx, cpu);
950		964
951	total = max(total, runtime_stat_avg(st,	965	total = max(total, runtime_stat_avg(st,
952	STAT_STALLED_CYCLES_BACK,	966	STAT_STALLED_CYCLES_BACK,
953	ctx, cpu));	967	cpu, &rsd));
954		968
955	if (total && avg) {	969	if (total && avg) {
956	out->new_line(config, ctxp);	970	out->new_line(config, ctxp);
@@ -960,8 +974,8 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, · 3 unmodified lines
960	ratio);	974	ratio);
961	}	975	}
962	} else if (evsel__match(evsel, HARDWARE, HW_BRANCH_MISSES)) {	976	} else if (evsel__match(evsel, HARDWARE, HW_BRANCH_MISSES)) {
963	if (runtime_stat_n(st, STAT_BRANCHES, ctx, cpu) != 0)	977	if (runtime_stat_n(st, STAT_BRANCHES, cpu, &rsd) != 0)
964	print_branch_misses(config, cpu, evsel, avg, out, st);	978	print_branch_misses(config, cpu, avg, out, st, &rsd);
965	else	979	else
966	print_metric(config, ctxp, NULL, NULL, "of all branches", 0);	980	print_metric(config, ctxp, NULL, NULL, "of all branches", 0);
967	} else if (	981	} else if (
@@ -970,8 +984,8 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, · 2 unmodified lines
970	((PERF_COUNT_HW_CACHE_OP_READ) << 8) \|	984	((PERF_COUNT_HW_CACHE_OP_READ) << 8) \|
971	((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) {	985	((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) {
972		986
973	if (runtime_stat_n(st, STAT_L1_DCACHE, ctx, cpu) != 0)	987	if (runtime_stat_n(st, STAT_L1_DCACHE, cpu, &rsd) != 0)
974	print_l1_dcache_misses(config, cpu, evsel, avg, out, st);	988	print_l1_dcache_misses(config, cpu, avg, out, st, &rsd);
975	else	989	else
976	print_metric(config, ctxp, NULL, NULL, "of all L1-dcache accesses", 0);	990	print_metric(config, ctxp, NULL, NULL, "of all L1-dcache accesses", 0);
977	} else if (	991	} else if (
@@ -980,8 +994,8 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, · 2 unmodified lines
980	((PERF_COUNT_HW_CACHE_OP_READ) << 8) \|	994	((PERF_COUNT_HW_CACHE_OP_READ) << 8) \|
981	((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) {	995	((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) {
982		996
983	if (runtime_stat_n(st, STAT_L1_ICACHE, ctx, cpu) != 0)	997	if (runtime_stat_n(st, STAT_L1_ICACHE, cpu, &rsd) != 0)
984	print_l1_icache_misses(config, cpu, evsel, avg, out, st);	998	print_l1_icache_misses(config, cpu, avg, out, st, &rsd);
985	else	999	else
986	print_metric(config, ctxp, NULL, NULL, "of all L1-icache accesses", 0);	1000	print_metric(config, ctxp, NULL, NULL, "of all L1-icache accesses", 0);
987	} else if (	1001	} else if (
@@ -990,8 +1004,8 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, · 2 unmodified lines
990	((PERF_COUNT_HW_CACHE_OP_READ) << 8) \|	1004	((PERF_COUNT_HW_CACHE_OP_READ) << 8) \|
991	((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) {	1005	((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) {
992		1006
993	if (runtime_stat_n(st, STAT_DTLB_CACHE, ctx, cpu) != 0)	1007	if (runtime_stat_n(st, STAT_DTLB_CACHE, cpu, &rsd) != 0)
994	print_dtlb_cache_misses(config, cpu, evsel, avg, out, st);	1008	print_dtlb_cache_misses(config, cpu, avg, out, st, &rsd);
995	else	1009	else
996	print_metric(config, ctxp, NULL, NULL, "of all dTLB cache accesses", 0);	1010	print_metric(config, ctxp, NULL, NULL, "of all dTLB cache accesses", 0);
997	} else if (	1011	} else if (
@@ -1000,8 +1014,8 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, · 2 unmodified lines
1000	((PERF_COUNT_HW_CACHE_OP_READ) << 8) \|	1014	((PERF_COUNT_HW_CACHE_OP_READ) << 8) \|
1001	((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) {	1015	((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) {
1002		1016
1003	if (runtime_stat_n(st, STAT_ITLB_CACHE, ctx, cpu) != 0)	1017	if (runtime_stat_n(st, STAT_ITLB_CACHE, cpu, &rsd) != 0)
1004	print_itlb_cache_misses(config, cpu, evsel, avg, out, st);	1018	print_itlb_cache_misses(config, cpu, avg, out, st, &rsd);
1005	else	1019	else
1006	print_metric(config, ctxp, NULL, NULL, "of all iTLB cache accesses", 0);	1020	print_metric(config, ctxp, NULL, NULL, "of all iTLB cache accesses", 0);
1007	} else if (	1021	} else if (
@@ -1010,27 +1024,27 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, · 2 unmodified lines
1010	((PERF_COUNT_HW_CACHE_OP_READ) << 8) \|	1024	((PERF_COUNT_HW_CACHE_OP_READ) << 8) \|
1011	((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) {	1025	((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) {
1012		1026
1013	if (runtime_stat_n(st, STAT_LL_CACHE, ctx, cpu) != 0)	1027	if (runtime_stat_n(st, STAT_LL_CACHE, cpu, &rsd) != 0)
1014	print_ll_cache_misses(config, cpu, evsel, avg, out, st);	1028	print_ll_cache_misses(config, cpu, avg, out, st, &rsd);
1015	else	1029	else
1016	print_metric(config, ctxp, NULL, NULL, "of all LL-cache accesses", 0);	1030	print_metric(config, ctxp, NULL, NULL, "of all LL-cache accesses", 0);
1017	} else if (evsel__match(evsel, HARDWARE, HW_CACHE_MISSES)) {	1031	} else if (evsel__match(evsel, HARDWARE, HW_CACHE_MISSES)) {
1018	total = runtime_stat_avg(st, STAT_CACHEREFS, ctx, cpu);	1032	total = runtime_stat_avg(st, STAT_CACHEREFS, cpu, &rsd);
1019		1033
1020	if (total)	1034	if (total)
1021	ratio = avg * 100 / total;	1035	ratio = avg * 100 / total;
1022		1036
1023	if (runtime_stat_n(st, STAT_CACHEREFS, ctx, cpu) != 0)	1037	if (runtime_stat_n(st, STAT_CACHEREFS, cpu, &rsd) != 0)
1024	print_metric(config, ctxp, NULL, "%8.3f %%",	1038	print_metric(config, ctxp, NULL, "%8.3f %%",
1025	"of all cache refs", ratio);	1039	"of all cache refs", ratio);
1026	else	1040	else
1027	print_metric(config, ctxp, NULL, NULL, "of all cache refs", 0);	1041	print_metric(config, ctxp, NULL, NULL, "of all cache refs", 0);
1028	} else if (evsel__match(evsel, HARDWARE, HW_STALLED_CYCLES_FRONTEND)) {	1042	} else if (evsel__match(evsel, HARDWARE, HW_STALLED_CYCLES_FRONTEND)) {
1029	print_stalled_cycles_frontend(config, cpu, evsel, avg, out, st);	1043	print_stalled_cycles_frontend(config, cpu, avg, out, st, &rsd);
1030	} else if (evsel__match(evsel, HARDWARE, HW_STALLED_CYCLES_BACKEND)) {	1044	} else if (evsel__match(evsel, HARDWARE, HW_STALLED_CYCLES_BACKEND)) {
1031	print_stalled_cycles_backend(config, cpu, evsel, avg, out, st);	1045	print_stalled_cycles_backend(config, cpu, avg, out, st, &rsd);
1032	} else if (evsel__match(evsel, HARDWARE, HW_CPU_CYCLES)) {	1046	} else if (evsel__match(evsel, HARDWARE, HW_CPU_CYCLES)) {
1033	total = runtime_stat_avg(st, STAT_NSECS, 0, cpu);	1047	total = runtime_stat_avg(st, STAT_NSECS, cpu, &rsd);
1034		1048
1035	if (total) {	1049	if (total) {
1036	ratio = avg / total;	1050	ratio = avg / total;
@@ -1039,7 +1053,7 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, · 2 unmodified lines
1039	print_metric(config, ctxp, NULL, NULL, "Ghz", 0);	1053	print_metric(config, ctxp, NULL, NULL, "Ghz", 0);
1040	}	1054	}
1041	} else if (perf_stat_evsel__is(evsel, CYCLES_IN_TX)) {	1055	} else if (perf_stat_evsel__is(evsel, CYCLES_IN_TX)) {
1042	total = runtime_stat_avg(st, STAT_CYCLES, ctx, cpu);	1056	total = runtime_stat_avg(st, STAT_CYCLES, cpu, &rsd);
1043		1057
1044	if (total)	1058	if (total)
1045	print_metric(config, ctxp, NULL,	1059	print_metric(config, ctxp, NULL,
@@ -1049,8 +1063,8 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, · 3 unmodified lines
1049	print_metric(config, ctxp, NULL, NULL, "transactional cycles",	1063	print_metric(config, ctxp, NULL, NULL, "transactional cycles",
1050	0);	1064	0);
1051	} else if (perf_stat_evsel__is(evsel, CYCLES_IN_TX_CP)) {	1065	} else if (perf_stat_evsel__is(evsel, CYCLES_IN_TX_CP)) {
1052	total = runtime_stat_avg(st, STAT_CYCLES, ctx, cpu);	1066	total = runtime_stat_avg(st, STAT_CYCLES, cpu, &rsd);
1053	total2 = runtime_stat_avg(st, STAT_CYCLES_IN_TX, ctx, cpu);	1067	total2 = runtime_stat_avg(st, STAT_CYCLES_IN_TX, cpu, &rsd);
1054		1068
1055	if (total2 < avg)	1069	if (total2 < avg)
1056	total2 = avg;	1070	total2 = avg;
@@ -1060,21 +1074,19 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, · 3 unmodified lines
1060	else	1074	else
1061	print_metric(config, ctxp, NULL, NULL, "aborted cycles", 0);	1075	print_metric(config, ctxp, NULL, NULL, "aborted cycles", 0);
1062	} else if (perf_stat_evsel__is(evsel, TRANSACTION_START)) {	1076	} else if (perf_stat_evsel__is(evsel, TRANSACTION_START)) {
1063	total = runtime_stat_avg(st, STAT_CYCLES_IN_TX,	1077	total = runtime_stat_avg(st, STAT_CYCLES_IN_TX, cpu, &rsd);
1064	ctx, cpu);
1065		1078
1066	if (avg)	1079	if (avg)
1067	ratio = total / avg;	1080	ratio = total / avg;
1068		1081
1069	if (runtime_stat_n(st, STAT_CYCLES_IN_TX, ctx, cpu) != 0)	1082	if (runtime_stat_n(st, STAT_CYCLES_IN_TX, cpu, &rsd) != 0)
1070	print_metric(config, ctxp, NULL, "%8.0f",	1083	print_metric(config, ctxp, NULL, "%8.0f",
1071	"cycles / transaction", ratio);	1084	"cycles / transaction", ratio);
1072	else	1085	else
1073	print_metric(config, ctxp, NULL, NULL, "cycles / transaction",	1086	print_metric(config, ctxp, NULL, NULL, "cycles / transaction",
1074	0);	1087	0);
1075	} else if (perf_stat_evsel__is(evsel, ELISION_START)) {	1088	} else if (perf_stat_evsel__is(evsel, ELISION_START)) {
1076	total = runtime_stat_avg(st, STAT_CYCLES_IN_TX,	1089	total = runtime_stat_avg(st, STAT_CYCLES_IN_TX, cpu, &rsd);
1077	ctx, cpu);
1078		1090
1079	if (avg)	1091	if (avg)
1080	ratio = total / avg;	1092	ratio = total / avg;
@@ -1087,28 +1099,28 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, · 6 unmodified lines
1087	else	1099	else
1088	print_metric(config, ctxp, NULL, NULL, "CPUs utilized", 0);	1100	print_metric(config, ctxp, NULL, NULL, "CPUs utilized", 0);
1089	} else if (perf_stat_evsel__is(evsel, TOPDOWN_FETCH_BUBBLES)) {	1101	} else if (perf_stat_evsel__is(evsel, TOPDOWN_FETCH_BUBBLES)) {
1090	double fe_bound = td_fe_bound(ctx, cpu, st);	1102	double fe_bound = td_fe_bound(cpu, st, &rsd);
1091		1103
1092	if (fe_bound > 0.2)	1104	if (fe_bound > 0.2)
1093	color = PERF_COLOR_RED;	1105	color = PERF_COLOR_RED;
1094	print_metric(config, ctxp, color, "%8.1f%%", "frontend bound",	1106	print_metric(config, ctxp, color, "%8.1f%%", "frontend bound",
1095	fe_bound * 100.);	1107	fe_bound * 100.);
1096	} else if (perf_stat_evsel__is(evsel, TOPDOWN_SLOTS_RETIRED)) {	1108	} else if (perf_stat_evsel__is(evsel, TOPDOWN_SLOTS_RETIRED)) {
1097	double retiring = td_retiring(ctx, cpu, st);	1109	double retiring = td_retiring(cpu, st, &rsd);
1098		1110
1099	if (retiring > 0.7)	1111	if (retiring > 0.7)
1100	color = PERF_COLOR_GREEN;	1112	color = PERF_COLOR_GREEN;
1101	print_metric(config, ctxp, color, "%8.1f%%", "retiring",	1113	print_metric(config, ctxp, color, "%8.1f%%", "retiring",
1102	retiring * 100.);	1114	retiring * 100.);
1103	} else if (perf_stat_evsel__is(evsel, TOPDOWN_RECOVERY_BUBBLES)) {	1115	} else if (perf_stat_evsel__is(evsel, TOPDOWN_RECOVERY_BUBBLES)) {
1104	double bad_spec = td_bad_spec(ctx, cpu, st);	1116	double bad_spec = td_bad_spec(cpu, st, &rsd);
1105		1117
1106	if (bad_spec > 0.1)	1118	if (bad_spec > 0.1)
1107	color = PERF_COLOR_RED;	1119	color = PERF_COLOR_RED;
1108	print_metric(config, ctxp, color, "%8.1f%%", "bad speculation",	1120	print_metric(config, ctxp, color, "%8.1f%%", "bad speculation",
1109	bad_spec * 100.);	1121	bad_spec * 100.);
1110	} else if (perf_stat_evsel__is(evsel, TOPDOWN_SLOTS_ISSUED)) {	1122	} else if (perf_stat_evsel__is(evsel, TOPDOWN_SLOTS_ISSUED)) {
1111	double be_bound = td_be_bound(ctx, cpu, st);	1123	double be_bound = td_be_bound(cpu, st, &rsd);
1112	const char *name = "backend bound";	1124	const char *name = "backend bound";
1113	static int have_recovery_bubbles = -1;	1125	static int have_recovery_bubbles = -1;
1114		1126
@@ -1121,43 +1133,43 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, · 6 unmodified lines
1121		1133
1122	if (be_bound > 0.2)	1134	if (be_bound > 0.2)
1123	color = PERF_COLOR_RED;	1135	color = PERF_COLOR_RED;
1124	if (td_total_slots(ctx, cpu, st) > 0)	1136	if (td_total_slots(cpu, st, &rsd) > 0)
1125	print_metric(config, ctxp, color, "%8.1f%%", name,	1137	print_metric(config, ctxp, color, "%8.1f%%", name,
1126	be_bound * 100.);	1138	be_bound * 100.);
1127	else	1139	else
1128	print_metric(config, ctxp, NULL, NULL, name, 0);	1140	print_metric(config, ctxp, NULL, NULL, name, 0);
1129	} else if (perf_stat_evsel__is(evsel, TOPDOWN_RETIRING) &&	1141	} else if (perf_stat_evsel__is(evsel, TOPDOWN_RETIRING) &&
1130	full_td(ctx, cpu, st)) {	1142	full_td(cpu, st, &rsd)) {
1131	double retiring = td_metric_ratio(ctx, cpu,	1143	double retiring = td_metric_ratio(cpu,
1132	STAT_TOPDOWN_RETIRING, st);	1144	STAT_TOPDOWN_RETIRING, st,
1133		1145	&rsd);
1134	if (retiring > 0.7)	1146	if (retiring > 0.7)
1135	color = PERF_COLOR_GREEN;	1147	color = PERF_COLOR_GREEN;
1136	print_metric(config, ctxp, color, "%8.1f%%", "retiring",	1148	print_metric(config, ctxp, color, "%8.1f%%", "retiring",
1137	retiring * 100.);	1149	retiring * 100.);
1138	} else if (perf_stat_evsel__is(evsel, TOPDOWN_FE_BOUND) &&	1150	} else if (perf_stat_evsel__is(evsel, TOPDOWN_FE_BOUND) &&
1139	full_td(ctx, cpu, st)) {	1151	full_td(cpu, st, &rsd)) {
1140	double fe_bound = td_metric_ratio(ctx, cpu,	1152	double fe_bound = td_metric_ratio(cpu,
1141	STAT_TOPDOWN_FE_BOUND, st);	1153	STAT_TOPDOWN_FE_BOUND, st,
1142		1154	&rsd);
1143	if (fe_bound > 0.2)	1155	if (fe_bound > 0.2)
1144	color = PERF_COLOR_RED;	1156	color = PERF_COLOR_RED;
1145	print_metric(config, ctxp, color, "%8.1f%%", "frontend bound",	1157	print_metric(config, ctxp, color, "%8.1f%%", "frontend bound",
1146	fe_bound * 100.);	1158	fe_bound * 100.);
1147	} else if (perf_stat_evsel__is(evsel, TOPDOWN_BE_BOUND) &&	1159	} else if (perf_stat_evsel__is(evsel, TOPDOWN_BE_BOUND) &&
1148	full_td(ctx, cpu, st)) {	1160	full_td(cpu, st, &rsd)) {
1149	double be_bound = td_metric_ratio(ctx, cpu,	1161	double be_bound = td_metric_ratio(cpu,
1150	STAT_TOPDOWN_BE_BOUND, st);	1162	STAT_TOPDOWN_BE_BOUND, st,
1151		1163	&rsd);
1152	if (be_bound > 0.2)	1164	if (be_bound > 0.2)
1153	color = PERF_COLOR_RED;	1165	color = PERF_COLOR_RED;
1154	print_metric(config, ctxp, color, "%8.1f%%", "backend bound",	1166	print_metric(config, ctxp, color, "%8.1f%%", "backend bound",
1155	be_bound * 100.);	1167	be_bound * 100.);
1156	} else if (perf_stat_evsel__is(evsel, TOPDOWN_BAD_SPEC) &&	1168	} else if (perf_stat_evsel__is(evsel, TOPDOWN_BAD_SPEC) &&
1157	full_td(ctx, cpu, st)) {	1169	full_td(cpu, st, &rsd)) {
1158	double bad_spec = td_metric_ratio(ctx, cpu,	1170	double bad_spec = td_metric_ratio(cpu,
1159	STAT_TOPDOWN_BAD_SPEC, st);	1171	STAT_TOPDOWN_BAD_SPEC, st,
1160		1172	&rsd);
1161	if (bad_spec > 0.1)	1173	if (bad_spec > 0.1)
1162	color = PERF_COLOR_RED;	1174	color = PERF_COLOR_RED;
1163	print_metric(config, ctxp, color, "%8.1f%%", "bad speculation",	1175	print_metric(config, ctxp, color, "%8.1f%%", "bad speculation",
@@ -1165,11 +1177,11 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, · 1 unmodified line
1165	} else if (evsel->metric_expr) {	1177	} else if (evsel->metric_expr) {
1166	generic_metric(config, evsel->metric_expr, evsel->metric_events, NULL,	1178	generic_metric(config, evsel->metric_expr, evsel->metric_events, NULL,
1167	evsel->name, evsel->metric_name, NULL, 1, cpu, out, st);	1179	evsel->name, evsel->metric_name, NULL, 1, cpu, out, st);
1168	} else if (runtime_stat_n(st, STAT_NSECS, 0, cpu) != 0) {	1180	} else if (runtime_stat_n(st, STAT_NSECS, cpu, &rsd) != 0) {
1169	char unit = 'M';	1181	char unit = 'M';
1170	char unit_buf[10];	1182	char unit_buf[10];
1171		1183
1172	total = runtime_stat_avg(st, STAT_NSECS, 0, cpu);	1184	total = runtime_stat_avg(st, STAT_NSECS, cpu, &rsd);
1173		1185
1174	if (total)	1186	if (total)
1175	ratio = 1000.0 * avg / total;	1187	ratio = 1000.0 * avg / total;
@@ -1180,7 +1192,7 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, · 4 unmodified lines
1180	snprintf(unit_buf, sizeof(unit_buf), "%c/sec", unit);	1192	snprintf(unit_buf, sizeof(unit_buf), "%c/sec", unit);
1181	print_metric(config, ctxp, NULL, "%8.3f", unit_buf, ratio);	1193	print_metric(config, ctxp, NULL, "%8.3f", unit_buf, ratio);
1182	} else if (perf_stat_evsel__is(evsel, SMI_NUM)) {	1194	} else if (perf_stat_evsel__is(evsel, SMI_NUM)) {
1183	print_smi_cost(config, cpu, evsel, out, st);	1195	print_smi_cost(config, cpu, out, st, &rsd);
1184	} else {	1196	} else {
1185	num = 0;	1197	num = 0;
1186	}	1198	}

tools/testing/selftests/arm64/fp/fpsimd-test.S+1−1

@@ -457,7 +457,7 @@ function barf · 456 unmodified lines
457	mov x11, x1 // actual data	457	mov x11, x1 // actual data
458	mov x12, x2 // data size	458	mov x12, x2 // data size
459		459
460	puts "Mistatch: PID="	460	puts "Mismatch: PID="
461	mov x0, x20	461	mov x0, x20
462	bl putdec	462	bl putdec
463	puts ", iteration="	463	puts ", iteration="

tools/testing/selftests/arm64/fp/sve-test.S+1−1

@@ -625,7 +625,7 @@ function barf · 624 unmodified lines
625	mov x11, x1 // actual data	625	mov x11, x1 // actual data
626	mov x12, x2 // data size	626	mov x12, x2 // data size
627		627
628	puts "Mistatch: PID="	628	puts "Mismatch: PID="
629	mov x0, x20	629	mov x0, x20
630	bl putdec	630	bl putdec
631	puts ", iteration="	631	puts ", iteration="

tools/testing/selftests/bpf/prog_tests/test_local_storage.c+26−70

 	struct bpf_spin_lock lock;
 };
-/* Copies an rm binary to a temp file. dest is a mkstemp template */
-static int copy_rm(char *dest)
-{
-	int fd_in, fd_out = -1, ret = 0;
-	struct stat stat;
-	char *buf = NULL;
-	fd_in = open("/bin/rm", O_RDONLY);
-	if (fd_in < 0)
-		return -errno;
-	fd_out = mkstemp(dest);
-	if (fd_out < 0) {
-		ret = -errno;
-		goto out;
-	}
-	ret = fstat(fd_in, &stat);
-	if (ret == -1) {
-		ret = -errno;
-		goto out;
-	}
-	buf = malloc(stat.st_blksize);
-	if (!buf) {
-		ret = -errno;
-		goto out;
-	}
-	while (ret = read(fd_in, buf, stat.st_blksize), ret > 0) {
-		ret = write(fd_out, buf, ret);
-		if (ret < 0) {
-			ret = -errno;
-			goto out;
-		}
-	}
-	if (ret < 0) {
-		ret = -errno;
-		goto out;
-	}
-	/* Set executable permission on the copied file */
-	ret = chmod(dest, 0100);
-	if (ret == -1)
-		ret = -errno;
-out:
-	free(buf);
-	close(fd_in);
-	close(fd_out);
-	return ret;
-}
 /* Fork and exec the provided rm binary and return the exit code of the
  * forked process and its pid.
  */
 void test_test_local_storage(void)
 {
-	char tmp_exec_path[PATH_MAX] = "/tmp/copy_of_rmXXXXXX";
+	char tmp_dir_path[64] = "/tmp/local_storageXXXXXX";
 	int err, serv_sk = -1, task_fd = -1, rm_fd = -1;
 	struct local_storage *skel = NULL;
+	char tmp_exec_path[64];
+	char cmd[256];
 	skel = local_storage__open_and_load();
 	if (CHECK(!skel, "skel_load", "lsm skeleton failed\n"))
 				      task_fd))
 		goto close_prog;
-	err = copy_rm(tmp_exec_path);
+	if (CHECK(!mkdtemp(tmp_dir_path), "mkdtemp",
-	if (CHECK(err < 0, "copy_rm", "err %d errno %d\n", err, errno))
+		  "unable to create tmpdir: %d\n", errno))
 		goto close_prog;
+	snprintf(tmp_exec_path, sizeof(tmp_exec_path), "%s/copy_of_rm",
+		 tmp_dir_path);
+	snprintf(cmd, sizeof(cmd), "cp /bin/rm %s", tmp_exec_path);
+	if (CHECK_FAIL(system(cmd)))
+		goto close_prog_rmdir;
 	rm_fd = open(tmp_exec_path, O_RDONLY);
 	if (CHECK(rm_fd < 0, "open", "failed to open %s err:%d, errno:%d",
 		  tmp_exec_path, rm_fd, errno))
-		goto close_prog;
+		goto close_prog_rmdir;
 	if (!check_syscall_operations(bpf_map__fd(skel->maps.inode_storage_map),
 				      rm_fd))
-		goto close_prog;
+		goto close_prog_rmdir;
 	/* Sets skel->bss->monitored_pid to the pid of the forked child
 	 * forks a child process that executes tmp_exec_path and tries to
 	 */
 	err = run_self_unlink(&skel->bss->monitored_pid, tmp_exec_path);
 	if (CHECK(err != EPERM, "run_self_unlink", "err %d want EPERM\n", err))
-		goto close_prog_unlink;
+		goto close_prog_rmdir;
 	/* Set the process being monitored to be the current process */
 	skel->bss->monitored_pid = getpid();
-	/* Remove the temporary created executable */
+	/* Move copy_of_rm to a new location so that it triggers the
-	err = unlink(tmp_exec_path);
+	 * inode_rename LSM hook with a new_dentry that has a NULL inode ptr.
-	if (CHECK(err != 0, "unlink", "unable to unlink %s: %d", tmp_exec_path,
+	 */
-		  errno))
+	snprintf(cmd, sizeof(cmd), "mv %s/copy_of_rm %s/check_null_ptr",
-		goto close_prog_unlink;
+		 tmp_dir_path, tmp_dir_path);
+	if (CHECK_FAIL(system(cmd)))
+		goto close_prog_rmdir;
 	CHECK(skel->data->inode_storage_result != 0, "inode_storage_result",
 	      "inode_local_storage not set\n");
 	serv_sk = start_server(AF_INET6, SOCK_STREAM, NULL, 0, 0);
 	if (CHECK(serv_sk < 0, "start_server", "failed to start server\n"))
-		goto close_prog;
+		goto close_prog_rmdir;
 	CHECK(skel->data->sk_storage_result != 0, "sk_storage_result",
 	      "sk_local_storage not set\n");
 	if (!check_syscall_operations(bpf_map__fd(skel->maps.sk_storage_map),
 				      serv_sk))
-		goto close_prog;
+		goto close_prog_rmdir;
-close_prog_unlink:
+close_prog_rmdir:
-	unlink(tmp_exec_path);
+	snprintf(cmd, sizeof(cmd), "rm -rf %s", tmp_dir_path);
+	system(cmd);
 close_prog:
 	close(serv_sk);
 	close(rm_fd);

tools/testing/selftests/bpf/progs/local_storage.c+35−27

 	__u32 pid = bpf_get_current_pid_tgid() >> 32;
 	struct local_storage *storage;
 	bool is_self_unlink;
-	int err;
 	if (pid != monitored_pid)
 		return 0;
 			return -EPERM;
 	}
-	storage = bpf_inode_storage_get(&inode_storage_map, victim->d_inode, 0,
+	return 0;
-					BPF_LOCAL_STORAGE_GET_F_CREATE);
+}
+SEC("lsm/inode_rename")
+int BPF_PROG(inode_rename, struct inode *old_dir, struct dentry *old_dentry,
+	     struct inode *new_dir, struct dentry *new_dentry,
+	     unsigned int flags)
+{
+	__u32 pid = bpf_get_current_pid_tgid() >> 32;
+	struct local_storage *storage;
+	int err;
+	/* new_dentry->d_inode can be NULL when the inode is renamed to a file
+	 * that did not exist before. The helper should be able to handle this
+	 * NULL pointer.
+	 */
+	bpf_inode_storage_get(&inode_storage_map, new_dentry->d_inode, 0,
+			      BPF_LOCAL_STORAGE_GET_F_CREATE);
+	storage = bpf_inode_storage_get(&inode_storage_map, old_dentry->d_inode,
+					0, 0);
 	if (!storage)
 		return 0;
 		inode_storage_result = -1;
 	bpf_spin_unlock(&storage->lock);
-	err = bpf_inode_storage_delete(&inode_storage_map, victim->d_inode);
+	err = bpf_inode_storage_delete(&inode_storage_map, old_dentry->d_inode);
 	if (!err)
 		inode_storage_result = err;
 	return 0;
 }
-SEC("lsm/file_open")
-int BPF_PROG(file_open, struct file *file)
-{
-	__u32 pid = bpf_get_current_pid_tgid() >> 32;
-	struct local_storage *storage;
-	if (pid != monitored_pid)
-		return 0;
-	if (!file->f_inode)
-		return 0;
-	storage = bpf_inode_storage_get(&inode_storage_map, file->f_inode, 0,
-					BPF_LOCAL_STORAGE_GET_F_CREATE);
-	if (!storage)
-		return 0;
-	bpf_spin_lock(&storage->lock);
-	storage->value = DUMMY_STORAGE_VALUE;
-	bpf_spin_unlock(&storage->lock);
-	return 0;
-}
 /* This uses the local storage to remember the inode of the binary that a
  * process was originally executing.
  */
 SEC("lsm/bprm_committed_creds")
 void BPF_PROG(exec, struct linux_binprm *bprm)
 {
+	__u32 pid = bpf_get_current_pid_tgid() >> 32;
 	struct local_storage *storage;
+	if (pid != monitored_pid)
+		return;
 	storage = bpf_task_storage_get(&task_storage_map,
 				       bpf_get_current_task_btf(), 0,
 				       BPF_LOCAL_STORAGE_GET_F_CREATE);
 		storage->exec_inode = bprm->file->f_inode;
 		bpf_spin_unlock(&storage->lock);
 	}
+	storage = bpf_inode_storage_get(&inode_storage_map, bprm->file->f_inode,
+					0, BPF_LOCAL_STORAGE_GET_F_CREATE);
+	if (!storage)
+		return;
+	bpf_spin_lock(&storage->lock);
+	storage->value = DUMMY_STORAGE_VALUE;
+	bpf_spin_unlock(&storage->lock);
 }

tools/testing/selftests/bpf/test_verifier.c+11−1

 #define MAX_INSNS	BPF_MAXINSNS
 #define MAX_TEST_INSNS	1000000
 #define MAX_FIXUPS	8
-#define MAX_NR_MAPS	20
+#define MAX_NR_MAPS	21
 #define MAX_TEST_RUNS	8
 #define POINTER_VALUE	0xcafe4all
 #define TEST_DATA_LEN	64
 	int fixup_sk_storage_map[MAX_FIXUPS];
 	int fixup_map_event_output[MAX_FIXUPS];
 	int fixup_map_reuseport_array[MAX_FIXUPS];
+	int fixup_map_ringbuf[MAX_FIXUPS];
 	const char *errstr;
 	const char *errstr_unpriv;
 	uint32_t insn_processed;
 	int *fixup_sk_storage_map = test->fixup_sk_storage_map;
 	int *fixup_map_event_output = test->fixup_map_event_output;
 	int *fixup_map_reuseport_array = test->fixup_map_reuseport_array;
+	int *fixup_map_ringbuf = test->fixup_map_ringbuf;
 	if (test->fill_helper) {
 		test->fill_insns = calloc(MAX_TEST_INSNS, sizeof(struct bpf_insn));
 			fixup_map_reuseport_array++;
 		} while (*fixup_map_reuseport_array);
 	}
+	if (*fixup_map_ringbuf) {
+		map_fds[20] = create_map(BPF_MAP_TYPE_RINGBUF, 0,
+					   0, 4096);
+		do {
+			prog[*fixup_map_ringbuf].imm = map_fds[20];
+			fixup_map_ringbuf++;
+		} while (*fixup_map_ringbuf);
+	}
 }
 struct libcap {

tools/testing/selftests/bpf/verifier/spill_fill.c+30−0

@@ -28,6 +28,36 @@ · 27 unmodified lines
28	.result = ACCEPT,	28	.result = ACCEPT,
29	.result_unpriv = ACCEPT,	29	.result_unpriv = ACCEPT,
30	},	30	},
		31	{
		32	"check valid spill/fill, ptr to mem",
		33	.insns = {
		34	/* reserve 8 byte ringbuf memory */
		35	BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0),
		36	BPF_LD_MAP_FD(BPF_REG_1, 0),
		37	BPF_MOV64_IMM(BPF_REG_2, 8),
		38	BPF_MOV64_IMM(BPF_REG_3, 0),
		39	BPF_RAW_INSN(BPF_JMP \| BPF_CALL, 0, 0, 0, BPF_FUNC_ringbuf_reserve),
		40	/* store a pointer to the reserved memory in R6 */
		41	BPF_MOV64_REG(BPF_REG_6, BPF_REG_0),
		42	/* check whether the reservation was successful */
		43	BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0, 6),
		44	/* spill R6(mem) into the stack */
		45	BPF_STX_MEM(BPF_DW, BPF_REG_10, BPF_REG_6, -8),
		46	/* fill it back in R7 */
		47	BPF_LDX_MEM(BPF_DW, BPF_REG_7, BPF_REG_10, -8),
		48	/* should be able to access (R7) = 0 /
		49	BPF_ST_MEM(BPF_DW, BPF_REG_7, 0, 0),
		50	/* submit the reserved ringbuf memory */
		51	BPF_MOV64_REG(BPF_REG_1, BPF_REG_7),
		52	BPF_MOV64_IMM(BPF_REG_2, 0),
		53	BPF_RAW_INSN(BPF_JMP \| BPF_CALL, 0, 0, 0, BPF_FUNC_ringbuf_submit),
		54	BPF_MOV64_IMM(BPF_REG_0, 0),
		55	BPF_EXIT_INSN(),
		56	},
		57	.fixup_map_ringbuf = { 1 },
		58	.result = ACCEPT,
		59	.result_unpriv = ACCEPT,
		60	},
31	{	61	{
32	"check corrupted spill/fill",	62	"check corrupted spill/fill",
33	.insns = {	63	.insns = {

tools/testing/selftests/net/fib_tests.sh+0−1

@@ -1055,7 +1055,6 @@ ipv6_addr_metric_test() · 1054 unmodified lines
1055		1055
1056	check_route6 "2001:db8:104::1 dev dummy2 proto kernel metric 260"	1056	check_route6 "2001:db8:104::1 dev dummy2 proto kernel metric 260"
1057	log_test $? 0 "Set metric with peer route on local side"	1057	log_test $? 0 "Set metric with peer route on local side"
1058	log_test $? 0 "User specified metric on local address"
1059	check_route6 "2001:db8:104::2 dev dummy2 proto kernel metric 260"	1058	check_route6 "2001:db8:104::2 dev dummy2 proto kernel metric 260"
1060	log_test $? 0 "Set metric with peer route on peer side"	1059	log_test $? 0 "Set metric with peer route on peer side"
1061		1060