Pull PCI updates from Bjorn Helgaas: - skip AER driver error recovery callbacks for correctable errors reported via ACPI APEI, as we already do for errors reported via the native path (Tyler Baicar) - fix DPC shared interrupt handling (Alex Williamson) - print full DPC interrupt number (Keith Busch) - enable DPC only if AER is available (Keith Busch) - simplify DPC code (Bjorn Helgaas) - calculate ASPM L1 substate parameter instead of hardcoding it (Bjorn Helgaas) - enable Latency Tolerance Reporting for ASPM L1 substates (Bjorn Helgaas) - move ASPM internal interfaces out of public header (Bjorn Helgaas) - allow hot-removal of VGA devices (Mika Westerberg) - speed up unplug and shutdown by assuming Thunderbolt controllers don't support Command Completed events (Lukas Wunner) - add AtomicOps support for GPU and Infiniband drivers (Felix Kuehling, Jay Cornwall) - expose "ari_enabled" in sysfs to help NIC naming (Stuart Hayes) - clean up PCI DMA interface usage (Christoph Hellwig) - remove PCI pool API (replaced with DMA pool) (Romain Perier) - deprecate pci_get_bus_and_slot(), which assumed PCI domain 0 (Sinan Kaya) - move DT PCI code from drivers/of/ to drivers/pci/ (Rob Herring) - add PCI-specific wrappers for dev_info(), etc (Frederick Lawler) - remove warnings on sysfs mmap failure (Bjorn Helgaas) - quiet ROM validation messages (Alex Deucher) - remove redundant memory alloc failure messages (Markus Elfring) - fill in types for compile-time VGA and other I/O port resources (Bjorn Helgaas) - make "pci=pcie_scan_all" work for Root Ports as well as Downstream Ports to help AmigaOne X1000 (Bjorn Helgaas) - add SPDX tags to all PCI files (Bjorn Helgaas) - quirk Marvell 9128 DMA aliases (Alex Williamson) - quirk broken INTx disable on Ceton InfiniTV4 (Bjorn Helgaas) - fix CONFIG_PCI=n build by adding dummy pci_irqd_intx_xlate() (Niklas Cassel) - use DMA API to get MSI address for DesignWare IP (Niklas Cassel) - fix endpoint-mode DMA mask configuration (Kishon Vijay Abraham I) - fix ARTPEC-6 incorrect IS_ERR() usage (Wei Yongjun) - add support for ARTPEC-7 SoC (Niklas Cassel) - add endpoint-mode support for ARTPEC (Niklas Cassel) - add Cadence PCIe host and endpoint controller driver (Cyrille Pitchen) - handle multiple INTx status bits being set in dra7xx (Vignesh R) - translate dra7xx hwirq range to fix INTD handling (Vignesh R) - remove deprecated Exynos PHY initialization code (Jaehoon Chung) - fix MSI erratum workaround for HiSilicon Hip06/Hip07 (Dongdong Liu) - fix NULL pointer dereference in iProc BCMA driver (Ray Jui) - fix Keystone interrupt-controller-node lookup (Johan Hovold) - constify qcom driver structures (Julia Lawall) - rework Tegra config space mapping to increase space available for endpoints (Vidya Sagar) - simplify Tegra driver by using bus->sysdata (Manikanta Maddireddy) - remove PCI_REASSIGN_ALL_BUS usage on Tegra (Manikanta Maddireddy) - add support for Global Fabric Manager Server (GFMS) event to Microsemi Switchtec switch driver (Logan Gunthorpe) - add IDs for Switchtec PSX 24xG3 and PSX 48xG3 (Kelvin Cao) * tag 'pci-v4.16-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (140 commits) PCI: cadence: Add EndPoint Controller driver for Cadence PCIe controller dt-bindings: PCI: cadence: Add DT bindings for Cadence PCIe endpoint controller PCI: endpoint: Fix EPF device name to support multi-function devices PCI: endpoint: Add the function number as argument to EPC ops PCI: cadence: Add host driver for Cadence PCIe controller dt-bindings: PCI: cadence: Add DT bindings for Cadence PCIe host controller PCI: Add vendor ID for Cadence PCI: Add generic function to probe PCI host controllers PCI: generic: fix missing call of pci_free_resource_list() PCI: OF: Add generic function to parse and allocate PCI resources PCI: Regroup all PCI related entries into drivers/pci/Makefile PCI/DPC: Reformat DPC register definitions PCI/DPC: Add and use DPC Status register field definitions PCI/DPC: Squash dpc_rp_pio_get_info() into dpc_process_rp_pio_error() PCI/DPC: Remove unnecessary RP PIO register structs PCI/DPC: Push dpc->rp_pio_status assignment into dpc_rp_pio_get_info() PCI/DPC: Squash dpc_rp_pio_print_error() into dpc_rp_pio_get_info() PCI/DPC: Make RP PIO log size check more generic PCI/DPC: Rename local "status" to "dpc_status" PCI/DPC: Squash dpc_rp_pio_print_tlp_header() into dpc_rp_pio_print_error() ...
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| @@ -622,15 +622,19 @@ · 621 unmodified lines | |||
| 622 | * safely. | 622 | * safely. |
| 623 | */ | 623 | */ |
| 624 | #define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ | 624 | #define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ |
| 625 | #define PCI_EXP_DEVCAP2_COMP_TMOUT_DIS 0x00000010 /* Completion Timeout Disable supported */ | ||
| 625 | #define PCI_EXP_DEVCAP2_ARI 0x00000020 /* Alternative Routing-ID */ | 626 | #define PCI_EXP_DEVCAP2_ARI 0x00000020 /* Alternative Routing-ID */ |
| 626 | #define PCI_EXP_DEVCAP2_ATOMIC_ROUTE 0x00000040 /* Atomic Op routing */ | 627 | #define PCI_EXP_DEVCAP2_ATOMIC_ROUTE 0x00000040 /* Atomic Op routing */ |
| 627 | #define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 /* Atomic 64-bit compare */ | 628 | #define PCI_EXP_DEVCAP2_ATOMIC_COMP32 0x00000080 /* 32b AtomicOp completion */ |
| 629 | #define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 /* 64b AtomicOp completion */ | ||
| 630 | #define PCI_EXP_DEVCAP2_ATOMIC_COMP128 0x00000200 /* 128b AtomicOp completion */ | ||
| 628 | #define PCI_EXP_DEVCAP2_LTR 0x00000800 /* Latency tolerance reporting */ | 631 | #define PCI_EXP_DEVCAP2_LTR 0x00000800 /* Latency tolerance reporting */ |
| 629 | #define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */ | 632 | #define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */ |
| 630 | #define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */ | 633 | #define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */ |
| 631 | #define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */ | 634 | #define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */ |
| 632 | #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ | 635 | #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ |
| 633 | #define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */ | 636 | #define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */ |
| 637 | #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS 0x0010 /* Completion Timeout Disable */ | ||
| 634 | #define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */ | 638 | #define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */ |
| 635 | #define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */ | 639 | #define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */ |
| 636 | #define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */ | 640 | #define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */ |
| @@ -966,26 +970,28 @@ · 329 unmodified lines | |||
| 966 | 970 | ||
| 967 | /* Downstream Port Containment */ | 971 | /* Downstream Port Containment */ |
| 968 | #define PCI_EXP_DPC_CAP 4 /* DPC Capability */ | 972 | #define PCI_EXP_DPC_CAP 4 /* DPC Capability */ |
| 969 | #define PCI_EXP_DPC_IRQ 0x1f /* DPC Interrupt Message Number */ | 973 | #define PCI_EXP_DPC_IRQ 0x001F /* Interrupt Message Number */ |
| 970 | #define PCI_EXP_DPC_CAP_RP_EXT 0x20 /* Root Port Extensions for DPC */ | 974 | #define PCI_EXP_DPC_CAP_RP_EXT 0x0020 /* Root Port Extensions */ |
| 971 | #define PCI_EXP_DPC_CAP_POISONED_TLP 0x40 /* Poisoned TLP Egress Blocking Supported */ | 975 | #define PCI_EXP_DPC_CAP_POISONED_TLP 0x0040 /* Poisoned TLP Egress Blocking Supported */ |
| 972 | #define PCI_EXP_DPC_CAP_SW_TRIGGER 0x80 /* Software Triggering Supported */ | 976 | #define PCI_EXP_DPC_CAP_SW_TRIGGER 0x0080 /* Software Triggering Supported */ |
| 973 | #define PCI_EXP_DPC_RP_PIO_LOG_SIZE 0xF00 /* RP PIO log size */ | 977 | #define PCI_EXP_DPC_RP_PIO_LOG_SIZE 0x0F00 /* RP PIO Log Size */ |
| 974 | #define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 /* ERR_COR signal on DL_Active supported */ | 978 | #define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 /* ERR_COR signal on DL_Active supported */ |
| 975 | 979 | ||
| 976 | #define PCI_EXP_DPC_CTL 6 /* DPC control */ | 980 | #define PCI_EXP_DPC_CTL 6 /* DPC control */ |
| 977 | #define PCI_EXP_DPC_CTL_EN_NONFATAL 0x02 /* Enable trigger on ERR_NONFATAL message */ | 981 | #define PCI_EXP_DPC_CTL_EN_NONFATAL 0x0002 /* Enable trigger on ERR_NONFATAL message */ |
| 978 | #define PCI_EXP_DPC_CTL_INT_EN 0x08 /* DPC Interrupt Enable */ | 982 | #define PCI_EXP_DPC_CTL_INT_EN 0x0008 /* DPC Interrupt Enable */ |
| 979 | 983 | ||
| 980 | #define PCI_EXP_DPC_STATUS 8 /* DPC Status */ | 984 | #define PCI_EXP_DPC_STATUS 8 /* DPC Status */ |
| 981 | #define PCI_EXP_DPC_STATUS_TRIGGER 0x01 /* Trigger Status */ | 985 | #define PCI_EXP_DPC_STATUS_TRIGGER 0x0001 /* Trigger Status */ |
| 982 | #define PCI_EXP_DPC_STATUS_INTERRUPT 0x08 /* Interrupt Status */ | 986 | #define PCI_EXP_DPC_STATUS_TRIGGER_RSN 0x0006 /* Trigger Reason */ |
| 983 | #define PCI_EXP_DPC_RP_BUSY 0x10 /* Root Port Busy */ | 987 | #define PCI_EXP_DPC_STATUS_INTERRUPT 0x0008 /* Interrupt Status */ |
| 988 | #define PCI_EXP_DPC_RP_BUSY 0x0010 /* Root Port Busy */ | ||
| 989 | #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT 0x0060 /* Trig Reason Extension */ | ||
| 984 | 990 | ||
| 985 | #define PCI_EXP_DPC_SOURCE_ID 10 /* DPC Source Identifier */ | 991 | #define PCI_EXP_DPC_SOURCE_ID 10 /* DPC Source Identifier */ |
| 986 | 992 | ||
| 987 | #define PCI_EXP_DPC_RP_PIO_STATUS 0x0C /* RP PIO Status */ | 993 | #define PCI_EXP_DPC_RP_PIO_STATUS 0x0C /* RP PIO Status */ |
| 988 | #define PCI_EXP_DPC_RP_PIO_MASK 0x10 /* RP PIO MASK */ | 994 | #define PCI_EXP_DPC_RP_PIO_MASK 0x10 /* RP PIO Mask */ |
| 989 | #define PCI_EXP_DPC_RP_PIO_SEVERITY 0x14 /* RP PIO Severity */ | 995 | #define PCI_EXP_DPC_RP_PIO_SEVERITY 0x14 /* RP PIO Severity */ |
| 990 | #define PCI_EXP_DPC_RP_PIO_SYSERROR 0x18 /* RP PIO SysError */ | 996 | #define PCI_EXP_DPC_RP_PIO_SYSERROR 0x18 /* RP PIO SysError */ |
| 991 | #define PCI_EXP_DPC_RP_PIO_EXCEPTION 0x1C /* RP PIO Exception */ | 997 | #define PCI_EXP_DPC_RP_PIO_EXCEPTION 0x1C /* RP PIO Exception */ |
| @@ -88,7 +88,8 @@ struct switchtec_ioctl_event_summary { · 87 unmodified lines | |||
| 88 | #define SWITCHTEC_IOCTL_EVENT_FORCE_SPEED 26 | 88 | #define SWITCHTEC_IOCTL_EVENT_FORCE_SPEED 26 |
| 89 | #define SWITCHTEC_IOCTL_EVENT_CREDIT_TIMEOUT 27 | 89 | #define SWITCHTEC_IOCTL_EVENT_CREDIT_TIMEOUT 27 |
| 90 | #define SWITCHTEC_IOCTL_EVENT_LINK_STATE 28 | 90 | #define SWITCHTEC_IOCTL_EVENT_LINK_STATE 28 |
| 91 | #define SWITCHTEC_IOCTL_MAX_EVENTS 29 | 91 | #define SWITCHTEC_IOCTL_EVENT_GFMS 29 |
| 92 | #define SWITCHTEC_IOCTL_MAX_EVENTS 30 | ||
| 92 | 93 | ||
| 93 | #define SWITCHTEC_IOCTL_EVENT_LOCAL_PART_IDX -1 | 94 | #define SWITCHTEC_IOCTL_EVENT_LOCAL_PART_IDX -1 |
| 94 | #define SWITCHTEC_IOCTL_EVENT_IDX_ALL -2 | 95 | #define SWITCHTEC_IOCTL_EVENT_IDX_ALL -2 |