| @@ -1095,6 +1095,121 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) · 1094 unmodified lines |
| 1095 | */ | 1095 | */ |
| 1096 | #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0) | 1096 | #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0) |
| 1097 | | 1097 | |
| | 1098 | /* |
| | 1099 | * AMD modifiers |
| | 1100 | * |
| | 1101 | * Memory layout: |
| | 1102 | * |
| | 1103 | * without DCC: |
| | 1104 | * - main surface |
| | 1105 | * |
| | 1106 | * with DCC & without DCC_RETILE: |
| | 1107 | * - main surface in plane 0 |
| | 1108 | * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set) |
| | 1109 | * |
| | 1110 | * with DCC & DCC_RETILE: |
| | 1111 | * - main surface in plane 0 |
| | 1112 | * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned) |
| | 1113 | * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned) |
| | 1114 | * |
| | 1115 | * For multi-plane formats the above surfaces get merged into one plane for |
| | 1116 | * each format plane, based on the required alignment only. |
| | 1117 | */ |
| | 1118 | #define AMD_FMT_MOD fourcc_mod_code(AMD, 0) |
| | 1119 | |
| | 1120 | #define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD) |
| | 1121 | |
| | 1122 | /* Reserve 0 for GFX8 and older */ |
| | 1123 | #define AMD_FMT_MOD_TILE_VER_GFX9 1 |
| | 1124 | #define AMD_FMT_MOD_TILE_VER_GFX10 2 |
| | 1125 | #define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3 |
| | 1126 | |
| | 1127 | /* |
| | 1128 | * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical |
| | 1129 | * version. |
| | 1130 | */ |
| | 1131 | #define AMD_FMT_MOD_TILE_GFX9_64K_S 9 |
| | 1132 | |
| | 1133 | /* |
| | 1134 | * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has |
| | 1135 | * GFX9 as canonical version. |
| | 1136 | */ |
| | 1137 | #define AMD_FMT_MOD_TILE_GFX9_64K_D 10 |
| | 1138 | #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25 |
| | 1139 | #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26 |
| | 1140 | #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27 |
| | 1141 | |
| | 1142 | #define AMD_FMT_MOD_DCC_BLOCK_64B 0 |
| | 1143 | #define AMD_FMT_MOD_DCC_BLOCK_128B 1 |
| | 1144 | #define AMD_FMT_MOD_DCC_BLOCK_256B 2 |
| | 1145 | |
| | 1146 | #define AMD_FMT_MOD_TILE_VERSION_SHIFT 0 |
| | 1147 | #define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF |
| | 1148 | #define AMD_FMT_MOD_TILE_SHIFT 8 |
| | 1149 | #define AMD_FMT_MOD_TILE_MASK 0x1F |
| | 1150 | |
| | 1151 | /* Whether DCC compression is enabled. */ |
| | 1152 | #define AMD_FMT_MOD_DCC_SHIFT 13 |
| | 1153 | #define AMD_FMT_MOD_DCC_MASK 0x1 |
| | 1154 | |
| | 1155 | /* |
| | 1156 | * Whether to include two DCC surfaces, one which is rb & pipe aligned, and |
| | 1157 | * one which is not-aligned. |
| | 1158 | */ |
| | 1159 | #define AMD_FMT_MOD_DCC_RETILE_SHIFT 14 |
| | 1160 | #define AMD_FMT_MOD_DCC_RETILE_MASK 0x1 |
| | 1161 | |
| | 1162 | /* Only set if DCC_RETILE = false */ |
| | 1163 | #define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15 |
| | 1164 | #define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1 |
| | 1165 | |
| | 1166 | #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16 |
| | 1167 | #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1 |
| | 1168 | #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17 |
| | 1169 | #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1 |
| | 1170 | #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18 |
| | 1171 | #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x1 |
| | 1172 | |
| | 1173 | /* |
| | 1174 | * DCC supports embedding some clear colors directly in the DCC surface. |
| | 1175 | * However, on older GPUs the rendering HW ignores the embedded clear color |
| | 1176 | * and prefers the driver provided color. This necessitates doing a fastclear |
| | 1177 | * eliminate operation before a process transfers control. |
| | 1178 | * |
| | 1179 | * If this bit is set that means the fastclear eliminate is not needed for these |
| | 1180 | * embeddable colors. |
| | 1181 | */ |
| | 1182 | #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 19 |
| | 1183 | #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1 |
| | 1184 | |
| | 1185 | /* |
| | 1186 | * The below fields are for accounting for per GPU differences. These are only |
| | 1187 | * relevant for GFX9 and later and if the tile field is *_X/_T. |
| | 1188 | * |
| | 1189 | * PIPE_XOR_BITS = always needed |
| | 1190 | * BANK_XOR_BITS = only for TILE_VER_GFX9 |
| | 1191 | * PACKERS = only for TILE_VER_GFX10_RBPLUS |
| | 1192 | * RB = only for TILE_VER_GFX9 & DCC |
| | 1193 | * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN) |
| | 1194 | */ |
| | 1195 | #define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 20 |
| | 1196 | #define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7 |
| | 1197 | #define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 23 |
| | 1198 | #define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7 |
| | 1199 | #define AMD_FMT_MOD_PACKERS_SHIFT 26 /* aliases with BANK_XOR_BITS */ |
| | 1200 | #define AMD_FMT_MOD_PACKERS_MASK 0x7 |
| | 1201 | #define AMD_FMT_MOD_RB_SHIFT 29 |
| | 1202 | #define AMD_FMT_MOD_RB_MASK 0x7 |
| | 1203 | #define AMD_FMT_MOD_PIPE_SHIFT 32 |
| | 1204 | #define AMD_FMT_MOD_PIPE_MASK 0x7 |
| | 1205 | |
| | 1206 | #define AMD_FMT_MOD_SET(field, value) \ |
| | 1207 | ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT) |
| | 1208 | #define AMD_FMT_MOD_GET(field, value) \ |
| | 1209 | (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK) |
| | 1210 | #define AMD_FMT_MOD_CLEAR(field) \ |
| | 1211 | (~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT)) |
| | 1212 | |
| 1098 | #if defined(__cplusplus) | 1213 | #if defined(__cplusplus) |
| 1099 | } | 1214 | } |
| 1100 | #endif | 1215 | #endif |