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Merge drm/drm-next into drm-misc-next

We need commit f8f6ae5d077a ("mm: always have io_remap_pfn_range() set pgprot_decrypted()") to be able to merge Jason's cleanup patch.

Thomas Zimmermann committed 6 years ago

Commit 112e5052 parents 55c8bca 512bce5911 files · +294963 −7213Browse files

Showing the changes to include/uapi (4 of 911 files). Show all

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4 files
  1. include/uapi/drm/amdgpu_drm.h +5 −1
  2. include/uapi/drm/drm_fourcc.h +115 −0
  3. include/uapi/linux/icmpv6.h +1 −0
  4. include/uapi/sound/compress_offload.h +1 −1
include/uapi/drm/amdgpu_drm.h+5−1
@@ -667,7 +667,7 @@ struct drm_amdgpu_cs_chunk_data { · 666 unmodified lines
667667 };
668668 };
669669
670−/**
670+/*
671671 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
672672 *
673673 */
@@ -724,6 +724,8 @@ struct drm_amdgpu_cs_chunk_data { · 50 unmodified lines
724724 #define AMDGPU_INFO_FW_TA 0x13
725725 /* Subquery id: Query DMCUB firmware version */
726726 #define AMDGPU_INFO_FW_DMCUB 0x14
727+ /* Subquery id: Query TOC firmware version */
728+ #define AMDGPU_INFO_FW_TOC 0x15
727729
728730 /* number of bytes moved for TTM migration */
729731 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
@@ -946,6 +948,7 @@ struct drm_amdgpu_info_firmware { · 216 unmodified lines
946948 #define AMDGPU_VRAM_TYPE_DDR3 7
947949 #define AMDGPU_VRAM_TYPE_DDR4 8
948950 #define AMDGPU_VRAM_TYPE_GDDR6 9
951+#define AMDGPU_VRAM_TYPE_DDR5 10
949952
950953 struct drm_amdgpu_info_device {
951954 /** PCI Device ID */
@@ -1083,6 +1086,7 @@ struct drm_amdgpu_info_vce_clock_table { · 131 unmodified lines
10831086 #define AMDGPU_FAMILY_AI 141 /* Vega10 */
10841087 #define AMDGPU_FAMILY_RV 142 /* Raven */
10851088 #define AMDGPU_FAMILY_NV 143 /* Navi10 */
1089+#define AMDGPU_FAMILY_VGH 144 /* Van Gogh */
10861090
10871091 #if defined(__cplusplus)
10881092 }
include/uapi/drm/drm_fourcc.h+115−0
@@ -1095,6 +1095,121 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) · 1094 unmodified lines
10951095 */
10961096 #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0)
10971097
1098+/*
1099+ * AMD modifiers
1100+ *
1101+ * Memory layout:
1102+ *
1103+ * without DCC:
1104+ * - main surface
1105+ *
1106+ * with DCC & without DCC_RETILE:
1107+ * - main surface in plane 0
1108+ * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set)
1109+ *
1110+ * with DCC & DCC_RETILE:
1111+ * - main surface in plane 0
1112+ * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned)
1113+ * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned)
1114+ *
1115+ * For multi-plane formats the above surfaces get merged into one plane for
1116+ * each format plane, based on the required alignment only.
1117+ */
1118+#define AMD_FMT_MOD fourcc_mod_code(AMD, 0)
1119+
1120+#define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD)
1121+
1122+/* Reserve 0 for GFX8 and older */
1123+#define AMD_FMT_MOD_TILE_VER_GFX9 1
1124+#define AMD_FMT_MOD_TILE_VER_GFX10 2
1125+#define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3
1126+
1127+/*
1128+ * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical
1129+ * version.
1130+ */
1131+#define AMD_FMT_MOD_TILE_GFX9_64K_S 9
1132+
1133+/*
1134+ * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has
1135+ * GFX9 as canonical version.
1136+ */
1137+#define AMD_FMT_MOD_TILE_GFX9_64K_D 10
1138+#define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25
1139+#define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26
1140+#define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
1141+
1142+#define AMD_FMT_MOD_DCC_BLOCK_64B 0
1143+#define AMD_FMT_MOD_DCC_BLOCK_128B 1
1144+#define AMD_FMT_MOD_DCC_BLOCK_256B 2
1145+
1146+#define AMD_FMT_MOD_TILE_VERSION_SHIFT 0
1147+#define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF
1148+#define AMD_FMT_MOD_TILE_SHIFT 8
1149+#define AMD_FMT_MOD_TILE_MASK 0x1F
1150+
1151+/* Whether DCC compression is enabled. */
1152+#define AMD_FMT_MOD_DCC_SHIFT 13
1153+#define AMD_FMT_MOD_DCC_MASK 0x1
1154+
1155+/*
1156+ * Whether to include two DCC surfaces, one which is rb & pipe aligned, and
1157+ * one which is not-aligned.
1158+ */
1159+#define AMD_FMT_MOD_DCC_RETILE_SHIFT 14
1160+#define AMD_FMT_MOD_DCC_RETILE_MASK 0x1
1161+
1162+/* Only set if DCC_RETILE = false */
1163+#define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15
1164+#define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1
1165+
1166+#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16
1167+#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1
1168+#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17
1169+#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1
1170+#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18
1171+#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x1
1172+
1173+/*
1174+ * DCC supports embedding some clear colors directly in the DCC surface.
1175+ * However, on older GPUs the rendering HW ignores the embedded clear color
1176+ * and prefers the driver provided color. This necessitates doing a fastclear
1177+ * eliminate operation before a process transfers control.
1178+ *
1179+ * If this bit is set that means the fastclear eliminate is not needed for these
1180+ * embeddable colors.
1181+ */
1182+#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 19
1183+#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1
1184+
1185+/*
1186+ * The below fields are for accounting for per GPU differences. These are only
1187+ * relevant for GFX9 and later and if the tile field is *_X/_T.
1188+ *
1189+ * PIPE_XOR_BITS = always needed
1190+ * BANK_XOR_BITS = only for TILE_VER_GFX9
1191+ * PACKERS = only for TILE_VER_GFX10_RBPLUS
1192+ * RB = only for TILE_VER_GFX9 & DCC
1193+ * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN)
1194+ */
1195+#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 20
1196+#define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7
1197+#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 23
1198+#define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7
1199+#define AMD_FMT_MOD_PACKERS_SHIFT 26 /* aliases with BANK_XOR_BITS */
1200+#define AMD_FMT_MOD_PACKERS_MASK 0x7
1201+#define AMD_FMT_MOD_RB_SHIFT 29
1202+#define AMD_FMT_MOD_RB_MASK 0x7
1203+#define AMD_FMT_MOD_PIPE_SHIFT 32
1204+#define AMD_FMT_MOD_PIPE_MASK 0x7
1205+
1206+#define AMD_FMT_MOD_SET(field, value) \
1207+ ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT)
1208+#define AMD_FMT_MOD_GET(field, value) \
1209+ (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK)
1210+#define AMD_FMT_MOD_CLEAR(field) \
1211+ (~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))
1212+
10981213 #if defined(__cplusplus)
10991214 }
11001215 #endif
include/uapi/linux/icmpv6.h+1−0
@@ -138,6 +138,7 @@ struct icmp6hdr { · 137 unmodified lines
138138 #define ICMPV6_HDR_FIELD 0
139139 #define ICMPV6_UNK_NEXTHDR 1
140140 #define ICMPV6_UNK_OPTION 2
141+#define ICMPV6_HDR_INCOMP 3
141142
142143 /*
143144 * constants for (set|get)sockopt
include/uapi/sound/compress_offload.h+1−1
@@ -144,7 +144,7 @@ struct snd_compr_metadata { · 143 unmodified lines
144144 __u32 value[8];
145145 } __attribute__((packed, aligned(4)));
146146
147−/**
147+/*
148148 * compress path ioctl definitions
149149 * SNDRV_COMPRESS_GET_CAPS: Query capability of DSP
150150 * SNDRV_COMPRESS_GET_CODEC_CAPS: Query capability of a codec